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ti99: Using proper RAM devices instead of ROM_REGIONS, adapting logerror output

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This commit is contained in:
Michael Zapf 2016-08-08 01:23:07 +02:00
parent 7b8179bb04
commit 927d438f6b
10 changed files with 259 additions and 243 deletions
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32
src/devices/bus/ti99_peb/bwg.cpp
View File

@ -85,10 +85,15 @@
*/
snug_bwg_device::snug_bwg_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ti_expansion_card_device(mconfig, TI99_BWG, "SNUG BwG Floppy Controller", tag, owner, clock, "ti99_bwg", __FILE__), m_DRQ(), m_IRQ(), m_dip1(0), m_dip2(0), m_dip34(0), m_ram_page(0), m_rom_page(0), m_WAITena(false), m_inDsrArea(false), m_WDsel(false), m_WDsel0(false), m_RTCsel(false), m_lastK(false), m_dataregLB(false), m_rtc_enabled(false), m_MOTOR_ON(), m_lastval(0), m_address(0), m_DSEL(0), m_SIDSEL(), m_motor_on_timer(nullptr), m_dsrrom(nullptr), m_buffer_ram(nullptr), m_current_floppy(nullptr),
m_wd1773(*this, FDC_TAG),
m_clock(*this, CLOCK_TAG), m_debug_dataout(false)
{ }
: ti_expansion_card_device(mconfig, TI99_BWG, "SNUG BwG Floppy Controller", tag, owner, clock, "ti99_bwg", __FILE__),
m_DRQ(), m_IRQ(), m_dip1(0), m_dip2(0), m_dip34(0), m_ram_page(0),
m_rom_page(0), m_WAITena(false), m_inDsrArea(false), m_WDsel(false),
m_WDsel0(false), m_RTCsel(false), m_lastK(false), m_dataregLB(false),
m_rtc_enabled(false), m_MOTOR_ON(), m_lastval(0), m_address(0),
m_DSEL(0), m_SIDSEL(), m_motor_on_timer(nullptr), m_dsrrom(nullptr),
m_buffer_ram(*this, BUFFER), m_current_floppy(nullptr),
m_wd1773(*this, FDC_TAG),
m_clock(*this, CLOCK_TAG), m_debug_dataout(false) { }
/*
Operate the wait state logic.
@ -189,7 +194,7 @@ void snug_bwg_device::debug_read(offs_t offset, UINT8* value)
if ((offset & 0x1c00)==0x1c00)
{
if ((offset & 0x1fe0)!=0x1fe0)
*value = m_buffer_ram[(m_ram_page<<10) | (offset & 0x03ff)];
*value = m_buffer_ram->pointer()[(m_ram_page<<10) | (offset & 0x03ff)];
}
else
*value = m_dsrrom[(m_rom_page<<13) | (offset & 0x1fff)];
@ -201,7 +206,7 @@ void snug_bwg_device::debug_write(offs_t offset, UINT8 data)
if (((offset & m_select_mask)==m_select_value) && m_selected)
{
if (((offset & 0x1c00)==0x1c00) && ((offset & 0x1fe0)!=0x1fe0))
m_buffer_ram[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
m_buffer_ram->pointer()[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
}
}
@ -233,7 +238,7 @@ READ8Z_MEMBER(snug_bwg_device::readz)
}
else
{
*value = m_buffer_ram[(m_ram_page<<10) | (m_address & 0x03ff)];
*value = m_buffer_ram->pointer()[(m_ram_page<<10) | (m_address & 0x03ff)];
if (TRACE_RW) logerror("bwg: read ram: %04x (page %d)-> %02x\n", m_address & 0xffff, m_ram_page, *value);
}
}
@ -254,7 +259,7 @@ READ8Z_MEMBER(snug_bwg_device::readz)
}
else
{
*value = m_buffer_ram[(m_ram_page<<10) | (m_address & 0x03ff)];
*value = m_buffer_ram->pointer()[(m_ram_page<<10) | (m_address & 0x03ff)];
if (TRACE_RW) logerror("bwg: read ram: %04x (page %d)-> %02x\n", m_address & 0xffff, m_ram_page, *value);
}
}
@ -302,7 +307,7 @@ WRITE8_MEMBER(snug_bwg_device::write)
else
{
if (TRACE_RW) logerror("bwg: write ram: %04x (page %d) <- %02x\n", m_address & 0xffff, m_ram_page, data);
m_buffer_ram[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
m_buffer_ram->pointer()[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
}
}
else
@ -318,7 +323,7 @@ WRITE8_MEMBER(snug_bwg_device::write)
else
{
if (TRACE_RW) logerror("bwg: write ram: %04x (page %d) <- %02x\n", m_address & 0xffff, m_ram_page, data);
m_buffer_ram[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
m_buffer_ram->pointer()[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
}
}
}
@ -558,7 +563,6 @@ void snug_bwg_device::device_start(void)
{
logerror("bwg: BWG start\n");
m_dsrrom = memregion(DSRROM)->base();
m_buffer_ram = memregion(BUFFER)->base();
m_motor_on_timer = timer_alloc(MOTOR_TIMER);
m_cru_base = 0x1100;
}
@ -678,13 +682,15 @@ MACHINE_CONFIG_FRAGMENT( bwg_fdc )
MCFG_FLOPPY_DRIVE_SOUND(true)
MCFG_FLOPPY_DRIVE_ADD("3", bwg_floppies, nullptr, snug_bwg_device::floppy_formats)
MCFG_FLOPPY_DRIVE_SOUND(true)
MCFG_RAM_ADD(BUFFER)
MCFG_RAM_DEFAULT_SIZE("2K")
MCFG_RAM_DEFAULT_VALUE(0)
MACHINE_CONFIG_END
ROM_START( bwg_fdc )
ROM_REGION(0x8000, DSRROM, 0)
ROM_LOAD("bwg_dsr.u15", 0x0000, 0x8000, CRC(06f1ec89) SHA1(6ad77033ed268f986d9a5439e65f7d391c4b7651)) /* BwG disk DSR ROM */
ROM_REGION(0x0800, BUFFER, 0) /* BwG RAM buffer */
ROM_FILL(0x0000, 0x0400, 0x00)
ROM_END
machine_config_constructor snug_bwg_device::device_mconfig_additions() const

3
src/devices/bus/ti99_peb/bwg.h
View File

@ -17,6 +17,7 @@
#include "imagedev/flopdrv.h"
#include "machine/mm58274c.h"
#include "machine/wd_fdc.h"
#include "machine/ram.h"
extern const device_type TI99_BWG;
@ -119,7 +120,7 @@ private:
UINT8* m_dsrrom;
// Buffer RAM
UINT8* m_buffer_ram;
required_device<ram_device> m_buffer_ram;
// Link to the attached floppy drives
floppy_image_device* m_floppy[4];

127
src/devices/bus/ti99_peb/hfdc.cpp
View File

@ -90,9 +90,14 @@
myarc_hfdc_device::myarc_hfdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ti_expansion_card_device(mconfig, TI99_HFDC, "Myarc Hard and Floppy Disk Controller", tag, owner, clock, "ti99_hfdc", __FILE__), m_motor_on_timer(nullptr),
m_hdc9234(*this, FDC_TAG),
m_clock(*this, CLOCK_TAG), m_current_floppy(nullptr), m_current_harddisk(nullptr), m_see_switches(false), m_irq(), m_dip(), m_motor_running(false),
m_inDsrArea(false), m_HDCsel(false), m_RTCsel(false), m_tapesel(false), m_RAMsel(false), m_ROMsel(false), m_address(0),
m_wait_for_hd1(false), m_dsrrom(nullptr), m_rom_page(0), m_buffer_ram(nullptr), m_status_latch(0), m_dma_address(0), m_output1_latch(0), m_output2_latch(0), m_lastval(0), m_MOTOR_ON(), m_readyflags(0)
m_clock(*this, CLOCK_TAG), m_current_floppy(nullptr),
m_current_harddisk(nullptr), m_see_switches(false),
m_irq(), m_dip(), m_motor_running(false),
m_inDsrArea(false), m_HDCsel(false), m_RTCsel(false),
m_tapesel(false), m_RAMsel(false), m_ROMsel(false), m_address(0),
m_wait_for_hd1(false), m_dsrrom(nullptr), m_rom_page(0),
m_buffer_ram(*this, BUFFER), m_status_latch(0), m_dma_address(0),
m_output1_latch(0), m_output2_latch(0), m_lastval(0), m_MOTOR_ON(), m_readyflags(0)
{
}
@ -151,7 +156,7 @@ void myarc_hfdc_device::debug_read(offs_t offset, UINT8* value)
if ((offset & 0x1000)==RAM_ADDR)
{
int bank = (offset & 0x0c00) >> 10;
*value = m_buffer_ram[(m_ram_page[bank]<<10) | (offset & 0x03ff)];
*value = m_buffer_ram->pointer()[(m_ram_page[bank]<<10) | (offset & 0x03ff)];
}
else
{
@ -170,7 +175,7 @@ void myarc_hfdc_device::debug_write(offs_t offset, UINT8 data)
if ((offset & 0x1000)==RAM_ADDR)
{
int bank = (offset & 0x0c00) >> 10;
m_buffer_ram[(m_ram_page[bank]<<10) | (m_address & 0x03ff)] = data;
m_buffer_ram->pointer()[(m_ram_page[bank]<<10) | (m_address & 0x03ff)] = data;
}
}
}
@ -202,21 +207,21 @@ READ8Z_MEMBER(myarc_hfdc_device::readz)
{
if (m_tapesel)
{
logerror("%s: Tape support not available on this HFDC version (access to address %04x)\n", tag(), m_address & 0xffff);
logerror("Tape support not available on this HFDC version (access to address %04x)\n", m_address & 0xffff);
return;
}
if (m_HDCsel)
{
*value = m_hdc9234->read(space, (m_address>>2)&1, 0xff);
if (TRACE_COMP) logerror("%s: %04x[HDC] -> %02x\n", tag(), m_address & 0xffff, *value);
if (TRACE_COMP) logerror("%04x[HDC] -> %02x\n", m_address & 0xffff, *value);
return;
}
if (m_RTCsel)
{
*value = m_clock->read(space, (m_address & 0x001e) >> 1);
if (TRACE_COMP) logerror("%s: %04x[CLK] -> %02x\n", tag(), m_address & 0xffff, *value);
if (TRACE_COMP) logerror("%04x[CLK] -> %02x\n", m_address & 0xffff, *value);
return;
}
@ -229,13 +234,13 @@ READ8Z_MEMBER(myarc_hfdc_device::readz)
int bank = (m_address & 0x0c00) >> 10;
// If a DMA is in progress, do not respond
if (m_dip == CLEAR_LINE) *value = m_buffer_ram[(m_ram_page[bank]<<10) | (m_address & 0x03ff)];
if (m_dip == CLEAR_LINE) *value = m_buffer_ram->pointer()[(m_ram_page[bank]<<10) | (m_address & 0x03ff)];
if (TRACE_RAM)
{
if (WORD_ALIGNED(m_address))
{
int valword = (((*value) << 8) | m_buffer_ram[(m_ram_page[bank]<<10) | ((m_address+1) & 0x03ff)])&0xffff;
logerror("%s: %04x[%02x] -> %04x\n", tag(), m_address & 0xffff, m_ram_page[bank], valword);
int valword = (((*value) << 8) | m_buffer_ram->pointer()[(m_ram_page[bank]<<10) | ((m_address+1) & 0x03ff)])&0xffff;
logerror("%04x[%02x] -> %04x\n", m_address & 0xffff, m_ram_page[bank], valword);
}
}
return;
@ -249,7 +254,7 @@ READ8Z_MEMBER(myarc_hfdc_device::readz)
if (WORD_ALIGNED(m_address))
{
int valword = (((*value) << 8) | m_dsrrom[(m_rom_page << 12) | ((m_address + 1) & 0x0fff)])&0xffff;
logerror("%s: %04x[%02x] -> %04x\n", tag(), m_address & 0xffff, m_rom_page, valword);
logerror("%04x[%02x] -> %04x\n", m_address & 0xffff, m_rom_page, valword);
}
}
return;
@ -281,20 +286,20 @@ WRITE8_MEMBER( myarc_hfdc_device::write )
{
if (m_tapesel)
{
logerror("%s: Tape support not available on this HFDC version (write access to address %04x: %02x)\n", tag(), m_address & 0xffff, data);
logerror("Tape support not available on this HFDC version (write access to address %04x: %02x)\n", m_address & 0xffff, data);
return;
}
if (m_HDCsel)
{
if (TRACE_COMP) logerror("%s: %04x[HDC] <- %02x\n", tag(), m_address & 0xffff, data);
if (TRACE_COMP) logerror("%04x[HDC] <- %02x\n", m_address & 0xffff, data);
m_hdc9234->write(space, (m_address>>2)&1, data, 0xff);
return;
}
if (m_RTCsel)
{
if (TRACE_COMP) logerror("%s: %04x[CLK] <- %02x\n", tag(), m_address & 0xffff, data);
if (TRACE_COMP) logerror("%04x[CLK] <- %02x\n", m_address & 0xffff, data);
m_clock->write(space, (m_address & 0x001e) >> 1, data);
return;
}
@ -306,16 +311,16 @@ WRITE8_MEMBER( myarc_hfdc_device::write )
// 0101 10xx xxxx xxxx bank 2
// 0101 11xx xxxx xxxx bank 3
int bank = (m_address & 0x0c00) >> 10;
if (TRACE_RAM) logerror("%s: %04x[%02x] <- %02x\n", tag(), m_address & 0xffff, m_ram_page[bank], data);
if (TRACE_RAM) logerror("%04x[%02x] <- %02x\n", m_address & 0xffff, m_ram_page[bank], data);
// When a DMA is in progress, do not change anything
if (m_dip == CLEAR_LINE) m_buffer_ram[(m_ram_page[bank]<<10) | (m_address & 0x03ff)] = data;
if (m_dip == CLEAR_LINE) m_buffer_ram->pointer()[(m_ram_page[bank]<<10) | (m_address & 0x03ff)] = data;
return;
}
// The rest is ROM
if (m_ROMsel)
{
if (TRACE_ROM) logerror("%s: Ignoring write ROM %04x[%02x]: %02x\n", tag(), m_address & 0xffff, m_rom_page, data);
if (TRACE_ROM) logerror("Ignoring write ROM %04x[%02x]: %02x\n", m_address & 0xffff, m_rom_page, data);
}
}
}
@ -388,7 +393,7 @@ READ8Z_MEMBER(myarc_hfdc_device::crureadz)
*value = 0;
}
if (TRACE_CRU) logerror("%s: CRU %04x -> %02x\n", tag(), offset & 0xffff, *value);
if (TRACE_CRU) logerror("CRU %04x -> %02x\n", offset & 0xffff, *value);
}
}
@ -420,7 +425,7 @@ WRITE8_MEMBER(myarc_hfdc_device::cruwrite)
{
if ((offset & 0xff00)==m_cru_base)
{
if (TRACE_CRU) logerror("%s: CRU %04x <- %d\n", tag(), offset & 0xffff, data);
if (TRACE_CRU) logerror("CRU %04x <- %d\n", offset & 0xffff, data);
int bit = (offset >> 1) & 0x1f;
@ -435,9 +440,9 @@ WRITE8_MEMBER(myarc_hfdc_device::cruwrite)
if (TRACE_CRU)
{
if (bit==0x0d) logerror("%s: RAM page @5400 = %d\n", tag(), m_ram_page[1]);
if (bit==0x12) logerror("%s: RAM page @5800 = %d\n", tag(), m_ram_page[2]);
if (bit==0x17) logerror("%s: RAM page @5C00 = %d\n", tag(), m_ram_page[3]);
if (bit==0x0d) logerror("RAM page @5400 = %d\n", m_ram_page[1]);
if (bit==0x12) logerror("RAM page @5800 = %d\n", m_ram_page[2]);
if (bit==0x17) logerror("RAM page @5C00 = %d\n", m_ram_page[3]);
}
return;
}
@ -448,12 +453,12 @@ WRITE8_MEMBER(myarc_hfdc_device::cruwrite)
{
bool turnOn = (data!=0);
// Avoid too many meaningless log outputs
if (TRACE_CRU) if (m_selected != turnOn) logerror("%s: card %s\n", tag(), turnOn? "selected" : "unselected");
if (TRACE_CRU) if (m_selected != turnOn) logerror("card %s\n", turnOn? "selected" : "unselected");
m_selected = turnOn;
break;
}
case 1:
if (TRACE_CRU) if (data==0) logerror("%s: trigger HDC reset\n", tag());
if (TRACE_CRU) if (data==0) logerror("trigger HDC reset\n");
m_hdc9234->reset((data == 0)? ASSERT_LINE : CLEAR_LINE);
break;
@ -477,17 +482,17 @@ WRITE8_MEMBER(myarc_hfdc_device::cruwrite)
case 3:
m_hdc9234->set_clock_divider(1, data);
m_rom_page = (data != 0)? (m_rom_page | 2) : (m_rom_page & 0xfd);
if (TRACE_CRU) logerror("%s: ROM page = %d\n", tag(), m_rom_page);
if (TRACE_CRU) logerror("ROM page = %d\n", m_rom_page);
break;
case 4:
m_see_switches = (data != 0);
m_rom_page = (data != 0)? (m_rom_page | 1) : (m_rom_page & 0xfe);
if (TRACE_CRU) logerror("%s: ROM page = %d, see_switches = %d\n", tag(), m_rom_page, m_see_switches);
if (TRACE_CRU) logerror("ROM page = %d, see_switches = %d\n", m_rom_page, m_see_switches);
break;
default:
logerror("%s: Attempt to set undefined CRU bit %d\n", tag(), bit);
logerror("Attempt to set undefined CRU bit %d\n", bit);
}
}
}
@ -505,7 +510,7 @@ void myarc_hfdc_device::device_timer(emu_timer &timer, device_timer_id id, int p
*/
void myarc_hfdc_device::floppy_index_callback(floppy_image_device *floppy, int state)
{
if (TRACE_LINES) if (state==1) logerror("%s: Floppy index pulse\n", tag());
if (TRACE_LINES) if (state==1) logerror("Floppy index pulse\n");
// m_status_latch = (state==ASSERT_LINE)? (m_status_latch | HDC_DS_INDEX) : (m_status_latch & ~HDC_DS_INDEX);
set_bits(m_status_latch, HDC_DS_INDEX, (state==ASSERT_LINE));
signal_drive_status();
@ -516,7 +521,7 @@ void myarc_hfdc_device::floppy_index_callback(floppy_image_device *floppy, int s
*/
void myarc_hfdc_device::harddisk_index_callback(mfm_harddisk_device *harddisk, int state)
{
if (TRACE_LINES) if (state==1) logerror("%s: HD index pulse\n", tag());
if (TRACE_LINES) if (state==1) logerror("HD index pulse\n");
set_bits(m_status_latch, HDC_DS_INDEX, (state==ASSERT_LINE));
signal_drive_status();
}
@ -526,7 +531,7 @@ void myarc_hfdc_device::harddisk_index_callback(mfm_harddisk_device *harddisk, i
*/
void myarc_hfdc_device::harddisk_ready_callback(mfm_harddisk_device *harddisk, int state)
{
if (TRACE_LINES) logerror("%s: HD READY = %d\n", tag(), state);
if (TRACE_LINES) logerror("HD READY = %d\n", state);
set_bits(m_status_latch, HDC_DS_READY, (state==ASSERT_LINE));
signal_drive_status();
}
@ -536,7 +541,7 @@ void myarc_hfdc_device::harddisk_ready_callback(mfm_harddisk_device *harddisk, i
*/
void myarc_hfdc_device::harddisk_skcom_callback(mfm_harddisk_device *harddisk, int state)
{
if (TRACE_LINES) logerror("%s: HD seek complete = %d\n", tag(), state);
if (TRACE_LINES) logerror("HD seek complete = %d\n", state);
set_bits(m_status_latch, HDC_DS_SKCOM, (state==ASSERT_LINE));
signal_drive_status();
}
@ -627,14 +632,14 @@ WRITE8_MEMBER( myarc_hfdc_device::auxbus_out )
switch (offset)
{
case HDC_INPUT_STATUS:
logerror("%s: Invalid operation: S0=S1=0, but tried to write (expected: read drive status)\n", tag());
logerror("Invalid operation: S0=S1=0, but tried to write (expected: read drive status)\n");
break;
case HDC_OUTPUT_DMA_ADDR:
// Value is dma address byte. Shift previous contents to the left.
// The value is latched inside the Gate Array.
m_dma_address = ((m_dma_address << 8) + (data&0xff))&0xffffff;
if (TRACE_DMA) logerror("%s: Setting DMA address; current value = %06x\n", tag(), m_dma_address);
if (TRACE_DMA) logerror("Setting DMA address; current value = %06x\n", m_dma_address);
break;
case HDC_OUTPUT_1:
@ -713,7 +718,7 @@ void myarc_hfdc_device::connect_floppy_unit(int index)
// Clear all latched flags from other drives
m_status_latch = 0;
disconnect_floppy_drives();
if (TRACE_LINES) logerror("%s: Select floppy drive DSK%d\n", tag(), index+1);
if (TRACE_LINES) logerror("Select floppy drive DSK%d\n", index+1);
// Connect new drive
m_current_floppy = m_floppy_unit[index];
@ -721,11 +726,11 @@ void myarc_hfdc_device::connect_floppy_unit(int index)
// We don't use the READY line of floppy drives.
// READY is asserted when DSKx = 1
// The controller fetches the state with the auxbus access
if (TRACE_LINES) logerror("%s: Connect index callback DSK%d\n", tag(), index+1);
if (TRACE_LINES) logerror("Connect index callback DSK%d\n", index+1);
if (m_current_floppy != nullptr)
m_current_floppy->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(FUNC(myarc_hfdc_device::floppy_index_callback), this));
else
logerror("%s: Connection to DSK%d failed because no drive is connected\n", tag(), index+1);
logerror("Connection to DSK%d failed because no drive is connected\n", index+1);
m_hdc9234->connect_floppy_drive(m_floppy_unit[index]);
}
@ -740,12 +745,12 @@ void myarc_hfdc_device::connect_harddisk_unit(int index)
// Clear all latched flags form other drives
m_status_latch = 0;
disconnect_hard_drives();
if (TRACE_LINES) logerror("%s: Select hard disk WDS%d\n", tag(), index+1);
if (TRACE_LINES) logerror("Select hard disk WDS%d\n", index+1);
// Connect new drive
m_current_harddisk = m_harddisk_unit[index];
if (TRACE_LINES) logerror("%s: Connect index callback WDS%d\n", tag(), index+1);
if (TRACE_LINES) logerror("Connect index callback WDS%d\n", index+1);
if (m_current_harddisk != nullptr)
{
m_current_harddisk->setup_index_pulse_cb(mfm_harddisk_device::index_pulse_cb(FUNC(myarc_hfdc_device::harddisk_index_callback), this));
@ -753,7 +758,7 @@ void myarc_hfdc_device::connect_harddisk_unit(int index)
m_current_harddisk->setup_seek_complete_cb(mfm_harddisk_device::seek_complete_cb(FUNC(myarc_hfdc_device::harddisk_skcom_callback), this));
}
else
logerror("%s: Connection to WDS%d failed because no drive is connected\n", tag(), index+1);
logerror("Connection to WDS%d failed because no drive is connected\n", index+1);
m_hdc9234->connect_hard_drive(m_current_harddisk);
}
@ -763,7 +768,7 @@ void myarc_hfdc_device::connect_harddisk_unit(int index)
void myarc_hfdc_device::disconnect_floppy_drives()
{
if (TRACE_LINES) logerror("%s: Unselect floppy drives\n", tag());
if (TRACE_LINES) logerror("Unselect floppy drives\n");
// Disconnect current floppy
if (m_current_floppy != nullptr)
{
@ -774,7 +779,7 @@ void myarc_hfdc_device::disconnect_floppy_drives()
void myarc_hfdc_device::disconnect_hard_drives()
{
if (TRACE_LINES) logerror("%s: Unselect hard drives\n", tag());
if (TRACE_LINES) logerror("Unselect hard drives\n");
if (m_current_harddisk != nullptr)
{
m_current_harddisk->setup_index_pulse_cb(mfm_harddisk_device::index_pulse_cb());
@ -791,13 +796,13 @@ void myarc_hfdc_device::set_floppy_motors_running(bool run)
if (run)
{
if (TRACE_MOTOR)
if (m_MOTOR_ON==CLEAR_LINE) logerror("%s: Motor START\n", tag());
if (m_MOTOR_ON==CLEAR_LINE) logerror("Motor START\n");
m_MOTOR_ON = ASSERT_LINE;
}
else
{
if (TRACE_MOTOR)
if (m_MOTOR_ON==ASSERT_LINE) logerror("%s: Motor STOP\n", tag());
if (m_MOTOR_ON==ASSERT_LINE) logerror("Motor STOP\n");
m_MOTOR_ON = CLEAR_LINE;
}
@ -812,7 +817,7 @@ void myarc_hfdc_device::set_floppy_motors_running(bool run)
WRITE_LINE_MEMBER( myarc_hfdc_device::intrq_w )
{
m_irq = (line_state)state;
if (TRACE_INT) logerror("%s: INT pin from controller = %d, propagating to INTA*\n", tag(), state);
if (TRACE_INT) logerror("INT pin from controller = %d, propagating to INTA*\n", state);
// Set INTA*
// Signal from SMC is active high, INTA* is active low; board inverts signal
@ -826,7 +831,7 @@ WRITE_LINE_MEMBER( myarc_hfdc_device::intrq_w )
*/
WRITE_LINE_MEMBER( myarc_hfdc_device::dmarq_w )
{
if (TRACE_DMA) logerror("%s: DMARQ pin from controller = %d\n", tag(), state);
if (TRACE_DMA) logerror("DMARQ pin from controller = %d\n", state);
if (state == ASSERT_LINE)
{
m_hdc9234->dmaack(ASSERT_LINE);
@ -846,9 +851,9 @@ WRITE_LINE_MEMBER( myarc_hfdc_device::dip_w )
*/
READ8_MEMBER( myarc_hfdc_device::read_buffer )
{
if (TRACE_DMA) logerror("%s: Read access to onboard SRAM at %04x\n", tag(), m_dma_address);
if (m_dma_address > 0x8000) logerror("%s: Read access beyond RAM size: %06x\n", tag(), m_dma_address);
UINT8 value = m_buffer_ram[m_dma_address & 0x7fff];
if (TRACE_DMA) logerror("Read access to onboard SRAM at %04x\n", m_dma_address);
if (m_dma_address > 0x8000) logerror("Read access beyond RAM size: %06x\n", m_dma_address);
UINT8 value = m_buffer_ram->pointer()[m_dma_address & 0x7fff];
m_dma_address = (m_dma_address+1) & 0x7fff;
return value;
}
@ -858,17 +863,15 @@ READ8_MEMBER( myarc_hfdc_device::read_buffer )
*/
WRITE8_MEMBER( myarc_hfdc_device::write_buffer )
{
if (TRACE_DMA) logerror("%s: Write access to onboard SRAM at %04x: %02x\n", tag(), m_dma_address, data);
if (m_dma_address > 0x8000) logerror("%s: Write access beyond RAM size: %06x\n", tag(), m_dma_address);
m_buffer_ram[m_dma_address & 0x7fff] = data;
if (TRACE_DMA) logerror("Write access to onboard SRAM at %04x: %02x\n", m_dma_address, data);
if (m_dma_address > 0x8000) logerror("Write access beyond RAM size: %06x\n", m_dma_address);
m_buffer_ram->pointer()[m_dma_address & 0x7fff] = data;
m_dma_address = (m_dma_address+1) & 0x7fff;
}
void myarc_hfdc_device::device_start()
{
if (TRACE_EMU) logerror("%s: start\n", tag());
m_dsrrom = memregion(DSRROM)->base();
m_buffer_ram = memregion(BUFFER)->base();
m_motor_on_timer = timer_alloc(MOTOR_TIMER);
// The HFDC does not use READY; it has on-board RAM for DMA
m_current_floppy = nullptr;
@ -877,8 +880,6 @@ void myarc_hfdc_device::device_start()
void myarc_hfdc_device::device_reset()
{
if (TRACE_EMU) logerror("%s: reset\n", tag());
// The GenMOD mod; our implementation automagically adapts all cards
if (m_genmod)
{
@ -914,17 +915,17 @@ void myarc_hfdc_device::device_reset()
for (int i=0; i < 4; i++)
{
if (m_floppy_unit[i] != nullptr)
logerror("%s: FD connector %d with %s\n", tag(), i+1, m_floppy_unit[i]->name());
logerror("FD connector %d with %s\n", i+1, m_floppy_unit[i]->name());
else
logerror("%s: FD connector %d has no floppy attached\n", tag(), i+1);
logerror("FD connector %d has no floppy attached\n", i+1);
}
for (int i=0; i < 3; i++)
{
if (m_harddisk_unit[i] != nullptr)
logerror("%s: HD connector %d with %s\n", tag(), i+1, m_harddisk_unit[i]->name());
logerror("HD connector %d with %s\n", i+1, m_harddisk_unit[i]->name());
else
logerror("%s: HD connector %d has no drive attached\n", tag(), i+1);
logerror("HD connector %d has no drive attached\n", i+1);
}
// Disconnect all units
@ -1053,13 +1054,15 @@ MACHINE_CONFIG_FRAGMENT( ti99_hfdc )
MCFG_DEVICE_ADD(CLOCK_TAG, MM58274C, 0)
MCFG_MM58274C_MODE24(1) // 24 hour
MCFG_MM58274C_DAY1(0) // sunday
MCFG_RAM_ADD(BUFFER)
MCFG_RAM_DEFAULT_SIZE("32K")
MCFG_RAM_DEFAULT_VALUE(0)
MACHINE_CONFIG_END
ROM_START( ti99_hfdc )
ROM_REGION(0x4000, DSRROM, 0)
ROM_LOAD("hfdc_dsr.u34", 0x0000, 0x4000, CRC(66fbe0ed) SHA1(11df2ecef51de6f543e4eaf8b2529d3e65d0bd59)) /* HFDC disk DSR ROM */
ROM_REGION(0x8000, BUFFER, 0) /* HFDC RAM buffer 32 KiB */
ROM_FILL(0x0000, 0x8000, 0x00)
ROM_END

3
src/devices/bus/ti99_peb/hfdc.h
View File

@ -21,6 +21,7 @@
#include "machine/mm58274c.h"
#include "machine/hdc92x4.h"
#include "machine/ram.h"
extern const device_type TI99_HFDC;
@ -149,7 +150,7 @@ private:
int m_rom_page;
// HFDC on-board SRAM (8K or 32K)
UINT8* m_buffer_ram;
required_device<ram_device> m_buffer_ram;
// RAM page registers
int m_ram_page[4];

31
src/devices/bus/ti99_peb/tn_ide.cpp
View File

@ -34,7 +34,7 @@
#define CRU_BASE 0x1000
#define BUFFER_TAG "ram"
#define RAMREGION "ram"
/* previously 0xff */
#define PAGE_MASK 0x3f
@ -52,8 +52,9 @@ enum
nouspikel_ide_interface_device::nouspikel_ide_interface_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ti_expansion_card_device(mconfig, TI99_IDE, "Nouspikel IDE interface card", tag, owner, clock, "ti99_ide", __FILE__), m_ata_irq(false),
m_cru_register(0), m_rtc(nullptr),
m_ata(*this, "ata"), m_clk_irq(false), m_sram_enable(false), m_sram_enable_dip(false), m_cur_page(0), m_tms9995_mode(false),
m_input_latch(0), m_output_latch(0), m_ram(nullptr)
m_ata(*this, "ata"), m_clk_irq(false), m_sram_enable(false),
m_sram_enable_dip(false), m_cur_page(0), m_tms9995_mode(false),
m_input_latch(0), m_output_latch(0), m_ram(*this, RAMREGION)
{
}
@ -180,9 +181,9 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz)
else
{ /* sram */
if ((m_cru_register & cru_reg_page_0) || (addr >= 0x1000))
reply = m_ram[addr+0x2000 * m_cur_page];
reply = m_ram->pointer()[addr+0x2000 * m_cur_page];
else
reply = m_ram[addr];
reply = m_ram->pointer()[addr];
}
*value = reply;
}
@ -267,9 +268,9 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::write)
if (! (m_cru_register & cru_reg_wp))
{
if ((m_cru_register & cru_reg_page_0) || (addr >= 0x1000))
m_ram[addr+0x2000 * m_cur_page] = data;
m_ram->pointer()[addr+0x2000 * m_cur_page] = data;
else
m_ram[addr] = data;
m_ram->pointer()[addr] = data;
}
}
}
@ -304,8 +305,6 @@ WRITE_LINE_MEMBER(nouspikel_ide_interface_device::clock_interrupt_callback)
void nouspikel_ide_interface_device::device_start()
{
m_rtc = subdevice<rtc65271_device>("ide_rtc");
m_ram = memregion(BUFFER_TAG)->base();
m_sram_enable_dip = false; // TODO: what is this?
}
@ -338,12 +337,11 @@ MACHINE_CONFIG_FRAGMENT( tn_ide )
MCFG_RTC65271_INTERRUPT_CB(WRITELINE(nouspikel_ide_interface_device, clock_interrupt_callback))
MCFG_ATA_INTERFACE_ADD( "ata", ata_devices, "hdd", nullptr, false)
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(nouspikel_ide_interface_device, ide_interrupt_callback))
MACHINE_CONFIG_END
ROM_START( tn_ide )
ROM_REGION(0x80000, BUFFER_TAG, 0) /* RAM buffer 512 KiB */
ROM_FILL(0x0000, 0x80000, 0x00)
ROM_END
MCFG_RAM_ADD(RAMREGION)
MCFG_RAM_DEFAULT_SIZE("512K")
MCFG_RAM_DEFAULT_VALUE(0)
MACHINE_CONFIG_END
INPUT_PORTS_START( tn_ide )
PORT_START( "CRUIDE" )
@ -371,11 +369,6 @@ machine_config_constructor nouspikel_ide_interface_device::device_mconfig_additi
return MACHINE_CONFIG_NAME( tn_ide );
}
const tiny_rom_entry *nouspikel_ide_interface_device::device_rom_region() const
{
return ROM_NAME( tn_ide );
}
ioport_constructor nouspikel_ide_interface_device::device_input_ports() const
{
return INPUT_PORTS_NAME(tn_ide);

4
src/devices/bus/ti99_peb/tn_ide.h
View File

@ -17,6 +17,7 @@
#include "emu.h"
#include "machine/ataintf.h"
#include "machine/rtc65271.h"
#include "machine/ram.h"
extern const device_type TI99_IDE;
@ -40,7 +41,6 @@ public:
protected:
virtual void device_start(void) override;
virtual void device_reset(void) override;
virtual const tiny_rom_entry *device_rom_region() const override;
virtual machine_config_constructor device_mconfig_additions() const override;
virtual ioport_constructor device_input_ports() const override;
@ -58,7 +58,7 @@ private:
UINT16 m_input_latch;
UINT16 m_output_latch;
UINT8 *m_ram;
required_device<ram_device> m_ram;
};
#endif

169
src/devices/bus/ti99x/genboard.cpp
View File

@ -206,12 +206,22 @@
#define TRACE_VIDEOWS 0
#define TRACE_PFM 0
#define SRAM_PAR_TAG ":sram"
#define DRAM_PAR_TAG ":dram"
geneve_mapper_device::geneve_mapper_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, GENEVE_MAPPER, "Geneve Gate Array", tag, owner, clock, "geneve_mapper", __FILE__), m_gromwaddr_LSB(false), m_gromraddr_LSB(false), m_grom_address(0), m_video_waitstates(false), m_extra_waitstates(false), m_ready_asserted(false), m_read_mode(false), m_debug_no_ws(false), m_geneve_mode(false), m_direct_mode(false), m_cartridge_size(0), m_cartridge_secondpage(false), m_cartridge6_writable(false), m_cartridge7_writable(false), m_turbo(false), m_genmod(false), m_timode(false), m_pfm_mode(0), m_pfm_bank(0), m_pfm_output_enable(false), m_sram_mask(0), m_sram_val(0),
: device_t(mconfig, GENEVE_MAPPER, "Geneve Gate Array", tag, owner, clock, "geneve_mapper", __FILE__), m_gromwaddr_LSB(false),
m_gromraddr_LSB(false), m_grom_address(0), m_video_waitstates(false),
m_extra_waitstates(false), m_ready_asserted(false), m_read_mode(false),
m_debug_no_ws(false), m_geneve_mode(false), m_direct_mode(false),
m_cartridge_size(0), m_cartridge_secondpage(false),
m_cartridge6_writable(false), m_cartridge7_writable(false),
m_turbo(false), m_genmod(false), m_timode(false), m_pfm_mode(0),
m_pfm_bank(0), m_pfm_output_enable(false), m_sram_mask(0), m_sram_val(0),
m_ready(*this), m_waitcount(0), m_ext_waitcount(0),
m_clock(nullptr), m_cpu(nullptr), m_pfm512(nullptr),
m_pfm512a(nullptr), m_sound(nullptr), m_keyboard(nullptr),
m_video(nullptr), m_peribox(nullptr), m_sram(nullptr), m_dram(nullptr)
m_video(nullptr), m_peribox(nullptr), m_sram(*this, SRAM_PAR_TAG), m_dram(*this, DRAM_PAR_TAG)
{
m_eprom = nullptr;
}
@ -225,12 +235,12 @@ INPUT_CHANGED_MEMBER( geneve_mapper_device::settings_changed )
{
case 1:
// Turbo switch. May be changed at any time.
if (TRACE_SETTING) logerror("%s: Setting turbo flag to %d\n", tag(), value);
if (TRACE_SETTING) logerror("Setting turbo flag to %d\n", value);
m_turbo = (value!=0);
break;
case 2:
// TIMode switch. Causes reset when changed.
if (TRACE_SETTING) logerror("%s: Setting timode flag to %d\n", tag(), value);
if (TRACE_SETTING) logerror("Setting timode flag to %d\n", value);
m_timode = (value!=0);
machine().schedule_hard_reset();
break;
@ -239,7 +249,7 @@ INPUT_CHANGED_MEMBER( geneve_mapper_device::settings_changed )
set_boot_rom(value);
break;
default:
logerror("%s: Unknown setting %d ignored\n", tag(), number);
logerror("Unknown setting %d ignored\n", number);
}
}
@ -277,7 +287,7 @@ READ8_MEMBER( geneve_mapper_device::read_grom )
// GROM data handling
// GROMs are stored in pages 38..3f
int page = 0x38;
reply = m_dram[(page<<13) + m_grom_address];
reply = m_dram->pointer()[(page<<13) + m_grom_address];
m_grom_address = (m_grom_address + 1) & 0xffff;
m_gromraddr_LSB = m_gromwaddr_LSB = false;
}
@ -310,7 +320,7 @@ WRITE8_MEMBER( geneve_mapper_device::write_grom )
{ // write GPL data
// The Geneve GROM simulator allows for GROM writing (verified with a real system)
int page = 0x38;
m_dram[(page<<13) + m_grom_address] = data;
m_dram->pointer()[(page<<13) + m_grom_address] = data;
m_grom_address = (m_grom_address + 1) & 0xffff;
m_gromraddr_LSB = m_gromwaddr_LSB = false;
@ -330,7 +340,7 @@ void geneve_mapper_device::set_wait(int min)
m_waitcount = min + 1;
if (m_waitcount > 1)
{
if (TRACE_LINES) logerror("%s: Pulling down READY line for %d cycles\n", tag(), min);
if (TRACE_LINES) logerror("Pulling down READY line for %d cycles\n", min);
m_ready(CLEAR_LINE);
m_ready_asserted = false;
}
@ -347,62 +357,62 @@ void geneve_mapper_device::set_boot_rom(int selection)
switch (selection)
{
case GENEVE_098:
logerror("%s: Using 0.98 boot eprom\n", tag());
logerror("Using 0.98 boot eprom\n");
m_eprom = machine().root_device().memregion("maincpu")->base() + 0x4000;
m_pfm_mode = 0;
break;
case GENEVE_100:
logerror("%s: Using 1.00 boot eprom\n", tag());
logerror("Using 1.00 boot eprom\n");
m_eprom = machine().root_device().memregion("maincpu")->base();
m_pfm_mode = 0;
break;
case GENEVE_PFM512:
logerror("%s: Using PFM512 (AT29C040)\n", tag());
logerror("Using PFM512 (AT29C040)\n");
m_pfm_mode = 1;
break;
case GENEVE_PFM512A:
logerror("%s: Using PFM512A (AT29C040A)\n", tag());
logerror("Using PFM512A (AT29C040A)\n");
m_pfm_mode = 2;
break;
default:
logerror("%s: Unknown boot ROM selection\n", tag());
logerror("Unknown boot ROM selection\n");
}
}
void geneve_mapper_device::set_geneve_mode(bool geneve)
{
if (TRACE_SETTING) logerror("%s: Setting Geneve mode = %d\n", tag(), geneve);
if (TRACE_SETTING) logerror("Setting Geneve mode = %d\n", geneve);
m_geneve_mode = geneve;
}
void geneve_mapper_device::set_direct_mode(bool direct)
{
if (TRACE_SETTING) logerror("%s: Setting direct mode = %d\n", tag(), direct);
if (TRACE_SETTING) logerror("Setting direct mode = %d\n", direct);
m_direct_mode = direct;
}
void geneve_mapper_device::set_cartridge_size(int size)
{
if (TRACE_SETTING) logerror("%s: Setting cartridge size to %d\n", tag(), size);
if (TRACE_SETTING) logerror("Setting cartridge size to %d\n", size);
m_cartridge_size = size;
}
void geneve_mapper_device::set_cartridge_writable(int base, bool write)
{
if (TRACE_SETTING) logerror("%s: Cartridge %04x space writable = %d\n", tag(), base, write);
if (TRACE_SETTING) logerror("Cartridge %04x space writable = %d\n", base, write);
if (base==0x6000) m_cartridge6_writable = write;
else m_cartridge7_writable = write;
}
void geneve_mapper_device::set_video_waitstates(bool wait)
{
if (TRACE_VIDEOWS) logerror("%s: Setting video waitstates = %d\n", tag(), wait);
if (TRACE_VIDEOWS) logerror("Setting video waitstates = %d\n", wait);
m_video_waitstates = wait;
}
void geneve_mapper_device::set_extra_waitstates(bool wait)
{
if (TRACE_SETTING) logerror("%s: Setting extra waitstates = %d\n", tag(), wait);
if (TRACE_SETTING) logerror("Setting extra waitstates = %d\n", wait);
m_extra_waitstates = wait;
}
@ -473,7 +483,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
if (!space.debugger_access())
{
value = m_video->read(space, dec->offset>>1);
if (TRACE_READ) logerror("%s: Read video %04x -> %02x\n", tag(), dec->offset, value);
if (TRACE_READ) logerror("Read video %04x -> %02x\n", dec->offset, value);
// Video wait states are created *after* the access
// Accordingly, they have no effect when execution is in onchip RAM
if (m_video_waitstates) set_ext_wait(15);
@ -483,13 +493,13 @@ READ8_MEMBER( geneve_mapper_device::readm )
case MLGMAPPER:
// mapper
value = m_map[dec->offset];
if (TRACE_READ) logerror("%s: read mapper %04x -> %02x\n", tag(), dec->offset, value);
if (TRACE_READ) logerror("read mapper %04x -> %02x\n", dec->offset, value);
break;
case MLGKEY:
// key
if (!space.debugger_access()) value = m_keyboard->get_recent_key();
if (TRACE_READ) logerror("%s: Read keyboard -> %02x\n", tag(), value);
if (TRACE_READ) logerror("Read keyboard -> %02x\n", value);
break;
case MLGCLOCK:
@ -497,19 +507,19 @@ READ8_MEMBER( geneve_mapper_device::readm )
// tests on the real machine showed that
// upper nibble is 0xf (probably because of the location at 0xf130?)
value = m_clock->read(space, dec->offset) | 0xf0;
if (TRACE_READ) logerror("%s: Read clock %04x -> %02x\n", tag(), dec->offset, value);
if (TRACE_READ) logerror("Read clock %04x -> %02x\n", dec->offset, value);
break;
case MLTMAPPER:
// mapper
value = m_map[dec->offset];
if (TRACE_READ) logerror("%s: Read mapper %04x -> %02x\n", tag(), dec->offset, value);
if (TRACE_READ) logerror("Read mapper %04x -> %02x\n", dec->offset, value);
break;
case MLTKEY:
// key
if (!space.debugger_access()) value = m_keyboard->get_recent_key();
if (TRACE_READ) logerror("%s: Read keyboard -> %02x\n", tag(), value);
if (TRACE_READ) logerror("Read keyboard -> %02x\n", value);
break;
case MLTCLOCK:
@ -523,7 +533,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
// value floating around.
value = m_clock->read(space, dec->offset);
value |= (dec->offset==0x000f)? 0x20 : 0x10;
if (TRACE_READ) logerror("%s: Read clock %04x -> %02x\n", tag(), dec->offset, value);
if (TRACE_READ) logerror("Read clock %04x -> %02x\n", dec->offset, value);
break;
case MLTVIDEO:
@ -533,7 +543,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
if (!space.debugger_access())
{
value = m_video->read(space, dec->offset>>1);
if (TRACE_READ) logerror("%s: Read video %04x -> %02x\n", tag(), dec->offset, value);
if (TRACE_READ) logerror("Read video %04x -> %02x\n", dec->offset, value);
// See above
if (m_video_waitstates) set_ext_wait(15);
}
@ -546,7 +556,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
// We need to add the address prefix bits
m_peribox->readz(space, dec->offset, &value, 0xff);
m_peribox->memen_in(CLEAR_LINE);
if (TRACE_READ) logerror("%s: Read speech -> %02x\n", tag(), value);
if (TRACE_READ) logerror("Read speech -> %02x\n", value);
break;
case MLTGROM:
@ -554,7 +564,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
// ++++ ++-- ---- ---+
// 1001 1000 0000 00x0
if (!space.debugger_access()) value = read_grom(space, dec->offset, 0xff);
if (TRACE_READ) logerror("%s: Read GROM %04x -> %02x\n", tag(), dec->offset, value);
if (TRACE_READ) logerror("Read GROM %04x -> %02x\n", dec->offset, value);
break;
case MLGSOUND:
@ -565,14 +575,14 @@ READ8_MEMBER( geneve_mapper_device::readm )
case MPGDRAM:
// DRAM.
value = m_dram[dec->physaddr];
value = m_dram->pointer()[dec->physaddr];
// LOG("dram read physaddr = %06x logaddr = %04x value = %02x\n", dec->physaddr, dec->offset, value);
if (TRACE_READ) logerror("%s: Read DRAM %04x (%06x) -> %02x\n", tag(), dec->offset, dec->physaddr, value);
if (TRACE_READ) logerror("Read DRAM %04x (%06x) -> %02x\n", dec->offset, dec->physaddr, value);
break;
case MPGEXP:
// On-board memory expansion for standard Geneve (never used)
if (TRACE_READ) logerror("%s: Read unmapped area %06x\n", tag(), dec->physaddr);
if (TRACE_READ) logerror("Read unmapped area %06x\n", dec->physaddr);
value = 0;
break;
@ -582,7 +592,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
if (m_pfm_mode == 0)
{
value = m_eprom[dec->physaddr & 0x003fff];
if (TRACE_READ) logerror("%s: Read EPROM %04x (%06x) -> %02x\n", tag(), dec->offset, dec->physaddr, value);
if (TRACE_READ) logerror("Read EPROM %04x (%06x) -> %02x\n", dec->offset, dec->physaddr, value);
}
else value = read_from_pfm(space, dec->physaddr, 0xff);
@ -591,12 +601,12 @@ READ8_MEMBER( geneve_mapper_device::readm )
case MPGSRAM:
if ((dec->physaddr & m_sram_mask)==m_sram_val)
{
value = m_sram[dec->physaddr & ~m_sram_mask];
value = m_sram->pointer()[dec->physaddr & ~m_sram_mask];
}
else value = 0;
// Return in any case
// LOG("sram read physaddr = %06x logaddr = %04x value = %02x\n", dec->physaddr, dec->offset, value);
if (TRACE_READ) logerror("%s: Read SRAM %04x (%06x) -> %02x\n", tag(), dec->offset, dec->physaddr, value);
if (TRACE_READ) logerror("Read SRAM %04x (%06x) -> %02x\n", dec->offset, dec->physaddr, value);
break;
case MPGBOX:
@ -606,12 +616,12 @@ READ8_MEMBER( geneve_mapper_device::readm )
m_peribox->readz(space, dec->physaddr, &value, 0xff);
m_peribox->memen_in(CLEAR_LINE);
if (TRACE_READ) logerror("%s: Read P-Box %04x (%06x) -> %02x\n", tag(), dec->offset, dec->physaddr, value);
if (TRACE_READ) logerror("Read P-Box %04x (%06x) -> %02x\n", dec->offset, dec->physaddr, value);
break;
case MPGMDRAM:
// DRAM. One wait state.
value = m_dram[dec->physaddr];
value = m_dram->pointer()[dec->physaddr];
break;
case MPGMEPROM:
@ -620,7 +630,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
if (m_pfm_mode == 0)
{
value = m_eprom[dec->physaddr & 0x003fff];
if (TRACE_READ) logerror("%s: Read EPROM %04x (%06x) -> %02x\n", tag(), dec->offset, dec->physaddr, value);
if (TRACE_READ) logerror("Read EPROM %04x (%06x) -> %02x\n", dec->offset, dec->physaddr, value);
}
else value = read_from_pfm(space, dec->physaddr, 0xff);
break;
@ -663,7 +673,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
if (!space.debugger_access())
{
m_video->write(space, dec->offset>>1, data);
if (TRACE_WRITE) logerror("%s: Write video %04x <- %02x\n", tag(), offset, data);
if (TRACE_WRITE) logerror("Write video %04x <- %02x\n", offset, data);
// See above
if (m_video_waitstates) set_ext_wait(15);
}
@ -672,33 +682,33 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
case MLGMAPPER:
// mapper
m_map[dec->offset] = data;
if (TRACE_WRITE) logerror("%s: Write mapper %04x <- %02x\n", tag(), offset, data);
if (TRACE_WRITE) logerror("Write mapper %04x <- %02x\n", offset, data);
break;
case MLGCLOCK:
// clock
// ++++ ++++ ++++ ----
m_clock->write(space, dec->offset, data);
if (TRACE_WRITE) logerror("%s: Write clock %04x <- %02x\n", tag(), offset, data);
if (TRACE_WRITE) logerror("Write clock %04x <- %02x\n", offset, data);
break;
case MLGSOUND:
// sound
// ++++ ++++ ++++ ---+
m_sound->write(space, 0, data, 0xff);
if (TRACE_WRITE) logerror("%s: Write sound <- %02x\n", tag(), data);
if (TRACE_WRITE) logerror("Write sound <- %02x\n", data);
break;
case MLTMAPPER:
// mapper
m_map[dec->offset] = data;
if (TRACE_WRITE) logerror("%s: Write mapper %04x <- %02x\n", tag(), offset, data);
if (TRACE_WRITE) logerror("Write mapper %04x <- %02x\n", offset, data);
break;
case MLTCLOCK:
// clock
m_clock->write(space, dec->offset, data);
if (TRACE_WRITE) logerror("%s: Write clock %04x <- %02x\n", tag(), offset, data);
if (TRACE_WRITE) logerror("Write clock %04x <- %02x\n", offset, data);
break;
case MLTVIDEO:
@ -709,7 +719,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
if (!space.debugger_access())
{
m_video->write(space, dec->offset>>1, data);
if (TRACE_WRITE) logerror("%s: Write video %04x <- %02x\n", tag(), offset, data);
if (TRACE_WRITE) logerror("Write video %04x <- %02x\n", offset, data);
// See above
if (m_video_waitstates) set_ext_wait(15);
}
@ -722,7 +732,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
// We need to add the address prefix bits
m_peribox->write(space, dec->offset, data, 0xff);
m_peribox->memen_in(CLEAR_LINE);
if (TRACE_WRITE) logerror("%s: Write speech <- %02x\n", tag(), data);
if (TRACE_WRITE) logerror("Write speech <- %02x\n", data);
break;
case MLTGROM:
@ -730,7 +740,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
// ++++ ++-- ---- ---+
// 1001 1100 0000 00c0
write_grom(space, dec->offset, data, 0xff);
if (TRACE_WRITE) logerror("%s: Write GROM %04x <- %02x\n", tag(), offset, data);
if (TRACE_WRITE) logerror("Write GROM %04x <- %02x\n", offset, data);
break;
case MLTSOUND:
@ -738,7 +748,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
// ++++ ++-- ---- ---+
// 1000 0100 0000 0000
m_sound->write(space, 0, data, 0xff);
if (TRACE_WRITE) logerror("%s: Write sound <- %02x\n", tag(), data);
if (TRACE_WRITE) logerror("Write sound <- %02x\n", data);
break;
case MLTKEY:
@ -747,13 +757,13 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
case MPGDRAM:
// DRAM write. One wait state. (only for normal Geneve)
m_dram[dec->physaddr] = data;
if (TRACE_WRITE) logerror("%s: Write DRAM %04x (%06x) <- %02x\n", tag(), offset, dec->physaddr, data);
m_dram->pointer()[dec->physaddr] = data;
if (TRACE_WRITE) logerror("Write DRAM %04x (%06x) <- %02x\n", offset, dec->physaddr, data);
break;
case MPGEXP:
// On-board memory expansion for standard Geneve (never used)
if (TRACE_WRITE) logerror("%s: Write unmapped area %06x\n", tag(), dec->physaddr);
if (TRACE_WRITE) logerror("Write unmapped area %06x\n", dec->physaddr);
break;
case MPGEPROM:
@ -762,27 +772,27 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
// Ignore EPROM write (unless PFM)
if (m_pfm_mode != 0) write_to_pfm(space, dec->physaddr, data, 0xff);
else
logerror("%s: Write EPROM %04x (%06x) <- %02x, ignored\n", tag(), offset, dec->physaddr, data);
logerror("Write EPROM %04x (%06x) <- %02x, ignored\n", offset, dec->physaddr, data);
break;
case MPGSRAM:
if ((dec->physaddr & m_sram_mask)==m_sram_val)
{
m_sram[dec->physaddr & ~m_sram_mask] = data;
m_sram->pointer()[dec->physaddr & ~m_sram_mask] = data;
}
if (TRACE_WRITE) logerror("%s: Write SRAM %04x (%06x) <- %02x\n", tag(), offset, dec->physaddr, data);
if (TRACE_WRITE) logerror("Write SRAM %04x (%06x) <- %02x\n", offset, dec->physaddr, data);
break;
case MPGBOX:
dec->physaddr = (dec->physaddr & 0x0007ffff); // 19 bit address
if (TRACE_WRITE) logerror("%s: Write P-Box %04x (%06x) <- %02x\n", tag(), offset, dec->physaddr, data);
if (TRACE_WRITE) logerror("Write P-Box %04x (%06x) <- %02x\n", offset, dec->physaddr, data);
m_peribox->write(space, dec->physaddr, data, 0xff);
m_peribox->memen_in(CLEAR_LINE);
break;
case MPGMDRAM:
// DRAM. One wait state.
m_dram[dec->physaddr] = data;
m_dram->pointer()[dec->physaddr] = data;
break;
case MPGMEPROM:
@ -791,7 +801,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
// Ignore EPROM write
if (m_pfm_mode != 0) write_to_pfm(space, dec->physaddr, data, 0xff);
else
logerror("%s: Write EPROM %04x (%06x) <- %02x, ignored\n", tag(), offset, dec->physaddr, data);
logerror("Write EPROM %04x (%06x) <- %02x, ignored\n", offset, dec->physaddr, data);
break;
case MPGMBOX:
@ -1119,7 +1129,7 @@ void geneve_mapper_device::decode(address_space& space, offs_t offset, bool read
if (m_cartridge_size==0x4000)
{
m_cartridge_secondpage = ((dec->offset & 0x0002)!=0);
if (TRACE_WRITE) logerror("%s: Set cartridge page %02x\n", tag(), m_cartridge_secondpage);
if (TRACE_WRITE) logerror("Set cartridge page %02x\n", m_cartridge_secondpage);
set_wait(1);
return;
}
@ -1129,7 +1139,7 @@ void geneve_mapper_device::decode(address_space& space, offs_t offset, bool read
if ((((dec->offset & 0x1000)==0x0000) && !m_cartridge6_writable)
|| (((dec->offset & 0x1000)==0x1000) && !m_cartridge7_writable))
{
logerror("%s: Writing to protected cartridge space %04x ignored\n", tag(), dec->offset);
logerror("Writing to protected cartridge space %04x ignored\n", dec->offset);
return;
}
else
@ -1229,11 +1239,11 @@ READ8_MEMBER( geneve_mapper_device::read_from_pfm )
value = m_pfm512a->read(space, address, mem_mask);
break;
default:
logerror("%s: Illegal mode for reading PFM: %d\n", tag(), m_pfm_mode);
logerror("Illegal mode for reading PFM: %d\n", m_pfm_mode);
return 0;
}
if (TRACE_PFM) logerror("%s: Reading from PFM at address %05x -> %02x\n", tag(), address, value);
if (TRACE_PFM) logerror("Reading from PFM at address %05x -> %02x\n", address, value);
return value;
}
@ -1242,7 +1252,7 @@ WRITE8_MEMBER( geneve_mapper_device::write_to_pfm )
// Nota bene: The PFM must be write protected on startup, or the RESET
// of the 9995 will attempt to write the return vector into the flash EEPROM
int address = (offset & 0x01ffff) | (m_pfm_bank<<17);
if (TRACE_PFM) logerror("%s: Writing to PFM at address %05x <- %02x\n", tag(), address, data);
if (TRACE_PFM) logerror("Writing to PFM at address %05x <- %02x\n", address, data);
switch (m_pfm_mode)
{
@ -1253,7 +1263,7 @@ WRITE8_MEMBER( geneve_mapper_device::write_to_pfm )
m_pfm512a->write(space, address, data, mem_mask);
break;
default:
logerror("%s: Illegal mode for writing to PFM: %d\n", tag(), m_pfm_mode);
logerror("Illegal mode for writing to PFM: %d\n", m_pfm_mode);
}
}
@ -1265,7 +1275,7 @@ WRITE8_MEMBER( geneve_mapper_device::write_to_pfm )
*/
SETOFFSET_MEMBER( geneve_mapper_device::setoffset )
{
if (TRACE_DETAIL) logerror("%s: setoffset = %04x\n", tag(), offset);
if (TRACE_DETAIL) logerror("setoffset = %04x\n", offset);
m_debug_no_ws = false;
decode(space, offset, m_read_mode, &m_decoded);
}
@ -1294,13 +1304,13 @@ WRITE_LINE_MEMBER( geneve_mapper_device::clock_in )
m_waitcount--;
if (m_waitcount == 0)
{
if (TRACE_CLOCK) logerror("%s: clock, READY asserted\n", tag());
if (TRACE_CLOCK) logerror("clock, READY asserted\n");
m_ready(ASSERT_LINE);
m_ready_asserted = true;
}
else
{
if (TRACE_CLOCK) logerror("%s: clock\n", tag());
if (TRACE_CLOCK) logerror("clock\n");
}
}
else
@ -1310,13 +1320,13 @@ WRITE_LINE_MEMBER( geneve_mapper_device::clock_in )
m_ext_waitcount--;
if (m_ext_waitcount == 0)
{
if (TRACE_CLOCK) logerror("%s: clock, READY asserted after video\n", tag());
if (TRACE_CLOCK) logerror("clock, READY asserted after video\n");
m_ready(ASSERT_LINE);
m_ready_asserted = true;
}
else
{
if (TRACE_CLOCK) logerror("%s: vclock, ew=%d\n", tag(), m_ext_waitcount);
if (TRACE_CLOCK) logerror("vclock, ew=%d\n", m_ext_waitcount);
}
}
}
@ -1328,7 +1338,7 @@ WRITE_LINE_MEMBER( geneve_mapper_device::clock_in )
// Do we have video wait states? In that case, clear the line again
if ((m_waitcount == 0) && (m_ext_waitcount > 0) && m_ready_asserted)
{
if (TRACE_CLOCK) logerror("%s: clock, READY cleared for video\n", tag());
if (TRACE_CLOCK) logerror("clock, READY cleared for video\n");
m_ready(CLEAR_LINE);
m_ready_asserted = false;
}
@ -1341,7 +1351,7 @@ WRITE_LINE_MEMBER( geneve_mapper_device::clock_in )
WRITE_LINE_MEMBER( geneve_mapper_device::dbin_in )
{
m_read_mode = (state==ASSERT_LINE);
if (TRACE_DETAIL) logerror("%s: dbin = %02x\n", tag(), m_read_mode? 1:0);
if (TRACE_DETAIL) logerror("dbin = %02x\n", m_read_mode? 1:0);
}
/*
@ -1351,21 +1361,21 @@ WRITE_LINE_MEMBER( geneve_mapper_device::pfm_select_lsb )
{
if (state==ASSERT_LINE) m_pfm_bank |= 1;
else m_pfm_bank &= 0xfe;
if (TRACE_PFM) logerror("%s: Setting bank (l) = %d\n", tag(), m_pfm_bank);
if (TRACE_PFM) logerror("Setting bank (l) = %d\n", m_pfm_bank);
}
WRITE_LINE_MEMBER( geneve_mapper_device::pfm_select_msb )
{
if (state==ASSERT_LINE) m_pfm_bank |= 2;
else m_pfm_bank &= 0xfd;
if (TRACE_PFM) logerror("%s: Setting bank (u) = %d\n", tag(), m_pfm_bank);
if (TRACE_PFM) logerror("Setting bank (u) = %d\n", m_pfm_bank);
}
WRITE_LINE_MEMBER( geneve_mapper_device::pfm_output_enable )
{
// Negative logic
m_pfm_output_enable = (state==CLEAR_LINE);
if (TRACE_PFM) logerror("%s: PFM output %s\n", tag(), m_pfm_output_enable? "enable" : "disable");
if (TRACE_PFM) logerror("PFM output %s\n", m_pfm_output_enable? "enable" : "disable");
}
//====================================================================
@ -1386,9 +1396,6 @@ void geneve_mapper_device::device_start()
m_pfm512a = machine().device<at29c040a_device>(PFM512A_TAG);
m_ready.resolve();
m_sram = machine().root_device().memregion(SRAM_TAG)->base();
m_dram = machine().root_device().memregion(DRAM_TAG)->base();
m_cpu = static_cast<tms9995_device*>(machine().device("maincpu"));
m_geneve_mode = false;
@ -1425,7 +1432,7 @@ void geneve_mapper_device::device_reset()
// Check for GenMod. We assume that GenMod can be combined with PFM.
if (machine().root_device().ioport("MODE")->read()!=0)
{
logerror("%s: Using GenMod modification\n", tag());
logerror("Using GenMod modification\n");
m_eprom = machine().root_device().memregion("maincpu")->base() + 0x8000;
if (m_eprom[0] != 0xf0)
{
@ -1508,7 +1515,7 @@ void geneve_keyboard_device::post_in_key_queue(int keycode)
m_key_queue[(m_key_queue_head + m_key_queue_length) % KEYQUEUESIZE] = keycode;
m_key_queue_length++;
if (TRACE_KEYBOARD) logerror("%s: Posting keycode %02x\n", tag(), keycode);
if (TRACE_KEYBOARD) logerror("Posting keycode %02x\n", keycode);
}
void geneve_keyboard_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
@ -1523,7 +1530,7 @@ void geneve_keyboard_device::poll()
int i, j;
int keycode;
int pressed;
if (TRACE_KEYBOARD) logerror("%s: Poll keyboard\n", tag());
if (TRACE_KEYBOARD) logerror("Poll keyboard\n");
if (m_key_reset) return;
/* Poll keyboard */
@ -1729,7 +1736,7 @@ void geneve_keyboard_device::signal_when_key_available()
// buffer clear is disabled, and key queue is not empty. */
if ((!m_key_reset) && (m_keyboard_clock) && (m_keep_keybuf) && (m_key_queue_length != 0))
{
if (TRACE_KEYBOARD) logerror("%s: Signalling key available\n", tag());
if (TRACE_KEYBOARD) logerror("Signalling key available\n");
m_interrupt(ASSERT_LINE);
m_key_in_buffer = true;
}
@ -1739,7 +1746,7 @@ WRITE_LINE_MEMBER( geneve_keyboard_device::clock_control )
{
bool rising_edge = (!m_keyboard_clock && (state==ASSERT_LINE));
m_keyboard_clock = (state==ASSERT_LINE);
if (TRACE_KEYBOARD) logerror("%s: Keyboard clock_control state=%d\n", tag(), m_keyboard_clock);
if (TRACE_KEYBOARD) logerror("Keyboard clock_control state=%d\n", m_keyboard_clock);
if (rising_edge)
signal_when_key_available();
}

5
src/devices/bus/ti99x/genboard.h
View File

@ -21,6 +21,7 @@
#include "machine/at29x.h"
#include "bus/ti99_peb/peribox.h"
#include "sound/sn76496.h"
#include "machine/ram.h"
extern const device_type GENEVE_MOUSE;
extern const device_type GENEVE_KEYBOARD;
@ -212,8 +213,8 @@ private:
v9938_device* m_video;
peribox_device* m_peribox;
UINT8* m_eprom;
UINT8* m_sram;
UINT8* m_dram;
required_device<ram_device> m_sram;
required_device<ram_device> m_dram;
};
#define MCFG_GENEVE_READY_HANDLER( _intcallb ) \

66
src/devices/imagedev/mfmhd.cpp
View File

@ -406,7 +406,7 @@ image_init_result mfm_harddisk_device::call_load()
if (chdfile==nullptr)
{
logerror("%s: chdfile is null\n", tag());
logerror("chdfile is null\n");
return image_init_result::FAIL;
}
@ -414,24 +414,24 @@ image_init_result mfm_harddisk_device::call_load()
chd_error state = chdfile->read_metadata(HARD_DISK_METADATA_TAG, 0, metadata);
if (state != CHDERR_NONE)
{
logerror("%s: Failed to read CHD metadata\n", tag());
logerror("Failed to read CHD metadata\n");
return image_init_result::FAIL;
}
if (TRACE_CONFIG) logerror("%s: CHD metadata: %s\n", tag(), metadata.c_str());
if (TRACE_CONFIG) logerror("CHD metadata: %s\n", metadata.c_str());
// Parse the metadata
mfmhd_layout_params param;
param.encoding = m_encoding;
if (TRACE_CONFIG) logerror("%s: Set encoding to %d\n", tag(), m_encoding);
if (TRACE_CONFIG) logerror("Set encoding to %d\n", m_encoding);
if (sscanf(metadata.c_str(), HARD_DISK_METADATA_FORMAT, &param.cylinders, &param.heads, &param.sectors_per_track, &param.sector_size) != 4)
{
logerror("%s: Invalid CHD metadata\n", tag());
logerror("Invalid CHD metadata\n");
return image_init_result::FAIL;
}
if (TRACE_CONFIG) logerror("%s: CHD image has geometry cyl=%d, head=%d, sect=%d, size=%d\n", tag(), param.cylinders, param.heads, param.sectors_per_track, param.sector_size);
if (TRACE_CONFIG) logerror("CHD image has geometry cyl=%d, head=%d, sect=%d, size=%d\n", param.cylinders, param.heads, param.sectors_per_track, param.sector_size);
if (m_max_cylinders != 0 && (param.cylinders != m_max_cylinders || param.heads != m_max_heads))
{
@ -448,7 +448,7 @@ image_init_result mfm_harddisk_device::call_load()
state = chdfile->read_metadata(MFM_HARD_DISK_METADATA_TAG, 0, metadata);
if (state != CHDERR_NONE)
{
logerror("%s: Failed to read CHD sector arrangement/recording specs, applying defaults\n", tag());
logerror("Failed to read CHD sector arrangement/recording specs, applying defaults\n");
}
else
{
@ -457,17 +457,17 @@ image_init_result mfm_harddisk_device::call_load()
if (!param.sane_rec())
{
if (TRACE_CONFIG) logerror("%s: Sector arrangement/recording specs have invalid values, applying defaults\n", tag());
if (TRACE_CONFIG) logerror("Sector arrangement/recording specs have invalid values, applying defaults\n");
param.reset_rec();
}
else
if (TRACE_CONFIG) logerror("%s: MFM HD rec specs: interleave=%d, cylskew=%d, headskew=%d, wpcom=%d, rwc=%d\n",
if (TRACE_CONFIG) logerror("MFM HD rec specs: interleave=%d, cylskew=%d, headskew=%d, wpcom=%d, rwc=%d\n",
tag(), param.interleave, param.cylskew, param.headskew, param.write_precomp_cylinder, param.reduced_wcurr_cylinder);
state = chdfile->read_metadata(MFM_HARD_DISK_METADATA_TAG, 1, metadata);
if (state != CHDERR_NONE)
{
logerror("%s: Failed to read CHD track gap specs, applying defaults\n", tag());
logerror("Failed to read CHD track gap specs, applying defaults\n");
}
else
{
@ -476,11 +476,11 @@ image_init_result mfm_harddisk_device::call_load()
if (!param.sane_gap())
{
if (TRACE_CONFIG) logerror("%s: MFM HD gap specs have invalid values, applying defaults\n", tag());
if (TRACE_CONFIG) logerror("MFM HD gap specs have invalid values, applying defaults\n");
param.reset_gap();
}
else
if (TRACE_CONFIG) logerror("%s: MFM HD gap specs: gap1=%d, gap2=%d, gap3=%d, sync=%d, headerlen=%d, ecctype=%d\n",
if (TRACE_CONFIG) logerror("MFM HD gap specs: gap1=%d, gap2=%d, gap3=%d, sync=%d, headerlen=%d, ecctype=%d\n",
tag(), param.gap1, param.gap2, param.gap3, param.sync, param.headerlen, param.ecctype);
m_format->set_layout_params(param);
@ -501,7 +501,7 @@ image_init_result mfm_harddisk_device::call_load()
float realmax = (m_maxseek_time==0)? (m_actual_cylinders * 0.2) : (m_maxseek_time * 0.8);
float settle_us = ((m_actual_cylinders-1.0) * realnext - realmax) / (m_actual_cylinders-2.0) * 1000;
float step_us = realnext * 1000 - settle_us;
if (TRACE_CONFIG) logerror("%s: Calculated settle time: %0.2f ms, step: %d us\n", tag(), settle_us/1000, (int)step_us);
if (TRACE_CONFIG) logerror("Calculated settle time: %0.2f ms, step: %d us\n", settle_us/1000, (int)step_us);
m_settle_time = attotime::from_usec((int)settle_us);
m_step_time = attotime::from_usec((int)step_us);
@ -510,7 +510,7 @@ image_init_result mfm_harddisk_device::call_load()
}
else
{
logerror("%s: Could not load CHD\n", tag());
logerror("Could not load CHD\n");
}
return loaded;
}
@ -529,25 +529,25 @@ void mfm_harddisk_device::call_unload()
if (m_format->save_param(MFMHD_IL) && !params->equals_rec(oldparams))
{
logerror("%s: MFM HD sector arrangement and recording specs have changed; updating CHD metadata\n", tag());
logerror("MFM HD sector arrangement and recording specs have changed; updating CHD metadata\n");
chd_file* chdfile = get_chd_file();
chd_error err = chdfile->write_metadata(MFM_HARD_DISK_METADATA_TAG, 0, string_format(MFMHD_REC_METADATA_FORMAT, params->interleave, params->cylskew, params->headskew, params->write_precomp_cylinder, params->reduced_wcurr_cylinder), 0);
if (err != CHDERR_NONE)
{
logerror("%s: Failed to save MFM HD sector arrangement/recording specs to CHD\n", tag());
logerror("Failed to save MFM HD sector arrangement/recording specs to CHD\n");
}
}
if (m_format->save_param(MFMHD_GAP1) && !params->equals_gap(oldparams))
{
logerror("%s: MFM HD track gap specs have changed; updating CHD metadata\n", tag());
logerror("MFM HD track gap specs have changed; updating CHD metadata\n");
chd_file* chdfile = get_chd_file();
chd_error err = chdfile->write_metadata(MFM_HARD_DISK_METADATA_TAG, 1, string_format(MFMHD_GAP_METADATA_FORMAT, params->gap1, params->gap2, params->gap3, params->sync, params->headerlen, params->ecctype), 0);
if (err != CHDERR_NONE)
{
logerror("%s: Failed to save MFM HD track gap specs to CHD\n", tag());
logerror("Failed to save MFM HD track gap specs to CHD\n");
}
}
}
@ -586,7 +586,7 @@ attotime mfm_harddisk_device::track_end_time()
if (!m_revolution_start_time.is_never())
{
endtime = m_revolution_start_time + nexttime;
if (TRACE_TIMING) logerror("%s: Track start time = %s, end time = %s\n", tag(), tts(m_revolution_start_time).c_str(), tts(endtime).c_str());
if (TRACE_TIMING) logerror("Track start time = %s, end time = %s\n", tts(m_revolution_start_time).c_str(), tts(endtime).c_str());
}
return endtime;
}
@ -628,7 +628,7 @@ void mfm_harddisk_device::device_timer(emu_timer &timer, device_timer_id id, int
// Start the settle timer
m_step_phase = STEP_SETTLE;
m_seek_timer->adjust(m_settle_time);
if (TRACE_STEPS && TRACE_DETAIL) logerror("%s: Arrived at target cylinder %d, settling ...\n", tag(), m_current_cylinder);
if (TRACE_STEPS && TRACE_DETAIL) logerror("Arrived at target cylinder %d, settling ...\n", m_current_cylinder);
}
else
{
@ -646,12 +646,12 @@ void mfm_harddisk_device::device_timer(emu_timer &timer, device_timer_id id, int
{
m_ready = true;
m_recalibrated = true;
if (TRACE_STATE) logerror("%s: Spinup complete, drive recalibrated and positioned at cylinder %d; drive is READY\n", tag(), m_current_cylinder);
if (TRACE_STATE) logerror("Spinup complete, drive recalibrated and positioned at cylinder %d; drive is READY\n", m_current_cylinder);
if (!m_ready_cb.isnull()) m_ready_cb(this, ASSERT_LINE);
}
else
{
if (TRACE_SIGNALS) logerror("%s: Settling done at cylinder %d, seek complete\n", tag(), m_current_cylinder);
if (TRACE_SIGNALS) logerror("Settling done at cylinder %d, seek complete\n", m_current_cylinder);
}
m_seek_complete = true;
if (!m_seek_complete_cb.isnull()) m_seek_complete_cb(this, ASSERT_LINE);
@ -664,7 +664,7 @@ void mfm_harddisk_device::device_timer(emu_timer &timer, device_timer_id id, int
void mfm_harddisk_device::recalibrate()
{
if (TRACE_STEPS) logerror("%s: Recalibrate to track 0\n", tag());
if (TRACE_STEPS) logerror("Recalibrate to track 0\n");
direction_in_w(CLEAR_LINE);
while (-m_track_delta < m_phys_cylinders)
{
@ -677,13 +677,13 @@ void mfm_harddisk_device::head_move()
{
int steps = m_track_delta;
if (steps < 0) steps = -steps;
if (TRACE_STEPS) logerror("%s: Moving head by %d step(s) %s\n", tag(), steps, (m_track_delta<0)? "outward" : "inward");
if (TRACE_STEPS) logerror("Moving head by %d step(s) %s\n", steps, (m_track_delta<0)? "outward" : "inward");
// We simulate the head movement by pausing for n*step_time with n being the cylinder delta
m_step_phase = STEP_MOVING;
m_seek_timer->adjust(m_step_time * steps);
if (TRACE_TIMING) logerror("%s: Head movement takes %s time\n", tag(), tts(m_step_time * steps).c_str());
if (TRACE_TIMING) logerror("Head movement takes %s time\n", tts(m_step_time * steps).c_str());
// We pretend that we already arrived
// TODO: Check auto truncation?
m_current_cylinder += m_track_delta;
@ -695,7 +695,7 @@ void mfm_harddisk_device::head_move()
void mfm_harddisk_device::direction_in_w(line_state line)
{
m_seek_inward = (line == ASSERT_LINE);
if (TRACE_STEPS && TRACE_DETAIL) logerror("%s: Setting seek direction %s\n", tag(), m_seek_inward? "inward" : "outward");
if (TRACE_STEPS && TRACE_DETAIL) logerror("Setting seek direction %s\n", m_seek_inward? "inward" : "outward");
}
/*
@ -746,10 +746,10 @@ void mfm_harddisk_device::step_w(line_state line)
// Counter will be adjusted according to the direction (+-1)
m_track_delta += (m_seek_inward)? +1 : -1;
if (TRACE_STEPS && TRACE_DETAIL) logerror("%s: Got seek pulse; track delta %d\n", tag(), m_track_delta);
if (TRACE_STEPS && TRACE_DETAIL) logerror("Got seek pulse; track delta %d\n", m_track_delta);
if (m_track_delta < -m_phys_cylinders || m_track_delta > m_phys_cylinders)
{
if (TRACE_STEPS) logerror("%s: Excessive step pulses - doing auto-truncation\n", tag());
if (TRACE_STEPS) logerror("Excessive step pulses - doing auto-truncation\n");
m_autotruncation = true;
}
m_seek_timer->adjust(attotime::from_usec(250)); // Start step collect timer
@ -782,7 +782,7 @@ bool mfm_harddisk_device::find_position(attotime &from_when, const attotime &lim
// Reached the end
if (bytepos >= m_trackimage_size)
{
if (TRACE_TIMING) logerror("%s: Reached end: rev_start = %s, live = %s\n", tag(), tts(m_revolution_start_time).c_str(), tts(from_when).c_str());
if (TRACE_TIMING) logerror("Reached end: rev_start = %s, live = %s\n", tts(m_revolution_start_time).c_str(), tts(from_when).c_str());
m_revolution_start_time += m_rev_time;
cell = (from_when - m_revolution_start_time).as_ticks(freq);
bytepos = cell / 16;
@ -790,7 +790,7 @@ bool mfm_harddisk_device::find_position(attotime &from_when, const attotime &lim
if (bytepos < 0)
{
if (TRACE_TIMING) logerror("%s: Negative cell number: rev_start = %s, live = %s\n", tag(), tts(m_revolution_start_time).c_str(), tts(from_when).c_str());
if (TRACE_TIMING) logerror("Negative cell number: rev_start = %s, live = %s\n", tts(m_revolution_start_time).c_str(), tts(from_when).c_str());
bytepos = 0;
}
bit = cell % 16;
@ -827,12 +827,12 @@ bool mfm_harddisk_device::read(attotime &from_when, const attotime &limit, UINT1
{
// We will deliver a single bit
cdata = ((track[bytepos] << bitpos) & 0x8000) >> 15;
if (TRACE_BITS) logerror("%s: Reading (c=%d,h=%d,bit=%d) at cell %d [%s] = %d\n", tag(), m_current_cylinder, m_current_head, bitpos, ((bytepos<<4) + bitpos), tts(fw).c_str(), cdata);
if (TRACE_BITS) logerror("Reading (c=%d,h=%d,bit=%d) at cell %d [%s] = %d\n", m_current_cylinder, m_current_head, bitpos, ((bytepos<<4) + bitpos), tts(fw).c_str(), cdata);
}
else
{
// We will deliver a whole byte
if (TRACE_READ) logerror("%s: Reading (c=%d,h=%d) at position %d\n", tag(), m_current_cylinder, m_current_head, bytepos);
if (TRACE_READ) logerror("Reading (c=%d,h=%d) at position %d\n", m_current_cylinder, m_current_head, bytepos);
cdata = track[bytepos];
}
return false;
@ -885,7 +885,7 @@ bool mfm_harddisk_device::write(attotime &from_when, const attotime &limit, UINT
if (wpcom && (params->write_precomp_cylinder == -1 || m_current_cylinder < params->write_precomp_cylinder))
params->write_precomp_cylinder = m_current_cylinder;
if (TRACE_WRITE) if ((bitpos&0x0f)==0) logerror("%s: Wrote data=%04x (c=%d,h=%d) at position %04x, wpcom=%d, rwc=%d\n", tag(), track[bytepos], m_current_cylinder, m_current_head, bytepos, wpcom, reduced_wc);
if (TRACE_WRITE) if ((bitpos&0x0f)==0) logerror("Wrote data=%04x (c=%d,h=%d) at position %04x, wpcom=%d, rwc=%d\n", track[bytepos], m_current_cylinder, m_current_head, bytepos, wpcom, reduced_wc);
return false;
}

62
src/mame/drivers/geneve.cpp
View File

@ -218,8 +218,8 @@
#define TRACE_LINES 0
#define TRACE_CRU 0
#define SRAM_SIZE 384*1024 // maximum SRAM expansion on-board
#define DRAM_SIZE 512*1024
#define SRAM_GEN_TAG "sram"
#define DRAM_GEN_TAG "dram"
class geneve_state : public driver_device
{
@ -355,7 +355,7 @@ WRITE8_MEMBER ( geneve_state::cruwrite )
if ((addroff & 0xffc0) == CRU_SSTEP_BASE)
{
int bit = (addroff & 0x003e)>>1;
logerror("geneve: Single step not implemented; bit %d set to %d\n", bit, data);
logerror("Single step not implemented; bit %d set to %d\n", bit, data);
return;
}
@ -366,47 +366,47 @@ WRITE8_MEMBER ( geneve_state::cruwrite )
{
case 5:
// No one really cares...
if (TRACE_CRU) logerror("geneve: Set PAL flag = %02x\n", data);
if (TRACE_CRU) logerror("Set PAL flag = %02x\n", data);
// m_palvideo = (data!=0);
break;
case 7:
// m_capslock = (data!=0);
if (TRACE_CRU) logerror("geneve: Set capslock flag = %02x\n", data);
if (TRACE_CRU) logerror("Set capslock flag = %02x\n", data);
break;
case 8:
if (TRACE_CRU) logerror("geneve: Set keyboard clock flag = %02x\n", data);
if (TRACE_CRU) logerror("Set keyboard clock flag = %02x\n", data);
m_keyboard->clock_control((data!=0)? ASSERT_LINE : CLEAR_LINE);
break;
case 9:
if (TRACE_CRU) logerror("geneve: Set keyboard scan flag = %02x\n", data);
if (TRACE_CRU) logerror("Set keyboard scan flag = %02x\n", data);
m_keyboard->send_scancodes((data!=0)? ASSERT_LINE : CLEAR_LINE);
break;
case 10:
if (TRACE_CRU) logerror("geneve: Geneve mode = %02x\n", data);
if (TRACE_CRU) logerror("Geneve mode = %02x\n", data);
m_mapper->set_geneve_mode(data!=0);
break;
case 11:
if (TRACE_CRU) logerror("geneve: Direct mode = %02x\n", data);
if (TRACE_CRU) logerror("Direct mode = %02x\n", data);
m_mapper->set_direct_mode(data!=0);
break;
case 12:
if (TRACE_CRU) logerror("geneve: Cartridge size 8K = %02x\n", data);
if (TRACE_CRU) logerror("Cartridge size 8K = %02x\n", data);
m_mapper->set_cartridge_size((data!=0)? 0x2000 : 0x4000);
break;
case 13:
if (TRACE_CRU) logerror("geneve: Cartridge writable 6000 = %02x\n", data);
if (TRACE_CRU) logerror("Cartridge writable 6000 = %02x\n", data);
m_mapper->set_cartridge_writable(0x6000, (data!=0));
break;
case 14:
if (TRACE_CRU) logerror("geneve: Cartridge writable 7000 = %02x\n", data);
if (TRACE_CRU) logerror("Cartridge writable 7000 = %02x\n", data);
m_mapper->set_cartridge_writable(0x7000, (data!=0));
break;
case 15:
if (TRACE_CRU) logerror("geneve: Extra wait states = %02x\n", data==0);
if (TRACE_CRU) logerror("Extra wait states = %02x\n", data==0);
m_mapper->set_extra_waitstates(data==0); // let's use the inverse semantics
break;
default:
logerror("geneve: set CRU address %04x=%02x ignored\n", addroff, data);
logerror("set CRU address %04x=%02x ignored\n", addroff, data);
break;
}
}
@ -426,7 +426,7 @@ READ8_MEMBER( geneve_state::cruread )
if ((addroff & 0xffc0) == CRU_SSTEP_BASE)
{
int bit = (addroff & 0x003e)>>1;
logerror("geneve: Single step not implemented; attempting to read bit %d\n", bit);
logerror("Single step not implemented; attempting to read bit %d\n", bit);
return value;
}
@ -478,7 +478,7 @@ READ8_MEMBER( geneve_state::read_by_9901 )
if (m_intb==CLEAR_LINE) answer |= 0x10;
if (m_video_wait==ASSERT_LINE) answer |= 0x20;
// TODO: PAL pin 5
if (TRACE_LINES) logerror("geneve: INT15-8 = %02x\n", answer);
if (TRACE_LINES) logerror("INT15-8 = %02x\n", answer);
break;
case TMS9901_P0_P7:
@ -506,7 +506,7 @@ READ8_MEMBER( geneve_state::read_by_9901 )
*/
WRITE_LINE_MEMBER( geneve_state::peripheral_bus_reset )
{
logerror("geneve: Peripheral bus reset request; not implemented yet.\n");
logerror("Peripheral bus reset request; not implemented yet.\n");
}
/*
@ -514,7 +514,7 @@ WRITE_LINE_MEMBER( geneve_state::peripheral_bus_reset )
*/
WRITE_LINE_MEMBER( geneve_state::VDP_reset )
{
logerror("geneve: Video reset request; not implemented yet.\n");
logerror("Video reset request; not implemented yet.\n");
}
/*
@ -530,7 +530,7 @@ WRITE_LINE_MEMBER( geneve_state::joystick_select )
*/
WRITE_LINE_MEMBER( geneve_state::extbus_wait_states )
{
logerror("geneve: External bus wait states set to %d, not implemented yet.\n", state);
logerror("External bus wait states set to %d, not implemented yet.\n", state);
}
/*
@ -539,7 +539,7 @@ WRITE_LINE_MEMBER( geneve_state::extbus_wait_states )
*/
WRITE_LINE_MEMBER( geneve_state::video_wait_states )
{
if (TRACE_LINES) logerror("geneve: Video wait states set to %d\n", state);
if (TRACE_LINES) logerror("Video wait states set to %d\n", state);
m_mapper->set_video_waitstates(state==ASSERT_LINE);
m_video_wait = (state!=0)? ASSERT_LINE : CLEAR_LINE;
}
@ -581,14 +581,14 @@ WRITE_LINE_MEMBER( geneve_state::intb )
WRITE_LINE_MEMBER( geneve_state::ext_ready )
{
if (TRACE_READY) logerror("geneve: READY level (ext) = %02x\n", state);
if (TRACE_READY) logerror("READY level (ext) = %02x\n", state);
m_ready_line = state;
m_cpu->ready_line((m_ready_line == ASSERT_LINE && m_ready_line1 == ASSERT_LINE)? ASSERT_LINE : CLEAR_LINE);
}
WRITE_LINE_MEMBER( geneve_state::mapper_ready )
{
if (TRACE_READY) logerror("geneve: READY level (mapper) = %02x\n", state);
if (TRACE_READY) logerror("READY level (mapper) = %02x\n", state);
m_ready_line1 = state;
m_cpu->ready_line((m_ready_line == ASSERT_LINE && m_ready_line1 == ASSERT_LINE)? ASSERT_LINE : CLEAR_LINE);
}
@ -633,7 +633,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(geneve_state::geneve_hblank_interrupt)
WRITE8_MEMBER( geneve_state::external_operation )
{
static const char* extop[8] = { "inv1", "inv2", "IDLE", "RSET", "inv3", "CKON", "CKOF", "LREX" };
if (offset != IDLE_OP) logerror("geneve: External operation %s not implemented on Geneve board\n", extop[offset]);
if (offset != IDLE_OP) logerror("External operation %s not implemented on Geneve board\n", extop[offset]);
}
/*
@ -740,6 +740,16 @@ static MACHINE_CONFIG_START( geneve_60hz, geneve_state )
MCFG_AT29C040_ADD( PFM512_TAG )
MCFG_AT29C040A_ADD( PFM512A_TAG )
// DRAM 512K
MCFG_RAM_ADD(DRAM_GEN_TAG)
MCFG_RAM_DEFAULT_SIZE("512K")
MCFG_RAM_DEFAULT_VALUE(0)
// SRAM 384K (max; stock Geneve: 32K)
MCFG_RAM_ADD(SRAM_GEN_TAG)
MCFG_RAM_DEFAULT_SIZE("384K")
MCFG_RAM_DEFAULT_VALUE(0)
MACHINE_CONFIG_END
/*
@ -752,12 +762,6 @@ ROM_START(geneve)
ROM_LOAD("genbt100.bin", 0x0000, 0x4000, CRC(8001e386) SHA1(b44618b54dabac3882543e18555d482b299e0109)) /* CPU ROMs v1.0 */
ROM_LOAD_OPTIONAL("genbt098.bin", 0x4000, 0x4000, CRC(b2e20df9) SHA1(2d5d09177afe97d63ceb3ad59b498b1c9e2153f7)) /* CPU ROMs v0.98 */
ROM_LOAD_OPTIONAL("gnmbt100.bin", 0x8000, 0x4000, CRC(19b89479) SHA1(6ef297eda78dc705946f6494e9d7e95e5216ec47)) /* CPU ROMs GenMod */
ROM_REGION(SRAM_SIZE, SRAM_TAG, 0)
ROM_FILL(0x0000, SRAM_SIZE, 0x00)
ROM_REGION(DRAM_SIZE, DRAM_TAG, 0)
ROM_FILL(0x0000, DRAM_SIZE, 0x00)
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */