mirror of
https://github.com/holub/mame
synced 2025-07-05 18:08:04 +03:00
Major cpuintrf changes:
* added a set of cpu_* calls which accept a CPU device object; these are now the preferred means of manipulating a CPU * removed the cpunum_* calls; added an array of cpu[] to the running_machine object; converted all existing cpunum_* calls to cpu_* calls, pulling the CPU device object from the new array in the running_machine * removed the activecpu_* calls; added an activecpu member to the running_machine object; converted all existing activecpu_* calls to cpu_* calls, pulling the active CPU device object from the running_machine * changed cpuintrf_push_context() to cpu_push_context(), taking a CPU object pointer; changed cpuintrf_pop_context() to cpu_pop_context(); eventually these will go away * many other similar changes moving toward a model where all CPU references are done by the CPU object and not by index
This commit is contained in:
parent
7c2bd582be
commit
92f3053105
@ -704,7 +704,7 @@ static CPU_SET_INFO( ccpu )
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/* --- the following bits of info are set as 64-bit signed integers --- */
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case CPUINFO_INT_PC:
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case CPUINFO_INT_REGISTER + CCPU_PC: ccpu.PC = info->i; break;
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case CPUINFO_INT_REGISTER + CCPU_FLAGS:
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case CPUINFO_INT_REGISTER + Ccpu_get_flags:
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ccpu.a0flag = (info->i & 0x01) ? 1 : 0;
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ccpu.ncflag = (info->i & 0x02) ? 0x0000 : 0x1000;
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ccpu.cmpacc = 1;
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@ -760,7 +760,7 @@ CPU_GET_INFO( ccpu )
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case CPUINFO_INT_PC:
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case CPUINFO_INT_REGISTER + CCPU_PC: info->i = ccpu.PC; break;
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case CPUINFO_INT_REGISTER + CCPU_FLAGS: info->i = 0;
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case CPUINFO_INT_REGISTER + Ccpu_get_flags: info->i = 0;
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if (TEST_A0()) info->i |= 0x01;
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if (TEST_NC()) info->i |= 0x02;
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if (TEST_LT()) info->i |= 0x04;
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@ -807,7 +807,7 @@ CPU_GET_INFO( ccpu )
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TEST_DR() ? 'D' : 'd');
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break;
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case CPUINFO_STR_REGISTER + CCPU_FLAGS:
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case CPUINFO_STR_REGISTER + Ccpu_get_flags:
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sprintf(info->s, "FL:%c%c%c%c%c%c",
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TEST_A0() ? '0' : 'o',
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TEST_NC() ? 'N' : 'n',
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@ -23,7 +23,7 @@
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enum
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{
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CCPU_PC=1,
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CCPU_FLAGS,
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Ccpu_get_flags,
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CCPU_A,
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CCPU_B,
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CCPU_I,
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@ -54,7 +54,7 @@ static TIMER_CALLBACK(cop410_serial_tick)
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{
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int cpunum = param;
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cpuintrf_push_context(cpunum);
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cpu_push_context(machine->cpu[cpunum]);
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if (BIT(EN, 0))
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{
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@ -126,7 +126,7 @@ static TIMER_CALLBACK(cop410_serial_tick)
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SIO = ((SIO << 1) | IN_SI()) & 0x0f;
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}
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cpuintrf_pop_context();
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cpu_pop_context();
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}
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INLINE void WRITE_Q(UINT8 data)
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@ -233,7 +233,7 @@ static CPU_INIT( cop410 )
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/* set clock divider */
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cpunum_set_info_int(index, CPUINFO_INT_CLOCK_DIVIDER, R.intf->cki);
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cpu_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, R.intf->cki);
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/* allocate serial timer */
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@ -230,7 +230,7 @@ ADDRESS_MAP_END
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static TIMER_CALLBACK(cop420_counter_tick)
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{
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cpuintrf_push_context(param);
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cpu_push_context(machine->cpu[param]);
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R.counter++;
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@ -240,7 +240,7 @@ static TIMER_CALLBACK(cop420_counter_tick)
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R.timerlatch = 1;
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}
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cpuintrf_pop_context();
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cpu_pop_context();
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}
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/* IN Latches */
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@ -250,7 +250,7 @@ static TIMER_CALLBACK(cop420_inil_tick)
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UINT8 in;
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int i;
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cpuintrf_push_context(param);
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cpu_push_context(machine->cpu[param]);
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in = IN_IN();
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for (i = 0; i < 4; i++)
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@ -263,7 +263,7 @@ static TIMER_CALLBACK(cop420_inil_tick)
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}
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}
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cpuintrf_pop_context();
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cpu_pop_context();
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}
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/* Microbus */
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@ -272,7 +272,7 @@ static TIMER_CALLBACK(cop420_microbus_tick)
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{
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UINT8 in;
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cpuintrf_push_context(param);
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cpu_push_context(machine->cpu[param]);
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in = IN_IN();
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@ -298,7 +298,7 @@ static TIMER_CALLBACK(cop420_microbus_tick)
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}
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}
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cpuintrf_pop_context();
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cpu_pop_context();
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}
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/****************************************************************************
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@ -322,7 +322,7 @@ static CPU_INIT( cop420 )
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/* set clock divider */
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cpunum_set_info_int(index, CPUINFO_INT_CLOCK_DIVIDER, R.intf->cki);
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cpu_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, R.intf->cki);
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/* allocate serial timer */
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@ -1551,7 +1551,7 @@ static void cp1610_xori(int d)
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static CPU_RESET( cp1610 )
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{
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/* This is how we set the reset vector */
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cpunum_set_input_line(Machine, cpu_getactivecpu(), CP1610_RESET, PULSE_LINE);
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cpunum_set_input_line(Machine, cpunum_get_active(), CP1610_RESET, PULSE_LINE);
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}
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/***************************************************
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@ -122,7 +122,7 @@ INLINE void desc_free(drcfe_state *drcfe, opcode_desc *desc)
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drcfe_init - initializate the drcfe state
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-------------------------------------------------*/
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drcfe_state *drcfe_init(const drcfe_config *config, void *param)
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drcfe_state *drcfe_init(const device_config *cpu, const drcfe_config *config, void *param)
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{
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drcfe_state *drcfe;
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@ -142,14 +142,14 @@ drcfe_state *drcfe_init(const drcfe_config *config, void *param)
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drcfe->param = param;
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/* initialize the state */
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drcfe->pageshift = activecpu_page_shift(ADDRESS_SPACE_PROGRAM);
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drcfe->translate = (cpu_translate_func)activecpu_get_info_fct(CPUINFO_PTR_TRANSLATE);
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drcfe->pageshift = cpu_get_page_shift(cpu, ADDRESS_SPACE_PROGRAM);
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drcfe->translate = (cpu_translate_func)cpu_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
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#ifdef LSB_FIRST
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if (activecpu_endianness() == CPU_IS_BE)
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if (cpu_get_endianness(cpu) == CPU_IS_BE)
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#else
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if (activecpu_endianness() == CPU_IS_LE)
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if (cpu_get_endianness(cpu) == CPU_IS_LE)
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#endif
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drcfe->codexor = (activecpu_databus_width(ADDRESS_SPACE_PROGRAM) / 8 / activecpu_min_instruction_bytes() - 1) * activecpu_min_instruction_bytes();
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drcfe->codexor = (cpu_get_databus_width(cpu, ADDRESS_SPACE_PROGRAM) / 8 / cpu_get_min_opcode_bytes(cpu) - 1) * cpu_get_min_opcode_bytes(cpu);
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return drcfe;
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}
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@ -150,7 +150,7 @@ struct _drcfe_config
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***************************************************************************/
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/* initializate the drcfe state */
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drcfe_state *drcfe_init(const drcfe_config *config, void *param);
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drcfe_state *drcfe_init(const device_config *cpu, const drcfe_config *config, void *param);
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/* clean up after ourselves */
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void drcfe_exit(drcfe_state *drcfe);
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@ -452,17 +452,6 @@ static CPU_DISASSEMBLE( dsp32c )
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PARALLEL INTERFACE WRITES
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***************************************************************************/
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/* context finder */
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#ifdef UNUSED_FUNCTION
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INLINE dsp32_regs *FINDCONTEXT(int cpu)
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{
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dsp32_regs *context = cpunum_get_context_ptr(cpu);
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if (!context)
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context = &dsp32;
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return context;
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}
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#endif
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static const UINT32 regmap[4][16] =
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{
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{ /* DSP32 compatible mode */
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@ -560,7 +549,7 @@ void dsp32c_pio_w(int cpunum, int reg, int data)
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UINT16 mask;
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UINT8 mode;
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cpuintrf_push_context(cpunum);
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cpu_push_context(Machine->cpu[cpunum]);
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/* look up register and mask */
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mode = ((dsp32.pcr >> 8) & 2) | ((dsp32.pcr >> 1) & 1);
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@ -628,7 +617,7 @@ void dsp32c_pio_w(int cpunum, int reg, int data)
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break;
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}
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cpuintrf_pop_context();
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cpu_pop_context();
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}
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@ -642,7 +631,7 @@ int dsp32c_pio_r(int cpunum, int reg)
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UINT16 mask, result = 0xffff;
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UINT8 mode, shift = 0;
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cpuintrf_push_context(cpunum);
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cpu_push_context(Machine->cpu[cpunum]);
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/* look up register and mask */
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mode = ((dsp32.pcr >> 8) & 2) | ((dsp32.pcr >> 1) & 1);
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@ -702,7 +691,7 @@ int dsp32c_pio_r(int cpunum, int reg)
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break;
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}
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cpuintrf_pop_context();
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cpu_pop_context();
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return (result >> shift) & ~mask;
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}
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@ -628,7 +628,7 @@ static void adjust_timer_interrupt(void)
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UINT64 cycles_since_base = activecpu_gettotalcycles() - hyperstone.tr_base_cycles;
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UINT64 clocks_since_base = cycles_since_base >> hyperstone.clock_scale;
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UINT64 cycles_until_next_clock = cycles_since_base - (clocks_since_base << hyperstone.clock_scale);
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int cpunum = cpu_getactivecpu();
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int cpunum = cpunum_get_active();
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if (cycles_until_next_clock == 0)
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cycles_until_next_clock = (UINT64)(1 << hyperstone.clock_scale);
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@ -669,7 +669,7 @@ static TIMER_CALLBACK( e132xs_timer_callback )
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int update = param & 1;
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int cpunum = param >> 1;
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cpuintrf_push_context(cpunum);
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cpu_push_context(machine->cpu[cpunum]);
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/* update the values if necessary */
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if (update)
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@ -683,7 +683,7 @@ static TIMER_CALLBACK( e132xs_timer_callback )
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else
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adjust_timer_interrupt();
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cpuintrf_pop_context();
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cpu_pop_context();
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}
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@ -558,7 +558,7 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
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* set I flag, reset D flag and jump via IRQ vector
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***************************************************************/
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#define BRK \
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logerror("BRK %04x\n",activecpu_get_pc()); \
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logerror("BRK %04x\n",cpu_get_pc(Machine->activecpu)); \
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CLEAR_T; \
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PCW++; \
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PUSH(PCH); \
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@ -1106,7 +1106,7 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
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***************************************************************/
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#define SET \
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P |= _fT; \
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logerror("%04x: WARNING H6280 SET\n",activecpu_get_pc())
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logerror("%04x: WARNING H6280 SET\n",cpu_get_pc(Machine->activecpu))
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/* 6280 ********************************************************
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* SMB Set memory bit
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@ -9,6 +9,7 @@
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****************************************************************************/
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#include "debugger.h"
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#include "deprecat.h"
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#include "h83002.h"
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#include "h8priv.h"
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@ -515,7 +516,7 @@ UINT8 h8_3007_itu_read8(UINT8 reg)
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void h8_3007_itu_write8(UINT8 reg, UINT8 val)
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{
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//logerror("%06x: h8/3007 reg %02x = %02x\n",activecpu_get_pc(),reg,val);
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//logerror("%06x: h8/3007 reg %02x = %02x\n",cpu_get_pc(machine->activecpu),reg,val);
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h8.per_regs[reg] = val;
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switch(reg)
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{
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@ -687,7 +688,7 @@ UINT8 h8_3007_register1_read8(UINT32 address)
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case 0xfee018: return h8.per_regs[0xF8]; // IPRA
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}
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logerror("cpu #%d (PC=%08X): unmapped I/O(1) byte read from %08X\n",cpu_getactivecpu(),activecpu_get_pc(),address);
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logerror("cpu #%d (PC=%08X): unmapped I/O(1) byte read from %08X\n",cpunum_get_active(),cpu_get_pc(Machine->activecpu),address);
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return 0;
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}
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@ -699,7 +700,7 @@ void h8_3007_register1_write8(UINT32 address, UINT8 val)
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case 0xfee016: h8_ISR_w(val); return; // ISR
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case 0xfee018: h8.per_regs[0xF8] = val; return; // IPRA
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}
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logerror("cpu #%d (PC=%08X): unmapped I/O(1) byte write to %08X = %02X\n",cpu_getactivecpu(),activecpu_get_pc(),address,val);
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logerror("cpu #%d (PC=%08X): unmapped I/O(1) byte write to %08X = %02X\n",cpunum_get_active(),cpu_get_pc(Machine->activecpu),address,val);
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}
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void h8_3007_itu_init(void)
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@ -721,7 +722,7 @@ void h8_itu_init(void)
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h8_itu_reset();
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h8.cpu_number = cpu_getactivecpu();
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h8.cpu_number = cpunum_get_active();
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}
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void h8_itu_reset(void)
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@ -575,7 +575,7 @@ static void set_irq_line(int irqline, int state)
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{
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if (hd6309.nmi_state == state) return;
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hd6309.nmi_state = state;
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LOG(("HD6309#%d set_irq_line (NMI) %d (PC=%4.4X)\n", cpu_getactivecpu(), state, pPC.d));
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LOG(("HD6309#%d set_irq_line (NMI) %d (PC=%4.4X)\n", cpunum_get_active(), state, pPC.d));
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if( state == CLEAR_LINE ) return;
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/* if the stack was not yet initialized */
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@ -614,7 +614,7 @@ static void set_irq_line(int irqline, int state)
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}
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else if (irqline < 2)
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{
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LOG(("HD6309#%d set_irq_line %d, %d (PC=%4.4X)\n", cpu_getactivecpu(), irqline, state, pPC.d));
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LOG(("HD6309#%d set_irq_line %d, %d (PC=%4.4X)\n", cpunum_get_active(), irqline, state, pPC.d));
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hd6309.irq_state[irqline] = state;
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if (state == CLEAR_LINE) return;
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CHECK_IRQ_LINES();
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@ -301,7 +301,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
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break;
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case 0x1D: /* 0F 1D C6 - SET1 si,cl */
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/* logerror("PC=%06x : Set1 ",activecpu_get_pc()-2); */
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/* logerror("PC=%06x : Set1 ",cpu_get_pc(machine->activecpu)-2); */
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ModRM = FETCH;
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if (ModRM >= 0xc0)
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{
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@ -477,7 +477,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
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*
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* Clocks: 16
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*/
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logerror("PC=%06x : MOVSPA\n", activecpu_get_pc() - 2);
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logerror("PC=%06x : MOVSPA\n", cpu_get_pc(machine->activecpu) - 2);
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nec_ICount -= 16;
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break;
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case 0x26: /* 0F 22 59 - cmp4s */
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@ -567,7 +567,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
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* tmp &= 0xffff;
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* PutbackRMWord(ModRM,tmp);
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*/
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logerror("PC=%06x : ROL4 %02x\n", activecpu_get_pc() - 3, ModRM);
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logerror("PC=%06x : ROL4 %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
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break;
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case 0x2A: /* 0F 2a c2 - ROR4 bh */
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@ -612,7 +612,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
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* tmp = tmp2 | (tmp>>4);
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* PutbackRMWord(ModRM,tmp);
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*/
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logerror("PC=%06x : ROR4 %02x\n", activecpu_get_pc() - 3, ModRM);
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logerror("PC=%06x : ROR4 %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
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break;
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case 0x2D: /* 0Fh 2Dh <1111 1RRR> */
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@ -677,13 +677,13 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
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* Flags Affected: None
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*/
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ModRM = FETCH;
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logerror("PC=%06x : BRKCS %02x\n", activecpu_get_pc() - 3, ModRM);
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logerror("PC=%06x : BRKCS %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
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nec_ICount -= 15; /* checked ! */
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break;
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case 0x31: /* 0F 31 [mod:reg:r/m] - INS reg8,reg8 or INS reg8,imm4 */
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ModRM = FETCH;
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logerror("PC=%06x : INS ", activecpu_get_pc() - 2);
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logerror("PC=%06x : INS ", cpu_get_pc(machine->activecpu) - 2);
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if (ModRM >= 0xc0)
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{
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tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
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@ -739,7 +739,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
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case 0x33: /* 0F 33 [mod:reg:r/m] - EXT reg8,reg8 or EXT reg8,imm4 */
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ModRM = FETCH;
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logerror("PC=%06x : EXT ", activecpu_get_pc() - 2);
|
||||
logerror("PC=%06x : EXT ", cpu_get_pc(machine->activecpu) - 2);
|
||||
if (ModRM >= 0xc0)
|
||||
{
|
||||
tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
|
||||
@ -823,7 +823,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
|
||||
*
|
||||
* Clocks: 12
|
||||
*/
|
||||
logerror("PC=%06x : RETRBI\n", activecpu_get_pc() - 2);
|
||||
logerror("PC=%06x : RETRBI\n", cpu_get_pc(machine->activecpu) - 2);
|
||||
nec_ICount -= 12;
|
||||
break;
|
||||
|
||||
@ -856,7 +856,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
|
||||
*/
|
||||
ModRM = FETCH;
|
||||
|
||||
logerror("PC=%06x : TSCSW %02x\n", activecpu_get_pc() - 3, ModRM);
|
||||
logerror("PC=%06x : TSCSW %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
|
||||
nec_ICount -= 11;
|
||||
break;
|
||||
|
||||
@ -889,7 +889,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
|
||||
* Clocks: 11
|
||||
*/
|
||||
ModRM = FETCH;
|
||||
logerror("PC=%06x : MOVSPB %02x\n", activecpu_get_pc() - 3, ModRM);
|
||||
logerror("PC=%06x : MOVSPB %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
|
||||
nec_ICount -= 11;
|
||||
break;
|
||||
|
||||
@ -917,7 +917,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
|
||||
*
|
||||
* Clocks: N/A
|
||||
*/
|
||||
logerror("PC=%06x : STOP\n", activecpu_get_pc() - 2);
|
||||
logerror("PC=%06x : STOP\n", cpu_get_pc(machine->activecpu) - 2);
|
||||
nec_ICount -= 2; /* of course this is crap */
|
||||
break;
|
||||
|
||||
@ -990,7 +990,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
|
||||
*/
|
||||
|
||||
ModRM = FETCH;
|
||||
logerror("PC=%06x : BRKXA %02x\n", activecpu_get_pc() - 3, ModRM);
|
||||
logerror("PC=%06x : BRKXA %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
|
||||
nec_ICount -= 12;
|
||||
break;
|
||||
|
||||
@ -1027,7 +1027,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
|
||||
* Clocks: 12
|
||||
*/
|
||||
ModRM = FETCH;
|
||||
logerror("PC=%06x : RETXA %02x\n", activecpu_get_pc() - 3, ModRM);
|
||||
logerror("PC=%06x : RETXA %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
|
||||
nec_ICount -= 12;
|
||||
break;
|
||||
|
||||
@ -1058,7 +1058,7 @@ static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
|
||||
*/
|
||||
ModRM = FETCH;
|
||||
nec_ICount -= 38;
|
||||
logerror("PC=%06x : BRKEM %02x\n", activecpu_get_pc() - 3, ModRM);
|
||||
logerror("PC=%06x : BRKEM %02x\n", cpu_get_pc(machine->activecpu) - 3, ModRM);
|
||||
PREFIXV30(_interrupt) (ModRM, 1);
|
||||
break;
|
||||
}
|
||||
@ -1099,7 +1099,7 @@ static void PREFIXV30(_brkn) (void) /* Opcode 0x63 BRKN - Break to Native Mode
|
||||
unsigned int_vector;
|
||||
|
||||
int_vector = FETCH;
|
||||
logerror("PC=%06x : BRKN %02x\n", activecpu_get_pc() - 2, int_vector);
|
||||
logerror("PC=%06x : BRKN %02x\n", cpu_get_pc(machine->activecpu) - 2, int_vector);
|
||||
}
|
||||
|
||||
static void PREFIXV30(repc) (int flagval)
|
||||
@ -1269,7 +1269,7 @@ static void PREFIXV30(_setalc) (void) /* Opcode 0xd6 */
|
||||
*/
|
||||
I.regs.b[AL] = (CF) ? 0xff : 0x00;
|
||||
nec_ICount -= 3; // V30
|
||||
logerror("PC=%06x : SETALC\n", activecpu_get_pc() - 1);
|
||||
logerror("PC=%06x : SETALC\n", cpu_get_pc(machine->activecpu) - 1);
|
||||
}
|
||||
|
||||
#if 0
|
||||
@ -1306,6 +1306,6 @@ static void PREFIXV30(_brks) (void) /* Opcode 0xf1 - Break to Security Mode */
|
||||
unsigned int_vector;
|
||||
|
||||
int_vector = FETCH;
|
||||
logerror("PC=%06x : BRKS %02x\n", activecpu_get_pc() - 2, int_vector);
|
||||
logerror("PC=%06x : BRKS %02x\n", cpu_get_pc(machine->activecpu) - 2, int_vector);
|
||||
}
|
||||
#endif
|
||||
|
@ -1180,7 +1180,7 @@ static CPU_SET_INFO( i8x41 )
|
||||
break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + I8X41_STAT:
|
||||
logerror("i8x41 #%d:%03x Setting STAT DBBI to %02x\n", cpu_getactivecpu(), PC, (UINT8)info->i);
|
||||
logerror("i8x41 #%d:%03x Setting STAT DBBI to %02x\n", cpunum_get_active(), PC, (UINT8)info->i);
|
||||
/* writing status.. hmm, should we issue interrupts here too? */
|
||||
STATE = info->i;
|
||||
break;
|
||||
@ -1266,7 +1266,7 @@ CPU_GET_INFO( i8041 )
|
||||
break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + I8X41_STAT:
|
||||
logerror("i8x41 #%d:%03x Reading STAT %02x\n", cpu_getactivecpu(), PC, STATE);
|
||||
logerror("i8x41 #%d:%03x Reading STAT %02x\n", cpunum_get_active(), PC, STATE);
|
||||
info->i = STATE;
|
||||
break;
|
||||
|
||||
|
@ -10,7 +10,7 @@
|
||||
***********************************/
|
||||
OP_HANDLER( illegal )
|
||||
{
|
||||
logerror("i8x41 #%d: illegal opcode at 0x%03x: %02x\n", cpu_getactivecpu(), PC, ROP(PC));
|
||||
logerror("i8x41 #%d: illegal opcode at 0x%03x: %02x\n", cpunum_get_active(), PC, ROP(PC));
|
||||
}
|
||||
|
||||
/***********************************
|
||||
|
@ -506,7 +506,7 @@ static CPU_EXECUTE( jaguargpu )
|
||||
/* if we're halted, we shouldn't be here */
|
||||
if (!(jaguar.ctrl[G_CTRL] & 1))
|
||||
{
|
||||
cpunum_set_input_line(Machine, cpu_getactivecpu(), INPUT_LINE_HALT, ASSERT_LINE);
|
||||
cpunum_set_input_line(Machine, cpunum_get_active(), INPUT_LINE_HALT, ASSERT_LINE);
|
||||
return cycles;
|
||||
}
|
||||
|
||||
@ -518,7 +518,7 @@ static CPU_EXECUTE( jaguargpu )
|
||||
change_pc(jaguar.PC);
|
||||
|
||||
/* remember that we're executing */
|
||||
executing_cpu = cpu_getactivecpu();
|
||||
executing_cpu = cpunum_get_active();
|
||||
|
||||
/* core execution loop */
|
||||
do
|
||||
@ -552,7 +552,7 @@ static CPU_EXECUTE( jaguardsp )
|
||||
/* if we're halted, we shouldn't be here */
|
||||
if (!(jaguar.ctrl[G_CTRL] & 1))
|
||||
{
|
||||
cpunum_set_input_line(Machine, cpu_getactivecpu(), INPUT_LINE_HALT, ASSERT_LINE);
|
||||
cpunum_set_input_line(Machine, cpunum_get_active(), INPUT_LINE_HALT, ASSERT_LINE);
|
||||
return cycles;
|
||||
}
|
||||
|
||||
@ -564,7 +564,7 @@ static CPU_EXECUTE( jaguardsp )
|
||||
change_pc(jaguar.PC);
|
||||
|
||||
/* remember that we're executing */
|
||||
executing_cpu = cpu_getactivecpu();
|
||||
executing_cpu = cpunum_get_active();
|
||||
|
||||
/* core execution loop */
|
||||
do
|
||||
@ -1299,12 +1299,12 @@ UINT32 jaguargpu_ctrl_r(int cpunum, offs_t offset)
|
||||
{
|
||||
UINT32 result;
|
||||
|
||||
if (LOG_GPU_IO) logerror("%08X/%d:GPU read register @ F021%02X\n", activecpu_get_previouspc(), cpu_getactivecpu(), offset * 4);
|
||||
if (LOG_GPU_IO) logerror("%08X/%d:GPU read register @ F021%02X\n", cpu_get_previouspc(Machine->activecpu), cpunum_get_active(), offset * 4);
|
||||
|
||||
/* switch to the target context */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
result = jaguar.ctrl[offset];
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
return result;
|
||||
}
|
||||
@ -1315,10 +1315,10 @@ void jaguargpu_ctrl_w(int cpunum, offs_t offset, UINT32 data, UINT32 mem_mask)
|
||||
UINT32 oldval, newval;
|
||||
|
||||
if (LOG_GPU_IO && offset != G_HIDATA)
|
||||
logerror("%08X/%d:GPU write register @ F021%02X = %08X\n", activecpu_get_previouspc(), cpu_getactivecpu(), offset * 4, data);
|
||||
logerror("%08X/%d:GPU write register @ F021%02X = %08X\n", cpu_get_previouspc(Machine->activecpu), cpunum_get_active(), offset * 4, data);
|
||||
|
||||
/* switch to the target context */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
|
||||
/* remember the old and set the new */
|
||||
oldval = jaguar.ctrl[offset];
|
||||
@ -1367,7 +1367,7 @@ void jaguargpu_ctrl_w(int cpunum, offs_t offset, UINT32 data, UINT32 mem_mask)
|
||||
if ((oldval ^ newval) & 0x01)
|
||||
{
|
||||
cpunum_set_input_line(Machine, cpunum, INPUT_LINE_HALT, (newval & 1) ? CLEAR_LINE : ASSERT_LINE);
|
||||
if (cpu_getexecutingcpu() >= 0)
|
||||
if (cpunum_get_executing() >= 0)
|
||||
cpu_yield();
|
||||
}
|
||||
if (newval & 0x02)
|
||||
@ -1395,7 +1395,7 @@ void jaguargpu_ctrl_w(int cpunum, offs_t offset, UINT32 data, UINT32 mem_mask)
|
||||
}
|
||||
|
||||
/* restore old context */
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
@ -1409,12 +1409,12 @@ UINT32 jaguardsp_ctrl_r(int cpunum, offs_t offset)
|
||||
UINT32 result;
|
||||
|
||||
if (LOG_DSP_IO && offset != D_FLAGS)
|
||||
logerror("%08X/%d:DSP read register @ F1A1%02X\n", activecpu_get_previouspc(), cpu_getactivecpu(), offset * 4);
|
||||
logerror("%08X/%d:DSP read register @ F1A1%02X\n", cpu_get_previouspc(Machine->activecpu), cpunum_get_active(), offset * 4);
|
||||
|
||||
/* switch to the target context */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
result = jaguar.ctrl[offset];
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
return result;
|
||||
}
|
||||
@ -1425,10 +1425,10 @@ void jaguardsp_ctrl_w(int cpunum, offs_t offset, UINT32 data, UINT32 mem_mask)
|
||||
UINT32 oldval, newval;
|
||||
|
||||
if (LOG_DSP_IO && offset != D_FLAGS)
|
||||
logerror("%08X/%d:DSP write register @ F1A1%02X = %08X\n", activecpu_get_previouspc(), cpu_getactivecpu(), offset * 4, data);
|
||||
logerror("%08X/%d:DSP write register @ F1A1%02X = %08X\n", cpu_get_previouspc(Machine->activecpu), cpunum_get_active(), offset * 4, data);
|
||||
|
||||
/* switch to the target context */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
|
||||
/* remember the old and set the new */
|
||||
oldval = jaguar.ctrl[offset];
|
||||
@ -1478,7 +1478,7 @@ void jaguardsp_ctrl_w(int cpunum, offs_t offset, UINT32 data, UINT32 mem_mask)
|
||||
if ((oldval ^ newval) & 0x01)
|
||||
{
|
||||
cpunum_set_input_line(Machine, cpunum, INPUT_LINE_HALT, (newval & 1) ? CLEAR_LINE : ASSERT_LINE);
|
||||
if (cpu_getexecutingcpu() >= 0)
|
||||
if (cpunum_get_executing() >= 0)
|
||||
cpu_yield();
|
||||
}
|
||||
if (newval & 0x02)
|
||||
@ -1506,7 +1506,7 @@ void jaguardsp_ctrl_w(int cpunum, offs_t offset, UINT32 data, UINT32 mem_mask)
|
||||
}
|
||||
|
||||
/* restore old context */
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
|
@ -438,7 +438,7 @@ static void set_irq_line(int irqline, int state)
|
||||
{
|
||||
if (konami.nmi_state == state) return;
|
||||
konami.nmi_state = state;
|
||||
LOG(("KONAMI#%d set_nmi_line %d\n", cpu_getactivecpu(), state));
|
||||
LOG(("KONAMI#%d set_nmi_line %d\n", cpunum_get_active(), state));
|
||||
if( state == CLEAR_LINE ) return;
|
||||
|
||||
/* if the stack was not yet initialized */
|
||||
@ -470,7 +470,7 @@ static void set_irq_line(int irqline, int state)
|
||||
}
|
||||
else if (irqline < 2)
|
||||
{
|
||||
LOG(("KONAMI#%d set_irq_line %d, %d\n", cpu_getactivecpu(), irqline, state));
|
||||
LOG(("KONAMI#%d set_irq_line %d, %d\n", cpunum_get_active(), irqline, state));
|
||||
konami.irq_state[irqline] = state;
|
||||
if (state == CLEAR_LINE) return;
|
||||
CHECK_IRQ_LINES;
|
||||
|
@ -274,13 +274,13 @@ static TIMER_CALLBACK( m37710_timer_cb )
|
||||
int curirq = M37710_LINE_TIMERA0 - which;
|
||||
int cpunum = param;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
timer_adjust_oneshot(m37710i_cpu.timers[which], m37710i_cpu.reload[which], cpunum);
|
||||
|
||||
m37710i_cpu.m37710_regs[m37710_irq_levels[curirq]] |= 0x04;
|
||||
m37710_set_irq_line(curirq, PULSE_LINE);
|
||||
cpu_triggerint(machine, cpunum);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
static void m37710_external_tick(int timer, int state)
|
||||
@ -315,7 +315,7 @@ static void m37710_external_tick(int timer, int state)
|
||||
|
||||
static void m37710_recalc_timer(int timer)
|
||||
{
|
||||
int cpunum = cpu_getactivecpu();
|
||||
int cpunum = cpunum_get_active();
|
||||
int tval;
|
||||
static const int tcr[8] = { 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d };
|
||||
attotime time;
|
||||
@ -338,7 +338,7 @@ static void m37710_recalc_timer(int timer)
|
||||
switch (m37710i_cpu.m37710_regs[0x56+timer] & 0x3)
|
||||
{
|
||||
case 0: // timer mode
|
||||
time = attotime_mul(ATTOTIME_IN_HZ(cpunum_get_clock(cpu_getactivecpu())), tscales[m37710i_cpu.m37710_regs[tcr[timer]]>>6]);
|
||||
time = attotime_mul(ATTOTIME_IN_HZ(cpunum_get_clock(cpunum_get_active())), tscales[m37710i_cpu.m37710_regs[tcr[timer]]>>6]);
|
||||
time = attotime_mul(time, tval + 1);
|
||||
|
||||
#if M37710_DEBUG
|
||||
@ -373,7 +373,7 @@ static void m37710_recalc_timer(int timer)
|
||||
switch (m37710i_cpu.m37710_regs[0x56+timer] & 0x3)
|
||||
{
|
||||
case 0: // timer mode
|
||||
time = attotime_mul(ATTOTIME_IN_HZ(cpunum_get_clock(cpu_getactivecpu())), tscales[m37710i_cpu.m37710_regs[tcr[timer]]>>6]);
|
||||
time = attotime_mul(ATTOTIME_IN_HZ(cpunum_get_clock(cpunum_get_active())), tscales[m37710i_cpu.m37710_regs[tcr[timer]]>>6]);
|
||||
time = attotime_mul(time, tval + 1);
|
||||
|
||||
#if M37710_DEBUG
|
||||
|
@ -265,7 +265,7 @@ INLINE void m4510_take_irq(m4510_Regs *m4510)
|
||||
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M4510#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M4510#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
|
||||
/* call back the cpuintrf to let it clear the line */
|
||||
if (m4510->irq_callback) (*m4510->irq_callback)(m4510->device, 0);
|
||||
CHANGE_PC;
|
||||
@ -298,7 +298,7 @@ static CPU_EXECUTE( m4510 )
|
||||
/* check if the I flag was just reset (interrupts enabled) */
|
||||
if( m4510->after_cli )
|
||||
{
|
||||
LOG(("M4510#%d after_cli was >0", cpu_getactivecpu()));
|
||||
LOG(("M4510#%d after_cli was >0", cpunum_get_active()));
|
||||
m4510->after_cli = 0;
|
||||
if (m4510->irq_state != CLEAR_LINE)
|
||||
{
|
||||
@ -327,7 +327,7 @@ static void m4510_set_irq_line(m4510_Regs *m4510, int irqline, int state)
|
||||
m4510->nmi_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(("M4510#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(("M4510#%d set_nmi_line(ASSERT)\n", cpunum_get_active()));
|
||||
EAD = M4510_NMI_VEC;
|
||||
m4510->icount -= 7;
|
||||
PUSH(PCH);
|
||||
@ -336,7 +336,7 @@ static void m4510_set_irq_line(m4510_Regs *m4510, int irqline, int state)
|
||||
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M4510#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M4510#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
|
||||
CHANGE_PC;
|
||||
}
|
||||
}
|
||||
@ -345,7 +345,7 @@ static void m4510_set_irq_line(m4510_Regs *m4510, int irqline, int state)
|
||||
m4510->irq_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(("M4510#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(("M4510#%d set_irq_line(ASSERT)\n", cpunum_get_active()));
|
||||
m4510->pending_irq = 1;
|
||||
}
|
||||
}
|
||||
|
@ -222,7 +222,7 @@ INLINE void m6502_take_irq(m6502_Regs *m6502)
|
||||
P |= F_I; /* set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M6502#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M6502#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
|
||||
/* call back the cpuintrf to let it clear the line */
|
||||
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
|
||||
change_pc(PCD);
|
||||
@ -255,7 +255,7 @@ static CPU_EXECUTE( m6502 )
|
||||
/* check if the I flag was just reset (interrupts enabled) */
|
||||
if( m6502->after_cli )
|
||||
{
|
||||
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
|
||||
LOG(("M6502#%d after_cli was >0", cpunum_get_active()));
|
||||
m6502->after_cli = 0;
|
||||
if (m6502->irq_state != CLEAR_LINE)
|
||||
{
|
||||
@ -293,7 +293,7 @@ static void m6502_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
m6502->nmi_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpunum_get_active()));
|
||||
EAD = M6502_NMI_VEC;
|
||||
m6502->icount -= 2;
|
||||
PUSH(PCH);
|
||||
@ -302,7 +302,7 @@ static void m6502_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
P |= F_I; /* set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M6502#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M6502#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
|
||||
change_pc(PCD);
|
||||
}
|
||||
}
|
||||
@ -312,7 +312,7 @@ static void m6502_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
{
|
||||
if( m6502->so_state && !state )
|
||||
{
|
||||
LOG(( "M6502#%d set overflow\n", cpu_getactivecpu()));
|
||||
LOG(( "M6502#%d set overflow\n", cpunum_get_active()));
|
||||
P|=F_V;
|
||||
}
|
||||
m6502->so_state=state;
|
||||
@ -321,7 +321,7 @@ static void m6502_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
m6502->irq_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpunum_get_active()));
|
||||
m6502->pending_irq = 1;
|
||||
// m6502->pending_irq = 2;
|
||||
m6502->int_occured = m6502->icount;
|
||||
@ -452,7 +452,7 @@ INLINE void m65c02_take_irq(m6502_Regs *m6502)
|
||||
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M65c02#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M65c02#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
|
||||
/* call back the cpuintrf to let it clear the line */
|
||||
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
|
||||
change_pc(PCD);
|
||||
@ -486,7 +486,7 @@ static CPU_EXECUTE( m65c02 )
|
||||
/* check if the I flag was just reset (interrupts enabled) */
|
||||
if( m6502->after_cli )
|
||||
{
|
||||
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
|
||||
LOG(("M6502#%d after_cli was >0", cpunum_get_active()));
|
||||
m6502->after_cli = 0;
|
||||
if (m6502->irq_state != CLEAR_LINE)
|
||||
{
|
||||
@ -515,7 +515,7 @@ static void m65c02_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
m6502->nmi_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpunum_get_active()));
|
||||
EAD = M6502_NMI_VEC;
|
||||
m6502->icount -= 2;
|
||||
PUSH(PCH);
|
||||
@ -524,7 +524,7 @@ static void m65c02_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M6502#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M6502#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
|
||||
change_pc(PCD);
|
||||
}
|
||||
}
|
||||
@ -585,7 +585,7 @@ INLINE void deco16_take_irq(m6502_Regs *m6502)
|
||||
P |= F_I; /* set I flag */
|
||||
PCL = RDMEM(EAD+1);
|
||||
PCH = RDMEM(EAD);
|
||||
LOG(("M6502#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M6502#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
|
||||
/* call back the cpuintrf to let it clear the line */
|
||||
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
|
||||
change_pc(PCD);
|
||||
@ -601,7 +601,7 @@ static void deco16_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
m6502->nmi_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpunum_get_active()));
|
||||
EAD = DECO16_NMI_VEC;
|
||||
m6502->icount -= 7;
|
||||
PUSH(PCH);
|
||||
@ -610,7 +610,7 @@ static void deco16_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
P |= F_I; /* set I flag */
|
||||
PCL = RDMEM(EAD+1);
|
||||
PCH = RDMEM(EAD);
|
||||
LOG(("M6502#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M6502#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
|
||||
change_pc(PCD);
|
||||
}
|
||||
}
|
||||
@ -620,7 +620,7 @@ static void deco16_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
{
|
||||
if( m6502->so_state && !state )
|
||||
{
|
||||
LOG(( "M6502#%d set overflow\n", cpu_getactivecpu()));
|
||||
LOG(( "M6502#%d set overflow\n", cpunum_get_active()));
|
||||
P|=F_V;
|
||||
}
|
||||
m6502->so_state=state;
|
||||
@ -629,7 +629,7 @@ static void deco16_set_irq_line(m6502_Regs *m6502, int irqline, int state)
|
||||
m6502->irq_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpunum_get_active()));
|
||||
m6502->pending_irq = 1;
|
||||
}
|
||||
}
|
||||
@ -661,7 +661,7 @@ static CPU_EXECUTE( deco16 )
|
||||
/* check if the I flag was just reset (interrupts enabled) */
|
||||
if( m6502->after_cli )
|
||||
{
|
||||
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
|
||||
LOG(("M6502#%d after_cli was >0", cpunum_get_active()));
|
||||
m6502->after_cli = 0;
|
||||
if (m6502->irq_state != CLEAR_LINE)
|
||||
{
|
||||
|
@ -207,7 +207,7 @@ INLINE void m6509_take_irq( m6509_Regs *m6502)
|
||||
P |= F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M6509#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M6509#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
|
||||
/* call back the cpuintrf to let it clear the line */
|
||||
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
|
||||
change_pc(PCD);
|
||||
@ -241,7 +241,7 @@ static CPU_EXECUTE( m6509 )
|
||||
/* check if the I flag was just reset (interrupts enabled) */
|
||||
if( m6509->after_cli )
|
||||
{
|
||||
LOG(("M6509#%d after_cli was >0", cpu_getactivecpu()));
|
||||
LOG(("M6509#%d after_cli was >0", cpunum_get_active()));
|
||||
m6509->after_cli = 0;
|
||||
if (m6509->irq_state != CLEAR_LINE)
|
||||
{
|
||||
@ -272,7 +272,7 @@ static void m6509_set_irq_line(m6509_Regs *m6509, int irqline, int state)
|
||||
m6509->nmi_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "M6509#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "M6509#%d set_nmi_line(ASSERT)\n", cpunum_get_active()));
|
||||
EAD = M6509_NMI_VEC;
|
||||
EAWH = PBWH;
|
||||
m6502->icount -= 2;
|
||||
@ -282,7 +282,7 @@ static void m6509_set_irq_line(m6509_Regs *m6509, int irqline, int state)
|
||||
P |= F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M6509#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M6509#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
|
||||
change_pc(PCD);
|
||||
}
|
||||
}
|
||||
@ -292,7 +292,7 @@ static void m6509_set_irq_line(m6509_Regs *m6509, int irqline, int state)
|
||||
{
|
||||
if( m6509->so_state && !state )
|
||||
{
|
||||
LOG(( "M6509#%d set overflow\n", cpu_getactivecpu()));
|
||||
LOG(( "M6509#%d set overflow\n", cpunum_get_active()));
|
||||
P|=F_V;
|
||||
}
|
||||
m6509->so_state=state;
|
||||
@ -301,7 +301,7 @@ static void m6509_set_irq_line(m6509_Regs *m6509, int irqline, int state)
|
||||
m6509->irq_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "M6509#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "M6509#%d set_irq_line(ASSERT)\n", cpunum_get_active()));
|
||||
m6509->pending_irq = 1;
|
||||
}
|
||||
}
|
||||
|
@ -151,7 +151,7 @@ INLINE void m65ce02_take_irq(void)
|
||||
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M65ce02#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M65ce02#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
|
||||
/* call back the cpuintrf to let it clear the line */
|
||||
if (m65ce02.irq_callback) (*m65ce02.irq_callback)(m65ce02.device, 0);
|
||||
change_pc(PCD);
|
||||
@ -182,7 +182,7 @@ static CPU_EXECUTE( m65ce02 )
|
||||
/* check if the I flag was just reset (interrupts enabled) */
|
||||
if( m65ce02.after_cli )
|
||||
{
|
||||
LOG(("M65ce02#%d after_cli was >0", cpu_getactivecpu()));
|
||||
LOG(("M65ce02#%d after_cli was >0", cpunum_get_active()));
|
||||
m65ce02.after_cli = 0;
|
||||
if (m65ce02.irq_state != CLEAR_LINE)
|
||||
{
|
||||
@ -211,7 +211,7 @@ static void m65ce02_set_irq_line(int irqline, int state)
|
||||
m65ce02.nmi_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(("M65ce02#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(("M65ce02#%d set_nmi_line(ASSERT)\n", cpunum_get_active()));
|
||||
EAD = M65CE02_NMI_VEC;
|
||||
m65ce02->icount -= 7;
|
||||
PUSH(PCH);
|
||||
@ -220,7 +220,7 @@ static void m65ce02_set_irq_line(int irqline, int state)
|
||||
P = (P & ~F_D) | F_I; /* knock out D and set I flag */
|
||||
PCL = RDMEM(EAD);
|
||||
PCH = RDMEM(EAD+1);
|
||||
LOG(("M65ce02#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
|
||||
LOG(("M65ce02#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
|
||||
change_pc(PCD);
|
||||
}
|
||||
}
|
||||
@ -229,7 +229,7 @@ static void m65ce02_set_irq_line(int irqline, int state)
|
||||
m65ce02.irq_state = state;
|
||||
if( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(("M65ce02#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(("M65ce02#%d set_irq_line(ASSERT)\n", cpunum_get_active()));
|
||||
m65ce02.pending_irq = 1;
|
||||
}
|
||||
}
|
||||
|
@ -626,7 +626,7 @@
|
||||
if ( P & F_I ) { \
|
||||
PULL(P); \
|
||||
if ((m6502->irq_state != CLEAR_LINE) && !(P & F_I)) { \
|
||||
LOG(("M6502#%d PLP sets after_cli\n",cpu_getactivecpu())); \
|
||||
LOG(("M6502#%d PLP sets after_cli\n",cpunum_get_active())); \
|
||||
m6502->after_cli = 1; \
|
||||
} \
|
||||
} else { \
|
||||
@ -668,7 +668,7 @@
|
||||
P |= F_T | F_B; \
|
||||
if( (m6502->irq_state != CLEAR_LINE) && !(P & F_I) ) \
|
||||
{ \
|
||||
LOG(("M6502#%d RTI sets after_cli\n",cpu_getactivecpu())); \
|
||||
LOG(("M6502#%d RTI sets after_cli\n",cpunum_get_active())); \
|
||||
m6502->after_cli = 1; \
|
||||
} \
|
||||
CHANGE_PC
|
||||
|
@ -289,7 +289,7 @@
|
||||
t1=RDOPARG(); \
|
||||
t2=RDOPARG(); \
|
||||
t3=RDOPARG(); \
|
||||
logerror("m65ce02 at pc:%.4x reserved op aug %.2x %.2x %.2x\n", activecpu_get_pc(),t1,t2,t3);
|
||||
logerror("m65ce02 at pc:%.4x reserved op aug %.2x %.2x %.2x\n", cpu_get_pc(machine->activecpu),t1,t2,t3);
|
||||
|
||||
/* 65ce02 ******************************************************
|
||||
* BBR Branch if bit is reset
|
||||
@ -684,7 +684,7 @@
|
||||
PULL(temp); \
|
||||
P=(P&F_E)|F_B|(temp&~F_E); \
|
||||
if( IRQ_STATE != CLEAR_LINE && !(P & F_I) ) { \
|
||||
LOG(("M65ce02#%d PLP sets after_cli\n", cpu_getactivecpu())); \
|
||||
LOG(("M65ce02#%d PLP sets after_cli\n", cpunum_get_active())); \
|
||||
AFTER_CLI = 1; \
|
||||
} \
|
||||
} else { \
|
||||
@ -764,7 +764,7 @@
|
||||
PULL(PCH); \
|
||||
if( IRQ_STATE != CLEAR_LINE && !(P & F_I) ) \
|
||||
{ \
|
||||
LOG(("M65ce02#%d RTI sets after_cli\n", cpu_getactivecpu())); \
|
||||
LOG(("M65ce02#%d RTI sets after_cli\n", cpunum_get_active())); \
|
||||
AFTER_CLI = 1; \
|
||||
} \
|
||||
CHANGE_PC
|
||||
@ -797,7 +797,7 @@
|
||||
PULL(PCL); \
|
||||
PULL(PCH); \
|
||||
if( IRQ_STATE != CLEAR_LINE && !(P & F_I) ) { \
|
||||
LOG(("M65ce02#%d RTI sets after_cli\n", cpu_getactivecpu())); \
|
||||
LOG(("M65ce02#%d RTI sets after_cli\n", cpunum_get_active())); \
|
||||
AFTER_CLI = 1; \
|
||||
} \
|
||||
CHANGE_PC
|
||||
|
@ -9,7 +9,7 @@
|
||||
#define OP(nn) INLINE void deco16_##nn(m6502_Regs *m6502)
|
||||
|
||||
#define DECO16_BRK \
|
||||
logerror("%04x: BRK\n",activecpu_get_pc()); \
|
||||
logerror("%04x: BRK\n",cpu_get_pc(Machine->activecpu)); \
|
||||
RDOPARG(); \
|
||||
PUSH(PCH); \
|
||||
PUSH(PCL); \
|
||||
@ -89,7 +89,7 @@ OP(23) {
|
||||
RD_IMM;
|
||||
|
||||
if (DECO16_VERBOSE)
|
||||
logerror("%04x: OP23 %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OP23 %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
}
|
||||
OP(43) { RD_DUM; ILL; } /* 2 ILL */
|
||||
OP(63) {
|
||||
@ -99,7 +99,7 @@ OP(63) {
|
||||
RD_IMM;
|
||||
|
||||
if (DECO16_VERBOSE)
|
||||
logerror("%04x: OP63 %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OP63 %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
}
|
||||
OP(83) { RD_DUM; ILL; } /* 2 ILL */
|
||||
OP(a3) {
|
||||
@ -109,7 +109,7 @@ OP(a3) {
|
||||
RD_IMM;
|
||||
|
||||
if (DECO16_VERBOSE)
|
||||
logerror("%04x: OPA3 %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OPA3 %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
}
|
||||
OP(c3) { RD_DUM; ILL; } /* 2 ILL */
|
||||
OP(e3) { RD_DUM; ILL; } /* 2 ILL */
|
||||
@ -117,7 +117,7 @@ OP(e3) { RD_DUM; ILL; } /* 2 ILL */
|
||||
OP(13) { int tmp; m6502->icount -= 1; RD_IMM;
|
||||
|
||||
if (DECO16_VERBOSE)
|
||||
logerror("%04x: OP13 %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OP13 %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
|
||||
//bank select control?
|
||||
|
||||
@ -191,13 +191,13 @@ OP(67) {
|
||||
int tmp; RD_IMM;
|
||||
m6502->a=io_read_byte_8le(0);
|
||||
|
||||
// logerror("%04x: VBL (0x67)\n",activecpu_get_pc());
|
||||
// logerror("%04x: VBL (0x67)\n",cpu_get_pc(Machine->activecpu));
|
||||
|
||||
// really - wait for status?
|
||||
|
||||
} /* */
|
||||
OP(87) { int tmp; m6502->icount -= 1; RD_IMM;
|
||||
logerror("%04x: OP87 %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OP87 %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
|
||||
} /* */
|
||||
OP(a7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB2 ZPG ?? */
|
||||
@ -268,12 +268,12 @@ OP(f7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB7 ZPG ?? */
|
||||
#define deco16_fa m65c02_fa /* 4 PLX */
|
||||
|
||||
OP(0b) { int tmp; m6502->icount -= 1; RD_IMM;
|
||||
logerror("%04x: OP0B %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OP0B %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
|
||||
}
|
||||
OP(2b) { RD_DUM; ILL; } /* 2 ILL */
|
||||
OP(4b) { int tmp; m6502->icount -= 1; RD_IMM;
|
||||
logerror("%04x: OP4B %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OP4B %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
|
||||
// m6502->a=io_read_byte_8le(0);
|
||||
|
||||
@ -301,7 +301,7 @@ OP(bb) {
|
||||
RD_IMM;
|
||||
|
||||
if (DECO16_VERBOSE)
|
||||
logerror("%04x: OPBB %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OPBB %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
}
|
||||
OP(db) { RD_DUM; ILL; } /* 2 ILL */
|
||||
OP(fb) { RD_DUM; ILL; } /* 2 ILL */
|
||||
@ -365,7 +365,7 @@ OP(2f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR2 ZPG ?? */
|
||||
OP(4f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR4 ZPG ?? */
|
||||
OP(6f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR6 ZPG ?? */
|
||||
OP(8f) { int tmp; m6502->icount -= 1; RD_IMM;
|
||||
logerror("%04x: BANK (8F) %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: BANK (8F) %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
|
||||
io_write_byte_8le(0,tmp);
|
||||
|
||||
@ -384,7 +384,7 @@ OP(3f) {
|
||||
RD_IMM;
|
||||
|
||||
if (DECO16_VERBOSE)
|
||||
logerror("%04x: OP3F %02x\n",activecpu_get_pc(),tmp);
|
||||
logerror("%04x: OP3F %02x\n",cpu_get_pc(Machine->activecpu),tmp);
|
||||
}
|
||||
OP(5f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR5 ZPG ?? */
|
||||
OP(7f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR7 ZPG ?? */
|
||||
|
@ -524,7 +524,7 @@ INLINE void WM16( UINT32 Addr, PAIR *p )
|
||||
/* IRQ enter */
|
||||
static void ENTER_INTERRUPT(const char *message,UINT16 irq_vector)
|
||||
{
|
||||
LOG((message, cpu_getactivecpu()));
|
||||
LOG((message, cpunum_get_active()));
|
||||
if( m68xx.wai_state & (M6800_WAI|M6800_SLP) )
|
||||
{
|
||||
if( m68xx.wai_state & M6800_WAI )
|
||||
@ -674,9 +674,9 @@ static TIMER_CALLBACK(m6800_tx_tick)
|
||||
// send stop bit '1'
|
||||
m68xx.tx = 1;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
CHECK_IRQ_LINES();
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
m68xx.txbits = M6800_SERIAL_START;
|
||||
break;
|
||||
@ -746,9 +746,9 @@ static TIMER_CALLBACK(m6800_rx_tick)
|
||||
|
||||
m68xx.trcsr |= M6800_TRCSR_ORFE;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
CHECK_IRQ_LINES();
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -760,9 +760,9 @@ static TIMER_CALLBACK(m6800_rx_tick)
|
||||
// set RDRF flag
|
||||
m68xx.trcsr |= M6800_TRCSR_RDRF;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
CHECK_IRQ_LINES();
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -779,9 +779,9 @@ static TIMER_CALLBACK(m6800_rx_tick)
|
||||
m68xx.trcsr |= M6800_TRCSR_ORFE;
|
||||
m68xx.trcsr &= ~M6800_TRCSR_RDRF;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
CHECK_IRQ_LINES();
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
m68xx.rxbits = M6800_SERIAL_START;
|
||||
@ -927,7 +927,7 @@ static void set_irq_line(int irqline, int state)
|
||||
if (irqline == INPUT_LINE_NMI)
|
||||
{
|
||||
if (m68xx.nmi_state == state) return;
|
||||
LOG(("M6800#%d set_nmi_line %d \n", cpu_getactivecpu(), state));
|
||||
LOG(("M6800#%d set_nmi_line %d \n", cpunum_get_active(), state));
|
||||
m68xx.nmi_state = state;
|
||||
if (state == CLEAR_LINE) return;
|
||||
|
||||
@ -939,7 +939,7 @@ static void set_irq_line(int irqline, int state)
|
||||
int eddge;
|
||||
|
||||
if (m68xx.irq_state[irqline] == state) return;
|
||||
LOG(("M6800#%d set_irq_line %d,%d\n", cpu_getactivecpu(), irqline, state));
|
||||
LOG(("M6800#%d set_irq_line %d,%d\n", cpunum_get_active(), irqline, state));
|
||||
m68xx.irq_state[irqline] = state;
|
||||
|
||||
switch(irqline)
|
||||
@ -2348,7 +2348,7 @@ static READ8_HANDLER( m6803_internal_registers_r )
|
||||
case 0x0e:
|
||||
return (m68xx.input_capture >> 8) & 0xff;
|
||||
case 0x0f:
|
||||
logerror("CPU #%d PC %04x: warning - read from unsupported register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),offset);
|
||||
logerror("CPU #%d PC %04x: warning - read from unsupported register %02x\n",cpunum_get_active(),cpu_get_pc(machine->activecpu),offset);
|
||||
return 0;
|
||||
case 0x10:
|
||||
return m68xx.rmcr;
|
||||
@ -2365,7 +2365,7 @@ static READ8_HANDLER( m6803_internal_registers_r )
|
||||
case 0x13:
|
||||
return m68xx.tdr;
|
||||
case 0x14:
|
||||
logerror("CPU #%d PC %04x: read RAM control register\n",cpu_getactivecpu(),activecpu_get_pc());
|
||||
logerror("CPU #%d PC %04x: read RAM control register\n",cpunum_get_active(),cpu_get_pc(machine->activecpu));
|
||||
return m68xx.ram_ctrl;
|
||||
case 0x15:
|
||||
case 0x16:
|
||||
@ -2379,7 +2379,7 @@ static READ8_HANDLER( m6803_internal_registers_r )
|
||||
case 0x1e:
|
||||
case 0x1f:
|
||||
default:
|
||||
logerror("CPU #%d PC %04x: warning - read from reserved internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),offset);
|
||||
logerror("CPU #%d PC %04x: warning - read from reserved internal register %02x\n",cpunum_get_active(),cpu_get_pc(machine->activecpu),offset);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@ -2412,7 +2412,7 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
| (io_read_byte_8be(M6803_PORT2) & (m68xx.port2_ddr ^ 0xff)));
|
||||
|
||||
if (m68xx.port2_ddr & 2)
|
||||
logerror("CPU #%d PC %04x: warning - port 2 bit 1 set as output (OLVL) - not supported\n",cpu_getactivecpu(),activecpu_get_pc());
|
||||
logerror("CPU #%d PC %04x: warning - port 2 bit 1 set as output (OLVL) - not supported\n",cpunum_get_active(),cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
break;
|
||||
case 0x02:
|
||||
@ -2511,10 +2511,10 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x12:
|
||||
logerror("CPU #%d PC %04x: warning - write %02x to read only internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),data,offset);
|
||||
logerror("CPU #%d PC %04x: warning - write %02x to read only internal register %02x\n",cpunum_get_active(),cpu_get_pc(machine->activecpu),data,offset);
|
||||
break;
|
||||
case 0x0f:
|
||||
logerror("CPU #%d PC %04x: warning - write %02x to unsupported internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),data,offset);
|
||||
logerror("CPU #%d PC %04x: warning - write %02x to unsupported internal register %02x\n",cpunum_get_active(),cpu_get_pc(machine->activecpu),data,offset);
|
||||
break;
|
||||
case 0x10:
|
||||
m68xx.rmcr = data & 0x0f;
|
||||
@ -2532,8 +2532,8 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
{
|
||||
int divisor = M6800_RMCR_SS[m68xx.rmcr & M6800_RMCR_SS_MASK];
|
||||
|
||||
timer_adjust_periodic(m6800_rx_timer, attotime_zero, cpu_getactivecpu(), ATTOTIME_IN_HZ(m68xx.clock / divisor));
|
||||
timer_adjust_periodic(m6800_tx_timer, attotime_zero, cpu_getactivecpu(), ATTOTIME_IN_HZ(m68xx.clock / divisor));
|
||||
timer_adjust_periodic(m6800_rx_timer, attotime_zero, cpunum_get_active(), ATTOTIME_IN_HZ(m68xx.clock / divisor));
|
||||
timer_adjust_periodic(m6800_tx_timer, attotime_zero, cpunum_get_active(), ATTOTIME_IN_HZ(m68xx.clock / divisor));
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -2554,7 +2554,7 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
m68xx.tdr = data;
|
||||
break;
|
||||
case 0x14:
|
||||
logerror("CPU #%d PC %04x: write %02x to RAM control register\n",cpu_getactivecpu(),activecpu_get_pc(),data);
|
||||
logerror("CPU #%d PC %04x: write %02x to RAM control register\n",cpunum_get_active(),cpu_get_pc(machine->activecpu),data);
|
||||
m68xx.ram_ctrl = data;
|
||||
break;
|
||||
case 0x15:
|
||||
@ -2569,7 +2569,7 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
case 0x1e:
|
||||
case 0x1f:
|
||||
default:
|
||||
logerror("CPU #%d PC %04x: warning - write %02x to reserved internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),data,offset);
|
||||
logerror("CPU #%d PC %04x: warning - write %02x to reserved internal register %02x\n",cpunum_get_active(),cpu_get_pc(machine->activecpu),data,offset);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -3284,7 +3284,7 @@ M68KMAKE_OP(callm, 32, ., .)
|
||||
REG_PC += 2;
|
||||
(void)ea; /* just to avoid an 'unused variable' warning */
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68k_disassemble_quick(ADDRESS_68K(m68k, REG_PC - 2))));
|
||||
return;
|
||||
}
|
||||
@ -4362,7 +4362,7 @@ M68KMAKE_OP(cpbcc, 32, ., .)
|
||||
if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
|
||||
{
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68k_disassemble_quick(ADDRESS_68K(m68k, REG_PC - 2))));
|
||||
return;
|
||||
}
|
||||
@ -4375,7 +4375,7 @@ M68KMAKE_OP(cpdbcc, 32, ., .)
|
||||
if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
|
||||
{
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68k_disassemble_quick(ADDRESS_68K(m68k, REG_PC - 2))));
|
||||
return;
|
||||
}
|
||||
@ -4388,7 +4388,7 @@ M68KMAKE_OP(cpgen, 32, ., .)
|
||||
if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
|
||||
{
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68k_disassemble_quick(ADDRESS_68K(m68k, REG_PC - 2))));
|
||||
return;
|
||||
}
|
||||
@ -4401,7 +4401,7 @@ M68KMAKE_OP(cpscc, 32, ., .)
|
||||
if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
|
||||
{
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68k_disassemble_quick(ADDRESS_68K(m68k, REG_PC - 2))));
|
||||
return;
|
||||
}
|
||||
@ -4414,7 +4414,7 @@ M68KMAKE_OP(cptrapcc, 32, ., .)
|
||||
if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
|
||||
{
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68k_disassemble_quick(ADDRESS_68K(m68k, REG_PC - 2))));
|
||||
return;
|
||||
}
|
||||
@ -9326,7 +9326,7 @@ M68KMAKE_OP(rtm, 32, ., .)
|
||||
{
|
||||
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC - 2), m68k->ir,
|
||||
m68k_disassemble_quick(ADDRESS_68K(m68k, REG_PC - 2))));
|
||||
return;
|
||||
}
|
||||
|
@ -45,7 +45,7 @@ extern void m68040_fpu_op1(m68ki_cpu_core *m68k);
|
||||
/* ======================================================================== */
|
||||
|
||||
#ifdef M68K_LOG_ENABLE
|
||||
const char *const m68ki_cpu_names[] =
|
||||
const char *const m68ki_cpu_get_names[] =
|
||||
{
|
||||
"Invalid CPU",
|
||||
"M68000",
|
||||
|
@ -355,7 +355,7 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
|
||||
#if M68K_LOG_ENABLE
|
||||
#include <stdio.h>
|
||||
extern FILE* M68K_LOG_FILEHANDLE
|
||||
extern const char *const m68ki_cpu_names[];
|
||||
extern const char *const m68ki_cpu_get_names[];
|
||||
|
||||
#define M68K_DO_LOG(A) if(M68K_LOG_FILEHANDLE) fprintf A
|
||||
#if M68K_LOG_1010_1111
|
||||
@ -1625,7 +1625,7 @@ INLINE void m68ki_exception_1010(m68ki_cpu_core *m68k)
|
||||
UINT32 sr;
|
||||
#if M68K_LOG_1010_1111 == OPT_ON
|
||||
M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PPC), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PPC), m68k->ir,
|
||||
m68ki_disassemble_quick(ADDRESS_68K(m68k, REG_PPC))));
|
||||
#endif
|
||||
|
||||
@ -1644,7 +1644,7 @@ INLINE void m68ki_exception_1111(m68ki_cpu_core *m68k)
|
||||
|
||||
#if M68K_LOG_1010_1111 == OPT_ON
|
||||
M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PPC), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PPC), m68k->ir,
|
||||
m68ki_disassemble_quick(ADDRESS_68K(m68k, REG_PPC))));
|
||||
#endif
|
||||
|
||||
@ -1662,7 +1662,7 @@ INLINE void m68ki_exception_illegal(m68ki_cpu_core *m68k)
|
||||
UINT32 sr;
|
||||
|
||||
M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PPC), m68k->ir,
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PPC), m68k->ir,
|
||||
m68ki_disassemble_quick(ADDRESS_68K(m68k, REG_PPC))));
|
||||
|
||||
sr = m68ki_init_exception(m68k);
|
||||
@ -1749,7 +1749,7 @@ void m68ki_exception_interrupt(m68ki_cpu_core *m68k, UINT32 int_level)
|
||||
else if(vector > 255)
|
||||
{
|
||||
M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n",
|
||||
m68ki_cpu_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC), vector));
|
||||
m68ki_cpu_get_names[m68k->cpu_type], ADDRESS_68K(m68k, REG_PC), vector));
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -70,8 +70,8 @@ INLINE unsigned int m68kx_read_immediate_32(m68ki_cpu_core *m68k, unsigned int a
|
||||
|
||||
INLINE unsigned int m68kx_read_pcrelative_8(m68ki_cpu_core *m68k, unsigned int address)
|
||||
{
|
||||
if (address >= m68k_encrypted_opcode_start[cpu_getactivecpu()] &&
|
||||
address < m68k_encrypted_opcode_end[cpu_getactivecpu()])
|
||||
if (address >= m68k_encrypted_opcode_start[cpunum_get_active()] &&
|
||||
address < m68k_encrypted_opcode_end[cpunum_get_active()])
|
||||
return ((m68k_read_immediate_16(m68k, address&~1)>>(8*(1-(address & 1))))&0xff);
|
||||
else
|
||||
return m68k_read_memory_8(m68k, address);
|
||||
@ -79,8 +79,8 @@ INLINE unsigned int m68kx_read_pcrelative_8(m68ki_cpu_core *m68k, unsigned int a
|
||||
|
||||
INLINE unsigned int m68kx_read_pcrelative_16(m68ki_cpu_core *m68k, unsigned int address)
|
||||
{
|
||||
if (address >= m68k_encrypted_opcode_start[cpu_getactivecpu()] &&
|
||||
address < m68k_encrypted_opcode_end[cpu_getactivecpu()])
|
||||
if (address >= m68k_encrypted_opcode_start[cpunum_get_active()] &&
|
||||
address < m68k_encrypted_opcode_end[cpunum_get_active()])
|
||||
return m68k_read_immediate_16(m68k, address);
|
||||
else
|
||||
return m68k_read_memory_16(m68k, address);
|
||||
@ -88,8 +88,8 @@ INLINE unsigned int m68kx_read_pcrelative_16(m68ki_cpu_core *m68k, unsigned int
|
||||
|
||||
INLINE unsigned int m68kx_read_pcrelative_32(m68ki_cpu_core *m68k, unsigned int address)
|
||||
{
|
||||
if (address >= m68k_encrypted_opcode_start[cpu_getactivecpu()] &&
|
||||
address < m68k_encrypted_opcode_end[cpu_getactivecpu()])
|
||||
if (address >= m68k_encrypted_opcode_start[cpunum_get_active()] &&
|
||||
address < m68k_encrypted_opcode_end[cpunum_get_active()])
|
||||
return m68k_read_immediate_32(m68k, address);
|
||||
else
|
||||
return m68k_read_memory_32(m68k, address);
|
||||
|
@ -468,7 +468,7 @@ static void set_irq_line(int irqline, int state)
|
||||
{
|
||||
if (m6809.nmi_state == state) return;
|
||||
m6809.nmi_state = state;
|
||||
LOG(("M6809#%d set_irq_line (NMI) %d\n", cpu_getactivecpu(), state));
|
||||
LOG(("M6809#%d set_irq_line (NMI) %d\n", cpunum_get_active(), state));
|
||||
if( state == CLEAR_LINE ) return;
|
||||
|
||||
/* if the stack was not yet initialized */
|
||||
@ -500,7 +500,7 @@ static void set_irq_line(int irqline, int state)
|
||||
}
|
||||
else if (irqline < 2)
|
||||
{
|
||||
LOG(("M6809#%d set_irq_line %d, %d\n", cpu_getactivecpu(), irqline, state));
|
||||
LOG(("M6809#%d set_irq_line %d, %d\n", cpunum_get_active(), irqline, state));
|
||||
m6809.irq_state[irqline] = state;
|
||||
if (state == CLEAR_LINE) return;
|
||||
CHECK_IRQ_LINES();
|
||||
|
@ -216,7 +216,7 @@ INLINE UINT8 argument_fetch(offs_t address)
|
||||
|
||||
INLINE void update_regptr(mcs48_state *mcs48)
|
||||
{
|
||||
mcs48->regptr = memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_DATA, (PSW & B_FLAG) ? 24 : 0);
|
||||
mcs48->regptr = memory_get_write_ptr(cpunum_get_active(), ADDRESS_SPACE_DATA, (PSW & B_FLAG) ? 24 : 0);
|
||||
}
|
||||
|
||||
|
||||
|
@ -675,8 +675,8 @@ INLINE UINT8 r_psw(mcs51_state_t *mcs51_state) { return SFR_A(ADDR_PSW); }
|
||||
|
||||
INLINE void update_ptrs(mcs51_state_t *mcs51_state)
|
||||
{
|
||||
mcs51_state->internal_ram = memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_DATA, 0x00);
|
||||
mcs51_state->sfr_ram = memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_DATA, 0x100);
|
||||
mcs51_state->internal_ram = memory_get_write_ptr(cpunum_get_active(), ADDRESS_SPACE_DATA, 0x00);
|
||||
mcs51_state->sfr_ram = memory_get_write_ptr(cpunum_get_active(), ADDRESS_SPACE_DATA, 0x100);
|
||||
}
|
||||
|
||||
|
||||
@ -2006,7 +2006,7 @@ static void mcs51_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8 dat
|
||||
case ADDR_SCON:
|
||||
break;
|
||||
default:
|
||||
LOG(("mcs51 #%d: attemping to write to an invalid/non-implemented SFR address: %zx at 0x%04x, data=%x\n", cpu_getactivecpu(), offset,PC,data));
|
||||
LOG(("mcs51 #%d: attemping to write to an invalid/non-implemented SFR address: %zx at 0x%04x, data=%x\n", cpunum_get_active(), offset,PC,data));
|
||||
/* no write in this case according to manual */
|
||||
return;
|
||||
}
|
||||
@ -2046,7 +2046,7 @@ static UINT8 mcs51_sfr_read(mcs51_state_t *mcs51_state, size_t offset)
|
||||
return data_read_byte_8le((size_t) offset | 0x100);
|
||||
/* Illegal or non-implemented sfr */
|
||||
default:
|
||||
LOG(("mcs51 #%d: attemping to read an invalid/non-implemented SFR address: %zx at 0x%04x\n", cpu_getactivecpu(), offset,PC));
|
||||
LOG(("mcs51 #%d: attemping to read an invalid/non-implemented SFR address: %zx at 0x%04x\n", cpunum_get_active(), offset,PC));
|
||||
/* according to the manual, the read may return random bits */
|
||||
return 0xff;
|
||||
}
|
||||
@ -2298,8 +2298,8 @@ static CPU_INIT( i80c31 )
|
||||
#if 1 //#ifdef MCS51_TO_BE_ENABLED_LATER
|
||||
|
||||
|
||||
#define DS5_LOGW(a, d) LOG(("ds5002fp #%d: write to " # a " register at 0x%04x, data=%x\n", cpu_getactivecpu(), PC, d))
|
||||
#define DS5_LOGR(a, d) LOG(("ds5002fp #%d: read from " # a " register at 0x%04x\n", cpu_getactivecpu(), PC))
|
||||
#define DS5_LOGW(a, d) LOG(("ds5002fp #%d: write to " # a " register at 0x%04x, data=%x\n", cpunum_get_active(), PC, d))
|
||||
#define DS5_LOGR(a, d) LOG(("ds5002fp #%d: read from " # a " register at 0x%04x\n", cpunum_get_active(), PC))
|
||||
|
||||
INLINE UINT8 ds5002fp_protected(mcs51_state_t *mcs51_state, size_t offset, UINT8 data, UINT8 ta_mask, UINT8 mask)
|
||||
{
|
||||
@ -2325,7 +2325,7 @@ static void ds5002fp_sfr_write(mcs51_state_t *mcs51_state, size_t offset, UINT8
|
||||
if ((data == 0xaa) && (mcs51_state->ds5002fp.ta_window == 0))
|
||||
{
|
||||
mcs51_state->ds5002fp.ta_window = 6; /* 4*12 + 2*12 */
|
||||
LOG(("ds5002fp #%d: TA window initiated at 0x%04x\n", cpu_getactivecpu(), PC));
|
||||
LOG(("ds5002fp #%d: TA window initiated at 0x%04x\n", cpunum_get_active(), PC));
|
||||
}
|
||||
break;
|
||||
case ADDR_MCON: data = ds5002fp_protected(mcs51_state, ADDR_MCON, data, 0x0f, 0xf7); DS5_LOGW(MCON, data); break;
|
||||
|
@ -995,5 +995,5 @@ OPHANDLER( xrl_a_r )
|
||||
//illegal opcodes
|
||||
OPHANDLER( illegal )
|
||||
{
|
||||
LOG(("i8051 #%d: illegal opcode at 0x%03x: %02x\n", cpu_getactivecpu(), PC-1, r));
|
||||
LOG(("i8051 #%d: illegal opcode at 0x%03x: %02x\n", cpunum_get_active(), PC-1, r));
|
||||
}
|
||||
|
@ -89,7 +89,7 @@ void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, const
|
||||
mips->memory = *memory_get_accessors(ADDRESS_SPACE_PROGRAM, 32, mips->bigendian ? CPU_IS_BE : CPU_IS_LE);
|
||||
|
||||
/* allocate the virtual TLB */
|
||||
mips->vtlb = vtlb_alloc(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, 2 * MIPS3_TLB_ENTRIES + 2, 0);
|
||||
mips->vtlb = vtlb_alloc(device, ADDRESS_SPACE_PROGRAM, 2 * MIPS3_TLB_ENTRIES + 2, 0);
|
||||
|
||||
/* allocate a timer for the compare interrupt */
|
||||
mips->compare_int_timer = timer_alloc(compare_int_callback, NULL);
|
||||
@ -191,11 +191,11 @@ void mips3com_update_cycle_counting(mips3_state *mips)
|
||||
UINT32 count = (activecpu_gettotalcycles() - mips->count_zero_time) / 2;
|
||||
UINT32 compare = mips->cpr[0][COP0_Compare];
|
||||
UINT32 delta = compare - count;
|
||||
attotime newtime = ATTOTIME_IN_CYCLES(((UINT64)delta * 2), cpu_getactivecpu());
|
||||
timer_adjust_oneshot(mips->compare_int_timer, newtime, cpu_getactivecpu());
|
||||
attotime newtime = ATTOTIME_IN_CYCLES(((UINT64)delta * 2), cpunum_get_active());
|
||||
timer_adjust_oneshot(mips->compare_int_timer, newtime, cpunum_get_active());
|
||||
return;
|
||||
}
|
||||
timer_adjust_oneshot(mips->compare_int_timer, attotime_never, cpu_getactivecpu());
|
||||
timer_adjust_oneshot(mips->compare_int_timer, attotime_never, cpunum_get_active());
|
||||
}
|
||||
|
||||
|
||||
|
@ -430,7 +430,7 @@ static void mips3_init(mips3_flavor flavor, int bigendian, const device_config *
|
||||
/* initialize the front-end helper */
|
||||
if (SINGLE_INSTRUCTION_MODE)
|
||||
feconfig.max_sequence = 1;
|
||||
mips3->impstate->drcfe = drcfe_init(&feconfig, mips3);
|
||||
mips3->impstate->drcfe = drcfe_init(device, &feconfig, mips3);
|
||||
|
||||
/* allocate memory for cache-local state and initialize it */
|
||||
memcpy(mips3->impstate->fpmode, fpmode_source, sizeof(fpmode_source));
|
||||
@ -767,7 +767,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
|
||||
}
|
||||
|
||||
/* validate this code block if we're not pointing into ROM */
|
||||
if (memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, seqhead->physpc) != NULL)
|
||||
if (memory_get_write_ptr(cpunum_get_active(), ADDRESS_SPACE_PROGRAM, seqhead->physpc) != NULL)
|
||||
generate_checksum_block(block, &compiler, seqhead, seqlast);
|
||||
|
||||
/* label this instruction, if it may be jumped to locally */
|
||||
|
@ -4,6 +4,8 @@
|
||||
*/
|
||||
|
||||
#include "psx.h"
|
||||
#include "driver.h"
|
||||
#include "deprecat.h"
|
||||
|
||||
static char *make_signed_hex_str_16( UINT32 value )
|
||||
{
|
||||
@ -122,10 +124,10 @@ static char *effective_address( UINT32 pc, UINT32 op )
|
||||
{
|
||||
static char s_address[ 20 ];
|
||||
#ifndef STANDALONE
|
||||
if( pc == activecpu_get_pc() )
|
||||
if( pc == cpu_get_pc(Machine->activecpu) )
|
||||
{
|
||||
sprintf( s_address, "%s(%s) ; 0x%08x", make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ],
|
||||
(UINT32)( activecpu_get_reg( MIPS_R0 + INS_RS( op ) ) + (INT16)INS_IMMEDIATE( op ) ) );
|
||||
(UINT32)( cpu_get_reg( Machine->activecpu, MIPS_R0 + INS_RS( op ) ) + (INT16)INS_IMMEDIATE( op ) ) );
|
||||
return s_address;
|
||||
}
|
||||
#endif
|
||||
@ -137,9 +139,9 @@ static UINT32 relative_address( UINT32 pc, UINT32 op )
|
||||
{
|
||||
UINT32 nextpc = pc + 4;
|
||||
#ifndef STANDALONE
|
||||
if( pc == activecpu_get_pc() && activecpu_get_reg( MIPS_DELAYR ) == 32 )
|
||||
if( pc == cpu_get_pc(Machine->activecpu) && cpu_get_reg( Machine->activecpu, MIPS_DELAYR ) == 32 )
|
||||
{
|
||||
nextpc = activecpu_get_reg( MIPS_DELAYV );
|
||||
nextpc = cpu_get_reg( Machine->activecpu, MIPS_DELAYV );
|
||||
}
|
||||
#endif
|
||||
return nextpc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 );
|
||||
@ -149,9 +151,9 @@ static UINT32 jump_address( UINT32 pc, UINT32 op )
|
||||
{
|
||||
UINT32 nextpc = pc + 4;
|
||||
#ifndef STANDALONE
|
||||
if( pc == activecpu_get_pc() && activecpu_get_reg( MIPS_DELAYR ) == 32 )
|
||||
if( pc == cpu_get_pc(Machine->activecpu) && cpu_get_reg( Machine->activecpu, MIPS_DELAYR ) == 32 )
|
||||
{
|
||||
nextpc = activecpu_get_reg( MIPS_DELAYV );
|
||||
nextpc = cpu_get_reg( Machine->activecpu, MIPS_DELAYV );
|
||||
}
|
||||
#endif
|
||||
return ( nextpc & 0xf0000000 ) + ( INS_TARGET( op ) << 2 );
|
||||
|
@ -581,11 +581,11 @@ static UINT32 log_bioscall_parameter( int parm )
|
||||
{
|
||||
if( parm < 4 )
|
||||
{
|
||||
return activecpu_get_reg( MIPS_R4 + parm );
|
||||
return cpu_get_reg( Machine->activecpu, MIPS_R4 + parm );
|
||||
}
|
||||
else
|
||||
{
|
||||
return mipscpu.readword( activecpu_get_reg( MIPS_R29 ) + ( parm * 4 ) );
|
||||
return mipscpu.readword( cpu_get_reg( Machine->activecpu, MIPS_R29 ) + ( parm * 4 ) );
|
||||
}
|
||||
}
|
||||
|
||||
@ -675,13 +675,13 @@ static const char *log_bioscall_char( int parm )
|
||||
|
||||
static void log_bioscall( void )
|
||||
{
|
||||
int address = activecpu_get_reg( MIPS_PC ) - 0x04;
|
||||
int address = cpu_get_reg( Machine->activecpu, MIPS_PC ) - 0x04;
|
||||
if( address == 0xa0 ||
|
||||
address == 0xb0 ||
|
||||
address == 0xc0 )
|
||||
{
|
||||
char buf[ 1024 ];
|
||||
int operation = activecpu_get_reg( MIPS_R9 ) & 0xff;
|
||||
int operation = cpu_get_reg( Machine->activecpu, MIPS_R9 ) & 0xff;
|
||||
int bioscall = 0;
|
||||
|
||||
if( ( address == 0xa0 && operation == 0x3c ) ||
|
||||
@ -907,14 +907,14 @@ static void log_bioscall( void )
|
||||
{
|
||||
sprintf( buf, "unknown_%02x_%02x", address, operation );
|
||||
}
|
||||
logerror( "%08x: bioscall %s\n", (unsigned int)activecpu_get_reg( MIPS_R31 ) - 8, buf );
|
||||
logerror( "%08x: bioscall %s\n", (unsigned int)cpu_get_reg( Machine->activecpu, MIPS_R31 ) - 8, buf );
|
||||
}
|
||||
}
|
||||
|
||||
static void log_syscall( void )
|
||||
{
|
||||
char buf[ 1024 ];
|
||||
int operation = activecpu_get_reg( MIPS_R4 );
|
||||
int operation = cpu_get_reg( Machine->activecpu, MIPS_R4 );
|
||||
|
||||
switch( operation )
|
||||
{
|
||||
@ -934,7 +934,7 @@ static void log_syscall( void )
|
||||
sprintf( buf, "unknown_%02x", operation );
|
||||
break;
|
||||
}
|
||||
logerror( "%08x: syscall %s\n", (unsigned int)activecpu_get_reg( MIPS_R31 ) - 8, buf );
|
||||
logerror( "%08x: syscall %s\n", (unsigned int)cpu_get_reg( Machine->activecpu, MIPS_R31 ) - 8, buf );
|
||||
}
|
||||
|
||||
static UINT32 mips_cache_readword( UINT32 offset )
|
||||
@ -1251,7 +1251,7 @@ static WRITE32_HANDLER( psx_berr_w )
|
||||
|
||||
static void mips_update_scratchpad( running_machine *machine )
|
||||
{
|
||||
int cpu = cpu_getactivecpu();
|
||||
int cpu = cpunum_get_active();
|
||||
|
||||
if( ( mipscpu.biu & BIU_RAM ) == 0 )
|
||||
{
|
||||
|
@ -431,13 +431,13 @@ OP( 0x0f, i_pre_nec ) { UINT32 ModRM, tmp, tmp2;
|
||||
case 0x26 : CMP4S; CLKS(7,7,2); break;
|
||||
case 0x28 : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp <<= 4; tmp |= I.regs.b[AL] & 0xf; I.regs.b[AL] = (I.regs.b[AL] & 0xf0) | ((tmp>>8)&0xf); tmp &= 0xff; PutbackRMByte(ModRM,tmp); CLKM(13,13,9,28,28,15); break;
|
||||
case 0x2a : ModRM = FETCH(); tmp = GetRMByte(ModRM); tmp2 = (I.regs.b[AL] & 0xf)<<4; I.regs.b[AL] = (I.regs.b[AL] & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(17,17,13,32,32,19); break;
|
||||
case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",activecpu_get_pc()); break;
|
||||
case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",activecpu_get_pc()); break;
|
||||
case 0x31 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x33 : ModRM = FETCH(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x92 : CLK(2); break; /* V25/35 FINT */
|
||||
case 0xe0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",activecpu_get_pc()); break;
|
||||
case 0xf0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",activecpu_get_pc()); break;
|
||||
case 0xff : ModRM = FETCH(); ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",activecpu_get_pc()); break;
|
||||
default: logerror("%06x: Unknown V20 instruction\n",activecpu_get_pc()); break;
|
||||
case 0xe0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0xf0 : ModRM = FETCH(); ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0xff : ModRM = FETCH(); ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
default: logerror("%06x: Unknown V20 instruction\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -565,7 +565,7 @@ OP( 0x62, i_chkind ) {
|
||||
nec_interrupt(5,0);
|
||||
}
|
||||
nec_ICount-=20;
|
||||
logerror("%06x: bound %04x high %04x low %04x tmp\n",activecpu_get_pc(),high,low,tmp);
|
||||
logerror("%06x: bound %04x high %04x low %04x tmp\n",cpu_get_pc(Machine->activecpu),high,low,tmp);
|
||||
}
|
||||
OP( 0x63, i_brkn ) { nec_interrupt(FETCH(),1); CLKS(50,50,24); } // timing not verified, used by riskchal / gussun
|
||||
OP( 0x64, i_repnc ) { UINT32 next = fetchop(); UINT16 c = I.regs.w[CW];
|
||||
@ -591,7 +591,7 @@ OP( 0x64, i_repnc ) { UINT32 next = fetchop(); UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPNC invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPNC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
I.seg_prefix=FALSE;
|
||||
}
|
||||
@ -619,7 +619,7 @@ OP( 0x65, i_repc ) { UINT32 next = fetchop(); UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPC invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
I.seg_prefix=FALSE;
|
||||
}
|
||||
@ -723,7 +723,7 @@ OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); CLKR(15,
|
||||
case 0x08: I.sregs[PS] = src; break; /* mov cs,ew */
|
||||
case 0x10: I.sregs[SS] = src; break; /* mov ss,ew */
|
||||
case 0x18: I.sregs[DS0] = src; break; /* mov ds,ew */
|
||||
default: logerror("%06x: Mov Sreg - Invalid register\n",activecpu_get_pc());
|
||||
default: logerror("%06x: Mov Sreg - Invalid register\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
I.no_interrupt=1;
|
||||
}
|
||||
@ -794,7 +794,7 @@ OP( 0xc0, i_rotshft_bd8 ) {
|
||||
case 0x18: do { RORC_BYTE; c--; CLK(1); } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break;
|
||||
case 0x20: SHL_BYTE(c); break;
|
||||
case 0x28: SHR_BYTE(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_BYTE(c); break;
|
||||
}
|
||||
}
|
||||
@ -811,7 +811,7 @@ OP( 0xc1, i_rotshft_wd8 ) {
|
||||
case 0x18: do { RORC_WORD; c--; CLK(1); } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break;
|
||||
case 0x20: SHL_WORD(c); break;
|
||||
case 0x28: SHR_WORD(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_WORD(c); break;
|
||||
}
|
||||
}
|
||||
@ -861,7 +861,7 @@ OP( 0xd0, i_rotshft_b ) {
|
||||
case 0x18: RORC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); I.OverVal = (src^dst)&0x80; break;
|
||||
case 0x20: SHL_BYTE(1); I.OverVal = (src^dst)&0x80; break;
|
||||
case 0x28: SHR_BYTE(1); I.OverVal = (src^dst)&0x80; break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_BYTE(1); I.OverVal = 0; break;
|
||||
}
|
||||
}
|
||||
@ -876,7 +876,7 @@ OP( 0xd1, i_rotshft_w ) {
|
||||
case 0x18: RORC_WORD; PutbackRMWord(ModRM,(WORD)dst); I.OverVal = (src^dst)&0x8000; break;
|
||||
case 0x20: SHL_WORD(1); I.OverVal = (src^dst)&0x8000; break;
|
||||
case 0x28: SHR_WORD(1); I.OverVal = (src^dst)&0x8000; break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_WORD(1); I.OverVal = 0; break;
|
||||
}
|
||||
}
|
||||
@ -892,7 +892,7 @@ OP( 0xd2, i_rotshft_bcl ) {
|
||||
case 0x18: do { RORC_BYTE; c--; CLK(1); } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break;
|
||||
case 0x20: SHL_BYTE(c); break;
|
||||
case 0x28: SHR_BYTE(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_BYTE(c); break;
|
||||
}
|
||||
}
|
||||
@ -908,16 +908,16 @@ OP( 0xd3, i_rotshft_wcl ) {
|
||||
case 0x18: do { RORC_WORD; c--; CLK(1); } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break;
|
||||
case 0x20: SHL_WORD(c); break;
|
||||
case 0x28: SHR_WORD(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_WORD(c); break;
|
||||
}
|
||||
}
|
||||
|
||||
OP( 0xd4, i_aam ) { UINT32 mult=FETCH(); mult=0; I.regs.b[AH] = I.regs.b[AL] / 10; I.regs.b[AL] %= 10; SetSZPF_Word(I.regs.w[AW]); CLKS(15,15,12); }
|
||||
OP( 0xd5, i_aad ) { UINT32 mult=FETCH(); mult=0; I.regs.b[AL] = I.regs.b[AH] * 10 + I.regs.b[AL]; I.regs.b[AH] = 0; SetSZPF_Byte(I.regs.b[AL]); CLKS(7,7,8); }
|
||||
OP( 0xd6, i_setalc ) { I.regs.b[AL] = (CF)?0xff:0x00; nec_ICount-=3; logerror("%06x: Undefined opcode (SETALC)\n",activecpu_get_pc()); }
|
||||
OP( 0xd6, i_setalc ) { I.regs.b[AL] = (CF)?0xff:0x00; nec_ICount-=3; logerror("%06x: Undefined opcode (SETALC)\n",cpu_get_pc(Machine->activecpu)); }
|
||||
OP( 0xd7, i_trans ) { UINT32 dest = (I.regs.w[BW]+I.regs.b[AL])&0xffff; I.regs.b[AL] = GetMemB(DS0, dest); CLKS(9,9,5); }
|
||||
OP( 0xd8, i_fpo ) { GetModRM; nec_ICount-=2; logerror("%06x: Unimplemented floating point control %04x\n",activecpu_get_pc(),ModRM); }
|
||||
OP( 0xd8, i_fpo ) { GetModRM; nec_ICount-=2; logerror("%06x: Unimplemented floating point control %04x\n",cpu_get_pc(Machine->activecpu),ModRM); }
|
||||
|
||||
OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH(); I.regs.w[CW]--; if (!ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); }
|
||||
OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH(); I.regs.w[CW]--; if ( ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLKS(14,14,6); } else CLKS(5,5,3); }
|
||||
@ -937,7 +937,7 @@ OP( 0xed, i_inaxdx ) { I.regs.w[AW] = read_port_word(I.regs.w[DW]); CLKW(12,12
|
||||
OP( 0xee, i_outdxal ) { write_port_byte(I.regs.w[DW], I.regs.b[AL]); CLKS(8,8,3); }
|
||||
OP( 0xef, i_outdxax ) { write_port_word(I.regs.w[DW], I.regs.w[AW]); CLKW(12,12,5,12,8,3,I.regs.w[DW]); }
|
||||
|
||||
OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",activecpu_get_pc()); I.no_interrupt=1; CLK(2); }
|
||||
OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",cpu_get_pc(Machine->activecpu)); I.no_interrupt=1; CLK(2); }
|
||||
OP( 0xf2, i_repne ) { UINT32 next = fetchop(); UINT16 c = I.regs.w[CW];
|
||||
switch(next) { /* Segments */
|
||||
case 0x26: I.seg_prefix=TRUE; I.prefix_base=I.sregs[DS1]<<4; next = fetchop(); CLK(2); break;
|
||||
@ -961,7 +961,7 @@ OP( 0xf2, i_repne ) { UINT32 next = fetchop(); UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && ZF==0); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && ZF==0); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPNE invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPNE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
I.seg_prefix=FALSE;
|
||||
}
|
||||
@ -988,17 +988,17 @@ OP( 0xf3, i_repe ) { UINT32 next = fetchop(); UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && ZF==1); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && ZF==1); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPE invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
I.seg_prefix=FALSE;
|
||||
}
|
||||
OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",activecpu_get_pc()); nec_ICount=0; }
|
||||
OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",cpu_get_pc(Machine->activecpu)); nec_ICount=0; }
|
||||
OP( 0xf5, i_cmc ) { I.CarryVal = !CF; CLK(2); }
|
||||
OP( 0xf6, i_f6pre ) { UINT32 tmp; UINT32 uresult,uresult2; INT32 result,result2;
|
||||
GetModRM; tmp = GetRMByte(ModRM);
|
||||
switch (ModRM & 0x38) {
|
||||
case 0x00: tmp &= FETCH(); I.CarryVal = I.OverVal = 0; SetSZPF_Byte(tmp); nec_ICount-=(ModRM >=0xc0 )?4:11; break; /* TEST */
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",activecpu_get_pc()); break;
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x10: PutbackRMByte(ModRM,~tmp); nec_ICount-=(ModRM >=0xc0 )?2:16; break; /* NOT */
|
||||
case 0x18: I.CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Byte(tmp); PutbackRMByte(ModRM,tmp&0xff); nec_ICount-=(ModRM >=0xc0 )?2:16; break; /* NEG */
|
||||
case 0x20: uresult = I.regs.b[AL]*tmp; I.regs.w[AW]=(WORD)uresult; I.CarryVal=I.OverVal=(I.regs.b[AH]!=0); nec_ICount-=(ModRM >=0xc0 )?30:36; break; /* MULU */
|
||||
@ -1012,7 +1012,7 @@ OP( 0xf7, i_f7pre ) { UINT32 tmp,tmp2; UINT32 uresult,uresult2; INT32 result,r
|
||||
GetModRM; tmp = GetRMWord(ModRM);
|
||||
switch (ModRM & 0x38) {
|
||||
case 0x00: tmp2 = FETCHWORD(); tmp &= tmp2; I.CarryVal = I.OverVal = 0; SetSZPF_Word(tmp); nec_ICount-=(ModRM >=0xc0 )?4:11; break; /* TEST */
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",activecpu_get_pc()); break;
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x10: PutbackRMWord(ModRM,~tmp); nec_ICount-=(ModRM >=0xc0 )?2:16; break; /* NOT */
|
||||
case 0x18: I.CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Word(tmp); PutbackRMWord(ModRM,tmp&0xffff); nec_ICount-=(ModRM >=0xc0 )?2:16; break; /* NEG */
|
||||
case 0x20: uresult = I.regs.w[AW]*tmp; I.regs.w[AW]=uresult&0xffff; I.regs.w[DW]=((UINT32)uresult)>>16; I.CarryVal=I.OverVal=(I.regs.w[DW]!=0); nec_ICount-=(ModRM >=0xc0 )?30:36; break; /* MULU */
|
||||
@ -1032,7 +1032,7 @@ OP( 0xfe, i_fepre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMByte(ModRM);
|
||||
switch(ModRM & 0x38) {
|
||||
case 0x00: tmp1 = tmp+1; I.OverVal = (tmp==0x7f); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* INC */
|
||||
case 0x08: tmp1 = tmp-1; I.OverVal = (tmp==0x80); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(2,2,2,16,16,7); break; /* DEC */
|
||||
default: logerror("%06x: FE Pre with unimplemented mod\n",activecpu_get_pc());
|
||||
default: logerror("%06x: FE Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
}
|
||||
OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM);
|
||||
@ -1044,14 +1044,14 @@ OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM);
|
||||
case 0x20: I.ip = tmp; CHANGE_PC; nec_ICount-=13; break; /* JMP */
|
||||
case 0x28: I.ip = tmp; I.sregs[PS] = GetnextRMWord; CHANGE_PC; nec_ICount-=15; break; /* JMP FAR */
|
||||
case 0x30: PUSH(tmp); nec_ICount-=4; break;
|
||||
default: logerror("%06x: FF Pre with unimplemented mod\n",activecpu_get_pc());
|
||||
default: logerror("%06x: FF Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
}
|
||||
|
||||
static void i_invalid(void)
|
||||
{
|
||||
nec_ICount-=10;
|
||||
logerror("%06x: Invalid Opcode\n",activecpu_get_pc());
|
||||
logerror("%06x: Invalid Opcode\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
@ -303,7 +303,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
|
||||
unsigned di = I.regs.w[IY]; \
|
||||
unsigned si = I.regs.w[IX]; \
|
||||
static const UINT8 table[3]={18,19,19}; \
|
||||
if (I.seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",activecpu_get_pc()); \
|
||||
if (I.seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",cpu_get_pc(Machine->activecpu)); \
|
||||
I.ZeroVal = I.CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
nec_ICount-=table[I.chip_type/8]; \
|
||||
@ -328,7 +328,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
|
||||
unsigned di = I.regs.w[IY]; \
|
||||
unsigned si = I.regs.w[IX]; \
|
||||
static const UINT8 table[3]={18,19,19}; \
|
||||
if (I.seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",activecpu_get_pc()); \
|
||||
if (I.seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",cpu_get_pc(Machine->activecpu)); \
|
||||
I.ZeroVal = I.CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
nec_ICount-=table[I.chip_type/8]; \
|
||||
@ -358,7 +358,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
|
||||
unsigned di = I.regs.w[IY]; \
|
||||
unsigned si = I.regs.w[IX]; \
|
||||
static const UINT8 table[3]={14,19,19}; \
|
||||
if (I.seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",activecpu_get_pc()); \
|
||||
if (I.seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",cpu_get_pc(Machine->activecpu)); \
|
||||
I.ZeroVal = I.CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
nec_ICount-=table[I.chip_type/8]; \
|
||||
|
@ -1706,7 +1706,7 @@ static void null_iot(int op2, int nac, int mb, int *io, int ac)
|
||||
if (LOG_IOT_EXTRA)
|
||||
{
|
||||
if (op2 == 000)
|
||||
logerror("IOT sync instruction: mb=0%06o, pc=0%06o\n", (unsigned) mb, (unsigned) cpunum_get_reg(0, PDP1_PC));
|
||||
logerror("IOT sync instruction: mb=0%06o, pc=0%06o\n", (unsigned) mb, (unsigned) cpu_get_reg(Machine->cpu[0], PDP1_PC));
|
||||
}
|
||||
if (LOG)
|
||||
{
|
||||
|
@ -20,8 +20,8 @@ enum
|
||||
PDP1_IO_COMPLETE /* hack, do not use directly, use pdp1_pulse_iot_done instead */
|
||||
};
|
||||
|
||||
#define pdp1_pulse_start_clear() cpunum_set_reg(0, PDP1_START_CLEAR, 0)
|
||||
#define pdp1_pulse_iot_done() cpunum_set_reg(0, PDP1_IO_COMPLETE, 0)
|
||||
#define pdp1_pulse_start_clear() cpu_set_reg(machine->cpu[0], PDP1_START_CLEAR, 0)
|
||||
#define pdp1_pulse_iot_done() cpu_set_reg(machine->cpu[0], PDP1_IO_COMPLETE, 0)
|
||||
|
||||
typedef struct _pdp1_reset_param_t pdp1_reset_param_t;
|
||||
struct _pdp1_reset_param_t
|
||||
|
@ -21,8 +21,8 @@ enum
|
||||
TX0_IO_COMPLETE /* hack, do not use directly, use tx0_pulse_io_complete instead */
|
||||
};
|
||||
|
||||
#define tx0_pulse_reset() cpunum_set_reg(0, TX0_RESET, 0)
|
||||
#define tx0_pulse_io_complete() cpunum_set_reg(0, TX0_IO_COMPLETE, 0)
|
||||
#define tx0_pulse_reset() cpu_set_reg(machine->cpu[0], TX0_RESET, 0)
|
||||
#define tx0_pulse_io_complete() cpu_set_reg(machine->cpu[0], TX0_IO_COMPLETE, 0)
|
||||
|
||||
typedef struct _tx0_reset_param_t tx0_reset_param_t;
|
||||
struct _tx0_reset_param_t
|
||||
|
@ -56,7 +56,7 @@ static void ppcdrc_init(void)
|
||||
drconfig.cb_entrygen = ppcdrc_entrygen;
|
||||
|
||||
/* initialize the compiler */
|
||||
ppc.drc = drc_init(cpu_getactivecpu(), &drconfig);
|
||||
ppc.drc = drc_init(cpunum_get_active(), &drconfig);
|
||||
ppc.drcoptions = 0;
|
||||
}
|
||||
|
||||
@ -132,7 +132,7 @@ static UINT32 *ppcdrc_getopptr(UINT32 address)
|
||||
address &= ~0x07;
|
||||
}
|
||||
|
||||
result = (UINT32 *) memory_get_op_ptr(Machine, cpu_getactivecpu(), address, 0);
|
||||
result = (UINT32 *) memory_get_op_ptr(Machine, cpunum_get_active(), address, 0);
|
||||
if (result)
|
||||
result += offset;
|
||||
return result;
|
||||
|
@ -192,15 +192,15 @@ CPU_GET_INFO( mpc8240 );
|
||||
INLINE FUNCTIONS
|
||||
***************************************************************************/
|
||||
|
||||
INLINE void ppc4xx_spu_set_tx_handler(int cpunum, ppc4xx_spu_tx_handler handler)
|
||||
INLINE void ppc4xx_spu_set_tx_handler(const device_config *cpu, ppc4xx_spu_tx_handler handler)
|
||||
{
|
||||
cpunum_set_info_fct(cpunum, CPUINFO_PTR_SPU_TX_HANDLER, (genf *)handler);
|
||||
cpu_set_info_fct(cpu, CPUINFO_PTR_SPU_TX_HANDLER, (genf *)handler);
|
||||
}
|
||||
|
||||
|
||||
INLINE void ppc4xx_spu_receive_byte(int cpunum, UINT8 byteval)
|
||||
INLINE void ppc4xx_spu_receive_byte(const device_config *cpu, UINT8 byteval)
|
||||
{
|
||||
cpunum_set_info_int(cpunum, CPUINFO_INT_PPC_RX_DATA, byteval);
|
||||
cpu_set_info_int(cpu, CPUINFO_INT_PPC_RX_DATA, byteval);
|
||||
}
|
||||
|
||||
|
||||
|
@ -678,7 +678,7 @@ static void ppc403_spu_w(UINT32 a, UINT8 d)
|
||||
|
||||
case 0x9:
|
||||
ppc.spu.sptb = d;
|
||||
ppc403_spu_tx_callback(NULL/* Machine */, NULL, cpu_getactivecpu());
|
||||
ppc403_spu_tx_callback(NULL/* Machine */, NULL, cpunum_get_active());
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -209,7 +209,7 @@ static int ppc_translate_address(offs_t *addr_ptr, int flags)
|
||||
| (((ppc.sdr1 & 0x01FF) & (hash >> 10)) << 16)
|
||||
| ((hash & 0x03FF) << 6);
|
||||
|
||||
pteg_ptr[hash_type] = memory_get_read_ptr(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, pteg_address);
|
||||
pteg_ptr[hash_type] = memory_get_read_ptr(cpunum_get_active(), ADDRESS_SPACE_PROGRAM, pteg_address);
|
||||
if (pteg_ptr[hash_type])
|
||||
{
|
||||
for (i = 0; i < 8; i++)
|
||||
|
@ -190,7 +190,7 @@ void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_di
|
||||
|
||||
/* initialize based on the config */
|
||||
memset(ppc, 0, sizeof(*ppc));
|
||||
ppc->cpunum = cpu_getactivecpu();
|
||||
ppc->cpunum = cpunum_get_active();
|
||||
ppc->flavor = flavor;
|
||||
ppc->cap = cap;
|
||||
ppc->cache_line_size = 32;
|
||||
@ -202,7 +202,7 @@ void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT8 cap, int tb_di
|
||||
ppc->tb_divisor = (ppc->tb_divisor * clock + ppc->system_clock / 2 - 1) / ppc->system_clock;
|
||||
|
||||
/* allocate the virtual TLB */
|
||||
ppc->vtlb = vtlb_alloc(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, (cap & PPCCAP_603_MMU) ? PPC603_FIXED_TLB_ENTRIES : 0, POWERPC_TLB_ENTRIES);
|
||||
ppc->vtlb = vtlb_alloc(device, ADDRESS_SPACE_PROGRAM, (cap & PPCCAP_603_MMU) ? PPC603_FIXED_TLB_ENTRIES : 0, POWERPC_TLB_ENTRIES);
|
||||
|
||||
/* allocate a timer for the compare interrupt */
|
||||
if (cap & PPCCAP_OEA)
|
||||
@ -429,7 +429,7 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio
|
||||
for (hashnum = 0; hashnum < 2; hashnum++)
|
||||
{
|
||||
offs_t ptegaddr = hashbase | ((hash << 6) & hashmask);
|
||||
UINT32 *ptegptr = memory_get_read_ptr(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, ptegaddr);
|
||||
UINT32 *ptegptr = memory_get_read_ptr(cpunum_get_active(), ADDRESS_SPACE_PROGRAM, ptegaddr);
|
||||
|
||||
/* should only have valid memory here, but make sure */
|
||||
if (ptegptr != NULL)
|
||||
@ -1378,10 +1378,10 @@ static int ppc4xx_dma_fetch_transmit_byte(powerpc_state *ppc, int dmachan, UINT8
|
||||
return FALSE;
|
||||
|
||||
/* fetch the data */
|
||||
cpuintrf_push_context(ppc->cpunum);
|
||||
cpu_push_context(Machine->cpu[ppc->cpunum]);
|
||||
*byte = program_read_byte(dmaregs[DCR4XX_DMADA0]++);
|
||||
ppc4xx_dma_decrement_count(ppc, dmachan);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@ -1404,10 +1404,10 @@ static int ppc4xx_dma_handle_receive_byte(powerpc_state *ppc, int dmachan, UINT8
|
||||
return FALSE;
|
||||
|
||||
/* store the data */
|
||||
cpuintrf_push_context(ppc->cpunum);
|
||||
cpu_push_context(Machine->cpu[ppc->cpunum]);
|
||||
program_write_byte(dmaregs[DCR4XX_DMADA0]++, byte);
|
||||
ppc4xx_dma_decrement_count(ppc, dmachan);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@ -1723,7 +1723,7 @@ updateirq:
|
||||
|
||||
static READ8_HANDLER( ppc4xx_spu_r )
|
||||
{
|
||||
powerpc_state *ppc = activecpu_get_info_ptr(CPUINFO_PTR_CONTEXT);
|
||||
powerpc_state *ppc = cpu_get_info_ptr(machine->activecpu, CPUINFO_PTR_CONTEXT);
|
||||
UINT8 result = 0xff;
|
||||
|
||||
switch (offset)
|
||||
@ -1750,7 +1750,7 @@ static READ8_HANDLER( ppc4xx_spu_r )
|
||||
|
||||
static WRITE8_HANDLER( ppc4xx_spu_w )
|
||||
{
|
||||
powerpc_state *ppc = activecpu_get_info_ptr(CPUINFO_PTR_CONTEXT);
|
||||
powerpc_state *ppc = cpu_get_info_ptr(machine->activecpu, CPUINFO_PTR_CONTEXT);
|
||||
UINT8 oldstate, newstate;
|
||||
|
||||
if (PRINTF_SPU)
|
||||
|
@ -622,7 +622,7 @@ static void ppcdrc_init(powerpc_flavor flavor, UINT8 cap, int tb_divisor, const
|
||||
/* initialize the front-end helper */
|
||||
if (SINGLE_INSTRUCTION_MODE)
|
||||
feconfig.max_sequence = 1;
|
||||
ppc->impstate->drcfe = drcfe_init(&feconfig, ppc);
|
||||
ppc->impstate->drcfe = drcfe_init(device, &feconfig, ppc);
|
||||
|
||||
/* initialize the implementation state tables */
|
||||
memcpy(ppc->impstate->fpmode, fpmode_source, sizeof(fpmode_source));
|
||||
@ -976,7 +976,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
|
||||
}
|
||||
|
||||
/* validate this code block if we're not pointing into ROM */
|
||||
if (memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, seqhead->physpc) != NULL)
|
||||
if (memory_get_write_ptr(cpunum_get_active(), ADDRESS_SPACE_PROGRAM, seqhead->physpc) != NULL)
|
||||
generate_checksum_block(block, &compiler, seqhead, seqlast); // <checksum>
|
||||
|
||||
/* label this instruction, if it may be jumped to locally */
|
||||
@ -1437,7 +1437,7 @@ static void static_generate_memory_accessor(drcuml_state *drcuml, int mode, int
|
||||
/* on entry, address is in I0; data for writes is in I1; masks are in I2 */
|
||||
/* on exit, read result is in I0 */
|
||||
/* routine trashes I0-I3 */
|
||||
int fastxor = BYTE8_XOR_BE(0) >> (activecpu_databus_width(ADDRESS_SPACE_PROGRAM) < 64);
|
||||
int fastxor = BYTE8_XOR_BE(0) >> (cpu_get_databus_width(Machine->activecpu, ADDRESS_SPACE_PROGRAM) < 64);
|
||||
drcuml_block *block;
|
||||
jmp_buf errorbuf;
|
||||
int translate_type;
|
||||
|
@ -1,7 +1,7 @@
|
||||
#define IRQ_ADDRESS 0xf
|
||||
|
||||
#define saturn_assert(x) \
|
||||
do { if (!(x)) logerror("SATURN%d assertion failed: %s at %s:%i, pc=%05x\n", cpu_getactivecpu(), #x, __FILE__, __LINE__, saturn.pc); } while (0)
|
||||
do { if (!(x)) logerror("SATURN%d assertion failed: %s at %s:%i, pc=%05x\n", cpunum_get_active(), #x, __FILE__, __LINE__, saturn.pc); } while (0)
|
||||
|
||||
INLINE int READ_OP(void)
|
||||
{
|
||||
@ -186,24 +186,24 @@ INLINE void saturn_push(SaturnAdr adr)
|
||||
|
||||
INLINE void saturn_interrupt_on(void)
|
||||
{
|
||||
LOG(( "SATURN#%d at %05x: INTON\n", cpu_getactivecpu(), saturn.pc-4 ));
|
||||
LOG(( "SATURN#%d at %05x: INTON\n", cpunum_get_active(), saturn.pc-4 ));
|
||||
saturn.irq_enable=1;
|
||||
if (saturn.irq_state)
|
||||
{
|
||||
LOG(( "SATURN#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "SATURN#%d set_irq_line(ASSERT)\n", cpunum_get_active()));
|
||||
saturn.pending_irq=1;
|
||||
}
|
||||
}
|
||||
|
||||
INLINE void saturn_interrupt_off(void)
|
||||
{
|
||||
LOG(( "SATURN#%d at %05x: INTOFF\n", cpu_getactivecpu(), saturn.pc-4 ));
|
||||
LOG(( "SATURN#%d at %05x: INTOFF\n", cpunum_get_active(), saturn.pc-4 ));
|
||||
saturn.irq_enable=0;
|
||||
}
|
||||
|
||||
INLINE void saturn_reset_interrupt(void)
|
||||
{
|
||||
LOG(( "SATURN#%d at %05x: RSI\n", cpu_getactivecpu(), saturn.pc-5 ));
|
||||
LOG(( "SATURN#%d at %05x: RSI\n", cpunum_get_active(), saturn.pc-5 ));
|
||||
if (saturn.config&&saturn.config->rsi) saturn.config->rsi(Machine);
|
||||
}
|
||||
|
||||
@ -236,27 +236,27 @@ INLINE void saturn_shutdown(void)
|
||||
{
|
||||
saturn.sleeping=1;
|
||||
saturn.irq_enable=1;
|
||||
LOG(( "SATURN#%d at %05x: SHUTDN\n", cpu_getactivecpu(), saturn.pc-3 ));
|
||||
LOG(( "SATURN#%d at %05x: SHUTDN\n", cpunum_get_active(), saturn.pc-3 ));
|
||||
}
|
||||
|
||||
INLINE void saturn_bus_command_b(void)
|
||||
{
|
||||
logerror( "SATURN#%d at %05x: BUSCB opcode not handled\n", cpu_getactivecpu(), saturn.pc-4 );
|
||||
logerror( "SATURN#%d at %05x: BUSCB opcode not handled\n", cpunum_get_active(), saturn.pc-4 );
|
||||
}
|
||||
|
||||
INLINE void saturn_bus_command_c(void)
|
||||
{
|
||||
logerror( "SATURN#%d at %05x: BUSCC opcode not handled\n", cpu_getactivecpu(), saturn.pc-3 );
|
||||
logerror( "SATURN#%d at %05x: BUSCC opcode not handled\n", cpunum_get_active(), saturn.pc-3 );
|
||||
}
|
||||
|
||||
INLINE void saturn_bus_command_d(void)
|
||||
{
|
||||
logerror( "SATURN#%d at %05x: BUSCD opcode not handled\n", cpu_getactivecpu(), saturn.pc-4 );
|
||||
logerror( "SATURN#%d at %05x: BUSCD opcode not handled\n", cpunum_get_active(), saturn.pc-4 );
|
||||
}
|
||||
|
||||
INLINE void saturn_serial_request(void)
|
||||
{
|
||||
logerror( "SATURN#%d at %05x: SREQ? opcode not handled\n", cpu_getactivecpu(), saturn.pc-3 );
|
||||
logerror( "SATURN#%d at %05x: SREQ? opcode not handled\n", cpunum_get_active(), saturn.pc-3 );
|
||||
}
|
||||
|
||||
INLINE void saturn_out_c(void)
|
||||
@ -279,7 +279,7 @@ INLINE void saturn_in(int reg)
|
||||
saturn_assert(reg>=0 && reg<9);
|
||||
if (!(saturn.pc&1))
|
||||
logerror( "SATURN#%d at %05x: reg=IN opcode at odd addresse\n",
|
||||
cpu_getactivecpu(), saturn.pc-3 );
|
||||
cpunum_get_active(), saturn.pc-3 );
|
||||
if (saturn.config&&saturn.config->in) in = saturn.config->in(Machine);
|
||||
S64_WRITE_WORD(reg,in);
|
||||
monitor_in = in;
|
||||
@ -469,7 +469,7 @@ INLINE void saturn_return_carry_clear(void)
|
||||
|
||||
INLINE void saturn_return_interrupt(void)
|
||||
{
|
||||
LOG(( "SATURN#%d at %05x: RTI\n", cpu_getactivecpu(), saturn.pc-2 ));
|
||||
LOG(( "SATURN#%d at %05x: RTI\n", cpunum_get_active(), saturn.pc-2 ));
|
||||
saturn.in_irq=0; /* set to 1 when an IRQ is taken */
|
||||
saturn.pc=saturn_pop();
|
||||
// saturn_ICount-=10;
|
||||
|
@ -38,25 +38,25 @@ static const int sub_right[]={B,C,A,C, I,I,I,I, A,B,C,D, B,C,A,C};
|
||||
static void saturn_invalid3( int op1, int op2, int op3 )
|
||||
{
|
||||
logerror( "SATURN#%d invalid opcode %x%x%x at %05x\n",
|
||||
cpu_getactivecpu(), op1, op2, op3, saturn.pc-3 );
|
||||
cpunum_get_active(), op1, op2, op3, saturn.pc-3 );
|
||||
}
|
||||
|
||||
static void saturn_invalid4( int op1, int op2, int op3, int op4 )
|
||||
{
|
||||
logerror( "SATURN#%d invalid opcode %x%x%x%x at %05x\n",
|
||||
cpu_getactivecpu(), op1, op2, op3, op4, saturn.pc-4 );
|
||||
cpunum_get_active(), op1, op2, op3, op4, saturn.pc-4 );
|
||||
}
|
||||
|
||||
static void saturn_invalid5( int op1, int op2, int op3, int op4, int op5 )
|
||||
{
|
||||
logerror( "SATURN#%d invalid opcode %x%x%x%x%x at %05x\n",
|
||||
cpu_getactivecpu(), op1, op2, op3, op4, op5, saturn.pc-5 );
|
||||
cpunum_get_active(), op1, op2, op3, op4, op5, saturn.pc-5 );
|
||||
}
|
||||
|
||||
static void saturn_invalid6( int op1, int op2, int op3, int op4, int op5, int op6 )
|
||||
{
|
||||
logerror( "SATURN#%d invalid opcode %x%x%x%x%x%x at %05x\n",
|
||||
cpu_getactivecpu(), op1, op2, op3, op4, op5, op6, saturn.pc-6 );
|
||||
cpunum_get_active(), op1, op2, op3, op4, op5, op6, saturn.pc-6 );
|
||||
}
|
||||
|
||||
|
||||
|
@ -163,7 +163,7 @@ INLINE void saturn_take_irq(void)
|
||||
saturn_push(saturn.pc);
|
||||
saturn.pc=IRQ_ADDRESS;
|
||||
|
||||
LOG(("Saturn#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), saturn.pc));
|
||||
LOG(("Saturn#%d takes IRQ ($%04x)\n", cpunum_get_active(), saturn.pc));
|
||||
|
||||
if (saturn.irq_callback) (*saturn.irq_callback)(saturn.device, SATURN_IRQ_LINE);
|
||||
change_pc(saturn.pc);
|
||||
@ -208,7 +208,7 @@ static void saturn_set_nmi_line(int state)
|
||||
saturn.nmi_state = state;
|
||||
if ( state != CLEAR_LINE )
|
||||
{
|
||||
LOG(( "SATURN#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "SATURN#%d set_nmi_line(ASSERT)\n", cpunum_get_active()));
|
||||
saturn.pending_irq = 1;
|
||||
}
|
||||
}
|
||||
@ -219,7 +219,7 @@ static void saturn_set_irq_line(int state)
|
||||
saturn.irq_state = state;
|
||||
if ( state != CLEAR_LINE && saturn.irq_enable )
|
||||
{
|
||||
LOG(( "SATURN#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "SATURN#%d set_irq_line(ASSERT)\n", cpunum_get_active()));
|
||||
saturn.pending_irq = 1;
|
||||
}
|
||||
}
|
||||
@ -228,7 +228,7 @@ static void saturn_set_wakeup_line(int state)
|
||||
{
|
||||
if (saturn.sleeping && state==1)
|
||||
{
|
||||
LOG(( "SATURN#%d set_wakeup_line(ASSERT)\n", cpu_getactivecpu()));
|
||||
LOG(( "SATURN#%d set_wakeup_line(ASSERT)\n", cpunum_get_active()));
|
||||
if (saturn.irq_callback) (*saturn.irq_callback)(saturn.device, SATURN_WAKEUP_LINE);
|
||||
saturn.sleeping = 0;
|
||||
}
|
||||
|
@ -2335,7 +2335,7 @@ static CPU_SET_INFO( sh2 )
|
||||
case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break;
|
||||
|
||||
case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(cpu_getactivecpu(), info->i); break;
|
||||
case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(cpunum_get_active(), info->i); break;
|
||||
|
||||
/* --- the following bits of info are set as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SH2_FTCSR_READ_CALLBACK: sh2->ftcsr_read_callback = (void (*) (UINT32 ))info->f; break;
|
||||
|
@ -109,7 +109,7 @@ TIMER_CALLBACK( sh2_timer_callback )
|
||||
UINT16 frc;
|
||||
int cpunum = param;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
sh2_timer_resync();
|
||||
|
||||
frc = sh2->frc;
|
||||
@ -131,7 +131,7 @@ TIMER_CALLBACK( sh2_timer_callback )
|
||||
sh2_recalc_irq();
|
||||
sh2_timer_activate();
|
||||
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
TIMER_CALLBACK( sh2_dmac_callback )
|
||||
@ -139,12 +139,12 @@ TIMER_CALLBACK( sh2_dmac_callback )
|
||||
int cpunum = param >> 1;
|
||||
int dma = param & 1;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
LOG(("SH2.%d: DMA %d complete\n", cpunum, dma));
|
||||
sh2->m[0x63+4*dma] |= 2;
|
||||
sh2->dma_timer_active[dma] = 0;
|
||||
sh2_recalc_irq();
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
static void sh2_dmac_check(int dma)
|
||||
@ -300,7 +300,7 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
// logerror("sh2_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfffffe00+offset*4, offset, data, mem_mask);
|
||||
|
||||
// if(offset != 0x20)
|
||||
// printf("sh2_internal_w: Write %08x (%x), %08x @ %08x (PC %x)\n", 0xfffffe00+offset*4, offset, data, mem_mask, activecpu_get_pc());
|
||||
// printf("sh2_internal_w: Write %08x (%x), %08x @ %08x (PC %x)\n", 0xfffffe00+offset*4, offset, data, mem_mask, cpu_get_pc(machine->activecpu));
|
||||
|
||||
switch( offset )
|
||||
{
|
||||
@ -360,7 +360,7 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
{
|
||||
INT32 a = sh2->m[0x41];
|
||||
INT32 b = sh2->m[0x40];
|
||||
LOG(("SH2 #%d div+mod %d/%d\n", cpu_getactivecpu(), a, b));
|
||||
LOG(("SH2 #%d div+mod %d/%d\n", cpunum_get_active(), a, b));
|
||||
if (b)
|
||||
{
|
||||
sh2->m[0x45] = a / b;
|
||||
@ -388,7 +388,7 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
{
|
||||
INT64 a = sh2->m[0x45] | ((UINT64)(sh2->m[0x44]) << 32);
|
||||
INT64 b = (INT32)sh2->m[0x40];
|
||||
LOG(("SH2 #%d div+mod %lld/%lld\n", cpu_getactivecpu(), a, b));
|
||||
LOG(("SH2 #%d div+mod %lld/%lld\n", cpunum_get_active(), a, b));
|
||||
if (b)
|
||||
{
|
||||
INT64 q = a / b;
|
||||
@ -509,10 +509,10 @@ void sh2_set_frt_input(int cpunum, int state)
|
||||
return;
|
||||
}
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
|
||||
if(sh2->frt_input == state) {
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return;
|
||||
}
|
||||
|
||||
@ -520,12 +520,12 @@ void sh2_set_frt_input(int cpunum, int state)
|
||||
|
||||
if(sh2->m[5] & 0x8000) {
|
||||
if(state == CLEAR_LINE) {
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
if(state == ASSERT_LINE) {
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -535,7 +535,7 @@ void sh2_set_frt_input(int cpunum, int state)
|
||||
sh2->m[4] |= ICF;
|
||||
logerror("SH2.%d: ICF activated (%x)\n", sh2->cpu_number, sh2->pc & AM);
|
||||
sh2_recalc_irq();
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
void sh2_set_irq_line(int irqline, int state)
|
||||
@ -548,11 +548,11 @@ void sh2_set_irq_line(int irqline, int state)
|
||||
|
||||
if( state == CLEAR_LINE )
|
||||
{
|
||||
LOG(("SH-2 #%d cleared nmi\n", cpu_getactivecpu()));
|
||||
LOG(("SH-2 #%d cleared nmi\n", cpunum_get_active()));
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG(("SH-2 #%d assert nmi\n", cpu_getactivecpu()));
|
||||
LOG(("SH-2 #%d assert nmi\n", cpunum_get_active()));
|
||||
|
||||
sh2_exception("Set IRQ line", 16);
|
||||
|
||||
@ -569,12 +569,12 @@ void sh2_set_irq_line(int irqline, int state)
|
||||
|
||||
if( state == CLEAR_LINE )
|
||||
{
|
||||
LOG(("SH-2 #%d cleared irq #%d\n", cpu_getactivecpu(), irqline));
|
||||
LOG(("SH-2 #%d cleared irq #%d\n", cpunum_get_active(), irqline));
|
||||
sh2->pending_irq &= ~(1 << irqline);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG(("SH-2 #%d assert irq #%d\n", cpu_getactivecpu(), irqline));
|
||||
LOG(("SH-2 #%d assert irq #%d\n", cpunum_get_active(), irqline));
|
||||
sh2->pending_irq |= 1 << irqline;
|
||||
#ifdef USE_SH2DRC
|
||||
sh2->test_irq = 1;
|
||||
@ -645,27 +645,27 @@ void sh2_exception(const char *message, int irqline)
|
||||
if (sh2->internal_irq_level == irqline)
|
||||
{
|
||||
vector = sh2->internal_irq_vector;
|
||||
LOG(("SH-2 #%d exception #%d (internal vector: $%x) after [%s]\n", cpu_getactivecpu(), irqline, vector, message));
|
||||
LOG(("SH-2 #%d exception #%d (internal vector: $%x) after [%s]\n", cpunum_get_active(), irqline, vector, message));
|
||||
}
|
||||
else
|
||||
{
|
||||
if(sh2->m[0x38] & 0x00010000)
|
||||
{
|
||||
vector = sh2->irq_callback(sh2->device, irqline);
|
||||
LOG(("SH-2 #%d exception #%d (external vector: $%x) after [%s]\n", cpu_getactivecpu(), irqline, vector, message));
|
||||
LOG(("SH-2 #%d exception #%d (external vector: $%x) after [%s]\n", cpunum_get_active(), irqline, vector, message));
|
||||
}
|
||||
else
|
||||
{
|
||||
sh2->irq_callback(sh2->device, irqline);
|
||||
vector = 64 + irqline/2;
|
||||
LOG(("SH-2 #%d exception #%d (autovector: $%x) after [%s]\n", cpu_getactivecpu(), irqline, vector, message));
|
||||
LOG(("SH-2 #%d exception #%d (autovector: $%x) after [%s]\n", cpunum_get_active(), irqline, vector, message));
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
vector = 11;
|
||||
LOG(("SH-2 #%d nmi exception (autovector: $%x) after [%s]\n", cpu_getactivecpu(), vector, message));
|
||||
LOG(("SH-2 #%d nmi exception (autovector: $%x) after [%s]\n", cpunum_get_active(), vector, message));
|
||||
}
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
|
@ -725,7 +725,7 @@ static CPU_INIT( sh2 )
|
||||
/* initialize the front-end helper */
|
||||
if (SINGLE_INSTRUCTION_MODE)
|
||||
feconfig.max_sequence = 1;
|
||||
sh2->drcfe = drcfe_init(&feconfig, sh2);
|
||||
sh2->drcfe = drcfe_init(device, &feconfig, sh2);
|
||||
|
||||
/* compute the register parameters */
|
||||
for (regnum = 0; regnum < 16; regnum++)
|
||||
@ -968,7 +968,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
|
||||
}
|
||||
|
||||
/* validate this code block if we're not pointing into ROM */
|
||||
if (memory_get_write_ptr(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, seqhead->physpc) != NULL)
|
||||
if (memory_get_write_ptr(cpunum_get_active(), ADDRESS_SPACE_PROGRAM, seqhead->physpc) != NULL)
|
||||
generate_checksum_block(block, &compiler, seqhead, seqlast);
|
||||
|
||||
/* label this instruction, if it may be jumped to locally */
|
||||
@ -3395,7 +3395,7 @@ static CPU_SET_INFO( sh2 )
|
||||
case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break;
|
||||
|
||||
case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(cpu_getactivecpu(), info->i); break;
|
||||
case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(cpunum_get_active(), info->i); break;
|
||||
|
||||
/* --- the following bits of info are set as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SH2_FTCSR_READ_CALLBACK: sh2->ftcsr_read_callback = (void (*) (UINT32 ))info->f; break;
|
||||
|
@ -3610,8 +3610,8 @@ static CPU_SET_INFO( sh4 )
|
||||
case CPUINFO_STR_REGISTER + SH4_XF15: sh4.xf[15] = info->i; break;
|
||||
#endif
|
||||
|
||||
case CPUINFO_INT_SH4_IRLn_INPUT: sh4_set_irln_input(cpu_getactivecpu(), info->i); break;
|
||||
case CPUINFO_INT_SH4_FRT_INPUT: sh4_set_frt_input(cpu_getactivecpu(), info->i); break;
|
||||
case CPUINFO_INT_SH4_IRLn_INPUT: sh4_set_irln_input(cpunum_get_active(), info->i); break;
|
||||
case CPUINFO_INT_SH4_FRT_INPUT: sh4_set_frt_input(cpunum_get_active(), info->i); break;
|
||||
|
||||
/* --- the following bits of info are set as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SH4_FTCSR_READ_CALLBACK: sh4.ftcsr_read_callback = (void (*) (UINT32 ))info->f; break;
|
||||
|
@ -172,7 +172,7 @@ void sh4_exception(const char *message, int exception) // handle exception
|
||||
sh4.m[INTEVT] = 0x1c0;
|
||||
vector = 0x600;
|
||||
sh4.irq_callback(sh4.device, INPUT_LINE_NMI);
|
||||
LOG(("SH-4 #%d nmi exception after [%s]\n", cpu_getactivecpu(), message));
|
||||
LOG(("SH-4 #%d nmi exception after [%s]\n", cpunum_get_active(), message));
|
||||
} else {
|
||||
// if ((sh4.m[ICR] & 0x4000) && (sh4.nmi_line_state == ASSERT_LINE))
|
||||
// return;
|
||||
@ -186,7 +186,7 @@ void sh4_exception(const char *message, int exception) // handle exception
|
||||
sh4.irq_callback(sh4.device, SH4_INTC_IRL0-exception+SH4_IRL0);
|
||||
else
|
||||
sh4.irq_callback(sh4.device, SH4_IRL3+1);
|
||||
LOG(("SH-4 #%d interrupt exception #%d after [%s]\n", cpu_getactivecpu(), exception, message));
|
||||
LOG(("SH-4 #%d interrupt exception #%d after [%s]\n", cpunum_get_active(), exception, message));
|
||||
}
|
||||
sh4_exception_checkunrequest(exception);
|
||||
|
||||
@ -259,7 +259,7 @@ static TIMER_CALLBACK( sh4_refresh_timer_callback )
|
||||
{
|
||||
int cpunum = param;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
sh4.m[RTCNT] = 0;
|
||||
sh4_refresh_timer_recompute();
|
||||
sh4.m[RTCSR] |= 128;
|
||||
@ -272,7 +272,7 @@ static TIMER_CALLBACK( sh4_refresh_timer_callback )
|
||||
sh4.m[RTCSR] |= 4;
|
||||
}
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
static void increment_rtc_time(int mode)
|
||||
@ -372,7 +372,7 @@ static TIMER_CALLBACK( sh4_rtc_timer_callback )
|
||||
{
|
||||
int cpunum = param;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
timer_adjust_oneshot(sh4.rtc_timer, ATTOTIME_IN_HZ(128), cpunum);
|
||||
sh4.m[R64CNT] = (sh4.m[R64CNT]+1) & 0x7f;
|
||||
if (sh4.m[R64CNT] == 64)
|
||||
@ -381,7 +381,7 @@ static TIMER_CALLBACK( sh4_rtc_timer_callback )
|
||||
increment_rtc_time(0);
|
||||
//sh4_exception_request(SH4_INTC_NMI); // TEST
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
static TIMER_CALLBACK( sh4_timer_callback )
|
||||
@ -391,13 +391,13 @@ static TIMER_CALLBACK( sh4_timer_callback )
|
||||
int cpunum = param;
|
||||
int idx = tcr[which];
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
sh4.m[tcnt[which]] = sh4.m[tcor[which]];
|
||||
sh4_timer_recompute(which);
|
||||
sh4.m[idx] = sh4.m[idx] | 0x100;
|
||||
if (sh4.m[idx] & 0x20)
|
||||
sh4_exception_request(tuni[which]);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
static TIMER_CALLBACK( sh4_dmac_callback )
|
||||
@ -405,7 +405,7 @@ static TIMER_CALLBACK( sh4_dmac_callback )
|
||||
int cpunum = param >> 8;
|
||||
int channel = param & 255;
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
LOG(("SH4.%d: DMA %d complete\n", cpunum, channel));
|
||||
sh4.dma_timer_active[channel] = 0;
|
||||
switch (channel)
|
||||
@ -435,7 +435,7 @@ static TIMER_CALLBACK( sh4_dmac_callback )
|
||||
sh4_exception_request(SH4_INTC_DMTE3);
|
||||
break;
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
|
||||
@ -974,10 +974,10 @@ void sh4_set_frt_input(int cpunum, int state)
|
||||
return;
|
||||
}
|
||||
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
|
||||
if(sh4.frt_input == state) {
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return;
|
||||
}
|
||||
|
||||
@ -985,12 +985,12 @@ void sh4_set_frt_input(int cpunum, int state)
|
||||
|
||||
if(sh4.m[5] & 0x8000) {
|
||||
if(state == CLEAR_LINE) {
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
if(state == ASSERT_LINE) {
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -1002,7 +1002,7 @@ void sh4_set_frt_input(int cpunum, int state)
|
||||
logerror("SH4.%d: ICF activated (%x)\n", sh4.cpu_number, sh4.pc & AM);
|
||||
sh4_recalc_irq();
|
||||
#endif
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
void sh4_set_irln_input(int cpunum, int value)
|
||||
@ -1025,7 +1025,7 @@ int s;
|
||||
{
|
||||
if ((state == CLEAR_LINE) && (sh4.nmi_line_state == ASSERT_LINE)) // rising
|
||||
{
|
||||
LOG(("SH-4 #%d assert nmi\n", cpu_getactivecpu()));
|
||||
LOG(("SH-4 #%d assert nmi\n", cpunum_get_active()));
|
||||
sh4_exception_request(SH4_INTC_NMI);
|
||||
sh4_dmac_nmi();
|
||||
}
|
||||
@ -1034,7 +1034,7 @@ int s;
|
||||
{
|
||||
if ((state == ASSERT_LINE) && (sh4.nmi_line_state == CLEAR_LINE)) // falling
|
||||
{
|
||||
LOG(("SH-4 #%d assert nmi\n", cpu_getactivecpu()));
|
||||
LOG(("SH-4 #%d assert nmi\n", cpunum_get_active()));
|
||||
sh4_exception_request(SH4_INTC_NMI);
|
||||
sh4_dmac_nmi();
|
||||
}
|
||||
@ -1057,12 +1057,12 @@ int s;
|
||||
|
||||
if( state == CLEAR_LINE )
|
||||
{
|
||||
LOG(("SH-4 #%d cleared external irq IRL%d\n", cpu_getactivecpu(), irqline));
|
||||
LOG(("SH-4 #%d cleared external irq IRL%d\n", cpunum_get_active(), irqline));
|
||||
sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG(("SH-4 #%d assert external irq IRL%d\n", cpu_getactivecpu(), irqline));
|
||||
LOG(("SH-4 #%d assert external irq IRL%d\n", cpunum_get_active(), irqline));
|
||||
sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0);
|
||||
}
|
||||
}
|
||||
@ -1076,7 +1076,7 @@ int s;
|
||||
sh4_exception_unrequest(SH4_INTC_IRLn0+s);
|
||||
if (sh4.irln < 15)
|
||||
sh4_exception_request(SH4_INTC_IRLn0+sh4.irln);
|
||||
LOG(("SH-4 #%d IRLn0-IRLn3 level #%d\n", cpu_getactivecpu(), sh4.irln));
|
||||
LOG(("SH-4 #%d IRLn0-IRLn3 level #%d\n", cpunum_get_active(), sh4.irln));
|
||||
}
|
||||
}
|
||||
if (sh4.test_irq && (!sh4.delay))
|
||||
|
@ -1366,7 +1366,7 @@ void spc700_set_irq_callback(cpu_irq_callback callback)
|
||||
void spc700_state_save(void *file)
|
||||
{
|
||||
#if 0
|
||||
int cpu = cpu_getactivecpu();
|
||||
int cpu = cpunum_get_active();
|
||||
uint p = GET_REG_P();
|
||||
state_save_UINT16(file,"spc700",cpu,"PC",®_PC,2);
|
||||
state_save_UINT16(file,"spc700",cpu,"PPC",®_PPC,2);
|
||||
@ -1384,7 +1384,7 @@ void spc700_state_save(void *file)
|
||||
void spc700_state_load(void *file)
|
||||
{
|
||||
#if 0
|
||||
int cpu = cpu_getactivecpu();
|
||||
int cpu = cpunum_get_active();
|
||||
uint p;
|
||||
state_load_UINT16(file,"spc700",cpu,"PC",®_PC,2);
|
||||
state_load_UINT16(file,"spc700",cpu,"PPC",®_PPC,2);
|
||||
|
@ -983,7 +983,7 @@ static int sprint_arg(char *buffer, UINT32 pc, const char *pre, const e_mode mod
|
||||
case MODE_R16D8: return sprintf( buffer, "%s%s%c$%02X", pre, r16_names[r], (rb&0x80)?'-':'+', (rb&0x80)?((rb^0xff)+1):rb );
|
||||
|
||||
default:
|
||||
fatalerror("%04x: unimplemented addr mode = %d\n",activecpu_get_pc(),mode);
|
||||
fatalerror("%04x: unimplemented addr mode = %d\n",cpu_get_pc(Machine->activecpu),mode);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -1020,7 +1020,7 @@ INLINE UINT16 r8( const e_r r )
|
||||
case L: return T90.hl.b.l;
|
||||
|
||||
default:
|
||||
fatalerror("%04x: unimplemented r8 register index = %d\n",activecpu_get_pc(),r);
|
||||
fatalerror("%04x: unimplemented r8 register index = %d\n",cpu_get_pc(Machine->activecpu),r);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1037,7 +1037,7 @@ INLINE void w8( const e_r r, UINT16 value )
|
||||
case L: T90.hl.b.l = value; return;
|
||||
|
||||
default:
|
||||
fatalerror("%04x: unimplemented w8 register index = %d\n",activecpu_get_pc(),r);
|
||||
fatalerror("%04x: unimplemented w8 register index = %d\n",cpu_get_pc(Machine->activecpu),r);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1058,7 +1058,7 @@ case AF2: return (T90.af2.w.l & (~IF)) | (T90.af.w.l & IF);
|
||||
case PC: return T90.pc.w.l;
|
||||
|
||||
default:
|
||||
fatalerror("%04x: unimplemented r16 register index = %d\n",activecpu_get_pc(),r);
|
||||
fatalerror("%04x: unimplemented r16 register index = %d\n",cpu_get_pc(Machine->activecpu),r);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1077,7 +1077,7 @@ INLINE void w16( const e_r r, UINT16 value )
|
||||
case PC: change_pc( T90.pc.d = value ); return;
|
||||
|
||||
default:
|
||||
fatalerror("%04x: unimplemented w16 register index = %d\n",activecpu_get_pc(),r);
|
||||
fatalerror("%04x: unimplemented w16 register index = %d\n",cpu_get_pc(Machine->activecpu),r);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1105,7 +1105,7 @@ INLINE UINT8 Read##N##_8(void) { \
|
||||
} \
|
||||
return RM8((UINT16)(r16(r##N) + (INT8)r##N##b)); \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Read%d_8 mode = %d\n",activecpu_get_pc(),N,mode##N); \
|
||||
fatalerror("%04x: unimplemented Read%d_8 mode = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \
|
||||
} \
|
||||
return 0; \
|
||||
} \
|
||||
@ -1130,7 +1130,7 @@ INLINE UINT16 Read##N##_16(void) { \
|
||||
} \
|
||||
return RM16((UINT16)(r16(r##N) + (INT8)r##N##b)); \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Read%d_16 modes = %d\n",activecpu_get_pc(),N,mode##N); \
|
||||
fatalerror("%04x: unimplemented Read%d_16 modes = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \
|
||||
} \
|
||||
return 0; \
|
||||
}
|
||||
@ -1156,7 +1156,7 @@ INLINE void Write##N##_8( UINT8 value ) { \
|
||||
} \
|
||||
WM8((UINT16)(r16(r##N) + (INT8)r##N##b), value); return; \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Write%d_8 mode = %d\n",activecpu_get_pc(),N,mode##N); \
|
||||
fatalerror("%04x: unimplemented Write%d_8 mode = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \
|
||||
} \
|
||||
} \
|
||||
INLINE void Write##N##_16( UINT16 value ) \
|
||||
@ -1178,7 +1178,7 @@ INLINE void Write##N##_16( UINT16 value ) \
|
||||
} \
|
||||
WM16((UINT16)(r16(r##N) + (INT8)r##N##b), value); return; \
|
||||
default: \
|
||||
fatalerror("%04x: unimplemented Write%d_16 mode = %d\n",activecpu_get_pc(),N,mode##N); \
|
||||
fatalerror("%04x: unimplemented Write%d_16 mode = %d\n",cpu_get_pc(Machine->activecpu),N,mode##N); \
|
||||
} \
|
||||
}
|
||||
|
||||
@ -1209,7 +1209,7 @@ INLINE int Test( UINT8 cond )
|
||||
case NZ: return !(F & ZF);
|
||||
case NC: return !(F & CF);
|
||||
default:
|
||||
fatalerror("%04x: unimplemented condition = %d\n",activecpu_get_pc(),cond);
|
||||
fatalerror("%04x: unimplemented condition = %d\n",cpu_get_pc(Machine->activecpu),cond);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -1331,7 +1331,7 @@ static CPU_EXECUTE( t90 )
|
||||
do
|
||||
{
|
||||
T90.prvpc.d = T90.pc.d;
|
||||
debugger_instruction_hook(Machine, T90.pc.d);
|
||||
debugger_instruction_hook(device->machine, T90.pc.d);
|
||||
|
||||
check_interrupts();
|
||||
|
||||
@ -1948,7 +1948,7 @@ static CPU_EXECUTE( t90 )
|
||||
break;
|
||||
|
||||
default:
|
||||
fatalerror("%04x: unimplemented opcode, op=%02x\n",activecpu_get_pc(),op);
|
||||
fatalerror("%04x: unimplemented opcode, op=%02x\n",cpu_get_pc(device),op);
|
||||
}
|
||||
|
||||
if ( op != EI )
|
||||
@ -2320,22 +2320,22 @@ static void t90_start_timer(int i)
|
||||
// 16-bit mode
|
||||
if (i & 1)
|
||||
{
|
||||
logerror("%04X: CPU Timer %d clocked by Timer %d overflow signal\n", activecpu_get_pc(), i,i-1);
|
||||
logerror("%04X: CPU Timer %d clocked by Timer %d overflow signal\n", cpu_get_pc(Machine->activecpu), i,i-1);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
logerror("%04X: CPU Timer %d, unsupported PPG mode\n", activecpu_get_pc(), i);
|
||||
logerror("%04X: CPU Timer %d, unsupported PPG mode\n", cpu_get_pc(Machine->activecpu), i);
|
||||
return;
|
||||
case 3:
|
||||
logerror("%04X: CPU Timer %d, unsupported PWM mode\n", activecpu_get_pc(), i);
|
||||
logerror("%04X: CPU Timer %d, unsupported PWM mode\n", cpu_get_pc(Machine->activecpu), i);
|
||||
return;
|
||||
}
|
||||
|
||||
switch((T90.internal_registers[ T90_TCLK - T90_IOBASE ] >> (i * 2)) & 0x03)
|
||||
{
|
||||
case 0: if (i & 1) logerror("%04X: CPU Timer %d clocked by Timer %d match signal\n", activecpu_get_pc(), i,i-1);
|
||||
else logerror("%04X: CPU Timer %d, unsupported TCLK = 0\n", activecpu_get_pc(), i);
|
||||
case 0: if (i & 1) logerror("%04X: CPU Timer %d clocked by Timer %d match signal\n", cpu_get_pc(Machine->activecpu), i,i-1);
|
||||
else logerror("%04X: CPU Timer %d, unsupported TCLK = 0\n", cpu_get_pc(Machine->activecpu), i);
|
||||
return;
|
||||
case 2: prescaler = 16; break;
|
||||
case 3: prescaler = 256; break;
|
||||
@ -2348,7 +2348,7 @@ static void t90_start_timer(int i)
|
||||
|
||||
timer_adjust_periodic(T90.timer[i], period, i, period);
|
||||
|
||||
logerror("%04X: CPU Timer %d started at %lf Hz\n", activecpu_get_pc(), i, 1.0 / attotime_to_double(period));
|
||||
logerror("%04X: CPU Timer %d started at %lf Hz\n", cpu_get_pc(Machine->activecpu), i, 1.0 / attotime_to_double(period));
|
||||
}
|
||||
|
||||
static void t90_start_timer4(void)
|
||||
@ -2362,7 +2362,7 @@ static void t90_start_timer4(void)
|
||||
{
|
||||
case 1: prescaler = 1; break;
|
||||
case 2: prescaler = 16; break;
|
||||
default: logerror("%04X: CPU Timer 4, unsupported T4MOD = %d\n", activecpu_get_pc(),T90.internal_registers[ T90_T4MOD - T90_IOBASE ] & 0x03);
|
||||
default: logerror("%04X: CPU Timer 4, unsupported T4MOD = %d\n", cpu_get_pc(Machine->activecpu),T90.internal_registers[ T90_T4MOD - T90_IOBASE ] & 0x03);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -2370,14 +2370,14 @@ static void t90_start_timer4(void)
|
||||
|
||||
timer_adjust_periodic(T90.timer[4], period, 4, period);
|
||||
|
||||
logerror("%04X: CPU Timer 4 started at %lf Hz\n", activecpu_get_pc(), 1.0 / attotime_to_double(period));
|
||||
logerror("%04X: CPU Timer 4 started at %lf Hz\n", cpu_get_pc(Machine->activecpu), 1.0 / attotime_to_double(period));
|
||||
}
|
||||
|
||||
|
||||
static void t90_stop_timer(int i)
|
||||
{
|
||||
timer_adjust_oneshot(T90.timer[i], attotime_never, i);
|
||||
logerror("%04X: CPU Timer %d stopped\n", activecpu_get_pc(), i);
|
||||
logerror("%04X: CPU Timer %d stopped\n", cpu_get_pc(Machine->activecpu), i);
|
||||
}
|
||||
|
||||
static void t90_stop_timer4(void)
|
||||
@ -2655,7 +2655,7 @@ static CPU_INIT( t90 )
|
||||
T90.irq_callback = irqcallback;
|
||||
T90.device = device;
|
||||
|
||||
T90.timer_period = attotime_mul(ATTOTIME_IN_HZ(cpunum_get_clock(cpu_getactivecpu())), 8);
|
||||
T90.timer_period = attotime_mul(ATTOTIME_IN_HZ(cpunum_get_clock(cpunum_get_active())), 8);
|
||||
|
||||
// Reset registers to their initial values
|
||||
|
||||
|
@ -83,7 +83,7 @@ static int apply_window(const char *inst_name,int srcbpp, UINT32 *srcaddr, XY *d
|
||||
int diff, cycles = 3;
|
||||
|
||||
if (WINDOW_CHECKING == 2)
|
||||
logerror("%08x: %s apply_window window mode %d not supported!\n", activecpu_get_pc(), inst_name, WINDOW_CHECKING);
|
||||
logerror("%08x: %s apply_window window mode %d not supported!\n", cpu_get_pc(Machine->activecpu), inst_name, WINDOW_CHECKING);
|
||||
|
||||
CLR_V;
|
||||
if (WINDOW_CHECKING == 1)
|
||||
|
@ -97,7 +97,7 @@ static void unimpl(void)
|
||||
/* extra check to prevent bad things */
|
||||
if (PC == 0 || opcode_table[cpu_readop16(TOBYTE(PC)) >> 4] == unimpl)
|
||||
{
|
||||
cpunum_set_input_line(tms.screen->machine, cpu_getactivecpu(), INPUT_LINE_HALT, ASSERT_LINE);
|
||||
cpunum_set_input_line(tms.screen->machine, cpunum_get_active(), INPUT_LINE_HALT, ASSERT_LINE);
|
||||
debugger_break(tms.screen->machine);
|
||||
}
|
||||
}
|
||||
|
@ -541,13 +541,13 @@ static void check_interrupt(void)
|
||||
int irq;
|
||||
|
||||
/* if we're not actively executing, skip it */
|
||||
if (executing_cpu != 0xff && executing_cpu != cpu_getactivecpu())
|
||||
if (executing_cpu != 0xff && executing_cpu != cpunum_get_active())
|
||||
return;
|
||||
|
||||
/* check for NMI first */
|
||||
if (IOREG(REG_HSTCTLH) & 0x0100)
|
||||
{
|
||||
LOG(("TMS34010#%d takes NMI\n", cpu_getactivecpu()));
|
||||
LOG(("TMS34010#%d takes NMI\n", cpunum_get_active()));
|
||||
|
||||
/* ack the NMI */
|
||||
IOREG(REG_HSTCTLH) &= ~0x0100;
|
||||
@ -575,28 +575,28 @@ static void check_interrupt(void)
|
||||
/* host interrupt */
|
||||
if (irq & TMS34010_HI)
|
||||
{
|
||||
LOG(("TMS34010#%d takes HI\n", cpu_getactivecpu()));
|
||||
LOG(("TMS34010#%d takes HI\n", cpunum_get_active()));
|
||||
vector = 0xfffffec0;
|
||||
}
|
||||
|
||||
/* display interrupt */
|
||||
else if (irq & TMS34010_DI)
|
||||
{
|
||||
LOG(("TMS34010#%d takes DI\n", cpu_getactivecpu()));
|
||||
LOG(("TMS34010#%d takes DI\n", cpunum_get_active()));
|
||||
vector = 0xfffffea0;
|
||||
}
|
||||
|
||||
/* window violation interrupt */
|
||||
else if (irq & TMS34010_WV)
|
||||
{
|
||||
LOG(("TMS34010#%d takes WV\n", cpu_getactivecpu()));
|
||||
LOG(("TMS34010#%d takes WV\n", cpunum_get_active()));
|
||||
vector = 0xfffffe80;
|
||||
}
|
||||
|
||||
/* external 1 interrupt */
|
||||
else if (irq & TMS34010_INT1)
|
||||
{
|
||||
LOG(("TMS34010#%d takes INT1\n", cpu_getactivecpu()));
|
||||
LOG(("TMS34010#%d takes INT1\n", cpunum_get_active()));
|
||||
vector = 0xffffffc0;
|
||||
irqline = 0;
|
||||
}
|
||||
@ -604,7 +604,7 @@ static void check_interrupt(void)
|
||||
/* external 2 interrupt */
|
||||
else if (irq & TMS34010_INT2)
|
||||
{
|
||||
LOG(("TMS34010#%d takes INT2\n", cpu_getactivecpu()));
|
||||
LOG(("TMS34010#%d takes INT2\n", cpunum_get_active()));
|
||||
vector = 0xffffffa0;
|
||||
irqline = 1;
|
||||
}
|
||||
@ -777,7 +777,7 @@ static CPU_SET_CONTEXT( tms34020 )
|
||||
|
||||
static void set_irq_line(int irqline, int linestate)
|
||||
{
|
||||
LOG(("TMS34010#%d set irq line %d state %d\n", cpu_getactivecpu(), irqline, linestate));
|
||||
LOG(("TMS34010#%d set irq line %d state %d\n", cpunum_get_active(), irqline, linestate));
|
||||
|
||||
/* set the pending interrupt */
|
||||
switch (irqline)
|
||||
@ -810,10 +810,10 @@ static TIMER_CALLBACK( internal_interrupt_callback )
|
||||
int type = param >> 8;
|
||||
|
||||
/* call through to the CPU to generate the int */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
IOREG(REG_INTPEND) |= type;
|
||||
LOG(("TMS34010#%d set internal interrupt $%04x\n", cpu_getactivecpu(), type));
|
||||
cpuintrf_pop_context();
|
||||
LOG(("TMS34010#%d set internal interrupt $%04x\n", cpunum_get_active(), type));
|
||||
cpu_pop_context();
|
||||
|
||||
/* generate triggers so that spin loops can key off them */
|
||||
cpu_triggerint(machine, cpunum);
|
||||
@ -843,7 +843,7 @@ static CPU_EXECUTE( tms34010 )
|
||||
change_pc(TOBYTE(PC));
|
||||
|
||||
/* check interrupts first */
|
||||
executing_cpu = cpu_getactivecpu();
|
||||
executing_cpu = cpunum_get_active();
|
||||
check_interrupt();
|
||||
if ((tms.screen->machine->debug_flags & DEBUG_FLAG_ENABLED) == 0)
|
||||
{
|
||||
@ -963,7 +963,7 @@ static TIMER_CALLBACK( scanline_callback )
|
||||
int master;
|
||||
|
||||
/* set the CPU context */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
|
||||
/* fetch the core timing parameters */
|
||||
current_visarea = video_screen_get_visible_area(tms.screen);
|
||||
@ -1095,13 +1095,13 @@ static TIMER_CALLBACK( scanline_callback )
|
||||
timer_adjust_oneshot(tms.scantimer, attotime_add_attoseconds(video_screen_get_time_until_pos(tms.screen, vcount, 0), !master), cpunum | (vcount << 8));
|
||||
|
||||
/* restore the context */
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
void tms34010_get_display_params(int cpunum, tms34010_display_params *params)
|
||||
{
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
|
||||
params->enabled = ((SMART_IOREG(DPYCTL) & 0x8000) != 0);
|
||||
params->vcount = SMART_IOREG(VCOUNT);
|
||||
@ -1131,7 +1131,7 @@ void tms34010_get_display_params(int cpunum, tms34010_display_params *params)
|
||||
params->yoffset = (IOREG(REG020_DPYNXL) & 0x1f) / (IOREG(REG020_DINCL) & 0x1f);
|
||||
}
|
||||
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
@ -1204,7 +1204,7 @@ static const char *const ioreg_name[] =
|
||||
|
||||
WRITE16_HANDLER( tms34010_io_register_w )
|
||||
{
|
||||
int cpunum = cpu_getactivecpu();
|
||||
int cpunum = cpunum_get_active();
|
||||
int oldreg, newreg;
|
||||
|
||||
/* Set register */
|
||||
@ -1233,7 +1233,7 @@ WRITE16_HANDLER( tms34010_io_register_w )
|
||||
break;
|
||||
|
||||
case REG_PMASK:
|
||||
if (data) logerror("Plane masking not supported. PC=%08X\n", activecpu_get_pc());
|
||||
if (data) logerror("Plane masking not supported. PC=%08X\n", cpu_get_pc(machine->activecpu));
|
||||
break;
|
||||
|
||||
case REG_DPYCTL:
|
||||
@ -1318,7 +1318,7 @@ WRITE16_HANDLER( tms34010_io_register_w )
|
||||
}
|
||||
|
||||
if (LOG_CONTROL_REGS)
|
||||
logerror("CPU#%d@%08X: %s = %04X (%d)\n", cpunum, activecpu_get_pc(), ioreg_name[offset], IOREG(offset), video_screen_get_vpos(tms.screen));
|
||||
logerror("CPU#%d@%08X: %s = %04X (%d)\n", cpunum, cpu_get_pc(machine->activecpu), ioreg_name[offset], IOREG(offset), video_screen_get_vpos(tms.screen));
|
||||
}
|
||||
|
||||
|
||||
@ -1347,7 +1347,7 @@ static const char *const ioreg020_name[] =
|
||||
|
||||
WRITE16_HANDLER( tms34020_io_register_w )
|
||||
{
|
||||
int cpunum = cpu_getactivecpu();
|
||||
int cpunum = cpunum_get_active();
|
||||
int oldreg, newreg;
|
||||
|
||||
/* Set register */
|
||||
@ -1355,7 +1355,7 @@ WRITE16_HANDLER( tms34020_io_register_w )
|
||||
IOREG(offset) = data;
|
||||
|
||||
if (LOG_CONTROL_REGS)
|
||||
logerror("CPU#%d@%08X: %s = %04X (%d)\n", cpunum, activecpu_get_pc(), ioreg020_name[offset], IOREG(offset), video_screen_get_vpos(tms.screen));
|
||||
logerror("CPU#%d@%08X: %s = %04X (%d)\n", cpunum, cpu_get_pc(machine->activecpu), ioreg020_name[offset], IOREG(offset), video_screen_get_vpos(tms.screen));
|
||||
|
||||
switch (offset)
|
||||
{
|
||||
@ -1384,7 +1384,7 @@ WRITE16_HANDLER( tms34020_io_register_w )
|
||||
|
||||
case REG020_PMASKL:
|
||||
case REG020_PMASKH:
|
||||
if (data) logerror("Plane masking not supported. PC=%08X\n", activecpu_get_pc());
|
||||
if (data) logerror("Plane masking not supported. PC=%08X\n", cpu_get_pc(machine->activecpu));
|
||||
break;
|
||||
|
||||
case REG020_DPYCTL:
|
||||
@ -1510,11 +1510,11 @@ WRITE16_HANDLER( tms34020_io_register_w )
|
||||
|
||||
READ16_HANDLER( tms34010_io_register_r )
|
||||
{
|
||||
int cpunum = cpu_getactivecpu();
|
||||
int cpunum = cpunum_get_active();
|
||||
int result, total;
|
||||
|
||||
if (LOG_CONTROL_REGS)
|
||||
logerror("CPU#%d@%08X: read %s\n", cpunum, activecpu_get_pc(), ioreg_name[offset]);
|
||||
logerror("CPU#%d@%08X: read %s\n", cpunum, cpu_get_pc(machine->activecpu), ioreg_name[offset]);
|
||||
|
||||
switch (offset)
|
||||
{
|
||||
@ -1553,11 +1553,11 @@ READ16_HANDLER( tms34010_io_register_r )
|
||||
|
||||
READ16_HANDLER( tms34020_io_register_r )
|
||||
{
|
||||
int cpunum = cpu_getactivecpu();
|
||||
int cpunum = cpunum_get_active();
|
||||
int result, total;
|
||||
|
||||
if (LOG_CONTROL_REGS)
|
||||
logerror("CPU#%d@%08X: read %s\n", cpunum, activecpu_get_pc(), ioreg_name[offset]);
|
||||
logerror("CPU#%d@%08X: read %s\n", cpunum, cpu_get_pc(machine->activecpu), ioreg_name[offset]);
|
||||
|
||||
switch (offset)
|
||||
{
|
||||
@ -1596,9 +1596,9 @@ READ16_HANDLER( tms34020_io_register_r )
|
||||
int tms34010_io_display_blanked(int cpu)
|
||||
{
|
||||
int result;
|
||||
cpuintrf_push_context(cpu);
|
||||
cpu_push_context(Machine->cpu[cpu]);
|
||||
result = !(IOREG(REG_DPYCTL) & 0x8000);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return result;
|
||||
}
|
||||
|
||||
@ -1606,9 +1606,9 @@ int tms34010_io_display_blanked(int cpu)
|
||||
int tms34020_io_display_blanked(int cpu)
|
||||
{
|
||||
int result;
|
||||
cpuintrf_push_context(cpu);
|
||||
cpu_push_context(Machine->cpu[cpu]);
|
||||
result = !(IOREG(REG020_DPYCTL) & 0x8000);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return result;
|
||||
}
|
||||
|
||||
@ -1616,9 +1616,9 @@ int tms34020_io_display_blanked(int cpu)
|
||||
int tms34010_get_DPYSTRT(int cpu)
|
||||
{
|
||||
int result;
|
||||
cpuintrf_push_context(cpu);
|
||||
cpu_push_context(Machine->cpu[cpu]);
|
||||
result = IOREG(REG_DPYSTRT);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return result;
|
||||
}
|
||||
|
||||
@ -1626,9 +1626,9 @@ int tms34010_get_DPYSTRT(int cpu)
|
||||
int tms34020_get_DPYSTRT(int cpu)
|
||||
{
|
||||
int result;
|
||||
cpuintrf_push_context(cpu);
|
||||
cpu_push_context(Machine->cpu[cpu]);
|
||||
result = (IOREG(REG020_DPYSTH) << 16) | (IOREG(REG020_DPYSTL) & ~0x1f);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return result;
|
||||
}
|
||||
|
||||
@ -1655,7 +1655,7 @@ void tms34010_host_w(int cpunum, int reg, int data)
|
||||
unsigned int addr;
|
||||
|
||||
/* swap to the target cpu */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
|
||||
switch (reg)
|
||||
{
|
||||
@ -1700,7 +1700,7 @@ void tms34010_host_w(int cpunum, int reg, int data)
|
||||
}
|
||||
|
||||
/* swap back */
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
activecpu_reset_banking();
|
||||
}
|
||||
|
||||
@ -1716,7 +1716,7 @@ int tms34010_host_r(int cpunum, int reg)
|
||||
int result = 0;
|
||||
|
||||
/* swap to the target cpu */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(Machine->cpu[cpunum]);
|
||||
|
||||
switch (reg)
|
||||
{
|
||||
@ -1759,7 +1759,7 @@ int tms34010_host_r(int cpunum, int reg)
|
||||
}
|
||||
|
||||
/* swap back */
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
activecpu_reset_banking();
|
||||
|
||||
return result;
|
||||
|
@ -186,7 +186,7 @@ static CPU_SET_CONTEXT( tms7000 )
|
||||
|
||||
static CPU_INIT( tms7000 )
|
||||
{
|
||||
int cpu = cpu_getactivecpu();
|
||||
int cpu = cpunum_get_active();
|
||||
|
||||
tms7000.irq_callback = irqcallback;
|
||||
tms7000.device = device;
|
||||
@ -386,7 +386,7 @@ void tms7000_set_irq_line(int irqline, int state)
|
||||
{ /* check for transition */
|
||||
tms7000.irq_state[irqline] = state;
|
||||
|
||||
LOG(("tms7000: (cpu #%d) set_irq_line (INT%d, state %d)\n", cpu_getactivecpu(), irqline+1, state));
|
||||
LOG(("tms7000: (cpu #%d) set_irq_line (INT%d, state %d)\n", cpunum_get_active(), irqline+1, state));
|
||||
|
||||
if (state == CLEAR_LINE)
|
||||
{
|
||||
@ -562,7 +562,7 @@ static void tms7000_service_timer1( void )
|
||||
if( --tms7000.t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
|
||||
{
|
||||
tms7000.t1_decrementer = tms7000.pf[2]; /* Reload decrementer (8 bit) */
|
||||
cpunum_set_input_line(Machine, cpu_getactivecpu(), TMS7000_IRQ2_LINE, HOLD_LINE);
|
||||
cpunum_set_input_line(Machine, cpunum_get_active(), TMS7000_IRQ2_LINE, HOLD_LINE);
|
||||
//LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", activecpu_gettotalcycles(), activecpu_gettotalcycles() - tick, tms7000_cycles_per_INT2-(activecpu_gettotalcycles() - tick) );
|
||||
//tick = activecpu_gettotalcycles() );
|
||||
/* Also, cascade out to timer 2 - timer 2 unimplemented */
|
||||
|
@ -95,19 +95,19 @@ Other references can be found on spies.com:
|
||||
|
||||
#define TMS99XX_PREFIX ti990_10
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( ti990_10 )
|
||||
#define TMS99XX_CPU_NAME "TI990/10"
|
||||
#define TMS99XX_cpu_get_name "TI990/10"
|
||||
|
||||
#elif (TMS99XX_MODEL == TMS9900_ID)
|
||||
|
||||
#define TMS99XX_PREFIX tms9900
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms9900 )
|
||||
#define TMS99XX_CPU_NAME "TMS9900"
|
||||
#define TMS99XX_cpu_get_name "TMS9900"
|
||||
|
||||
#elif (TMS99XX_MODEL == TMS9940_ID)
|
||||
|
||||
#define TMS99XX_PREFIX tms9940
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms9940 )
|
||||
#define TMS99XX_CPU_NAME "TMS9940"
|
||||
#define TMS99XX_cpu_get_name "TMS9940"
|
||||
|
||||
#error "tms9940 is not yet supported"
|
||||
|
||||
@ -115,13 +115,13 @@ Other references can be found on spies.com:
|
||||
|
||||
#define TMS99XX_PREFIX tms9980a
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms9980a )
|
||||
#define TMS99XX_CPU_NAME "TMS9980A/TMS9981"
|
||||
#define TMS99XX_cpu_get_name "TMS9980A/TMS9981"
|
||||
|
||||
#elif (TMS99XX_MODEL == TMS9985_ID)
|
||||
|
||||
#define TMS99XX_PREFIX tms9985
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms9985 )
|
||||
#define TMS99XX_CPU_NAME "TMS9985"
|
||||
#define TMS99XX_cpu_get_name "TMS9985"
|
||||
|
||||
#error "tms9985 is not yet supported"
|
||||
|
||||
@ -129,7 +129,7 @@ Other references can be found on spies.com:
|
||||
|
||||
#define TMS99XX_PREFIX tms9989
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms9989 )
|
||||
#define TMS99XX_CPU_NAME "TMS9989"
|
||||
#define TMS99XX_cpu_get_name "TMS9989"
|
||||
|
||||
#error "tms9989 is not yet supported"
|
||||
|
||||
@ -137,13 +137,13 @@ Other references can be found on spies.com:
|
||||
|
||||
#define TMS99XX_PREFIX tms9995
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms9995 )
|
||||
#define TMS99XX_CPU_NAME "TMS9995"
|
||||
#define TMS99XX_cpu_get_name "TMS9995"
|
||||
|
||||
#elif (TMS99XX_MODEL == TMS99000_ID)
|
||||
|
||||
#define TMS99XX_PREFIX tms99000
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms99000 )
|
||||
#define TMS99XX_CPU_NAME "TMS99000"
|
||||
#define TMS99XX_cpu_get_name "TMS99000"
|
||||
|
||||
#error "tms99000 is not yet supported"
|
||||
|
||||
@ -151,7 +151,7 @@ Other references can be found on spies.com:
|
||||
|
||||
#define TMS99XX_PREFIX tms99105a
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms99105a )
|
||||
#define TMS99XX_CPU_NAME "TMS99105A"
|
||||
#define TMS99XX_cpu_get_name "TMS99105A"
|
||||
|
||||
#error "tms99105a is not yet supported"
|
||||
|
||||
@ -159,7 +159,7 @@ Other references can be found on spies.com:
|
||||
|
||||
#define TMS99XX_PREFIX tms99110a
|
||||
#define TMS99XX_GET_INFO CPU_GET_INFO_NAME( tms99110a )
|
||||
#define TMS99XX_CPU_NAME "TMS99110A"
|
||||
#define TMS99XX_cpu_get_name "TMS99110A"
|
||||
|
||||
#error "tms99110a is not yet supported"
|
||||
|
||||
@ -932,7 +932,7 @@ WRITE8_HANDLER(tms9995_internal2_w)
|
||||
/* read decrementer */
|
||||
if (I.decrementer_enabled && !(I.flag & 1))
|
||||
/* timer mode, timer enabled */
|
||||
return ceil(ATTOTIME_TO_CYCLES(cpu_getactivecpu(), attotime_div(timer_timeleft(I.timer), 16)));
|
||||
return ceil(ATTOTIME_TO_CYCLES(cpunum_get_active(), attotime_div(timer_timeleft(I.timer), 16)));
|
||||
else
|
||||
/* event counter mode or timer mode, timer disabled */
|
||||
return I.decrementer_count;
|
||||
@ -996,7 +996,7 @@ WRITE8_HANDLER(tms9995_internal2_w)
|
||||
|
||||
if (I.decrementer_enabled && !(I.flag & 1))
|
||||
/* timer mode, timer enabled */
|
||||
value = ceil(ATTOTIME_TO_CYCLES(cpu_getactivecpu(), attotime_div(timer_timeleft(I.timer), 16)));
|
||||
value = ceil(ATTOTIME_TO_CYCLES(cpunum_get_active(), attotime_div(timer_timeleft(I.timer), 16)));
|
||||
else
|
||||
/* event counter mode or timer mode, timer disabled */
|
||||
value = I.decrementer_count;
|
||||
@ -1827,7 +1827,7 @@ static void reset_decrementer(void)
|
||||
|
||||
if (I.decrementer_enabled && ! (I.flag & 1))
|
||||
{ /* timer */
|
||||
attotime period = ATTOTIME_IN_CYCLES(I.decrementer_interval * 16L, cpu_getactivecpu());
|
||||
attotime period = ATTOTIME_IN_CYCLES(I.decrementer_interval * 16L, cpunum_get_active());
|
||||
timer_adjust_periodic(I.timer, period, 0, period);
|
||||
}
|
||||
}
|
||||
@ -4815,7 +4815,7 @@ void TMS99XX_GET_INFO(UINT32 state, cpuinfo *info)
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &TMS99XX_ICOUNT; break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, TMS99XX_CPU_NAME); break;
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, TMS99XX_cpu_get_name); break;
|
||||
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Texas Instruments 9900"); break;
|
||||
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "2.0"); break;
|
||||
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
||||
|
@ -9,12 +9,12 @@
|
||||
|
||||
static void illegal(void)
|
||||
{
|
||||
logerror("uPD7810 #%d: illegal opcode %02x at PC:%04x\n", cpu_getactivecpu(), OP, PC);
|
||||
logerror("uPD7810 #%d: illegal opcode %02x at PC:%04x\n", cpunum_get_active(), OP, PC);
|
||||
}
|
||||
|
||||
static void illegal2(void)
|
||||
{
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpu_getactivecpu(), OP, OP2, PC);
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, OP2, PC);
|
||||
}
|
||||
|
||||
/* prefix 48 */
|
||||
@ -8654,7 +8654,7 @@ static void SKN_bit(void)
|
||||
val = RP( UPD7807_PORTT );
|
||||
break;
|
||||
default:
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpu_getactivecpu(), OP, imm, PC);
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC);
|
||||
val = 0;
|
||||
break;
|
||||
}
|
||||
@ -8708,7 +8708,7 @@ static void SETB(void)
|
||||
// PT is input only
|
||||
// break;
|
||||
default:
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpu_getactivecpu(), OP, imm, PC);
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -8758,7 +8758,7 @@ static void CLR(void)
|
||||
// PT is input only
|
||||
// break;
|
||||
default:
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpu_getactivecpu(), OP, imm, PC);
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -8807,7 +8807,7 @@ static void SK_bit(void)
|
||||
val = RP( UPD7807_PORTT );
|
||||
break;
|
||||
default:
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpu_getactivecpu(), OP, imm, PC);
|
||||
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC);
|
||||
val = 0;
|
||||
break;
|
||||
}
|
||||
|
@ -246,13 +246,13 @@ OP( 0x0f, i_pre_nec ) { UINT32 ModRM, tmp, tmp2;
|
||||
case 0x26 : CMP4S; break;
|
||||
case 0x28 : ModRM = FETCH; tmp = GetRMByte(ModRM); tmp <<= 4; tmp |= I.regs.b[AL] & 0xf; I.regs.b[AL] = (I.regs.b[AL] & 0xf0) | ((tmp>>8)&0xf); tmp &= 0xff; PutbackRMByte(ModRM,tmp); CLKM(9,15); break;
|
||||
case 0x2a : ModRM = FETCH; tmp = GetRMByte(ModRM); tmp2 = (I.regs.b[AL] & 0xf)<<4; I.regs.b[AL] = (I.regs.b[AL] & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(13,19); break;
|
||||
case 0x31 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",activecpu_get_pc()); break;
|
||||
case 0x33 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",activecpu_get_pc()); break;
|
||||
case 0x31 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x33 : ModRM = FETCH; ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x92 : CLK(2); break; /* V25/35 FINT */
|
||||
case 0xe0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",activecpu_get_pc()); break;
|
||||
case 0xf0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",activecpu_get_pc()); break;
|
||||
case 0xff : ModRM = FETCH; ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",activecpu_get_pc()); break;
|
||||
default: logerror("%06x: Unknown V20 instruction\n",activecpu_get_pc()); break;
|
||||
case 0xe0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented BRKXA (break to expansion address)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0xf0 : ModRM = FETCH; ModRM=0; logerror("%06x: V33 unimplemented RETXA (return from expansion address)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0xff : ModRM = FETCH; ModRM=0; logerror("%06x: unimplemented BRKEM (break to 8080 emulation mode)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
default: logerror("%06x: Unknown V20 instruction\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -382,7 +382,7 @@ OP( 0x62, i_chkind ) {
|
||||
} else {
|
||||
CLK(13);
|
||||
}
|
||||
logerror("%06x: bound %04x high %04x low %04x tmp\n",activecpu_get_pc(),high,low,tmp);
|
||||
logerror("%06x: bound %04x high %04x low %04x tmp\n",cpu_get_pc(Machine->activecpu),high,low,tmp);
|
||||
}
|
||||
OP( 0x64, i_repnc ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW];
|
||||
switch(next) { /* Segments */
|
||||
@ -407,7 +407,7 @@ OP( 0x64, i_repnc ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && !CF); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPNC invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPNC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
seg_prefix=FALSE;
|
||||
}
|
||||
@ -435,7 +435,7 @@ OP( 0x65, i_repc ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(2); if (c) do { i_lodsw(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(2); if (c) do { i_scasb(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(2); if (c) do { i_scasw(); c--; } while (c>0 && CF); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPC invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPC invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
seg_prefix=FALSE;
|
||||
}
|
||||
@ -539,7 +539,7 @@ OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); CLKM(2,3
|
||||
case 0x08: I.sregs[CS] = src; break; /* mov cs,ew */
|
||||
case 0x10: I.sregs[SS] = src; break; /* mov ss,ew */
|
||||
case 0x18: I.sregs[DS] = src; break; /* mov ds,ew */
|
||||
default: logerror("%06x: Mov Sreg - Invalid register\n",activecpu_get_pc());
|
||||
default: logerror("%06x: Mov Sreg - Invalid register\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
I.no_interrupt=1;
|
||||
}
|
||||
@ -560,7 +560,7 @@ OP( 0x97, i_xchg_axdi ) { XchgAWReg(IY); CLK(3); }
|
||||
OP( 0x98, i_cbw ) { I.regs.b[AH] = (I.regs.b[AL] & 0x80) ? 0xff : 0; CLK(1); }
|
||||
OP( 0x99, i_cwd ) { I.regs.w[DW] = (I.regs.b[AH] & 0x80) ? 0xffff : 0; CLK(1); }
|
||||
OP( 0x9a, i_call_far ) { UINT32 tmp, tmp2; FETCHWORD(tmp); FETCHWORD(tmp2); PUSH(I.sregs[CS]); PUSH(I.ip); I.ip = (WORD)tmp; I.sregs[CS] = (WORD)tmp2; CHANGE_PC; CLK(10); }
|
||||
OP( 0x9b, i_wait ) { logerror("%06x: Hardware POLL\n",activecpu_get_pc()); }
|
||||
OP( 0x9b, i_wait ) { logerror("%06x: Hardware POLL\n",cpu_get_pc(Machine->activecpu)); }
|
||||
OP( 0x9c, i_pushf ) { PUSH( CompressFlags() ); CLK(2); }
|
||||
OP( 0x9d, i_popf ) { UINT32 tmp; POP(tmp); ExpandFlags(tmp); CLK(3); if (I.TF) nec_trap(); }
|
||||
OP( 0x9e, i_sahf ) { UINT32 tmp = (CompressFlags() & 0xff00) | (I.regs.b[AH] & 0xd5); ExpandFlags(tmp); CLK(4); }
|
||||
@ -614,7 +614,7 @@ OP( 0xc0, i_rotshft_bd8 ) {
|
||||
case 0x18: do { RORC_BYTE; c--; } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break;
|
||||
case 0x20: SHL_BYTE(c); break;
|
||||
case 0x28: SHR_BYTE(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_BYTE(c); break;
|
||||
}
|
||||
}
|
||||
@ -631,7 +631,7 @@ OP( 0xc1, i_rotshft_wd8 ) {
|
||||
case 0x18: do { RORC_WORD; c--; } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break;
|
||||
case 0x20: SHL_WORD(c); break;
|
||||
case 0x28: SHR_WORD(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xc1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_WORD(c); break;
|
||||
}
|
||||
}
|
||||
@ -681,7 +681,7 @@ OP( 0xd0, i_rotshft_b ) {
|
||||
case 0x18: RORC_BYTE; PutbackRMByte(ModRM,(BYTE)dst); I.OverVal = (src^dst)&0x80; break;
|
||||
case 0x20: SHL_BYTE(1); I.OverVal = (src^dst)&0x80; break;
|
||||
case 0x28: SHR_BYTE(1); I.OverVal = (src^dst)&0x80; break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd0 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_BYTE(1); I.OverVal = 0; break;
|
||||
}
|
||||
}
|
||||
@ -696,7 +696,7 @@ OP( 0xd1, i_rotshft_w ) {
|
||||
case 0x18: RORC_WORD; PutbackRMWord(ModRM,(WORD)dst); I.OverVal = (src^dst)&0x8000; break;
|
||||
case 0x20: SHL_WORD(1); I.OverVal = (src^dst)&0x8000; break;
|
||||
case 0x28: SHR_WORD(1); I.OverVal = (src^dst)&0x8000; break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd1 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_WORD(1); I.OverVal = 0; break;
|
||||
}
|
||||
}
|
||||
@ -712,7 +712,7 @@ OP( 0xd2, i_rotshft_bcl ) {
|
||||
case 0x18: do { RORC_BYTE; c--; } while (c>0); PutbackRMByte(ModRM,(BYTE)dst); break;
|
||||
case 0x20: SHL_BYTE(c); break;
|
||||
case 0x28: SHR_BYTE(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd2 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_BYTE(c); break;
|
||||
}
|
||||
}
|
||||
@ -728,16 +728,16 @@ OP( 0xd3, i_rotshft_wcl ) {
|
||||
case 0x18: do { RORC_WORD; c--; } while (c>0); PutbackRMWord(ModRM,(WORD)dst); break;
|
||||
case 0x20: SHL_WORD(c); break;
|
||||
case 0x28: SHR_WORD(c); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",activecpu_get_pc()); break;
|
||||
case 0x30: logerror("%06x: Undefined opcode 0xd3 0x30 (SHLA)\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x38: SHRA_WORD(c); break;
|
||||
}
|
||||
}
|
||||
|
||||
OP( 0xd4, i_aam ) { UINT32 mult=FETCH; mult=0; I.regs.b[AH] = I.regs.b[AL] / 10; I.regs.b[AL] %= 10; SetSZPF_Word(I.regs.w[AW]); CLK(17); }
|
||||
OP( 0xd5, i_aad ) { UINT32 mult=FETCH; mult=0; I.regs.b[AL] = I.regs.b[AH] * 10 + I.regs.b[AL]; I.regs.b[AH] = 0; SetSZPF_Byte(I.regs.b[AL]); CLK(5); }
|
||||
OP( 0xd6, i_setalc ) { I.regs.b[AL] = (CF)?0xff:0x00; CLK(3); logerror("%06x: Undefined opcode (SETALC)\n",activecpu_get_pc()); }
|
||||
OP( 0xd6, i_setalc ) { I.regs.b[AL] = (CF)?0xff:0x00; CLK(3); logerror("%06x: Undefined opcode (SETALC)\n",cpu_get_pc(Machine->activecpu)); }
|
||||
OP( 0xd7, i_trans ) { UINT32 dest = (I.regs.w[BW]+I.regs.b[AL])&0xffff; I.regs.b[AL] = GetMemB(DS, dest); CLK(5); }
|
||||
OP( 0xd8, i_fpo ) { GetModRM; CLK(1); logerror("%06x: Unimplemented floating point control %04x\n",activecpu_get_pc(),ModRM); }
|
||||
OP( 0xd8, i_fpo ) { GetModRM; CLK(1); logerror("%06x: Unimplemented floating point control %04x\n",cpu_get_pc(Machine->activecpu),ModRM); }
|
||||
|
||||
OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if (!ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLK(6); } else CLK(3); }
|
||||
OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if ( ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLK(6); } else CLK(3); }
|
||||
@ -760,7 +760,7 @@ OP( 0xed, i_inaxdx ) { UINT32 port = I.regs.w[DW]; I.regs.b[AL] = read_port(po
|
||||
OP( 0xee, i_outdxal ) { write_port(I.regs.w[DW], I.regs.b[AL]); CLK(6); }
|
||||
OP( 0xef, i_outdxax ) { UINT32 port = I.regs.w[DW]; write_port(port, I.regs.b[AL]); write_port(port+1, I.regs.b[AH]); CLK(6); }
|
||||
|
||||
OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",activecpu_get_pc()); I.no_interrupt=1; CLK(1); }
|
||||
OP( 0xf0, i_lock ) { logerror("%06x: Warning - BUSLOCK\n",cpu_get_pc(Machine->activecpu)); I.no_interrupt=1; CLK(1); }
|
||||
OP( 0xf2, i_repne ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW];
|
||||
switch(next) { /* Segments */
|
||||
case 0x26: seg_prefix=TRUE; prefix_base=I.sregs[ES]<<4; next = FETCHOP; CLK(2); break;
|
||||
@ -784,7 +784,7 @@ OP( 0xf2, i_repne ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(3); if (c) do { i_lodsw(); c--; } while (c>0); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(3); if (c) do { i_scasb(); c--; } while (c>0 && ZF==0); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(3); if (c) do { i_scasw(); c--; } while (c>0 && ZF==0); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPNE invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPNE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
seg_prefix=FALSE;
|
||||
}
|
||||
@ -811,17 +811,17 @@ OP( 0xf3, i_repe ) { UINT32 next = FETCHOP; UINT16 c = I.regs.w[CW];
|
||||
case 0xad: CLK(3); if (c) do { i_lodsw(); c--; } while (c>0); I.regs.w[CW]=c; break;
|
||||
case 0xae: CLK(3); if (c) do { i_scasb(); c--; } while (c>0 && ZF==1); I.regs.w[CW]=c; break;
|
||||
case 0xaf: CLK(3); if (c) do { i_scasw(); c--; } while (c>0 && ZF==1); I.regs.w[CW]=c; break;
|
||||
default: logerror("%06x: REPE invalid\n",activecpu_get_pc()); nec_instruction[next]();
|
||||
default: logerror("%06x: REPE invalid\n",cpu_get_pc(Machine->activecpu)); nec_instruction[next]();
|
||||
}
|
||||
seg_prefix=FALSE;
|
||||
}
|
||||
OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",activecpu_get_pc()); nec_ICount=0; }
|
||||
OP( 0xf4, i_hlt ) { logerror("%06x: HALT\n",cpu_get_pc(Machine->activecpu)); nec_ICount=0; }
|
||||
OP( 0xf5, i_cmc ) { I.CarryVal = !CF; CLK(4); }
|
||||
OP( 0xf6, i_f6pre ) { UINT32 tmp; UINT32 uresult,uresult2; INT32 result,result2;
|
||||
GetModRM; tmp = GetRMByte(ModRM);
|
||||
switch (ModRM & 0x38) {
|
||||
case 0x00: tmp &= FETCH; I.CarryVal = I.OverVal = 0; SetSZPF_Byte(tmp); CLKM(1,2); break; /* TEST */
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",activecpu_get_pc()); break;
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf6 0x08\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x10: PutbackRMByte(ModRM,~tmp); CLKM(1,3); break; /* NOT */
|
||||
case 0x18: I.CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Byte(tmp); PutbackRMByte(ModRM,tmp&0xff); CLKM(1,3); break; /* NEG */
|
||||
case 0x20: uresult = I.regs.b[AL]*tmp; I.regs.w[AW]=(WORD)uresult; I.CarryVal=I.OverVal=(I.regs.b[AH]!=0); CLKM(3,4); break; /* MULU */
|
||||
@ -835,7 +835,7 @@ OP( 0xf7, i_f7pre ) { UINT32 tmp,tmp2; UINT32 uresult,uresult2; INT32 result,r
|
||||
GetModRM; tmp = GetRMWord(ModRM);
|
||||
switch (ModRM & 0x38) {
|
||||
case 0x00: FETCHWORD(tmp2); tmp &= tmp2; I.CarryVal = I.OverVal = 0; SetSZPF_Word(tmp); CLKM(1,2); break; /* TEST */
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",activecpu_get_pc()); break;
|
||||
case 0x08: logerror("%06x: Undefined opcode 0xf7 0x08\n",cpu_get_pc(Machine->activecpu)); break;
|
||||
case 0x10: PutbackRMWord(ModRM,~tmp); CLKM(1,3); break; /* NOT */
|
||||
case 0x18: I.CarryVal=(tmp!=0); tmp=(~tmp)+1; SetSZPF_Word(tmp); PutbackRMWord(ModRM,tmp&0xffff); CLKM(1,3); break; /* NEG */
|
||||
case 0x20: uresult = I.regs.w[AW]*tmp; I.regs.w[AW]=uresult&0xffff; I.regs.w[DW]=((UINT32)uresult)>>16; I.CarryVal=I.OverVal=(I.regs.w[DW]!=0); CLKM(3,4); break; /* MULU */
|
||||
@ -855,7 +855,7 @@ OP( 0xfe, i_fepre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMByte(ModRM);
|
||||
switch(ModRM & 0x38) {
|
||||
case 0x00: tmp1 = tmp+1; I.OverVal = (tmp==0x7f); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(1,3); break; /* INC */
|
||||
case 0x08: tmp1 = tmp-1; I.OverVal = (tmp==0x80); SetAF(tmp1,tmp,1); SetSZPF_Byte(tmp1); PutbackRMByte(ModRM,(BYTE)tmp1); CLKM(1,3); break; /* DEC */
|
||||
default: logerror("%06x: FE Pre with unimplemented mod\n",activecpu_get_pc());
|
||||
default: logerror("%06x: FE Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
}
|
||||
OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM);
|
||||
@ -867,14 +867,14 @@ OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM);
|
||||
case 0x20: I.ip = tmp; CHANGE_PC; CLKM(4,5); break; /* JMP */
|
||||
case 0x28: I.ip = tmp; I.sregs[CS] = GetnextRMWord; CHANGE_PC; CLK(10); break; /* JMP FAR */
|
||||
case 0x30: PUSH(tmp); CLK(1); break;
|
||||
default: logerror("%06x: FF Pre with unimplemented mod\n",activecpu_get_pc());
|
||||
default: logerror("%06x: FF Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
}
|
||||
|
||||
static void i_invalid(void)
|
||||
{
|
||||
nec_ICount-=10;
|
||||
logerror("%06x: Invalid Opcode\n",activecpu_get_pc());
|
||||
logerror("%06x: Invalid Opcode\n",cpu_get_pc(Machine->activecpu));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
@ -280,7 +280,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
|
||||
unsigned di = I.regs.w[IY]; \
|
||||
unsigned si = I.regs.w[IX]; \
|
||||
static const UINT8 table[3]={18,19,19}; \
|
||||
if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",activecpu_get_pc()); \
|
||||
if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",cpu_get_pc(Machine->activecpu)); \
|
||||
I.ZeroVal = I.CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
nec_ICount-=table[chip_type/8]; \
|
||||
@ -305,7 +305,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
|
||||
unsigned di = I.regs.w[IY]; \
|
||||
unsigned si = I.regs.w[IX]; \
|
||||
static const UINT8 table[3]={18,19,19}; \
|
||||
if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",activecpu_get_pc()); \
|
||||
if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",cpu_get_pc(Machine->activecpu)); \
|
||||
I.ZeroVal = I.CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
nec_ICount-=table[chip_type/8]; \
|
||||
@ -335,7 +335,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
|
||||
unsigned di = I.regs.w[IY]; \
|
||||
unsigned si = I.regs.w[IX]; \
|
||||
static const UINT8 table[3]={14,19,19}; \
|
||||
if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",activecpu_get_pc()); \
|
||||
if (seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",cpu_get_pc(Machine->activecpu)); \
|
||||
I.ZeroVal = I.CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
nec_ICount-=table[chip_type/8]; \
|
||||
|
@ -54,8 +54,9 @@ struct _vtlb_state
|
||||
given CPU
|
||||
-------------------------------------------------*/
|
||||
|
||||
vtlb_state *vtlb_alloc(int cpunum, int space, int fixed_entries, int dynamic_entries)
|
||||
vtlb_state *vtlb_alloc(const device_config *cpu, int space, int fixed_entries, int dynamic_entries)
|
||||
{
|
||||
char tempname[100];
|
||||
vtlb_state *vtlb;
|
||||
|
||||
/* allocate memory for the core structure */
|
||||
@ -66,31 +67,33 @@ vtlb_state *vtlb_alloc(int cpunum, int space, int fixed_entries, int dynamic_ent
|
||||
vtlb->space = space;
|
||||
vtlb->dynamic = dynamic_entries;
|
||||
vtlb->fixed = fixed_entries;
|
||||
vtlb->pageshift = cpunum_page_shift(cpunum, space);
|
||||
vtlb->addrwidth = cpunum_logaddr_width(cpunum, space);
|
||||
vtlb->translate = (cpu_translate_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_TRANSLATE);
|
||||
vtlb->pageshift = cpu_get_page_shift(cpu, space);
|
||||
vtlb->addrwidth = cpu_get_logaddr_width(cpu, space);
|
||||
vtlb->translate = (cpu_translate_func)cpu_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
|
||||
|
||||
/* validate CPU information */
|
||||
assert((1 << vtlb->pageshift) > VTLB_FLAGS_MASK);
|
||||
assert(vtlb->translate != NULL);
|
||||
assert(vtlb->addrwidth > vtlb->pageshift);
|
||||
|
||||
state_save_combine_module_and_tag(tempname, "vtlb", cpu->tag);
|
||||
|
||||
/* allocate the entry array */
|
||||
vtlb->live = malloc_or_die(sizeof(vtlb->live[0]) * (fixed_entries + dynamic_entries));
|
||||
memset(vtlb->live, 0, sizeof(vtlb->live[0]) * (fixed_entries + dynamic_entries));
|
||||
state_save_register_item_pointer("vtlb", cpunum * ADDRESS_SPACES + space, vtlb->live, fixed_entries + dynamic_entries);
|
||||
state_save_register_item_pointer(tempname, space, vtlb->live, fixed_entries + dynamic_entries);
|
||||
|
||||
/* allocate the lookup table */
|
||||
vtlb->table = malloc_or_die(sizeof(vtlb->table[0]) << (vtlb->addrwidth - vtlb->pageshift));
|
||||
memset(vtlb->table, 0, sizeof(vtlb->table[0]) << (vtlb->addrwidth - vtlb->pageshift));
|
||||
state_save_register_item_pointer("vtlb", cpunum * ADDRESS_SPACES + space, vtlb->table, 1 << (vtlb->addrwidth - vtlb->pageshift));
|
||||
state_save_register_item_pointer(tempname, space, vtlb->table, 1 << (vtlb->addrwidth - vtlb->pageshift));
|
||||
|
||||
/* allocate the fixed page count array */
|
||||
if (fixed_entries > 0)
|
||||
{
|
||||
vtlb->fixedpages = malloc_or_die(sizeof(vtlb->fixedpages[0]) * fixed_entries);
|
||||
memset(vtlb->fixedpages, 0, sizeof(vtlb->fixedpages[0]) * fixed_entries);
|
||||
state_save_register_item_pointer("vtlb", cpunum * ADDRESS_SPACES + space, vtlb->fixedpages, fixed_entries);
|
||||
state_save_register_item_pointer(tempname, space, vtlb->fixedpages, fixed_entries);
|
||||
}
|
||||
return vtlb;
|
||||
}
|
||||
|
@ -56,7 +56,7 @@ typedef struct _vtlb_state vtlb_state;
|
||||
/* ----- initialization/teardown ----- */
|
||||
|
||||
/* allocate a new VTLB for the given CPU */
|
||||
vtlb_state *vtlb_alloc(int cpunum, int space, int fixed_entries, int dynamic_entries);
|
||||
vtlb_state *vtlb_alloc(const device_config *cpu, int space, int fixed_entries, int dynamic_entries);
|
||||
|
||||
/* free an allocated VTLB */
|
||||
void vtlb_free(vtlb_state *vtlb);
|
||||
|
@ -824,68 +824,68 @@ static UINT8 z180_readcontrol(offs_t port)
|
||||
{
|
||||
case Z180_CNTLA0:
|
||||
data = IO_CNTLA0 & Z180_CNTLA0_RMASK;
|
||||
LOG(("Z180 #%d CNTLA0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CNTLA0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CNTLA1:
|
||||
data = IO_CNTLA1 & Z180_CNTLA1_RMASK;
|
||||
LOG(("Z180 #%d CNTLA1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CNTLA1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CNTLB0:
|
||||
data = IO_CNTLB0 & Z180_CNTLB0_RMASK;
|
||||
LOG(("Z180 #%d CNTLB0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CNTLB0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CNTLB1:
|
||||
data = IO_CNTLB1 & Z180_CNTLB1_RMASK;
|
||||
LOG(("Z180 #%d CNTLB1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CNTLB1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_STAT0:
|
||||
data = IO_STAT0 & Z180_STAT0_RMASK;
|
||||
data |= 0x02; // kludge for 20pacgal
|
||||
LOG(("Z180 #%d STAT0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d STAT0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_STAT1:
|
||||
data = IO_STAT1 & Z180_STAT1_RMASK;
|
||||
LOG(("Z180 #%d STAT1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d STAT1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_TDR0:
|
||||
data = IO_TDR0 & Z180_TDR0_RMASK;
|
||||
LOG(("Z180 #%d TDR0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TDR0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_TDR1:
|
||||
data = IO_TDR1 & Z180_TDR1_RMASK;
|
||||
LOG(("Z180 #%d TDR1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TDR1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_RDR0:
|
||||
data = IO_RDR0 & Z180_RDR0_RMASK;
|
||||
LOG(("Z180 #%d RDR0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d RDR0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_RDR1:
|
||||
data = IO_RDR1 & Z180_RDR1_RMASK;
|
||||
LOG(("Z180 #%d RDR1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d RDR1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CNTR:
|
||||
data = IO_CNTR & Z180_CNTR_RMASK;
|
||||
LOG(("Z180 #%d CNTR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CNTR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_TRDR:
|
||||
data = IO_TRDR & Z180_TRDR_RMASK;
|
||||
LOG(("Z180 #%d TRDR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TRDR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_TMDR0L:
|
||||
data = Z180.tmdr_value[0] & Z180_TMDR0L_RMASK;
|
||||
LOG(("Z180 #%d TMDR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TMDR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
/* if timer is counting, latch the MSB and set the latch flag */
|
||||
if ((IO_TCR & Z180_TCR_TDE0) == 0)
|
||||
{
|
||||
@ -925,17 +925,17 @@ data |= 0x02; // kludge for 20pacgal
|
||||
{
|
||||
Z180.read_tcr_tmdr[0] = 1;
|
||||
}
|
||||
LOG(("Z180 #%d TMDR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TMDR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_RLDR0L:
|
||||
data = IO_RLDR0L & Z180_RLDR0L_RMASK;
|
||||
LOG(("Z180 #%d RLDR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d RLDR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_RLDR0H:
|
||||
data = IO_RLDR0H & Z180_RLDR0H_RMASK;
|
||||
LOG(("Z180 #%d RLDR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d RLDR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_TCR:
|
||||
@ -961,27 +961,27 @@ data |= 0x02; // kludge for 20pacgal
|
||||
Z180.read_tcr_tmdr[1] = 1;
|
||||
}
|
||||
|
||||
LOG(("Z180 #%d TCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IO11:
|
||||
data = IO_IO11 & Z180_IO11_RMASK;
|
||||
LOG(("Z180 #%d IO11 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IO11 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_ASEXT0:
|
||||
data = IO_ASEXT0 & Z180_ASEXT0_RMASK;
|
||||
LOG(("Z180 #%d ASEXT0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d ASEXT0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_ASEXT1:
|
||||
data = IO_ASEXT1 & Z180_ASEXT1_RMASK;
|
||||
LOG(("Z180 #%d ASEXT1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d ASEXT1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_TMDR1L:
|
||||
data = Z180.tmdr_value[1] & Z180_TMDR1L_RMASK;
|
||||
LOG(("Z180 #%d TMDR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TMDR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
/* if timer is counting, latch the MSB and set the latch flag */
|
||||
if ((IO_TCR & Z180_TCR_TDE1) == 0)
|
||||
{
|
||||
@ -1021,217 +1021,217 @@ data |= 0x02; // kludge for 20pacgal
|
||||
{
|
||||
Z180.read_tcr_tmdr[1] = 1;
|
||||
}
|
||||
LOG(("Z180 #%d TMDR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d TMDR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_RLDR1L:
|
||||
data = IO_RLDR1L & Z180_RLDR1L_RMASK;
|
||||
LOG(("Z180 #%d RLDR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d RLDR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_RLDR1H:
|
||||
data = IO_RLDR1H & Z180_RLDR1H_RMASK;
|
||||
LOG(("Z180 #%d RLDR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d RLDR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_FRC:
|
||||
data = IO_FRC & Z180_FRC_RMASK;
|
||||
LOG(("Z180 #%d FRC rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d FRC rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IO19:
|
||||
data = IO_IO19 & Z180_IO19_RMASK;
|
||||
LOG(("Z180 #%d IO19 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IO19 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_ASTC0L:
|
||||
data = IO_ASTC0L & Z180_ASTC0L_RMASK;
|
||||
LOG(("Z180 #%d ASTC0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d ASTC0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_ASTC0H:
|
||||
data = IO_ASTC0H & Z180_ASTC0H_RMASK;
|
||||
LOG(("Z180 #%d ASTC0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d ASTC0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_ASTC1L:
|
||||
data = IO_ASTC1L & Z180_ASTC1L_RMASK;
|
||||
LOG(("Z180 #%d ASTC1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d ASTC1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_ASTC1H:
|
||||
data = IO_ASTC1H & Z180_ASTC1H_RMASK;
|
||||
LOG(("Z180 #%d ASTC1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d ASTC1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CMR:
|
||||
data = IO_CMR & Z180_CMR_RMASK;
|
||||
LOG(("Z180 #%d CMR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CMR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CCR:
|
||||
data = IO_CCR & Z180_CCR_RMASK;
|
||||
LOG(("Z180 #%d CCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_SAR0L:
|
||||
data = IO_SAR0L & Z180_SAR0L_RMASK;
|
||||
LOG(("Z180 #%d SAR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d SAR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_SAR0H:
|
||||
data = IO_SAR0H & Z180_SAR0H_RMASK;
|
||||
LOG(("Z180 #%d SAR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d SAR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_SAR0B:
|
||||
data = IO_SAR0B & Z180_SAR0B_RMASK;
|
||||
LOG(("Z180 #%d SAR0B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d SAR0B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_DAR0L:
|
||||
data = IO_DAR0L & Z180_DAR0L_RMASK;
|
||||
LOG(("Z180 #%d DAR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d DAR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_DAR0H:
|
||||
data = IO_DAR0H & Z180_DAR0H_RMASK;
|
||||
LOG(("Z180 #%d DAR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d DAR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_DAR0B:
|
||||
data = IO_DAR0B & Z180_DAR0B_RMASK;
|
||||
LOG(("Z180 #%d DAR0B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d DAR0B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_BCR0L:
|
||||
data = IO_BCR0L & Z180_BCR0L_RMASK;
|
||||
LOG(("Z180 #%d BCR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d BCR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_BCR0H:
|
||||
data = IO_BCR0H & Z180_BCR0H_RMASK;
|
||||
LOG(("Z180 #%d BCR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d BCR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_MAR1L:
|
||||
data = IO_MAR1L & Z180_MAR1L_RMASK;
|
||||
LOG(("Z180 #%d MAR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d MAR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_MAR1H:
|
||||
data = IO_MAR1H & Z180_MAR1H_RMASK;
|
||||
LOG(("Z180 #%d MAR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d MAR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_MAR1B:
|
||||
data = IO_MAR1B & Z180_MAR1B_RMASK;
|
||||
LOG(("Z180 #%d MAR1B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d MAR1B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IAR1L:
|
||||
data = IO_IAR1L & Z180_IAR1L_RMASK;
|
||||
LOG(("Z180 #%d IAR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IAR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IAR1H:
|
||||
data = IO_IAR1H & Z180_IAR1H_RMASK;
|
||||
LOG(("Z180 #%d IAR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IAR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IAR1B:
|
||||
data = IO_IAR1B & Z180_IAR1B_RMASK;
|
||||
LOG(("Z180 #%d IAR1B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IAR1B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_BCR1L:
|
||||
data = IO_BCR1L & Z180_BCR1L_RMASK;
|
||||
LOG(("Z180 #%d BCR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d BCR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_BCR1H:
|
||||
data = IO_BCR1H & Z180_BCR1H_RMASK;
|
||||
LOG(("Z180 #%d BCR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d BCR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_DSTAT:
|
||||
data = IO_DSTAT & Z180_DSTAT_RMASK;
|
||||
LOG(("Z180 #%d DSTAT rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d DSTAT rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_DMODE:
|
||||
data = IO_DMODE & Z180_DMODE_RMASK;
|
||||
LOG(("Z180 #%d DMODE rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d DMODE rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_DCNTL:
|
||||
data = IO_DCNTL & Z180_DCNTL_RMASK;
|
||||
LOG(("Z180 #%d DCNTL rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d DCNTL rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IL:
|
||||
data = IO_IL & Z180_IL_RMASK;
|
||||
LOG(("Z180 #%d IL rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IL rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_ITC:
|
||||
data = IO_ITC & Z180_ITC_RMASK;
|
||||
LOG(("Z180 #%d ITC rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d ITC rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IO35:
|
||||
data = IO_IO35 & Z180_IO35_RMASK;
|
||||
LOG(("Z180 #%d IO35 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IO35 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_RCR:
|
||||
data = IO_RCR & Z180_RCR_RMASK;
|
||||
LOG(("Z180 #%d RCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d RCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IO37:
|
||||
data = IO_IO37 & Z180_IO37_RMASK;
|
||||
LOG(("Z180 #%d IO37 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IO37 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CBR:
|
||||
data = IO_CBR & Z180_CBR_RMASK;
|
||||
LOG(("Z180 #%d CBR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CBR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_BBR:
|
||||
data = IO_BBR & Z180_BBR_RMASK;
|
||||
LOG(("Z180 #%d BBR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d BBR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_CBAR:
|
||||
data = IO_CBAR & Z180_CBAR_RMASK;
|
||||
LOG(("Z180 #%d CBAR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d CBAR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IO3B:
|
||||
data = IO_IO3B & Z180_IO3B_RMASK;
|
||||
LOG(("Z180 #%d IO3B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IO3B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IO3C:
|
||||
data = IO_IO3C & Z180_IO3C_RMASK;
|
||||
LOG(("Z180 #%d IO3C rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IO3C rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IO3D:
|
||||
data = IO_IO3D & Z180_IO3D_RMASK;
|
||||
LOG(("Z180 #%d IO3D rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IO3D rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_OMCR:
|
||||
data = IO_OMCR & Z180_OMCR_RMASK;
|
||||
LOG(("Z180 #%d OMCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d OMCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
|
||||
case Z180_IOCR:
|
||||
data = IO_IOCR & Z180_IOCR_RMASK;
|
||||
LOG(("Z180 #%d IOCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
|
||||
LOG(("Z180 #%d IOCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f]));
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1251,251 +1251,251 @@ static void z180_writecontrol(offs_t port, UINT8 data)
|
||||
switch (port + Z180_CNTLA0)
|
||||
{
|
||||
case Z180_CNTLA0:
|
||||
LOG(("Z180 #%d CNTLA0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLA0_WMASK));
|
||||
LOG(("Z180 #%d CNTLA0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLA0_WMASK));
|
||||
IO_CNTLA0 = (IO_CNTLA0 & ~Z180_CNTLA0_WMASK) | (data & Z180_CNTLA0_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_CNTLA1:
|
||||
LOG(("Z180 #%d CNTLA1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLA1_WMASK));
|
||||
LOG(("Z180 #%d CNTLA1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLA1_WMASK));
|
||||
IO_CNTLA1 = (IO_CNTLA1 & ~Z180_CNTLA1_WMASK) | (data & Z180_CNTLA1_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_CNTLB0:
|
||||
LOG(("Z180 #%d CNTLB0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLB0_WMASK));
|
||||
LOG(("Z180 #%d CNTLB0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLB0_WMASK));
|
||||
IO_CNTLB0 = (IO_CNTLB0 & ~Z180_CNTLB0_WMASK) | (data & Z180_CNTLB0_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_CNTLB1:
|
||||
LOG(("Z180 #%d CNTLB1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLB1_WMASK));
|
||||
LOG(("Z180 #%d CNTLB1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLB1_WMASK));
|
||||
IO_CNTLB1 = (IO_CNTLB1 & ~Z180_CNTLB1_WMASK) | (data & Z180_CNTLB1_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_STAT0:
|
||||
LOG(("Z180 #%d STAT0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_STAT0_WMASK));
|
||||
LOG(("Z180 #%d STAT0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_STAT0_WMASK));
|
||||
IO_STAT0 = (IO_STAT0 & ~Z180_STAT0_WMASK) | (data & Z180_STAT0_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_STAT1:
|
||||
LOG(("Z180 #%d STAT1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_STAT1_WMASK));
|
||||
LOG(("Z180 #%d STAT1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_STAT1_WMASK));
|
||||
IO_STAT1 = (IO_STAT1 & ~Z180_STAT1_WMASK) | (data & Z180_STAT1_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_TDR0:
|
||||
LOG(("Z180 #%d TDR0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TDR0_WMASK));
|
||||
LOG(("Z180 #%d TDR0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TDR0_WMASK));
|
||||
IO_TDR0 = (IO_TDR0 & ~Z180_TDR0_WMASK) | (data & Z180_TDR0_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_TDR1:
|
||||
LOG(("Z180 #%d TDR1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TDR1_WMASK));
|
||||
LOG(("Z180 #%d TDR1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TDR1_WMASK));
|
||||
IO_TDR1 = (IO_TDR1 & ~Z180_TDR1_WMASK) | (data & Z180_TDR1_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_RDR0:
|
||||
LOG(("Z180 #%d RDR0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RDR0_WMASK));
|
||||
LOG(("Z180 #%d RDR0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RDR0_WMASK));
|
||||
IO_RDR0 = (IO_RDR0 & ~Z180_RDR0_WMASK) | (data & Z180_RDR0_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_RDR1:
|
||||
LOG(("Z180 #%d RDR1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RDR1_WMASK));
|
||||
LOG(("Z180 #%d RDR1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RDR1_WMASK));
|
||||
IO_RDR1 = (IO_RDR1 & ~Z180_RDR1_WMASK) | (data & Z180_RDR1_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_CNTR:
|
||||
LOG(("Z180 #%d CNTR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTR_WMASK));
|
||||
LOG(("Z180 #%d CNTR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTR_WMASK));
|
||||
IO_CNTR = (IO_CNTR & ~Z180_CNTR_WMASK) | (data & Z180_CNTR_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_TRDR:
|
||||
LOG(("Z180 #%d TRDR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TRDR_WMASK));
|
||||
LOG(("Z180 #%d TRDR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TRDR_WMASK));
|
||||
IO_TRDR = (IO_TRDR & ~Z180_TRDR_WMASK) | (data & Z180_TRDR_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_TMDR0L:
|
||||
LOG(("Z180 #%d TMDR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR0L_WMASK));
|
||||
LOG(("Z180 #%d TMDR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR0L_WMASK));
|
||||
IO_TMDR0L = data & Z180_TMDR0L_WMASK;
|
||||
Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0xff00) | IO_TMDR0L;
|
||||
break;
|
||||
|
||||
case Z180_TMDR0H:
|
||||
LOG(("Z180 #%d TMDR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR0H_WMASK));
|
||||
LOG(("Z180 #%d TMDR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR0H_WMASK));
|
||||
IO_TMDR0H = data & Z180_TMDR0H_WMASK;
|
||||
Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0x00ff) | (IO_TMDR0H << 8);
|
||||
break;
|
||||
|
||||
case Z180_RLDR0L:
|
||||
LOG(("Z180 #%d RLDR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR0L_WMASK));
|
||||
LOG(("Z180 #%d RLDR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR0L_WMASK));
|
||||
IO_RLDR0L = (IO_RLDR0L & ~Z180_RLDR0L_WMASK) | (data & Z180_RLDR0L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_RLDR0H:
|
||||
LOG(("Z180 #%d RLDR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR0H_WMASK));
|
||||
LOG(("Z180 #%d RLDR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR0H_WMASK));
|
||||
IO_RLDR0H = (IO_RLDR0H & ~Z180_RLDR0H_WMASK) | (data & Z180_RLDR0H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_TCR:
|
||||
LOG(("Z180 #%d TCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TCR_WMASK));
|
||||
LOG(("Z180 #%d TCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TCR_WMASK));
|
||||
IO_TCR = (IO_TCR & ~Z180_TCR_WMASK) | (data & Z180_TCR_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IO11:
|
||||
LOG(("Z180 #%d IO11 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO11_WMASK));
|
||||
LOG(("Z180 #%d IO11 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO11_WMASK));
|
||||
IO_IO11 = (IO_IO11 & ~Z180_IO11_WMASK) | (data & Z180_IO11_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_ASEXT0:
|
||||
LOG(("Z180 #%d ASEXT0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASEXT0_WMASK));
|
||||
LOG(("Z180 #%d ASEXT0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASEXT0_WMASK));
|
||||
IO_ASEXT0 = (IO_ASEXT0 & ~Z180_ASEXT0_WMASK) | (data & Z180_ASEXT0_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_ASEXT1:
|
||||
LOG(("Z180 #%d ASEXT1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASEXT1_WMASK));
|
||||
LOG(("Z180 #%d ASEXT1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASEXT1_WMASK));
|
||||
IO_ASEXT1 = (IO_ASEXT1 & ~Z180_ASEXT1_WMASK) | (data & Z180_ASEXT1_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_TMDR1L:
|
||||
LOG(("Z180 #%d TMDR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR1L_WMASK));
|
||||
LOG(("Z180 #%d TMDR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR1L_WMASK));
|
||||
IO_TMDR1L = data & Z180_TMDR1L_WMASK;
|
||||
Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0xff00) | IO_TMDR1L;
|
||||
break;
|
||||
|
||||
case Z180_TMDR1H:
|
||||
LOG(("Z180 #%d TMDR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR1H_WMASK));
|
||||
LOG(("Z180 #%d TMDR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR1H_WMASK));
|
||||
IO_TMDR1H = data & Z180_TMDR1H_WMASK;
|
||||
Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0x00ff) | IO_TMDR1H;
|
||||
break;
|
||||
|
||||
case Z180_RLDR1L:
|
||||
LOG(("Z180 #%d RLDR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR1L_WMASK));
|
||||
LOG(("Z180 #%d RLDR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR1L_WMASK));
|
||||
IO_RLDR1L = (IO_RLDR1L & ~Z180_RLDR1L_WMASK) | (data & Z180_RLDR1L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_RLDR1H:
|
||||
LOG(("Z180 #%d RLDR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR1H_WMASK));
|
||||
LOG(("Z180 #%d RLDR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR1H_WMASK));
|
||||
IO_RLDR1H = (IO_RLDR1H & ~Z180_RLDR1H_WMASK) | (data & Z180_RLDR1H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_FRC:
|
||||
LOG(("Z180 #%d FRC wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_FRC_WMASK));
|
||||
LOG(("Z180 #%d FRC wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_FRC_WMASK));
|
||||
IO_FRC = (IO_FRC & ~Z180_FRC_WMASK) | (data & Z180_FRC_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IO19:
|
||||
LOG(("Z180 #%d IO19 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO19_WMASK));
|
||||
LOG(("Z180 #%d IO19 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO19_WMASK));
|
||||
IO_IO19 = (IO_IO19 & ~Z180_IO19_WMASK) | (data & Z180_IO19_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_ASTC0L:
|
||||
LOG(("Z180 #%d ASTC0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC0L_WMASK));
|
||||
LOG(("Z180 #%d ASTC0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC0L_WMASK));
|
||||
IO_ASTC0L = (IO_ASTC0L & ~Z180_ASTC0L_WMASK) | (data & Z180_ASTC0L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_ASTC0H:
|
||||
LOG(("Z180 #%d ASTC0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC0H_WMASK));
|
||||
LOG(("Z180 #%d ASTC0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC0H_WMASK));
|
||||
IO_ASTC0H = (IO_ASTC0H & ~Z180_ASTC0H_WMASK) | (data & Z180_ASTC0H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_ASTC1L:
|
||||
LOG(("Z180 #%d ASTC1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC1L_WMASK));
|
||||
LOG(("Z180 #%d ASTC1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC1L_WMASK));
|
||||
IO_ASTC1L = (IO_ASTC1L & ~Z180_ASTC1L_WMASK) | (data & Z180_ASTC1L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_ASTC1H:
|
||||
LOG(("Z180 #%d ASTC1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC1H_WMASK));
|
||||
LOG(("Z180 #%d ASTC1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC1H_WMASK));
|
||||
IO_ASTC1H = (IO_ASTC1H & ~Z180_ASTC1H_WMASK) | (data & Z180_ASTC1H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_CMR:
|
||||
LOG(("Z180 #%d CMR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CMR_WMASK));
|
||||
LOG(("Z180 #%d CMR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CMR_WMASK));
|
||||
IO_CMR = (IO_CMR & ~Z180_CMR_WMASK) | (data & Z180_CMR_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_CCR:
|
||||
LOG(("Z180 #%d CCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CCR_WMASK));
|
||||
LOG(("Z180 #%d CCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CCR_WMASK));
|
||||
IO_CCR = (IO_CCR & ~Z180_CCR_WMASK) | (data & Z180_CCR_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_SAR0L:
|
||||
LOG(("Z180 #%d SAR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0L_WMASK));
|
||||
LOG(("Z180 #%d SAR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_SAR0L_WMASK));
|
||||
IO_SAR0L = (IO_SAR0L & ~Z180_SAR0L_WMASK) | (data & Z180_SAR0L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_SAR0H:
|
||||
LOG(("Z180 #%d SAR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0H_WMASK));
|
||||
LOG(("Z180 #%d SAR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_SAR0H_WMASK));
|
||||
IO_SAR0H = (IO_SAR0H & ~Z180_SAR0H_WMASK) | (data & Z180_SAR0H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_SAR0B:
|
||||
LOG(("Z180 #%d SAR0B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0B_WMASK));
|
||||
LOG(("Z180 #%d SAR0B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_SAR0B_WMASK));
|
||||
IO_SAR0B = (IO_SAR0B & ~Z180_SAR0B_WMASK) | (data & Z180_SAR0B_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_DAR0L:
|
||||
LOG(("Z180 #%d DAR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0L_WMASK));
|
||||
LOG(("Z180 #%d DAR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DAR0L_WMASK));
|
||||
IO_DAR0L = (IO_DAR0L & ~Z180_DAR0L_WMASK) | (data & Z180_DAR0L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_DAR0H:
|
||||
LOG(("Z180 #%d DAR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0H_WMASK));
|
||||
LOG(("Z180 #%d DAR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DAR0H_WMASK));
|
||||
IO_DAR0H = (IO_DAR0H & ~Z180_DAR0H_WMASK) | (data & Z180_DAR0H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_DAR0B:
|
||||
LOG(("Z180 #%d DAR0B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0B_WMASK));
|
||||
LOG(("Z180 #%d DAR0B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DAR0B_WMASK));
|
||||
IO_DAR0B = (IO_DAR0B & ~Z180_DAR0B_WMASK) | (data & Z180_DAR0B_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_BCR0L:
|
||||
LOG(("Z180 #%d BCR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR0L_WMASK));
|
||||
LOG(("Z180 #%d BCR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR0L_WMASK));
|
||||
IO_BCR0L = (IO_BCR0L & ~Z180_BCR0L_WMASK) | (data & Z180_BCR0L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_BCR0H:
|
||||
LOG(("Z180 #%d BCR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR0H_WMASK));
|
||||
LOG(("Z180 #%d BCR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR0H_WMASK));
|
||||
IO_BCR0H = (IO_BCR0H & ~Z180_BCR0H_WMASK) | (data & Z180_BCR0H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_MAR1L:
|
||||
LOG(("Z180 #%d MAR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1L_WMASK));
|
||||
LOG(("Z180 #%d MAR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_MAR1L_WMASK));
|
||||
IO_MAR1L = (IO_MAR1L & ~Z180_MAR1L_WMASK) | (data & Z180_MAR1L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_MAR1H:
|
||||
LOG(("Z180 #%d MAR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1H_WMASK));
|
||||
LOG(("Z180 #%d MAR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_MAR1H_WMASK));
|
||||
IO_MAR1H = (IO_MAR1H & ~Z180_MAR1H_WMASK) | (data & Z180_MAR1H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_MAR1B:
|
||||
LOG(("Z180 #%d MAR1B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1B_WMASK));
|
||||
LOG(("Z180 #%d MAR1B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_MAR1B_WMASK));
|
||||
IO_MAR1B = (IO_MAR1B & ~Z180_MAR1B_WMASK) | (data & Z180_MAR1B_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IAR1L:
|
||||
LOG(("Z180 #%d IAR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1L_WMASK));
|
||||
LOG(("Z180 #%d IAR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IAR1L_WMASK));
|
||||
IO_IAR1L = (IO_IAR1L & ~Z180_IAR1L_WMASK) | (data & Z180_IAR1L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IAR1H:
|
||||
LOG(("Z180 #%d IAR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1H_WMASK));
|
||||
LOG(("Z180 #%d IAR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IAR1H_WMASK));
|
||||
IO_IAR1H = (IO_IAR1H & ~Z180_IAR1H_WMASK) | (data & Z180_IAR1H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IAR1B:
|
||||
LOG(("Z180 #%d IAR1B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1B_WMASK));
|
||||
LOG(("Z180 #%d IAR1B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IAR1B_WMASK));
|
||||
IO_IAR1B = (IO_IAR1B & ~Z180_IAR1B_WMASK) | (data & Z180_IAR1B_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_BCR1L:
|
||||
LOG(("Z180 #%d BCR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR1L_WMASK));
|
||||
LOG(("Z180 #%d BCR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR1L_WMASK));
|
||||
IO_BCR1L = (IO_BCR1L & ~Z180_BCR1L_WMASK) | (data & Z180_BCR1L_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_BCR1H:
|
||||
LOG(("Z180 #%d BCR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR1H_WMASK));
|
||||
LOG(("Z180 #%d BCR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR1H_WMASK));
|
||||
IO_BCR1H = (IO_BCR1H & ~Z180_BCR1H_WMASK) | (data & Z180_BCR1H_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_DSTAT:
|
||||
LOG(("Z180 #%d DSTAT wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DSTAT_WMASK));
|
||||
LOG(("Z180 #%d DSTAT wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DSTAT_WMASK));
|
||||
IO_DSTAT = (IO_DSTAT & ~Z180_DSTAT_WMASK) | (data & Z180_DSTAT_WMASK);
|
||||
if ((data & (Z180_DSTAT_DE1 | Z180_DSTAT_DWE1)) == Z180_DSTAT_DE1)
|
||||
IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
|
||||
@ -1504,80 +1504,80 @@ static void z180_writecontrol(offs_t port, UINT8 data)
|
||||
break;
|
||||
|
||||
case Z180_DMODE:
|
||||
LOG(("Z180 #%d DMODE wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DMODE_WMASK));
|
||||
LOG(("Z180 #%d DMODE wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DMODE_WMASK));
|
||||
IO_DMODE = (IO_DMODE & ~Z180_DMODE_WMASK) | (data & Z180_DMODE_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_DCNTL:
|
||||
LOG(("Z180 #%d DCNTL wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DCNTL_WMASK));
|
||||
LOG(("Z180 #%d DCNTL wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DCNTL_WMASK));
|
||||
IO_DCNTL = (IO_DCNTL & ~Z180_DCNTL_WMASK) | (data & Z180_DCNTL_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IL:
|
||||
LOG(("Z180 #%d IL wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IL_WMASK));
|
||||
LOG(("Z180 #%d IL wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IL_WMASK));
|
||||
IO_IL = (IO_IL & ~Z180_IL_WMASK) | (data & Z180_IL_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_ITC:
|
||||
LOG(("Z180 #%d ITC wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ITC_WMASK));
|
||||
LOG(("Z180 #%d ITC wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ITC_WMASK));
|
||||
IO_ITC = (IO_ITC & ~Z180_ITC_WMASK) | (data & Z180_ITC_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IO35:
|
||||
LOG(("Z180 #%d IO35 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO35_WMASK));
|
||||
LOG(("Z180 #%d IO35 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO35_WMASK));
|
||||
IO_IO35 = (IO_IO35 & ~Z180_IO35_WMASK) | (data & Z180_IO35_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_RCR:
|
||||
LOG(("Z180 #%d RCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RCR_WMASK));
|
||||
LOG(("Z180 #%d RCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RCR_WMASK));
|
||||
IO_RCR = (IO_RCR & ~Z180_RCR_WMASK) | (data & Z180_RCR_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IO37:
|
||||
LOG(("Z180 #%d IO37 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO37_WMASK));
|
||||
LOG(("Z180 #%d IO37 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO37_WMASK));
|
||||
IO_IO37 = (IO_IO37 & ~Z180_IO37_WMASK) | (data & Z180_IO37_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_CBR:
|
||||
LOG(("Z180 #%d CBR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CBR_WMASK));
|
||||
LOG(("Z180 #%d CBR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CBR_WMASK));
|
||||
IO_CBR = (IO_CBR & ~Z180_CBR_WMASK) | (data & Z180_CBR_WMASK);
|
||||
z180_mmu();
|
||||
break;
|
||||
|
||||
case Z180_BBR:
|
||||
LOG(("Z180 #%d BBR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BBR_WMASK));
|
||||
LOG(("Z180 #%d BBR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BBR_WMASK));
|
||||
IO_BBR = (IO_BBR & ~Z180_BBR_WMASK) | (data & Z180_BBR_WMASK);
|
||||
z180_mmu();
|
||||
break;
|
||||
|
||||
case Z180_CBAR:
|
||||
LOG(("Z180 #%d CBAR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CBAR_WMASK));
|
||||
LOG(("Z180 #%d CBAR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CBAR_WMASK));
|
||||
IO_CBAR = (IO_CBAR & ~Z180_CBAR_WMASK) | (data & Z180_CBAR_WMASK);
|
||||
z180_mmu();
|
||||
break;
|
||||
|
||||
case Z180_IO3B:
|
||||
LOG(("Z180 #%d IO3B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3B_WMASK));
|
||||
LOG(("Z180 #%d IO3B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO3B_WMASK));
|
||||
IO_IO3B = (IO_IO3B & ~Z180_IO3B_WMASK) | (data & Z180_IO3B_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IO3C:
|
||||
LOG(("Z180 #%d IO3C wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3C_WMASK));
|
||||
LOG(("Z180 #%d IO3C wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO3C_WMASK));
|
||||
IO_IO3C = (IO_IO3C & ~Z180_IO3C_WMASK) | (data & Z180_IO3C_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IO3D:
|
||||
LOG(("Z180 #%d IO3D wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3D_WMASK));
|
||||
LOG(("Z180 #%d IO3D wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO3D_WMASK));
|
||||
IO_IO3D = (IO_IO3D & ~Z180_IO3D_WMASK) | (data & Z180_IO3D_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_OMCR:
|
||||
LOG(("Z180 #%d OMCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_OMCR_WMASK));
|
||||
LOG(("Z180 #%d OMCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_OMCR_WMASK));
|
||||
IO_OMCR = (IO_OMCR & ~Z180_OMCR_WMASK) | (data & Z180_OMCR_WMASK);
|
||||
break;
|
||||
|
||||
case Z180_IOCR:
|
||||
LOG(("Z180 #%d IOCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IOCR_WMASK));
|
||||
LOG(("Z180 #%d IOCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IOCR_WMASK));
|
||||
IO_IOCR = (IO_IOCR & ~Z180_IOCR_WMASK) | (data & Z180_IOCR_WMASK);
|
||||
break;
|
||||
}
|
||||
@ -1780,120 +1780,120 @@ static void z180_write_iolines(UINT32 data)
|
||||
/* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
|
||||
if (changes & Z180_CKA0)
|
||||
{
|
||||
LOG(("Z180 #%d CKA0 %d\n", cpu_getactivecpu(), data & Z180_CKA0 ? 1 : 0));
|
||||
LOG(("Z180 #%d CKA0 %d\n", cpunum_get_active(), data & Z180_CKA0 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_CKA0) | (data & Z180_CKA0);
|
||||
}
|
||||
|
||||
/* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
|
||||
if (changes & Z180_CKA1)
|
||||
{
|
||||
LOG(("Z180 #%d CKA1 %d\n", cpu_getactivecpu(), data & Z180_CKA1 ? 1 : 0));
|
||||
LOG(("Z180 #%d CKA1 %d\n", cpunum_get_active(), data & Z180_CKA1 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_CKA1) | (data & Z180_CKA1);
|
||||
}
|
||||
|
||||
/* I/O serial clock (active high) */
|
||||
if (changes & Z180_CKS)
|
||||
{
|
||||
LOG(("Z180 #%d CKS %d\n", cpu_getactivecpu(), data & Z180_CKS ? 1 : 0));
|
||||
LOG(("Z180 #%d CKS %d\n", cpunum_get_active(), data & Z180_CKS ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_CKS) | (data & Z180_CKS);
|
||||
}
|
||||
|
||||
/* I clear to send 0 (active low) */
|
||||
if (changes & Z180_CTS0)
|
||||
{
|
||||
LOG(("Z180 #%d CTS0 %d\n", cpu_getactivecpu(), data & Z180_CTS0 ? 1 : 0));
|
||||
LOG(("Z180 #%d CTS0 %d\n", cpunum_get_active(), data & Z180_CTS0 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_CTS0) | (data & Z180_CTS0);
|
||||
}
|
||||
|
||||
/* I clear to send 1 (active low) or RXS (mux) */
|
||||
if (changes & Z180_CTS1)
|
||||
{
|
||||
LOG(("Z180 #%d CTS1 %d\n", cpu_getactivecpu(), data & Z180_CTS1 ? 1 : 0));
|
||||
LOG(("Z180 #%d CTS1 %d\n", cpunum_get_active(), data & Z180_CTS1 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_CTS1) | (data & Z180_CTS1);
|
||||
}
|
||||
|
||||
/* I data carrier detect (active low) */
|
||||
if (changes & Z180_DCD0)
|
||||
{
|
||||
LOG(("Z180 #%d DCD0 %d\n", cpu_getactivecpu(), data & Z180_DCD0 ? 1 : 0));
|
||||
LOG(("Z180 #%d DCD0 %d\n", cpunum_get_active(), data & Z180_DCD0 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_DCD0) | (data & Z180_DCD0);
|
||||
}
|
||||
|
||||
/* I data request DMA ch 0 (active low) or CKA0 (mux) */
|
||||
if (changes & Z180_DREQ0)
|
||||
{
|
||||
LOG(("Z180 #%d DREQ0 %d\n", cpu_getactivecpu(), data & Z180_DREQ0 ? 1 : 0));
|
||||
LOG(("Z180 #%d DREQ0 %d\n", cpunum_get_active(), data & Z180_DREQ0 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_DREQ0) | (data & Z180_DREQ0);
|
||||
}
|
||||
|
||||
/* I data request DMA ch 1 (active low) */
|
||||
if (changes & Z180_DREQ1)
|
||||
{
|
||||
LOG(("Z180 #%d DREQ1 %d\n", cpu_getactivecpu(), data & Z180_DREQ1 ? 1 : 0));
|
||||
LOG(("Z180 #%d DREQ1 %d\n", cpunum_get_active(), data & Z180_DREQ1 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_DREQ1) | (data & Z180_DREQ1);
|
||||
}
|
||||
|
||||
/* I asynchronous receive data 0 (active high) */
|
||||
if (changes & Z180_RXA0)
|
||||
{
|
||||
LOG(("Z180 #%d RXA0 %d\n", cpu_getactivecpu(), data & Z180_RXA0 ? 1 : 0));
|
||||
LOG(("Z180 #%d RXA0 %d\n", cpunum_get_active(), data & Z180_RXA0 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_RXA0) | (data & Z180_RXA0);
|
||||
}
|
||||
|
||||
/* I asynchronous receive data 1 (active high) */
|
||||
if (changes & Z180_RXA1)
|
||||
{
|
||||
LOG(("Z180 #%d RXA1 %d\n", cpu_getactivecpu(), data & Z180_RXA1 ? 1 : 0));
|
||||
LOG(("Z180 #%d RXA1 %d\n", cpunum_get_active(), data & Z180_RXA1 ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_RXA1) | (data & Z180_RXA1);
|
||||
}
|
||||
|
||||
/* I clocked serial receive data (active high) or CTS1 (mux) */
|
||||
if (changes & Z180_RXS)
|
||||
{
|
||||
LOG(("Z180 #%d RXS %d\n", cpu_getactivecpu(), data & Z180_RXS ? 1 : 0));
|
||||
LOG(("Z180 #%d RXS %d\n", cpunum_get_active(), data & Z180_RXS ? 1 : 0));
|
||||
Z180.iol = (Z180.iol & ~Z180_RXS) | (data & Z180_RXS);
|
||||
}
|
||||
|
||||
/* O request to send (active low) */
|
||||
if (changes & Z180_RTS0)
|
||||
{
|
||||
LOG(("Z180 #%d RTS0 won't change output\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d RTS0 won't change output\n", cpunum_get_active()));
|
||||
}
|
||||
|
||||
/* O transfer end 0 (active low) or CKA1 (mux) */
|
||||
if (changes & Z180_TEND0)
|
||||
{
|
||||
LOG(("Z180 #%d TEND0 won't change output\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d TEND0 won't change output\n", cpunum_get_active()));
|
||||
}
|
||||
|
||||
/* O transfer end 1 (active low) */
|
||||
if (changes & Z180_TEND1)
|
||||
{
|
||||
LOG(("Z180 #%d TEND1 won't change output\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d TEND1 won't change output\n", cpunum_get_active()));
|
||||
}
|
||||
|
||||
/* O transfer out (PRT channel, active low) or A18 (mux) */
|
||||
if (changes & Z180_A18_TOUT)
|
||||
{
|
||||
LOG(("Z180 #%d TOUT won't change output\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d TOUT won't change output\n", cpunum_get_active()));
|
||||
}
|
||||
|
||||
/* O asynchronous transmit data 0 (active high) */
|
||||
if (changes & Z180_TXA0)
|
||||
{
|
||||
LOG(("Z180 #%d TXA0 won't change output\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d TXA0 won't change output\n", cpunum_get_active()));
|
||||
}
|
||||
|
||||
/* O asynchronous transmit data 1 (active high) */
|
||||
if (changes & Z180_TXA1)
|
||||
{
|
||||
LOG(("Z180 #%d TXA1 won't change output\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d TXA1 won't change output\n", cpunum_get_active()));
|
||||
}
|
||||
|
||||
/* O clocked serial transmit data (active high) */
|
||||
if (changes & Z180_TXS)
|
||||
{
|
||||
LOG(("Z180 #%d TXS won't change output\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d TXS won't change output\n", cpunum_get_active()));
|
||||
}
|
||||
}
|
||||
|
||||
@ -1902,7 +1902,7 @@ static CPU_INIT( z180 )
|
||||
{
|
||||
Z180.daisy = NULL;
|
||||
if (device->static_config)
|
||||
Z180.daisy = z80daisy_init(Machine, Machine->config->cpu[cpu_getactivecpu()].tag, device->static_config);
|
||||
Z180.daisy = z80daisy_init(Machine, Machine->config->cpu[cpunum_get_active()].tag, device->static_config);
|
||||
Z180.irq_callback = irqcallback;
|
||||
Z180.device = device;
|
||||
|
||||
@ -2197,7 +2197,7 @@ static CPU_EXECUTE( z180 )
|
||||
/* to just check here */
|
||||
if (Z180.nmi_pending)
|
||||
{
|
||||
LOG(("Z180 #%d take NMI\n", cpu_getactivecpu()));
|
||||
LOG(("Z180 #%d take NMI\n", cpunum_get_active()));
|
||||
_PPC = -1; /* there isn't a valid previous program counter */
|
||||
LEAVE_HALT; /* Check if processor was halted */
|
||||
|
||||
@ -2335,7 +2335,7 @@ static void set_irq_line(int irqline, int state)
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG(("Z180 #%d set_irq_line %d = %d\n",cpu_getactivecpu() , irqline,state));
|
||||
LOG(("Z180 #%d set_irq_line %d = %d\n",cpunum_get_active() , irqline,state));
|
||||
|
||||
/* update the IRQ state */
|
||||
Z180.irq_state[irqline] = state;
|
||||
|
@ -1,6 +1,6 @@
|
||||
OP(illegal,1) {
|
||||
logerror("Z180 #%d ill. opcode $%02x $%02x\n",
|
||||
cpu_getactivecpu(), cpu_readop((_PCD-1)&0xffff), cpu_readop(_PCD));
|
||||
cpunum_get_active(), cpu_readop((_PCD-1)&0xffff), cpu_readop(_PCD));
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
|
@ -1,7 +1,7 @@
|
||||
OP(illegal,2)
|
||||
{
|
||||
logerror("Z180 #%d ill. opcode $ed $%02x\n",
|
||||
cpu_getactivecpu(), cpu_readop((_PCD-1)&0xffff));
|
||||
cpunum_get_active(), cpu_readop((_PCD-1)&0xffff));
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
|
@ -315,7 +315,7 @@ static void take_interrupt(int irq)
|
||||
else
|
||||
irq_vector = (*Z180.irq_callback)(Z180.device, 0);
|
||||
|
||||
LOG(("Z180 #%d single int. irq_vector $%02x\n", cpu_getactivecpu(), irq_vector));
|
||||
LOG(("Z180 #%d single int. irq_vector $%02x\n", cpunum_get_active(), irq_vector));
|
||||
|
||||
/* Interrupt mode 2. Call [Z180.I:databyte] */
|
||||
if( _IM == 2 )
|
||||
@ -323,7 +323,7 @@ static void take_interrupt(int irq)
|
||||
irq_vector = (irq_vector & 0xff) + (_I << 8);
|
||||
PUSH( PC );
|
||||
RM16( irq_vector, &Z180.PC );
|
||||
LOG(("Z180 #%d IM2 [$%04x] = $%04x\n",cpu_getactivecpu() , irq_vector, _PCD));
|
||||
LOG(("Z180 #%d IM2 [$%04x] = $%04x\n",cpunum_get_active() , irq_vector, _PCD));
|
||||
/* CALL opcode timing */
|
||||
z180_icount -= cc[Z180_TABLE_op][0xcd];
|
||||
}
|
||||
@ -331,7 +331,7 @@ static void take_interrupt(int irq)
|
||||
/* Interrupt mode 1. RST 38h */
|
||||
if( _IM == 1 )
|
||||
{
|
||||
LOG(("Z180 #%d IM1 $0038\n",cpu_getactivecpu() ));
|
||||
LOG(("Z180 #%d IM1 $0038\n",cpunum_get_active() ));
|
||||
PUSH( PC );
|
||||
_PCD = 0x0038;
|
||||
/* RST $38 + 'interrupt latency' cycles */
|
||||
@ -342,7 +342,7 @@ static void take_interrupt(int irq)
|
||||
/* Interrupt mode 0. We check for CALL and JP instructions, */
|
||||
/* if neither of these were found we assume a 1 byte opcode */
|
||||
/* was placed on the databus */
|
||||
LOG(("Z180 #%d IM0 $%04x\n",cpu_getactivecpu() , irq_vector));
|
||||
LOG(("Z180 #%d IM0 $%04x\n",cpunum_get_active() , irq_vector));
|
||||
switch (irq_vector & 0xff0000)
|
||||
{
|
||||
case 0xcd0000: /* call */
|
||||
@ -371,7 +371,7 @@ static void take_interrupt(int irq)
|
||||
irq_vector = (_I << 8) + (irq_vector & 0xff);
|
||||
PUSH( PC );
|
||||
RM16( irq_vector, &Z180.PC );
|
||||
LOG(("Z180 #%d INT%d [$%04x] = $%04x\n", cpu_getactivecpu(), irq, irq_vector, _PCD));
|
||||
LOG(("Z180 #%d INT%d [$%04x] = $%04x\n", cpunum_get_active(), irq, irq_vector, _PCD));
|
||||
/* CALL opcode timing */
|
||||
z180_icount -= cc[Z180_TABLE_op][0xcd];
|
||||
}
|
||||
|
@ -276,7 +276,7 @@ void z180_setOPbase(int pc)
|
||||
* RETN
|
||||
***************************************************************/
|
||||
#define RETN { \
|
||||
LOG(("Z180 #%d RETN IFF1:%d IFF2:%d\n", cpu_getactivecpu(), _IFF1, _IFF2)); \
|
||||
LOG(("Z180 #%d RETN IFF1:%d IFF2:%d\n", cpunum_get_active(), _IFF1, _IFF2)); \
|
||||
POP(PC); \
|
||||
z180_change_pc(_PCD); \
|
||||
_IFF1 = _IFF2; \
|
||||
|
@ -824,7 +824,7 @@ INLINE UINT32 ARG16(z80_state *z80)
|
||||
* RETN
|
||||
***************************************************************/
|
||||
#define RETN { \
|
||||
LOG(("Z80 #%d RETN IFF1:%d IFF2:%d\n", cpu_getactivecpu(), IFF1, IFF2)); \
|
||||
LOG(("Z80 #%d RETN IFF1:%d IFF2:%d\n", cpunum_get_active(), IFF1, IFF2)); \
|
||||
POP( pc ); \
|
||||
MEMPTR = PC; \
|
||||
change_pc(PCD); \
|
||||
@ -2173,7 +2173,7 @@ OP(xycb,ff) { A = SET(7, RM(EA) ); WM( EA,A ); } /* SET 7,A=(XY+o) */
|
||||
|
||||
OP(illegal,1) {
|
||||
logerror("Z80 #%d ill. opcode $%02x $%02x\n",
|
||||
cpu_getactivecpu(), cpu_readop((PCD-1)&0xffff), cpu_readop(PCD));
|
||||
cpunum_get_active(), cpu_readop((PCD-1)&0xffff), cpu_readop(PCD));
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
@ -2761,7 +2761,7 @@ OP(fd,ff) { illegal_1(z80); op_ff(z80); } /* DB FD */
|
||||
OP(illegal,2)
|
||||
{
|
||||
logerror("Z80 #%d ill. opcode $ed $%02x\n",
|
||||
cpu_getactivecpu(), cpu_readop((PCD-1)&0xffff));
|
||||
cpunum_get_active(), cpu_readop((PCD-1)&0xffff));
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
@ -3369,7 +3369,7 @@ static void take_interrupt(z80_state *z80)
|
||||
else
|
||||
irq_vector = (*z80->irq_callback)(z80->device, 0);
|
||||
|
||||
LOG(("Z80 #%d single int. irq_vector $%02x\n", cpu_getactivecpu(), irq_vector));
|
||||
LOG(("Z80 #%d single int. irq_vector $%02x\n", cpunum_get_active(), irq_vector));
|
||||
|
||||
/* Interrupt mode 2. Call [z80->i:databyte] */
|
||||
if( IM == 2 )
|
||||
@ -3377,7 +3377,7 @@ static void take_interrupt(z80_state *z80)
|
||||
irq_vector = (irq_vector & 0xff) | (I << 8);
|
||||
PUSH( pc );
|
||||
RM16( irq_vector, &z80->pc );
|
||||
LOG(("Z80 #%d IM2 [$%04x] = $%04x\n",cpu_getactivecpu() , irq_vector, PCD));
|
||||
LOG(("Z80 #%d IM2 [$%04x] = $%04x\n",cpunum_get_active() , irq_vector, PCD));
|
||||
/* CALL opcode timing */
|
||||
z80->icount -= cc[Z80_TABLE_op][0xcd];
|
||||
}
|
||||
@ -3385,7 +3385,7 @@ static void take_interrupt(z80_state *z80)
|
||||
/* Interrupt mode 1. RST 38h */
|
||||
if( IM == 1 )
|
||||
{
|
||||
LOG(("Z80 #%d IM1 $0038\n",cpu_getactivecpu() ));
|
||||
LOG(("Z80 #%d IM1 $0038\n",cpunum_get_active() ));
|
||||
PUSH( pc );
|
||||
PCD = 0x0038;
|
||||
/* RST $38 + 'interrupt latency' cycles */
|
||||
@ -3396,7 +3396,7 @@ static void take_interrupt(z80_state *z80)
|
||||
/* Interrupt mode 0. We check for CALL and JP instructions, */
|
||||
/* if neither of these were found we assume a 1 byte opcode */
|
||||
/* was placed on the databus */
|
||||
LOG(("Z80 #%d IM0 $%04x\n",cpu_getactivecpu() , irq_vector));
|
||||
LOG(("Z80 #%d IM0 $%04x\n",cpunum_get_active() , irq_vector));
|
||||
switch (irq_vector & 0xff0000)
|
||||
{
|
||||
case 0xcd0000: /* call */
|
||||
@ -3552,7 +3552,7 @@ static CPU_INIT( z80 )
|
||||
/* Reset registers to their initial values */
|
||||
memset(z80, 0, sizeof(*z80));
|
||||
if (device->static_config != NULL)
|
||||
z80->daisy = z80daisy_init(Machine, Machine->config->cpu[cpu_getactivecpu()].tag, device->static_config);
|
||||
z80->daisy = z80daisy_init(Machine, Machine->config->cpu[cpunum_get_active()].tag, device->static_config);
|
||||
z80->irq_callback = irqcallback;
|
||||
z80->device = device;
|
||||
IX = IY = 0xffff; /* IX and IY are FFFF after a reset! */
|
||||
@ -3606,7 +3606,7 @@ static CPU_EXECUTE( z80 )
|
||||
/* to just check here */
|
||||
if (z80->nmi_pending)
|
||||
{
|
||||
LOG(("Z80 #%d take NMI\n", cpu_getactivecpu()));
|
||||
LOG(("Z80 #%d take NMI\n", cpunum_get_active()));
|
||||
PRVPC = -1; /* there isn't a valid previous program counter */
|
||||
LEAVE_HALT; /* Check if processor was halted */
|
||||
|
||||
|
@ -350,7 +350,7 @@ INLINE void set_irq(int type)
|
||||
IRQ_REQ = type;
|
||||
break;
|
||||
case Z8000_SYSCALL >> 8:
|
||||
LOG(("Z8K#%d SYSCALL $%02x\n", cpu_getactivecpu(), type & 0xff));
|
||||
LOG(("Z8K#%d SYSCALL $%02x\n", cpunum_get_active(), type & 0xff));
|
||||
IRQ_REQ = type;
|
||||
break;
|
||||
default:
|
||||
@ -388,7 +388,7 @@ INLINE void Interrupt(void)
|
||||
IRQ_SRV = IRQ_REQ;
|
||||
IRQ_REQ &= ~Z8000_TRAP;
|
||||
PC = TRAP;
|
||||
LOG(("Z8K#%d trap $%04x\n", cpu_getactivecpu(), PC ));
|
||||
LOG(("Z8K#%d trap $%04x\n", cpunum_get_active(), PC ));
|
||||
}
|
||||
else
|
||||
if ( IRQ_REQ & Z8000_SYSCALL )
|
||||
@ -400,7 +400,7 @@ INLINE void Interrupt(void)
|
||||
IRQ_SRV = IRQ_REQ;
|
||||
IRQ_REQ &= ~Z8000_SYSCALL;
|
||||
PC = SYSCALL;
|
||||
LOG(("Z8K#%d syscall $%04x\n", cpu_getactivecpu(), PC ));
|
||||
LOG(("Z8K#%d syscall $%04x\n", cpunum_get_active(), PC ));
|
||||
}
|
||||
else
|
||||
if ( IRQ_REQ & Z8000_SEGTRAP )
|
||||
@ -412,7 +412,7 @@ INLINE void Interrupt(void)
|
||||
IRQ_SRV = IRQ_REQ;
|
||||
IRQ_REQ &= ~Z8000_SEGTRAP;
|
||||
PC = SEGTRAP;
|
||||
LOG(("Z8K#%d segtrap $%04x\n", cpu_getactivecpu(), PC ));
|
||||
LOG(("Z8K#%d segtrap $%04x\n", cpunum_get_active(), PC ));
|
||||
}
|
||||
else
|
||||
if ( IRQ_REQ & Z8000_NMI )
|
||||
@ -427,7 +427,7 @@ INLINE void Interrupt(void)
|
||||
IRQ_REQ &= ~Z8000_NMI;
|
||||
CHANGE_FCW(fcw);
|
||||
PC = NMI;
|
||||
LOG(("Z8K#%d NMI $%04x\n", cpu_getactivecpu(), PC ));
|
||||
LOG(("Z8K#%d NMI $%04x\n", cpunum_get_active(), PC ));
|
||||
}
|
||||
else
|
||||
if ( (IRQ_REQ & Z8000_NVI) && (FCW & F_NVIE) )
|
||||
@ -441,7 +441,7 @@ INLINE void Interrupt(void)
|
||||
PC = RDMEM_W( NVI + 2 );
|
||||
IRQ_REQ &= ~Z8000_NVI;
|
||||
CHANGE_FCW(fcw);
|
||||
LOG(("Z8K#%d NVI $%04x\n", cpu_getactivecpu(), PC ));
|
||||
LOG(("Z8K#%d NVI $%04x\n", cpunum_get_active(), PC ));
|
||||
}
|
||||
else
|
||||
if ( (IRQ_REQ & Z8000_VI) && (FCW & F_VIE) )
|
||||
@ -455,7 +455,7 @@ INLINE void Interrupt(void)
|
||||
PC = RDMEM_W( VEC00 + 2 * (IRQ_REQ & 0xff) );
|
||||
IRQ_REQ &= ~Z8000_VI;
|
||||
CHANGE_FCW(fcw);
|
||||
LOG(("Z8K#%d VI [$%04x/$%04x] fcw $%04x, pc $%04x\n", cpu_getactivecpu(), IRQ_VEC, VEC00 + VEC00 + 2 * (IRQ_REQ & 0xff), FCW, PC ));
|
||||
LOG(("Z8K#%d VI [$%04x/$%04x] fcw $%04x, pc $%04x\n", cpunum_get_active(), IRQ_VEC, VEC00 + VEC00 + 2 * (IRQ_REQ & 0xff), FCW, PC ));
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1530,7 +1530,7 @@ static void Z0D_ddN0_1001_imm16(void)
|
||||
static void Z0E_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: ext0e $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: ext0e $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -1544,7 +1544,7 @@ static void Z0E_imm8(void)
|
||||
static void Z0F_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: ext0f $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: ext0f $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -2274,7 +2274,7 @@ static void Z36_0000_0000(void)
|
||||
static void Z36_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvd36 $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvd36 $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -2312,7 +2312,7 @@ static void Z37_ddN0_ssss_imm16(void)
|
||||
static void Z38_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvd38 $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvd38 $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -4354,7 +4354,7 @@ static void Z77_ddN0_ssss_0000_xxxx_0000_0000(void)
|
||||
static void Z78_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvd78 $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvd78 $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -4414,7 +4414,7 @@ static void Z7B_0000_0000(void)
|
||||
IRQ_SRV &= ~tag; /* remove IRQ serviced flag */
|
||||
CHANGE_FCW(fcw); /* check for user/system mode change */
|
||||
change_pc(PC);
|
||||
LOG(("Z8K#%d IRET tag $%04x, fcw $%04x, pc $%04x\n", cpu_getactivecpu(), tag, fcw, PC));
|
||||
LOG(("Z8K#%d IRET tag $%04x, fcw $%04x, pc $%04x\n", cpunum_get_active(), tag, fcw, PC));
|
||||
}
|
||||
|
||||
/******************************************
|
||||
@ -4499,7 +4499,7 @@ static void Z7D_dddd_0ccc(void)
|
||||
RW(dst) = NSP;
|
||||
break;
|
||||
default:
|
||||
LOG(("Z8K#%d LDCTL R%d,%d\n", cpu_getactivecpu(), dst, imm3));
|
||||
LOG(("Z8K#%d LDCTL R%d,%d\n", cpunum_get_active(), dst, imm3));
|
||||
}
|
||||
}
|
||||
|
||||
@ -4529,7 +4529,7 @@ static void Z7D_ssss_1ccc(void)
|
||||
NSP = RW(src);
|
||||
break;
|
||||
default:
|
||||
LOG(("Z8K#%d LDCTL %d,R%d\n", cpu_getactivecpu(), imm3, src));
|
||||
LOG(("Z8K#%d LDCTL %d,R%d\n", cpunum_get_active(), imm3, src));
|
||||
}
|
||||
}
|
||||
|
||||
@ -4540,7 +4540,7 @@ static void Z7D_ssss_1ccc(void)
|
||||
static void Z7E_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvd7e $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvd7e $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -4836,7 +4836,7 @@ static void Z8D_imm4_0101(void)
|
||||
static void Z8E_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: ext8e $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: ext8e $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -4850,7 +4850,7 @@ static void Z8E_imm8(void)
|
||||
static void Z8F_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: ext8f $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: ext8f $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -5008,7 +5008,7 @@ static void Z9C_dddd_1000(void)
|
||||
static void Z9D_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvd9d $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvd9d $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -5050,7 +5050,7 @@ static void Z9E_0000_cccc(void)
|
||||
static void Z9F_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvd9f $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvd9f $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -5751,7 +5751,7 @@ static void ZB8_ddN0_1100_0000_rrrr_ssN0_0000(void)
|
||||
static void ZB9_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvdb9 $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvdb9 $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
@ -6409,7 +6409,7 @@ static void ZBE_aaaa_bbbb(void)
|
||||
static void ZBF_imm8(void)
|
||||
{
|
||||
GET_IMM8(0);
|
||||
LOG(("Z8K#%d %04x: rsvdbf $%02x\n", cpu_getactivecpu(), PC, imm8));
|
||||
LOG(("Z8K#%d %04x: rsvdbf $%02x\n", cpunum_get_active(), PC, imm8));
|
||||
if (FCW & F_EPU) {
|
||||
/* Z8001 EPU code goes here */
|
||||
(void)imm8;
|
||||
|
@ -34,11 +34,11 @@ extern const cpu_irq_callback cpu_irq_callbacks[];
|
||||
***************************************************************************/
|
||||
|
||||
#define VERIFY_ACTIVECPU(name) \
|
||||
int activecpu = cpu_getactivecpu(); \
|
||||
int activecpu = cpunum_get_active(); \
|
||||
assert_always(activecpu >= 0, #name "() called with no active cpu!")
|
||||
|
||||
#define VERIFY_EXECUTINGCPU(name) \
|
||||
int activecpu = cpu_getexecutingcpu(); \
|
||||
int activecpu = cpunum_get_executing(); \
|
||||
assert_always(activecpu >= 0, #name "() called with no executing cpu!")
|
||||
|
||||
#define VERIFY_CPUNUM(name) \
|
||||
@ -210,7 +210,7 @@ static void cpuexec_reset(running_machine *machine)
|
||||
cpu[cpunum].totalcycles = 0;
|
||||
|
||||
/* then reset the CPU directly */
|
||||
cpunum_reset(cpunum);
|
||||
cpu_reset(machine->cpu[cpunum]);
|
||||
}
|
||||
}
|
||||
|
||||
@ -272,11 +272,11 @@ void cpuexec_timeslice(running_machine *machine)
|
||||
/* via the call to the cpunum_execute */
|
||||
cycles_stolen = 0;
|
||||
if (!call_debugger)
|
||||
ran = cpunum_execute(cpunum, cycles_running);
|
||||
ran = cpu_execute(machine->cpu[cpunum], cycles_running);
|
||||
else
|
||||
{
|
||||
debugger_start_cpu_hook(machine, cpunum, target);
|
||||
ran = cpunum_execute(cpunum, cycles_running);
|
||||
ran = cpu_execute(machine->cpu[cpunum], cycles_running);
|
||||
debugger_stop_cpu_hook(machine, cpunum);
|
||||
}
|
||||
|
||||
@ -362,7 +362,7 @@ void activecpu_abort_timeslice(void)
|
||||
int current_icount;
|
||||
|
||||
VERIFY_EXECUTINGCPU(activecpu_abort_timeslice);
|
||||
LOG(("activecpu_abort_timeslice (CPU=%d, cycles_left=%d)\n", cpu_getexecutingcpu(), activecpu_get_icount() + 1));
|
||||
LOG(("activecpu_abort_timeslice (CPU=%d, cycles_left=%d)\n", cpunum_get_executing(), activecpu_get_icount() + 1));
|
||||
|
||||
/* swallow the remaining cycles */
|
||||
current_icount = activecpu_get_icount() + 1;
|
||||
@ -383,7 +383,7 @@ void cpunum_suspend(int cpunum, int reason, int eatcycles)
|
||||
LOG(("cpunum_suspend (CPU=%d, r=%X, eat=%d)\n", cpunum, reason, eatcycles));
|
||||
cpu[cpunum].nextsuspend |= reason;
|
||||
cpu[cpunum].nexteatcycles = eatcycles;
|
||||
if (cpu_getexecutingcpu() >= 0)
|
||||
if (cpunum_get_executing() >= 0)
|
||||
activecpu_abort_timeslice();
|
||||
}
|
||||
|
||||
@ -398,7 +398,7 @@ void cpunum_resume(int cpunum, int reason)
|
||||
VERIFY_CPUNUM(cpunum_resume);
|
||||
LOG(("cpunum_resume (CPU=%d, r=%X)\n", cpunum, reason));
|
||||
cpu[cpunum].nextsuspend &= ~reason;
|
||||
if (cpu_getexecutingcpu() >= 0)
|
||||
if (cpunum_get_executing() >= 0)
|
||||
activecpu_abort_timeslice();
|
||||
}
|
||||
|
||||
@ -519,7 +519,7 @@ attotime cpunum_get_localtime(int cpunum)
|
||||
|
||||
/* if we're active, add in the time from the current slice */
|
||||
result = cpu[cpunum].localtime;
|
||||
if (cpunum == cpu_getexecutingcpu())
|
||||
if (cpunum == cpunum_get_executing())
|
||||
{
|
||||
int cycles = cycles_running - activecpu_get_icount();
|
||||
result = attotime_add(result, ATTOTIME_IN_CYCLES(cycles, cpunum));
|
||||
@ -537,7 +537,7 @@ attotime cpunum_get_localtime(int cpunum)
|
||||
UINT64 activecpu_gettotalcycles(void)
|
||||
{
|
||||
VERIFY_ACTIVECPU(activecpu_gettotalcycles);
|
||||
if (activecpu == cpu_getexecutingcpu())
|
||||
if (activecpu == cpunum_get_executing())
|
||||
return cpu[activecpu].totalcycles + cycles_running - activecpu_get_icount();
|
||||
else
|
||||
return cpu[activecpu].totalcycles;
|
||||
@ -553,7 +553,7 @@ UINT64 activecpu_gettotalcycles(void)
|
||||
UINT64 cpunum_gettotalcycles(int cpunum)
|
||||
{
|
||||
VERIFY_CPUNUM(cpunum_gettotalcycles);
|
||||
if (cpunum == cpu_getexecutingcpu())
|
||||
if (cpunum == cpunum_get_executing())
|
||||
return cpu[cpunum].totalcycles + cycles_running - activecpu_get_icount();
|
||||
else
|
||||
return cpu[cpunum].totalcycles;
|
||||
@ -600,7 +600,7 @@ static void cpunum_suspend_until_trigger(int cpunum, int trigger, int eatcycles)
|
||||
|
||||
void cpu_yield(void)
|
||||
{
|
||||
int cpunum = cpu_getexecutingcpu();
|
||||
int cpunum = cpunum_get_executing();
|
||||
VERIFY_EXECUTINGCPU(cpu_yield);
|
||||
cpunum_suspend(cpunum, SUSPEND_REASON_TIMESLICE, FALSE);
|
||||
}
|
||||
@ -613,7 +613,7 @@ void cpu_yield(void)
|
||||
|
||||
void cpu_spin(void)
|
||||
{
|
||||
int cpunum = cpu_getexecutingcpu();
|
||||
int cpunum = cpunum_get_executing();
|
||||
VERIFY_EXECUTINGCPU(cpu_spin);
|
||||
cpunum_suspend(cpunum, SUSPEND_REASON_TIMESLICE, TRUE);
|
||||
}
|
||||
@ -626,7 +626,7 @@ void cpu_spin(void)
|
||||
|
||||
void cpu_spinuntil_trigger(int trigger)
|
||||
{
|
||||
int cpunum = cpu_getexecutingcpu();
|
||||
int cpunum = cpunum_get_executing();
|
||||
VERIFY_EXECUTINGCPU(cpu_yielduntil_trigger);
|
||||
cpunum_suspend_until_trigger(cpunum, trigger, TRUE);
|
||||
}
|
||||
@ -651,7 +651,7 @@ void cpunum_spinuntil_trigger(int cpunum, int trigger)
|
||||
|
||||
void cpu_spinuntil_int(void)
|
||||
{
|
||||
int cpunum = cpu_getexecutingcpu();
|
||||
int cpunum = cpunum_get_executing();
|
||||
VERIFY_EXECUTINGCPU(cpu_spinuntil_int);
|
||||
cpunum_suspend_until_trigger(cpunum, TRIGGER_INT + cpunum, TRUE);
|
||||
}
|
||||
@ -665,7 +665,7 @@ void cpu_spinuntil_int(void)
|
||||
void cpu_spinuntil_time(attotime duration)
|
||||
{
|
||||
static int timetrig = 0;
|
||||
int cpunum = cpu_getexecutingcpu();
|
||||
int cpunum = cpunum_get_executing();
|
||||
VERIFY_EXECUTINGCPU(cpu_spinuntil_time);
|
||||
cpunum_suspend_until_trigger(cpunum, TRIGGER_SUSPENDTIME + timetrig, TRUE);
|
||||
cpu_triggertime(duration, TRIGGER_SUSPENDTIME + timetrig);
|
||||
@ -687,7 +687,7 @@ void cpu_trigger(running_machine *machine, int trigger)
|
||||
int cpunum;
|
||||
|
||||
/* cause an immediate resynchronization */
|
||||
if (cpu_getexecutingcpu() >= 0)
|
||||
if (cpunum_get_executing() >= 0)
|
||||
activecpu_abort_timeslice();
|
||||
|
||||
/* look for suspended CPUs waiting for this trigger and unsuspend them */
|
||||
@ -797,9 +797,9 @@ static void on_vblank(const device_config *device, void *param, int vblank_state
|
||||
{
|
||||
if (!cpunum_is_suspended(cpunum, SUSPEND_REASON_HALT | SUSPEND_REASON_RESET | SUSPEND_REASON_DISABLE))
|
||||
{
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(device->machine->cpu[cpunum]);
|
||||
(*config->vblank_interrupt)(device->machine, cpunum);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
/* if we have more than one interrupt per frame, start the timer now to trigger the rest of them */
|
||||
@ -833,9 +833,9 @@ static TIMER_CALLBACK( trigger_partial_frame_interrupt )
|
||||
/* call the interrupt handler */
|
||||
if (!cpunum_is_suspended(cpunum, SUSPEND_REASON_HALT | SUSPEND_REASON_RESET | SUSPEND_REASON_DISABLE))
|
||||
{
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
(*config->vblank_interrupt)(machine, cpunum);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
/* more? */
|
||||
@ -854,9 +854,9 @@ static TIMER_CALLBACK( cpu_timedintcallback )
|
||||
/* bail if there is no routine */
|
||||
if (machine->config->cpu[param].timed_interrupt != NULL && !cpunum_is_suspended(param, SUSPEND_REASON_HALT | SUSPEND_REASON_RESET | SUSPEND_REASON_DISABLE))
|
||||
{
|
||||
cpuintrf_push_context(param);
|
||||
cpu_push_context(machine->cpu[param]);
|
||||
(*machine->config->cpu[param].timed_interrupt)(machine, param);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -126,7 +126,7 @@ void cpuint_init(running_machine *machine)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
void cpuint_reset(void)
|
||||
void cpuint_reset(running_machine *machine)
|
||||
{
|
||||
int cpunum, line;
|
||||
|
||||
@ -134,7 +134,7 @@ void cpuint_reset(void)
|
||||
for (cpunum = 0; cpunum < cpu_gettotalcpu(); cpunum++)
|
||||
for (line = 0; line < MAX_INPUT_LINES; line++)
|
||||
{
|
||||
interrupt_vector[cpunum][line] = cpunum_default_irq_vector(cpunum);
|
||||
interrupt_vector[cpunum][line] = cpu_get_default_irq_vector(machine->cpu[cpunum]);
|
||||
input_event_index[cpunum][line] = 0;
|
||||
}
|
||||
}
|
||||
@ -161,7 +161,7 @@ static TIMER_CALLBACK( cpunum_empty_event_queue )
|
||||
int i;
|
||||
|
||||
/* swap to the CPU's context */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
|
||||
/* loop over all events */
|
||||
for (i = 0; i < input_event_index[cpunum][line]; i++)
|
||||
@ -187,7 +187,7 @@ static TIMER_CALLBACK( cpunum_empty_event_queue )
|
||||
/* if we're clearing the line that was previously asserted, or if we're just */
|
||||
/* pulsing the line, reset the CPU */
|
||||
if ((state == CLEAR_LINE && cpunum_is_suspended(cpunum, SUSPEND_REASON_RESET)) || state == PULSE_LINE)
|
||||
cpunum_reset(cpunum);
|
||||
cpu_reset(machine->cpu[cpunum]);
|
||||
|
||||
/* if we're clearing the line, make sure the CPU is not halted */
|
||||
cpunum_resume(cpunum, SUSPEND_REASON_RESET);
|
||||
@ -215,17 +215,17 @@ static TIMER_CALLBACK( cpunum_empty_event_queue )
|
||||
case PULSE_LINE:
|
||||
/* temporary: PULSE_LINE only makes sense for NMI lines on Z80 */
|
||||
assert(machine->config->cpu[cpunum].type != CPU_Z80 || line == INPUT_LINE_NMI);
|
||||
activecpu_set_input_line(line, INTERNAL_ASSERT_LINE);
|
||||
activecpu_set_input_line(line, INTERNAL_CLEAR_LINE);
|
||||
cpu_set_info_int(machine->activecpu, CPUINFO_INT_INPUT_STATE + line, ASSERT_LINE);
|
||||
cpu_set_info_int(machine->activecpu, CPUINFO_INT_INPUT_STATE + line, CLEAR_LINE);
|
||||
break;
|
||||
|
||||
case HOLD_LINE:
|
||||
case ASSERT_LINE:
|
||||
activecpu_set_input_line(line, INTERNAL_ASSERT_LINE);
|
||||
cpu_set_info_int(machine->activecpu, CPUINFO_INT_INPUT_STATE + line, ASSERT_LINE);
|
||||
break;
|
||||
|
||||
case CLEAR_LINE:
|
||||
activecpu_set_input_line(line, INTERNAL_CLEAR_LINE);
|
||||
cpu_set_info_int(machine->activecpu, CPUINFO_INT_INPUT_STATE + line, CLEAR_LINE);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -239,7 +239,7 @@ static TIMER_CALLBACK( cpunum_empty_event_queue )
|
||||
}
|
||||
|
||||
/* swap back */
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
/* reset counter */
|
||||
input_event_index[cpunum][line] = 0;
|
||||
@ -409,7 +409,7 @@ INLINE int generic_irq_callback(running_machine *machine, int cpunum, int line)
|
||||
if (input_line_state[cpunum][line] == HOLD_LINE)
|
||||
{
|
||||
LOG(("->set_irq_line(%d,%d,%d)\n", cpunum, line, CLEAR_LINE));
|
||||
activecpu_set_input_line(line, INTERNAL_CLEAR_LINE);
|
||||
cpu_set_info_int(machine->activecpu, CPUINFO_INT_INPUT_STATE + line, CLEAR_LINE);
|
||||
input_line_state[cpunum][line] = CLEAR_LINE;
|
||||
}
|
||||
|
||||
|
@ -29,7 +29,7 @@
|
||||
|
||||
void cpuint_init(running_machine *machine);
|
||||
|
||||
void cpuint_reset(void);
|
||||
void cpuint_reset(running_machine *machine);
|
||||
|
||||
|
||||
|
||||
|
@ -263,11 +263,11 @@ CPU_GET_INFO( cxd8661r );
|
||||
*
|
||||
*************************************/
|
||||
|
||||
#define VERIFY_ACTIVECPU(name) \
|
||||
assert_always(activecpu >= 0, #name "() called with no active cpu!")
|
||||
#define VERIFY_CPU(name) \
|
||||
assert_always(cpu != NULL, #name "() called with invalid cpu!")
|
||||
|
||||
#define VERIFY_CPUNUM(name) \
|
||||
assert_always(cpunum >= 0 && cpunum < totalcpu, #name "() called for invalid cpu num!")
|
||||
#define VERIFY_ACTIVECPU(name) \
|
||||
assert_always(activecpunum >= 0, #name "() called with no active cpu!")
|
||||
|
||||
#define VERIFY_CPUTYPE(name) \
|
||||
assert_always(cputype >= 0 && cputype < CPU_COUNT, #name "() called for invalid cpu type!")
|
||||
@ -283,11 +283,13 @@ CPU_GET_INFO( cxd8661r );
|
||||
typedef struct _cpuintrf_data cpuintrf_data;
|
||||
struct _cpuintrf_data
|
||||
{
|
||||
int index; /* index of this CPU */
|
||||
int family; /* family index of this CPU */
|
||||
cpu_interface intf; /* copy of the interface data */
|
||||
cpu_type cputype; /* type index of this CPU */
|
||||
int family; /* family index of this CPU */
|
||||
device_config *device; /* dummy device for now */
|
||||
int *icount;
|
||||
cpu_disassemble_func dasm_override;
|
||||
};
|
||||
|
||||
|
||||
@ -941,18 +943,16 @@ static const struct
|
||||
*
|
||||
*************************************/
|
||||
|
||||
int activecpu; /* index of active CPU (or -1) */
|
||||
int executingcpu; /* index of executing CPU (or -1) */
|
||||
const device_config *executingcpu;
|
||||
int activecpunum; /* index of active CPU (or -1) */
|
||||
int executingcpunum; /* index of executing CPU (or -1) */
|
||||
int totalcpu; /* total number of CPUs */
|
||||
|
||||
static cpuintrf_data cpu[MAX_CPU];
|
||||
|
||||
static int cpu_active_context[CPU_COUNT];
|
||||
static int cpu_context_stack[4];
|
||||
static const device_config *cpu_context_stack[4];
|
||||
static int cpu_context_stack_ptr;
|
||||
|
||||
static offs_t (*cpu_dasm_override[CPU_COUNT])(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
|
||||
#define TEMP_STRING_POOL_ENTRIES 16
|
||||
static char temp_string_pool[TEMP_STRING_POOL_ENTRIES][256];
|
||||
static int temp_string_pool_index;
|
||||
@ -965,25 +965,28 @@ static int temp_string_pool_index;
|
||||
*
|
||||
*************************************/
|
||||
|
||||
INLINE void set_cpu_context(running_machine *machine, int cpunum)
|
||||
INLINE void set_cpu_context(const device_config *oldcpu, const device_config *newcpu)
|
||||
{
|
||||
int newfamily = cpu[cpunum].family;
|
||||
int oldcontext = cpu_active_context[newfamily];
|
||||
cpuintrf_data *cpudata = NULL;
|
||||
|
||||
/* if nothing is changing, quick exit */
|
||||
if (newcpu == NULL || oldcpu == newcpu)
|
||||
return;
|
||||
|
||||
/* if we need to change contexts, save the one that was there */
|
||||
if (oldcontext != cpunum && oldcontext != -1)
|
||||
(*cpu[oldcontext].intf.get_context)(cpu[oldcontext].device->token);
|
||||
/* save the old context if we have one */
|
||||
if (oldcpu != NULL)
|
||||
{
|
||||
cpudata = oldcpu->classtoken;
|
||||
(*cpudata->intf.get_context)(oldcpu->token);
|
||||
}
|
||||
|
||||
/* swap memory spaces */
|
||||
activecpu = cpunum;
|
||||
memory_set_context(machine, cpunum);
|
||||
newcpu->machine->activecpu = newcpu;
|
||||
|
||||
/* if the new CPU's context is not swapped in, do it now */
|
||||
if (oldcontext != cpunum)
|
||||
{
|
||||
(*cpu[cpunum].intf.set_context)(cpu[cpunum].device->token);
|
||||
cpu_active_context[newfamily] = cpunum;
|
||||
}
|
||||
cpudata = newcpu->classtoken;
|
||||
activecpunum = cpudata->index;
|
||||
memory_set_context(newcpu->machine, activecpunum);
|
||||
(*cpudata->intf.set_context)(newcpu->token);
|
||||
}
|
||||
|
||||
|
||||
@ -994,31 +997,27 @@ INLINE void set_cpu_context(running_machine *machine, int cpunum)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
void cpuintrf_push_context(int cpunum)
|
||||
void cpu_push_context(const device_config *cpu)
|
||||
{
|
||||
/* push the old context onto the stack */
|
||||
cpu_context_stack[cpu_context_stack_ptr++] = activecpu;
|
||||
|
||||
/* do the rest only if this isn't the activecpu */
|
||||
if (cpunum != activecpu && cpunum != -1)
|
||||
set_cpu_context(Machine, cpunum);
|
||||
|
||||
/* this is now the active CPU */
|
||||
activecpu = cpunum;
|
||||
const device_config *oldcpu = cpu->machine->activecpu;
|
||||
cpu_context_stack[cpu_context_stack_ptr++] = oldcpu;
|
||||
set_cpu_context(oldcpu, cpu);
|
||||
}
|
||||
|
||||
|
||||
void cpuintrf_pop_context(void)
|
||||
void cpu_pop_context(void)
|
||||
{
|
||||
/* push the old context onto the stack */
|
||||
int cpunum = cpu_context_stack[--cpu_context_stack_ptr];
|
||||
|
||||
/* do the rest only if this isn't the activecpu */
|
||||
if (cpunum != activecpu && cpunum != -1)
|
||||
set_cpu_context(Machine, cpunum);
|
||||
|
||||
/* this is now the active CPU */
|
||||
activecpu = cpunum;
|
||||
const device_config *cpu = cpu_context_stack[--cpu_context_stack_ptr];
|
||||
if (cpu != NULL)
|
||||
{
|
||||
const device_config *oldcpu = cpu->machine->activecpu;
|
||||
set_cpu_context(oldcpu, cpu);
|
||||
}
|
||||
else
|
||||
{
|
||||
Machine->activecpu = NULL;
|
||||
activecpunum = -1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1105,9 +1104,6 @@ void cpuintrf_init(running_machine *machine)
|
||||
/* get other miscellaneous stuff */
|
||||
intf->context_size = cputype_context_size(cputype);
|
||||
intf->address_shift = cputype_addrbus_shift(cputype, ADDRESS_SPACE_PROGRAM);
|
||||
|
||||
/* also reset the active CPU context info */
|
||||
cpu_active_context[cputype] = -1;
|
||||
}
|
||||
|
||||
/* fill in any empty entries with the dummy CPU */
|
||||
@ -1118,15 +1114,15 @@ void cpuintrf_init(running_machine *machine)
|
||||
/* zap the CPU data structure */
|
||||
memset(cpu, 0, sizeof(cpu));
|
||||
totalcpu = 0;
|
||||
memset(cpu_dasm_override, 0, sizeof(cpu_dasm_override));
|
||||
|
||||
/* reset the context stack */
|
||||
memset(cpu_context_stack, -1, sizeof(cpu_context_stack));
|
||||
memset(&cpu_context_stack[0], 0, sizeof(cpu_context_stack));
|
||||
cpu_context_stack_ptr = 0;
|
||||
|
||||
/* nothing active, nothing executing */
|
||||
activecpu = -1;
|
||||
executingcpu = -1;
|
||||
activecpunum = -1;
|
||||
executingcpu = NULL;
|
||||
executingcpunum = -1;
|
||||
totalcpu = 0;
|
||||
|
||||
/* compute information about the CPUs now if we have a machine */
|
||||
@ -1144,6 +1140,7 @@ void cpuintrf_init(running_machine *machine)
|
||||
break;
|
||||
|
||||
/* fill in the type and interface */
|
||||
cpu[totalcpu].index = totalcpu;
|
||||
cpu[totalcpu].intf = cpuintrf[cputype];
|
||||
cpu[totalcpu].cputype = cputype;
|
||||
|
||||
@ -1167,9 +1164,10 @@ void cpuintrf_init(running_machine *machine)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
void cpuintrf_set_dasm_override(int cpunum, offs_t (*dasm_override)(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram))
|
||||
void cpu_set_dasm_override(const device_config *cpu, cpu_disassemble_func dasm_override)
|
||||
{
|
||||
cpu_dasm_override[cpunum] = dasm_override;
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpudata->dasm_override = dasm_override;
|
||||
}
|
||||
|
||||
|
||||
@ -1182,33 +1180,43 @@ void cpuintrf_set_dasm_override(int cpunum, offs_t (*dasm_override)(char *buffer
|
||||
|
||||
int cpuintrf_init_cpu(int cpunum, cpu_type cputype, int clock, const void *config, cpu_irq_callback irqcallback)
|
||||
{
|
||||
cpuintrf_data *cpudata = &cpu[cpunum];
|
||||
cpuinfo info;
|
||||
|
||||
/* create a fake device for the CPU */
|
||||
cpu[cpunum].device = auto_malloc(sizeof(*cpu[cpunum].device) + strlen(Machine->config->cpu[cpunum].tag));
|
||||
memset(cpu[cpunum].device, 0, sizeof(*cpu[cpunum].device));
|
||||
strcpy(cpu[cpunum].device->tag, Machine->config->cpu[cpunum].tag);
|
||||
cpu[cpunum].device->static_config = config;
|
||||
cpu[cpunum].device->machine = Machine;
|
||||
cpu[cpunum].device->token = auto_malloc(cpu[cpunum].intf.context_size);
|
||||
memset(cpu[cpunum].device->token, 0, cpu[cpunum].intf.context_size);
|
||||
cpudata->device = auto_malloc(sizeof(*cpudata->device) + strlen(Machine->config->cpu[cpunum].tag));
|
||||
memset(cpudata->device, 0, sizeof(*cpudata->device));
|
||||
strcpy(cpudata->device->tag, Machine->config->cpu[cpunum].tag);
|
||||
cpudata->device->type = (device_type)cputype;
|
||||
cpudata->device->class = DEVICE_CLASS_CPU_CHIP;
|
||||
cpudata->device->static_config = config;
|
||||
cpudata->device->started = TRUE;
|
||||
cpudata->device->machine = Machine;
|
||||
cpudata->device->region = memory_region(Machine, cpudata->device->tag);
|
||||
cpudata->device->regionbytes = memory_region_length(Machine, cpudata->device->tag);
|
||||
|
||||
/* allocate a context token */
|
||||
cpudata->device->token = auto_malloc(cpudata->intf.context_size);
|
||||
memset(cpudata->device->token, 0, cpudata->intf.context_size);
|
||||
|
||||
/* set up the class token */
|
||||
cpudata->device->classtoken = &cpu[cpunum];
|
||||
|
||||
/* put a pointer to the device in the machine */
|
||||
Machine->cpu[cpunum] = cpu[cpunum].device;
|
||||
Machine->cpu[cpunum] = cpudata->device;
|
||||
|
||||
/* initialize the CPU and stash the context */
|
||||
activecpu = cpunum;
|
||||
(*cpu[cpunum].intf.init)(cpu[cpunum].device, cpunum, clock, irqcallback);
|
||||
(*cpu[cpunum].intf.get_context)(cpu[cpunum].device->token);
|
||||
activecpu = -1;
|
||||
Machine->activecpu = Machine->cpu[cpunum];
|
||||
activecpunum = cpunum;
|
||||
(*cpudata->intf.init)(cpudata->device, cpunum, clock, irqcallback);
|
||||
(*cpudata->intf.get_context)(cpudata->device->token);
|
||||
Machine->activecpu = NULL;
|
||||
activecpunum = -1;
|
||||
|
||||
/* get the instruction count pointer */
|
||||
info.icount = NULL;
|
||||
(*cpu[cpunum].intf.get_info)(CPUINFO_PTR_INSTRUCTION_COUNTER, &info);
|
||||
cpu[cpunum].icount = info.icount;
|
||||
|
||||
/* clear out the registered CPU for this family */
|
||||
cpu_active_context[cpu[cpunum].family] = -1;
|
||||
(*cpudata->intf.get_info)(CPUINFO_PTR_INSTRUCTION_COUNTER, &info);
|
||||
cpudata->icount = info.icount;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1222,13 +1230,15 @@ int cpuintrf_init_cpu(int cpunum, cpu_type cputype, int clock, const void *confi
|
||||
|
||||
void cpuintrf_exit_cpu(int cpunum)
|
||||
{
|
||||
cpuintrf_data *cpudata = &cpu[cpunum];
|
||||
|
||||
/* if the CPU core defines an exit function, call it now */
|
||||
if (cpu[cpunum].intf.exit)
|
||||
if (cpudata->intf.exit)
|
||||
{
|
||||
/* switch contexts to the CPU during the exit */
|
||||
cpuintrf_push_context(cpunum);
|
||||
(*cpu[cpunum].intf.exit)(cpu[cpunum].device);
|
||||
cpuintrf_pop_context();
|
||||
cpu_push_context(cpu->device);
|
||||
(*cpudata->intf.exit)(cpu->device);
|
||||
cpu_pop_context();
|
||||
}
|
||||
}
|
||||
|
||||
@ -1240,80 +1250,6 @@ void cpuintrf_exit_cpu(int cpunum)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
/*--------------------------
|
||||
Get info accessors
|
||||
--------------------------*/
|
||||
|
||||
INT64 activecpu_get_info_int(UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_ACTIVECPU(activecpu_get_info_int);
|
||||
info.i = 0;
|
||||
(*cpu[activecpu].intf.get_info)(state, &info);
|
||||
return info.i;
|
||||
}
|
||||
|
||||
void *activecpu_get_info_ptr(UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_ACTIVECPU(activecpu_get_info_ptr);
|
||||
info.p = NULL;
|
||||
(*cpu[activecpu].intf.get_info)(state, &info);
|
||||
return info.p;
|
||||
}
|
||||
|
||||
genf *activecpu_get_info_fct(UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_ACTIVECPU(activecpu_get_info_fct);
|
||||
info.f = NULL;
|
||||
(*cpu[activecpu].intf.get_info)(state, &info);
|
||||
return info.f;
|
||||
}
|
||||
|
||||
const char *activecpu_get_info_string(UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_ACTIVECPU(activecpu_get_info_string);
|
||||
info.s = cpuintrf_temp_str();
|
||||
(*cpu[activecpu].intf.get_info)(state, &info);
|
||||
return info.s;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Set info accessors
|
||||
--------------------------*/
|
||||
|
||||
void activecpu_set_info_int(UINT32 state, INT64 data)
|
||||
{
|
||||
cpuinfo info;
|
||||
VERIFY_ACTIVECPU(activecpu_set_info_int);
|
||||
info.i = data;
|
||||
(*cpu[activecpu].intf.set_info)(state, &info);
|
||||
}
|
||||
|
||||
void activecpu_set_info_ptr(UINT32 state, void *data)
|
||||
{
|
||||
cpuinfo info;
|
||||
VERIFY_ACTIVECPU(activecpu_set_info_ptr);
|
||||
info.p = data;
|
||||
(*cpu[activecpu].intf.set_info)(state, &info);
|
||||
}
|
||||
|
||||
void activecpu_set_info_fct(UINT32 state, genf *data)
|
||||
{
|
||||
cpuinfo info;
|
||||
VERIFY_ACTIVECPU(activecpu_set_info_fct);
|
||||
info.f = data;
|
||||
(*cpu[activecpu].intf.set_info)(state, &info);
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Adjust/get icount
|
||||
--------------------------*/
|
||||
@ -1321,14 +1257,14 @@ void activecpu_set_info_fct(UINT32 state, genf *data)
|
||||
void activecpu_adjust_icount(int delta)
|
||||
{
|
||||
VERIFY_ACTIVECPU(activecpu_adjust_icount);
|
||||
*cpu[activecpu].icount += delta;
|
||||
*cpu[activecpunum].icount += delta;
|
||||
}
|
||||
|
||||
|
||||
int activecpu_get_icount(void)
|
||||
{
|
||||
VERIFY_ACTIVECPU(activecpu_get_icount);
|
||||
return *cpu[activecpu].icount;
|
||||
return *cpu[activecpunum].icount;
|
||||
}
|
||||
|
||||
|
||||
@ -1339,23 +1275,179 @@ int activecpu_get_icount(void)
|
||||
void activecpu_reset_banking(void)
|
||||
{
|
||||
VERIFY_ACTIVECPU(activecpu_reset_banking);
|
||||
memory_set_opbase(activecpu_get_physical_pc_byte());
|
||||
memory_set_opbase(cpu_get_physical_pc_byte(Machine->activecpu));
|
||||
}
|
||||
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* Interfaces to a specific CPU
|
||||
*
|
||||
*************************************/
|
||||
|
||||
/*--------------------------
|
||||
Get info accessors
|
||||
--------------------------*/
|
||||
|
||||
INT64 cpu_get_info_int(const device_config *cpu, UINT32 state)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPU(cpu_get_info_int);
|
||||
cpu_push_context(cpu);
|
||||
info.i = 0;
|
||||
(*cpudata->intf.get_info)(state, &info);
|
||||
cpu_pop_context();
|
||||
return info.i;
|
||||
}
|
||||
|
||||
void *cpu_get_info_ptr(const device_config *cpu, UINT32 state)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPU(cpu_get_info_ptr);
|
||||
cpu_push_context(cpu);
|
||||
info.p = NULL;
|
||||
(*cpudata->intf.get_info)(state, &info);
|
||||
cpu_pop_context();
|
||||
return info.p;
|
||||
}
|
||||
|
||||
genf *cpu_get_info_fct(const device_config *cpu, UINT32 state)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPU(cpu_get_info_fct);
|
||||
cpu_push_context(cpu);
|
||||
info.f = NULL;
|
||||
(*cpudata->intf.get_info)(state, &info);
|
||||
cpu_pop_context();
|
||||
return info.f;
|
||||
}
|
||||
|
||||
const char *cpu_get_info_string(const device_config *cpu, UINT32 state)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPU(cpu_get_info_string);
|
||||
cpu_push_context(cpu);
|
||||
info.s = cpuintrf_temp_str();
|
||||
(*cpudata->intf.get_info)(state, &info);
|
||||
cpu_pop_context();
|
||||
return info.s;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Input line setting
|
||||
Set info accessors
|
||||
--------------------------*/
|
||||
|
||||
void activecpu_set_input_line(int irqline, int state)
|
||||
void cpu_set_info_int(const device_config *cpu, UINT32 state, INT64 data)
|
||||
{
|
||||
VERIFY_ACTIVECPU(activecpu_set_input_line);
|
||||
if (state != INTERNAL_CLEAR_LINE && state != INTERNAL_ASSERT_LINE)
|
||||
{
|
||||
logerror("activecpu_set_input_line called when cpu_set_input_line should have been used!\n");
|
||||
return;
|
||||
}
|
||||
activecpu_set_info_int(CPUINFO_INT_INPUT_STATE + irqline, state - INTERNAL_CLEAR_LINE);
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPU(cpu_set_info_int);
|
||||
info.i = data;
|
||||
cpu_push_context(cpu);
|
||||
(*cpudata->intf.set_info)(state, &info);
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
void cpu_set_info_ptr(const device_config *cpu, UINT32 state, void *data)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPU(cpu_set_info_ptr);
|
||||
info.p = data;
|
||||
cpu_push_context(cpu);
|
||||
(*cpudata->intf.set_info)(state, &info);
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
void cpu_set_info_fct(const device_config *cpu, UINT32 state, genf *data)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPU(cpu_set_info_ptr);
|
||||
info.f = data;
|
||||
cpu_push_context(cpu);
|
||||
(*cpudata->intf.set_info)(state, &info);
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Execute
|
||||
--------------------------*/
|
||||
|
||||
int cpu_execute(const device_config *cpu, int cycles)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
int ran;
|
||||
|
||||
VERIFY_CPU(cpu_execute);
|
||||
cpu_push_context(cpu);
|
||||
executingcpu = cpu;
|
||||
executingcpunum = cpudata->index;
|
||||
memory_set_opbase(cpu_get_physical_pc_byte(cpu));
|
||||
ran = (*cpudata->intf.execute)(cpu, cycles);
|
||||
executingcpu = NULL;
|
||||
executingcpunum = -1;
|
||||
cpu_pop_context();
|
||||
return ran;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Reset and set IRQ ack
|
||||
--------------------------*/
|
||||
|
||||
void cpu_reset(const device_config *cpu)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
|
||||
VERIFY_CPU(cpu_reset);
|
||||
cpu_push_context(cpu);
|
||||
memory_set_opbase(0);
|
||||
(*cpudata->intf.reset)(cpu);
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Read a byte
|
||||
--------------------------*/
|
||||
|
||||
UINT8 cpu_read_byte(const device_config *cpu, offs_t address)
|
||||
{
|
||||
int result;
|
||||
|
||||
VERIFY_CPU(cpu_read_byte);
|
||||
cpu_push_context(cpu);
|
||||
result = program_read_byte(address);
|
||||
cpu_pop_context();
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Write a byte
|
||||
--------------------------*/
|
||||
|
||||
void cpu_write_byte(const device_config *cpu, offs_t address, UINT8 data)
|
||||
{
|
||||
VERIFY_CPU(cpu_write_byte);
|
||||
|
||||
cpu_push_context(cpu);
|
||||
program_write_byte(address, data);
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
@ -1363,28 +1455,34 @@ void activecpu_set_input_line(int irqline, int state)
|
||||
Get/set PC
|
||||
--------------------------*/
|
||||
|
||||
offs_t activecpu_get_physical_pc_byte(void)
|
||||
offs_t cpu_get_physical_pc_byte(const device_config *cpu)
|
||||
{
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
offs_t pc;
|
||||
int shift;
|
||||
|
||||
VERIFY_ACTIVECPU(activecpu_get_physical_pc_byte);
|
||||
shift = cpu[activecpu].intf.address_shift;
|
||||
pc = activecpu_get_reg(REG_PC);
|
||||
VERIFY_CPU(cpu_get_physical_pc_byte);
|
||||
shift = cpudata->intf.address_shift;
|
||||
cpu_push_context(cpu);
|
||||
pc = cpu_get_info_int(cpu, CPUINFO_INT_PC);
|
||||
if (shift < 0)
|
||||
pc <<= -shift;
|
||||
else
|
||||
pc >>= shift;
|
||||
if (cpu[activecpu].intf.translate)
|
||||
(*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &pc);
|
||||
if (cpudata->intf.translate != NULL)
|
||||
(cpudata->intf.translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &pc);
|
||||
cpu_pop_context();
|
||||
return pc;
|
||||
}
|
||||
|
||||
|
||||
void activecpu_set_opbase(unsigned val)
|
||||
void cpu_set_opbase(const device_config *cpu, unsigned val)
|
||||
{
|
||||
VERIFY_ACTIVECPU(activecpu_set_opbase);
|
||||
VERIFY_CPU(cpu_set_opbase);
|
||||
|
||||
cpu_push_context(cpu);
|
||||
memory_set_opbase(val);
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
@ -1392,28 +1490,29 @@ void activecpu_set_opbase(unsigned val)
|
||||
Disassembly
|
||||
--------------------------*/
|
||||
|
||||
offs_t activecpu_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
offs_t cpu_dasm(const device_config *cpu, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
unsigned result;
|
||||
|
||||
VERIFY_ACTIVECPU(activecpu_dasm);
|
||||
cpuintrf_data *cpudata = cpu->classtoken;
|
||||
offs_t result;
|
||||
|
||||
VERIFY_CPU(cpu_dasm);
|
||||
cpu_push_context(cpu);
|
||||
|
||||
/* check for disassembler override */
|
||||
if (cpu_dasm_override[activecpu])
|
||||
if (cpudata->dasm_override != NULL)
|
||||
{
|
||||
result = (*cpu_dasm_override[activecpu])(buffer, pc, oprom, opram);
|
||||
result = (*cpudata->dasm_override)(buffer, pc, oprom, opram);
|
||||
if (result != 0)
|
||||
return result;
|
||||
}
|
||||
|
||||
if (cpu[activecpu].intf.disassemble != NULL)
|
||||
{
|
||||
result = (*cpu[activecpu].intf.disassemble)(buffer, pc, oprom, opram);
|
||||
}
|
||||
if (cpudata->intf.disassemble != NULL)
|
||||
result = (*cpudata->intf.disassemble)(buffer, pc, oprom, opram);
|
||||
|
||||
else
|
||||
{
|
||||
/* if no disassembler present, dump vanilla bytes */
|
||||
switch (activecpu_min_instruction_bytes())
|
||||
switch (cpu_get_min_opcode_bytes(cpu))
|
||||
{
|
||||
case 1:
|
||||
default:
|
||||
@ -1437,228 +1536,15 @@ offs_t activecpu_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *
|
||||
assert((result & DASMFLAG_LENGTHMASK) != 0);
|
||||
#ifdef MAME_DEBUG
|
||||
{
|
||||
int shift = activecpu_addrbus_shift(ADDRESS_SPACE_PROGRAM);
|
||||
int shift = cpu_get_addrbus_shift(cpu, ADDRESS_SPACE_PROGRAM);
|
||||
int bytes = (shift < 0) ? ((result & DASMFLAG_LENGTHMASK) << -shift) : ((result & DASMFLAG_LENGTHMASK) >> shift);
|
||||
assert(bytes >= activecpu_min_instruction_bytes());
|
||||
assert(bytes <= activecpu_max_instruction_bytes());
|
||||
assert(bytes >= cpu_get_min_opcode_bytes(cpu));
|
||||
assert(bytes <= cpu_get_max_opcode_bytes(cpu));
|
||||
(void) bytes; /* appease compiler */
|
||||
}
|
||||
#endif
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* Interfaces to a specific CPU
|
||||
*
|
||||
*************************************/
|
||||
|
||||
/*--------------------------
|
||||
Get info accessors
|
||||
--------------------------*/
|
||||
|
||||
INT64 cpunum_get_info_int(int cpunum, UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPUNUM(cpunum_get_info_int);
|
||||
cpuintrf_push_context(cpunum);
|
||||
info.i = 0;
|
||||
(*cpu[cpunum].intf.get_info)(state, &info);
|
||||
cpuintrf_pop_context();
|
||||
return info.i;
|
||||
}
|
||||
|
||||
void *cpunum_get_info_ptr(int cpunum, UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPUNUM(cpunum_get_info_ptr);
|
||||
cpuintrf_push_context(cpunum);
|
||||
info.p = NULL;
|
||||
(*cpu[cpunum].intf.get_info)(state, &info);
|
||||
cpuintrf_pop_context();
|
||||
return info.p;
|
||||
}
|
||||
|
||||
genf *cpunum_get_info_fct(int cpunum, UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPUNUM(cpunum_get_info_fct);
|
||||
cpuintrf_push_context(cpunum);
|
||||
info.f = NULL;
|
||||
(*cpu[cpunum].intf.get_info)(state, &info);
|
||||
cpuintrf_pop_context();
|
||||
return info.f;
|
||||
}
|
||||
|
||||
const char *cpunum_get_info_string(int cpunum, UINT32 state)
|
||||
{
|
||||
cpuinfo info;
|
||||
|
||||
VERIFY_CPUNUM(cpunum_get_info_string);
|
||||
cpuintrf_push_context(cpunum);
|
||||
info.s = cpuintrf_temp_str();
|
||||
(*cpu[cpunum].intf.get_info)(state, &info);
|
||||
cpuintrf_pop_context();
|
||||
return info.s;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Set info accessors
|
||||
--------------------------*/
|
||||
|
||||
void cpunum_set_info_int(int cpunum, UINT32 state, INT64 data)
|
||||
{
|
||||
cpuinfo info;
|
||||
VERIFY_CPUNUM(cpunum_set_info_int);
|
||||
info.i = data;
|
||||
cpuintrf_push_context(cpunum);
|
||||
(*cpu[cpunum].intf.set_info)(state, &info);
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
void cpunum_set_info_ptr(int cpunum, UINT32 state, void *data)
|
||||
{
|
||||
cpuinfo info;
|
||||
VERIFY_CPUNUM(cpunum_set_info_ptr);
|
||||
info.p = data;
|
||||
cpuintrf_push_context(cpunum);
|
||||
(*cpu[cpunum].intf.set_info)(state, &info);
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
void cpunum_set_info_fct(int cpunum, UINT32 state, genf *data)
|
||||
{
|
||||
cpuinfo info;
|
||||
VERIFY_CPUNUM(cpunum_set_info_ptr);
|
||||
info.f = data;
|
||||
cpuintrf_push_context(cpunum);
|
||||
(*cpu[cpunum].intf.set_info)(state, &info);
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Execute
|
||||
--------------------------*/
|
||||
|
||||
int cpunum_execute(int cpunum, int cycles)
|
||||
{
|
||||
int ran;
|
||||
VERIFY_CPUNUM(cpunum_execute);
|
||||
cpuintrf_push_context(cpunum);
|
||||
executingcpu = cpunum;
|
||||
memory_set_opbase(activecpu_get_physical_pc_byte());
|
||||
ran = (*cpu[cpunum].intf.execute)(cpu[cpunum].device, cycles);
|
||||
executingcpu = -1;
|
||||
cpuintrf_pop_context();
|
||||
return ran;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Reset and set IRQ ack
|
||||
--------------------------*/
|
||||
|
||||
void cpunum_reset(int cpunum)
|
||||
{
|
||||
VERIFY_CPUNUM(cpunum_reset);
|
||||
cpuintrf_push_context(cpunum);
|
||||
memory_set_opbase(0);
|
||||
(*cpu[cpunum].intf.reset)(cpu[cpunum].device);
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Read a byte
|
||||
--------------------------*/
|
||||
|
||||
UINT8 cpunum_read_byte(int cpunum, offs_t address)
|
||||
{
|
||||
int result;
|
||||
VERIFY_CPUNUM(cpunum_read_byte);
|
||||
cpuintrf_push_context(cpunum);
|
||||
result = program_read_byte(address);
|
||||
cpuintrf_pop_context();
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Write a byte
|
||||
--------------------------*/
|
||||
|
||||
void cpunum_write_byte(int cpunum, offs_t address, UINT8 data)
|
||||
{
|
||||
VERIFY_CPUNUM(cpunum_write_byte);
|
||||
cpuintrf_push_context(cpunum);
|
||||
program_write_byte(address, data);
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Get context pointer
|
||||
--------------------------*/
|
||||
|
||||
void *cpunum_get_context_ptr(int cpunum)
|
||||
{
|
||||
VERIFY_CPUNUM(cpunum_get_context_ptr);
|
||||
return (cpu_active_context[cpu[cpunum].family] == cpunum) ? NULL : cpu[cpunum].device->token;
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Get/set PC
|
||||
--------------------------*/
|
||||
|
||||
offs_t cpunum_get_physical_pc_byte(int cpunum)
|
||||
{
|
||||
offs_t pc;
|
||||
int shift;
|
||||
|
||||
VERIFY_CPUNUM(cpunum_get_physical_pc_byte);
|
||||
shift = cpu[cpunum].intf.address_shift;
|
||||
cpuintrf_push_context(cpunum);
|
||||
pc = activecpu_get_info_int(CPUINFO_INT_PC);
|
||||
if (shift < 0)
|
||||
pc <<= -shift;
|
||||
else
|
||||
pc >>= shift;
|
||||
if (cpu[activecpu].intf.translate)
|
||||
(*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &pc);
|
||||
cpuintrf_pop_context();
|
||||
return pc;
|
||||
}
|
||||
|
||||
|
||||
void cpunum_set_opbase(int cpunum, unsigned val)
|
||||
{
|
||||
VERIFY_CPUNUM(cpunum_set_opbase);
|
||||
cpuintrf_push_context(cpunum);
|
||||
memory_set_opbase(val);
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
|
||||
/*--------------------------
|
||||
Disassembly
|
||||
--------------------------*/
|
||||
|
||||
offs_t cpunum_dasm(int cpunum, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
||||
{
|
||||
unsigned result;
|
||||
VERIFY_CPUNUM(cpunum_dasm);
|
||||
cpuintrf_push_context(cpunum);
|
||||
result = activecpu_dasm(buffer, pc, oprom, opram);
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
return result;
|
||||
}
|
||||
|
||||
|
@ -37,10 +37,6 @@ enum
|
||||
HOLD_LINE, /* hold interrupt line until acknowledged */
|
||||
PULSE_LINE, /* pulse interrupt line for one instruction */
|
||||
|
||||
/* internal flags (not for use by drivers!) */
|
||||
INTERNAL_CLEAR_LINE = 100 + CLEAR_LINE,
|
||||
INTERNAL_ASSERT_LINE = 100 + ASSERT_LINE,
|
||||
|
||||
/* input lines */
|
||||
MAX_INPUT_LINES = 32+3,
|
||||
INPUT_LINE_IRQ0 = 0,
|
||||
@ -373,33 +369,16 @@ int cpuintrf_init_cpu(int cpunum, cpu_type cputype, int clock, const void *confi
|
||||
void cpuintrf_exit_cpu(int cpunum);
|
||||
|
||||
/* remember the previous context and set a new one */
|
||||
void cpuintrf_push_context(int cpunum);
|
||||
void cpu_push_context(const device_config *cpu);
|
||||
|
||||
/* restore the previous context */
|
||||
void cpuintrf_pop_context(void);
|
||||
void cpu_pop_context(void);
|
||||
|
||||
/* circular string buffer */
|
||||
char *cpuintrf_temp_str(void);
|
||||
|
||||
/* set the dasm override handler */
|
||||
void cpuintrf_set_dasm_override(int cpunum, offs_t (*dasm_override)(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram));
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
ACTIVE CPU ACCCESSORS
|
||||
***************************************************************************/
|
||||
|
||||
/* get info accessors */
|
||||
INT64 activecpu_get_info_int(UINT32 state);
|
||||
void *activecpu_get_info_ptr(UINT32 state);
|
||||
genf *activecpu_get_info_fct(UINT32 state);
|
||||
const char *activecpu_get_info_string(UINT32 state);
|
||||
|
||||
/* set info accessors */
|
||||
void activecpu_set_info_int(UINT32 state, INT64 data);
|
||||
void activecpu_set_info_ptr(UINT32 state, void *data);
|
||||
void activecpu_set_info_fct(UINT32 state, genf *data);
|
||||
void cpu_set_dasm_override(const device_config *cpu, cpu_disassemble_func dasm_override);
|
||||
|
||||
/* apply a +/- to the current icount */
|
||||
void activecpu_adjust_icount(int delta);
|
||||
@ -410,117 +389,75 @@ int activecpu_get_icount(void);
|
||||
/* ensure banking is reset properly */
|
||||
void activecpu_reset_banking(void);
|
||||
|
||||
/* set the input line on a CPU -- drivers use cpu_set_input_line() */
|
||||
void activecpu_set_input_line(int irqline, int state);
|
||||
|
||||
/* return the PC, corrected to a byte offset, on the active CPU */
|
||||
offs_t activecpu_get_physical_pc_byte(void);
|
||||
|
||||
/* update the banking on the active CPU */
|
||||
void activecpu_set_opbase(offs_t val);
|
||||
|
||||
/* disassemble a line at a given PC on the active CPU */
|
||||
offs_t activecpu_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
|
||||
#define activecpu_context_size() activecpu_get_info_int(CPUINFO_INT_CONTEXT_SIZE)
|
||||
#define activecpu_input_lines() activecpu_get_info_int(CPUINFO_INT_INPUT_LINES)
|
||||
#define activecpu_output_lines() activecpu_get_info_int(CPUINFO_INT_OUTPUT_LINES)
|
||||
#define activecpu_default_irq_vector() activecpu_get_info_int(CPUINFO_INT_DEFAULT_IRQ_VECTOR)
|
||||
#define activecpu_endianness() activecpu_get_info_int(CPUINFO_INT_ENDIANNESS)
|
||||
#define activecpu_clock_multiplier() activecpu_get_info_int(CPUINFO_INT_CLOCK_MULTIPLIER)
|
||||
#define activecpu_clock_divider() activecpu_get_info_int(CPUINFO_INT_CLOCK_DIVIDER)
|
||||
#define activecpu_min_instruction_bytes() activecpu_get_info_int(CPUINFO_INT_MIN_INSTRUCTION_BYTES)
|
||||
#define activecpu_max_instruction_bytes() activecpu_get_info_int(CPUINFO_INT_MAX_INSTRUCTION_BYTES)
|
||||
#define activecpu_min_cycles() activecpu_get_info_int(CPUINFO_INT_MIN_CYCLES)
|
||||
#define activecpu_max_cycles() activecpu_get_info_int(CPUINFO_INT_MAX_CYCLES)
|
||||
#define activecpu_databus_width(space) activecpu_get_info_int(CPUINFO_INT_DATABUS_WIDTH + (space))
|
||||
#define activecpu_addrbus_width(space) activecpu_get_info_int(CPUINFO_INT_ADDRBUS_WIDTH + (space))
|
||||
#define activecpu_addrbus_shift(space) activecpu_get_info_int(CPUINFO_INT_ADDRBUS_SHIFT + (space))
|
||||
#define activecpu_logaddr_width(space) activecpu_get_info_int(CPUINFO_INT_LOGADDR_WIDTH + (space))
|
||||
#define activecpu_page_shift(space) activecpu_get_info_int(CPUINFO_INT_PAGE_SHIFT + (space))
|
||||
#define activecpu_get_reg(reg) activecpu_get_info_int(CPUINFO_INT_REGISTER + (reg))
|
||||
#define activecpu_debug_register_list() activecpu_get_info_ptr(CPUINFO_PTR_DEBUG_REGISTER_LIST)
|
||||
#define activecpu_name() activecpu_get_info_string(CPUINFO_STR_NAME)
|
||||
#define activecpu_core_family() activecpu_get_info_string(CPUINFO_STR_CORE_FAMILY)
|
||||
#define activecpu_core_version() activecpu_get_info_string(CPUINFO_STR_CORE_VERSION)
|
||||
#define activecpu_core_file() activecpu_get_info_string(CPUINFO_STR_CORE_FILE)
|
||||
#define activecpu_core_credits() activecpu_get_info_string(CPUINFO_STR_CORE_CREDITS)
|
||||
#define activecpu_flags() activecpu_get_info_string(CPUINFO_STR_FLAGS)
|
||||
#define activecpu_irq_string(irq) activecpu_get_info_string(CPUINFO_STR_IRQ_STATE + (irq))
|
||||
#define activecpu_reg_string(reg) activecpu_get_info_string(CPUINFO_STR_REGISTER + (reg))
|
||||
|
||||
#define activecpu_set_reg(reg, val) activecpu_set_info_int(CPUINFO_INT_REGISTER + (reg), (val))
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
SPECIFIC CPU ACCCESSORS
|
||||
CORE CPU ACCCESSORS
|
||||
***************************************************************************/
|
||||
|
||||
/* get info accessors */
|
||||
INT64 cpunum_get_info_int(int cpunum, UINT32 state);
|
||||
void *cpunum_get_info_ptr(int cpunum, UINT32 state);
|
||||
genf *cpunum_get_info_fct(int cpunum, UINT32 state);
|
||||
const char *cpunum_get_info_string(int cpunum, UINT32 state);
|
||||
INT64 cpu_get_info_int(const device_config *cpu, UINT32 state);
|
||||
void *cpu_get_info_ptr(const device_config *cpu, UINT32 state);
|
||||
genf *cpu_get_info_fct(const device_config *cpu, UINT32 state);
|
||||
const char *cpu_get_info_string(const device_config *cpu, UINT32 state);
|
||||
|
||||
/* set info accessors */
|
||||
void cpunum_set_info_int(int cpunum, UINT32 state, INT64 data);
|
||||
void cpunum_set_info_ptr(int cpunum, UINT32 state, void *data);
|
||||
void cpunum_set_info_fct(int cpunum, UINT32 state, genf *data);
|
||||
void cpu_set_info_int(const device_config *cpu, UINT32 state, INT64 data);
|
||||
void cpu_set_info_ptr(const device_config *cpu, UINT32 state, void *data);
|
||||
void cpu_set_info_fct(const device_config *cpu, UINT32 state, genf *data);
|
||||
|
||||
/* execute the requested cycles on a given CPU */
|
||||
int cpunum_execute(int cpunum, int cycles);
|
||||
int cpu_execute(const device_config *cpu, int cycles);
|
||||
|
||||
/* signal a reset for a given CPU */
|
||||
void cpunum_reset(int cpunum);
|
||||
void cpu_reset(const device_config *cpu);
|
||||
|
||||
/* read a byte from another CPU's memory space */
|
||||
UINT8 cpunum_read_byte(int cpunum, offs_t address);
|
||||
UINT8 cpu_read_byte(const device_config *cpu, offs_t address);
|
||||
|
||||
/* write a byte from another CPU's memory space */
|
||||
void cpunum_write_byte(int cpunum, offs_t address, UINT8 data);
|
||||
|
||||
/* return a pointer to the saved context of a given CPU, or NULL if the
|
||||
context is active (and contained within the CPU core */
|
||||
void *cpunum_get_context_ptr(int cpunum);
|
||||
void cpu_write_byte(const device_config *cpu, offs_t address, UINT8 data);
|
||||
|
||||
/* return the PC, corrected to a byte offset, on a given CPU */
|
||||
offs_t cpunum_get_physical_pc_byte(int cpunum);
|
||||
offs_t cpu_get_physical_pc_byte(const device_config *cpu);
|
||||
|
||||
/* update the banking on a given CPU */
|
||||
void cpunum_set_opbase(int cpunum, offs_t val);
|
||||
void cpu_set_opbase(const device_config *cpu, offs_t val);
|
||||
|
||||
/* disassemble a line at a given PC on a given CPU */
|
||||
offs_t cpunum_dasm(int cpunum, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t cpu_dasm(const device_config *cpu, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
|
||||
#define cpunum_context_size(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_CONTEXT_SIZE)
|
||||
#define cpunum_input_lines(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_INPUT_LINES)
|
||||
#define cpunum_output_lines(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_OUTPUT_LINES)
|
||||
#define cpunum_default_irq_vector(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_DEFAULT_IRQ_VECTOR)
|
||||
#define cpunum_endianness(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_ENDIANNESS)
|
||||
#define cpunum_clock_multiplier(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_CLOCK_MULTIPLIER)
|
||||
#define cpunum_clock_divider(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_CLOCK_DIVIDER)
|
||||
#define cpunum_min_instruction_bytes(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_MIN_INSTRUCTION_BYTES)
|
||||
#define cpunum_max_instruction_bytes(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_MAX_INSTRUCTION_BYTES)
|
||||
#define cpunum_min_cycles(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_MIN_CYCLES)
|
||||
#define cpunum_max_cycles(cpunum) cpunum_get_info_int(cpunum, CPUINFO_INT_MAX_CYCLES)
|
||||
#define cpunum_databus_width(cpunum, space) cpunum_get_info_int(cpunum, CPUINFO_INT_DATABUS_WIDTH + (space))
|
||||
#define cpunum_addrbus_width(cpunum, space) cpunum_get_info_int(cpunum, CPUINFO_INT_ADDRBUS_WIDTH + (space))
|
||||
#define cpunum_addrbus_shift(cpunum, space) cpunum_get_info_int(cpunum, CPUINFO_INT_ADDRBUS_SHIFT + (space))
|
||||
#define cpunum_logaddr_width(cpunum, space) cpunum_get_info_int(cpunum, CPUINFO_INT_LOGADDR_WIDTH + (space))
|
||||
#define cpunum_page_shift(cpunum, space) cpunum_get_info_int(cpunum, CPUINFO_INT_PAGE_SHIFT + (space))
|
||||
#define cpunum_get_reg(cpunum, reg) cpunum_get_info_int(cpunum, CPUINFO_INT_REGISTER + (reg))
|
||||
#define cpunum_debug_register_list(cpunum) cpunum_get_info_ptr(cpunum, CPUINFO_PTR_DEBUG_REGISTER_LIST)
|
||||
#define cpunum_name(cpunum) cpunum_get_info_string(cpunum, CPUINFO_STR_NAME)
|
||||
#define cpunum_core_family(cpunum) cpunum_get_info_string(cpunum, CPUINFO_STR_CORE_FAMILY)
|
||||
#define cpunum_core_version(cpunum) cpunum_get_info_string(cpunum, CPUINFO_STR_CORE_VERSION)
|
||||
#define cpunum_core_file(cpunum) cpunum_get_info_string(cpunum, CPUINFO_STR_CORE_FILE)
|
||||
#define cpunum_core_credits(cpunum) cpunum_get_info_string(cpunum, CPUINFO_STR_CORE_CREDITS)
|
||||
#define cpunum_flags(cpunum) cpunum_get_info_string(cpunum, CPUINFO_STR_FLAGS)
|
||||
#define cpunum_irq_string(cpunum, irq) cpunum_get_info_string(cpunum, CPUINFO_STR_IRQ_STATE + (irq))
|
||||
#define cpunum_reg_string(cpunum, reg) cpunum_get_info_string(cpunum, CPUINFO_STR_REGISTER + (reg))
|
||||
#define cpu_get_context_size(cpu) cpu_get_info_int(cpu, CPUINFO_INT_CONTEXT_SIZE)
|
||||
#define cpu_get_input_lines(cpu) cpu_get_info_int(cpu, CPUINFO_INT_INPUT_LINES)
|
||||
#define cpu_get_output_lines(cpu) cpu_get_info_int(cpu, CPUINFO_INT_OUTPUT_LINES)
|
||||
#define cpu_get_default_irq_vector(cpu) cpu_get_info_int(cpu, CPUINFO_INT_DEFAULT_IRQ_VECTOR)
|
||||
#define cpu_get_endianness(cpu) cpu_get_info_int(cpu, CPUINFO_INT_ENDIANNESS)
|
||||
#define cpu_get_clock_multiplier(cpu) cpu_get_info_int(cpu, CPUINFO_INT_CLOCK_MULTIPLIER)
|
||||
#define cpu_get_clock_divider(cpu) cpu_get_info_int(cpu, CPUINFO_INT_CLOCK_DIVIDER)
|
||||
#define cpu_get_min_opcode_bytes(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MIN_INSTRUCTION_BYTES)
|
||||
#define cpu_get_max_opcode_bytes(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MAX_INSTRUCTION_BYTES)
|
||||
#define cpu_get_min_cycles(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MIN_CYCLES)
|
||||
#define cpu_get_max_cycles(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MAX_CYCLES)
|
||||
#define cpu_get_databus_width(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_DATABUS_WIDTH + (space))
|
||||
#define cpu_get_addrbus_width(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_ADDRBUS_WIDTH + (space))
|
||||
#define cpu_get_addrbus_shift(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_ADDRBUS_SHIFT + (space))
|
||||
#define cpu_get_logaddr_width(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_LOGADDR_WIDTH + (space))
|
||||
#define cpu_get_page_shift(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_PAGE_SHIFT + (space))
|
||||
#define cpu_get_reg(cpu, reg) cpu_get_info_int(cpu, CPUINFO_INT_REGISTER + (reg))
|
||||
#define cpu_get_previouspc(cpu) ((offs_t)cpu_get_info_int(cpu, REG_PREVIOUSPC))
|
||||
#define cpu_get_pc(cpu) ((offs_t)cpu_get_reg(cpu, REG_PC))
|
||||
#define cpu_get_sp(cpu) cpu_get_reg(cpu, REG_SP)
|
||||
#define cpu_get_debug_register_list(cpu) cpu_get_info_ptr(cpu, CPUINFO_PTR_DEBUG_REGISTER_LIST)
|
||||
#define cpu_get_name(cpu) cpu_get_info_string(cpu, CPUINFO_STR_NAME)
|
||||
#define cpu_get_core_family(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_FAMILY)
|
||||
#define cpu_get_core_version(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_VERSION)
|
||||
#define cpu_get_core_file(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_FILE)
|
||||
#define cpu_get_core_credits(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_CREDITS)
|
||||
#define cpu_get_flags_string(cpu) cpu_get_info_string(cpu, CPUINFO_STR_FLAGS)
|
||||
#define cpu_get_irq_string(cpu, irq) cpu_get_info_string(cpu, CPUINFO_STR_IRQ_STATE + (irq))
|
||||
#define cpu_get_reg_string(cpu, reg) cpu_get_info_string(cpu, CPUINFO_STR_REGISTER + (reg))
|
||||
|
||||
#define cpunum_set_reg(cpunum, reg, val) cpunum_set_info_int(cpunum, CPUINFO_INT_REGISTER + (reg), (val))
|
||||
#define cpu_set_reg(cpu, reg, val) cpu_set_info_int(cpu, CPUINFO_INT_REGISTER + (reg), (val))
|
||||
|
||||
|
||||
|
||||
@ -558,16 +495,6 @@ const char *cputype_get_info_string(cpu_type cputype, UINT32 state);
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
MACROS
|
||||
***************************************************************************/
|
||||
|
||||
#define activecpu_get_previouspc() ((offs_t)activecpu_get_reg(REG_PREVIOUSPC))
|
||||
#define activecpu_get_pc() ((offs_t)activecpu_get_reg(REG_PC))
|
||||
#define activecpu_get_sp() activecpu_get_reg(REG_SP)
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
CPU INTERFACE ACCESSORS
|
||||
***************************************************************************/
|
||||
@ -580,22 +507,30 @@ INLINE const cpu_interface *cputype_get_interface(cpu_type cputype)
|
||||
}
|
||||
|
||||
|
||||
/* return a the index of the active CPU */
|
||||
INLINE int cpu_getactivecpu(void)
|
||||
/* return the index of the active CPU */
|
||||
INLINE int cpunum_get_active(void)
|
||||
{
|
||||
extern int activecpu;
|
||||
return activecpu;
|
||||
extern int activecpunum;
|
||||
return activecpunum;
|
||||
}
|
||||
|
||||
|
||||
/* return a the index of the executing CPU */
|
||||
INLINE int cpu_getexecutingcpu(void)
|
||||
/* return a pointer to the executing CPU */
|
||||
INLINE const device_config *cpu_get_executing(void)
|
||||
{
|
||||
extern int executingcpu;
|
||||
extern const device_config *executingcpu;
|
||||
return executingcpu;
|
||||
}
|
||||
|
||||
|
||||
/* return the index of the executing CPU */
|
||||
INLINE int cpunum_get_executing(void)
|
||||
{
|
||||
extern int executingcpunum;
|
||||
return executingcpunum;
|
||||
}
|
||||
|
||||
|
||||
/* return a the total number of registered CPUs */
|
||||
INLINE int cpu_gettotalcpu(void)
|
||||
{
|
||||
@ -605,9 +540,9 @@ INLINE int cpu_gettotalcpu(void)
|
||||
|
||||
|
||||
/* return the current PC or ~0 if no CPU is active */
|
||||
INLINE offs_t safe_activecpu_get_pc(void)
|
||||
INLINE offs_t safe_cpu_get_pc(const device_config *cpu)
|
||||
{
|
||||
return (cpu_getactivecpu() >= 0) ? activecpu_get_pc() : ~0;
|
||||
return (cpu != NULL) ? cpu_get_pc(cpu) : ~0;
|
||||
}
|
||||
|
||||
|
||||
|
@ -248,7 +248,7 @@ void debug_command_init(running_machine *machine)
|
||||
for (cpunum = 0; cpunum < cpu_gettotalcpu(); cpunum++)
|
||||
{
|
||||
cpu_debug_init_func debug_init;
|
||||
debug_init = cpunum_get_info_fct(cpunum, CPUINFO_PTR_DEBUG_INIT);
|
||||
debug_init = cpu_get_info_fct(machine->cpu[cpunum], CPUINFO_PTR_DEBUG_INIT);
|
||||
if (debug_init != NULL)
|
||||
(*debug_init)();
|
||||
}
|
||||
@ -369,7 +369,7 @@ static void global_set(void *ref, UINT64 value)
|
||||
|
||||
int debug_command_parameter_number(const char *param, UINT64 *result)
|
||||
{
|
||||
EXPRERR err = expression_evaluate(param, debug_get_cpu_info(cpu_getactivecpu())->symtable, &debug_expression_callbacks, result);
|
||||
EXPRERR err = expression_evaluate(param, debug_get_cpu_info(cpunum_get_active())->symtable, &debug_expression_callbacks, result);
|
||||
if (err == EXPRERR_NONE)
|
||||
return 1;
|
||||
debug_console_printf("Error in expression: %s\n", param);
|
||||
@ -386,7 +386,7 @@ int debug_command_parameter_number(const char *param, UINT64 *result)
|
||||
|
||||
static int debug_command_parameter_expression(const char *param, parsed_expression **result)
|
||||
{
|
||||
EXPRERR err = expression_parse(param, debug_get_cpu_info(cpu_getactivecpu())->symtable, &debug_expression_callbacks, result);
|
||||
EXPRERR err = expression_parse(param, debug_get_cpu_info(cpunum_get_active())->symtable, &debug_expression_callbacks, result);
|
||||
if (err == EXPRERR_NONE)
|
||||
return 1;
|
||||
debug_console_printf("Error in expression: %s\n", param);
|
||||
@ -601,7 +601,7 @@ static void execute_logerror(running_machine *machine, int ref, int params, cons
|
||||
|
||||
static void execute_tracelog(running_machine *machine, int ref, int params, const char *param[])
|
||||
{
|
||||
FILE *file = debug_get_cpu_info(cpu_getactivecpu())->trace.file;
|
||||
FILE *file = debug_get_cpu_info(cpunum_get_active())->trace.file;
|
||||
UINT64 values[MAX_COMMAND_PARAMS];
|
||||
char buffer[1024];
|
||||
int i;
|
||||
@ -935,7 +935,7 @@ static void execute_comment(running_machine *machine, int ref, int params, const
|
||||
}
|
||||
|
||||
/* Now try adding the comment */
|
||||
debug_comment_add(cpu_getactivecpu(), address, param[1], 0x00ff0000, debug_comment_get_opcode_crc32(address));
|
||||
debug_comment_add(cpunum_get_active(), address, param[1], 0x00ff0000, debug_comment_get_opcode_crc32(address));
|
||||
debug_view_update_type(DVT_DISASSEMBLY);
|
||||
}
|
||||
|
||||
@ -954,7 +954,7 @@ static void execute_comment_del(running_machine *machine, int ref, int params, c
|
||||
|
||||
/* If it's a number, it must be an address */
|
||||
/* The bankoff and cbn will be pulled from what's currently active */
|
||||
debug_comment_remove(cpu_getactivecpu(), address, debug_comment_get_opcode_crc32(address));
|
||||
debug_comment_remove(cpunum_get_active(), address, debug_comment_get_opcode_crc32(address));
|
||||
debug_view_update_type(DVT_DISASSEMBLY);
|
||||
}
|
||||
|
||||
@ -983,7 +983,7 @@ static void execute_bpset(running_machine *machine, int ref, int params, const c
|
||||
int bpnum;
|
||||
|
||||
/* make sure that there is an active CPU */
|
||||
if (cpu_getactivecpu() < 0)
|
||||
if (cpunum_get_active() < 0)
|
||||
{
|
||||
debug_console_printf("No active CPU!\n");
|
||||
return;
|
||||
@ -1002,7 +1002,7 @@ static void execute_bpset(running_machine *machine, int ref, int params, const c
|
||||
return;
|
||||
|
||||
/* set the breakpoint */
|
||||
bpnum = debug_cpu_breakpoint_set(machine, cpu_getactivecpu(), address, condition, action);
|
||||
bpnum = debug_cpu_breakpoint_set(machine, cpunum_get_active(), address, condition, action);
|
||||
debug_console_printf("Breakpoint %X set\n", bpnum);
|
||||
}
|
||||
|
||||
@ -1176,7 +1176,7 @@ static void execute_wpset(running_machine *machine, int ref, int params, const c
|
||||
return;
|
||||
|
||||
/* set the watchpoint */
|
||||
wpnum = debug_cpu_watchpoint_set(machine, cpu_getactivecpu(), ref, type, address, length, condition, action);
|
||||
wpnum = debug_cpu_watchpoint_set(machine, cpunum_get_active(), ref, type, address, length, condition, action);
|
||||
debug_console_printf("Watchpoint %X set\n", wpnum);
|
||||
}
|
||||
|
||||
@ -1362,7 +1362,7 @@ static void execute_hotspot(running_machine *machine, int ref, int params, const
|
||||
}
|
||||
|
||||
/* extract parameters */
|
||||
cpunum = cpu_getactivecpu();
|
||||
cpunum = cpunum_get_active();
|
||||
count = 64;
|
||||
threshhold = 250;
|
||||
if (params > 0 && !debug_command_parameter_number(param[0], &cpunum))
|
||||
@ -1386,7 +1386,7 @@ static void execute_hotspot(running_machine *machine, int ref, int params, const
|
||||
|
||||
static void execute_save(running_machine *machine, int ref, int params, const char *param[])
|
||||
{
|
||||
UINT64 offset, endoffset, length, cpunum = cpu_getactivecpu();
|
||||
UINT64 offset, endoffset, length, cpunum = cpunum_get_active();
|
||||
const debug_cpu_info *info;
|
||||
int spacenum = ref;
|
||||
FILE *f;
|
||||
@ -1414,13 +1414,13 @@ static void execute_save(running_machine *machine, int ref, int params, const ch
|
||||
}
|
||||
|
||||
/* now write the data out */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
for (i = offset; i <= endoffset; i++)
|
||||
{
|
||||
UINT8 byte = debug_read_byte(spacenum, i, TRUE);
|
||||
fwrite(&byte, 1, 1, f);
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
/* close the file */
|
||||
fclose(f);
|
||||
@ -1434,7 +1434,7 @@ static void execute_save(running_machine *machine, int ref, int params, const ch
|
||||
|
||||
static void execute_dump(running_machine *machine, int ref, int params, const char *param[])
|
||||
{
|
||||
UINT64 offset, endoffset, length, width = 0, ascii = 1, cpunum = cpu_getactivecpu();
|
||||
UINT64 offset, endoffset, length, width = 0, ascii = 1, cpunum = cpunum_get_active();
|
||||
const debug_cpu_info *info;
|
||||
int spacenum = ref;
|
||||
FILE *f = NULL;
|
||||
@ -1480,7 +1480,7 @@ static void execute_dump(running_machine *machine, int ref, int params, const ch
|
||||
}
|
||||
|
||||
/* now write the data out */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
for (i = offset; i <= endoffset; i += 16)
|
||||
{
|
||||
char output[200];
|
||||
@ -1589,7 +1589,7 @@ static void execute_dump(running_machine *machine, int ref, int params, const ch
|
||||
/* output the result */
|
||||
fprintf(f, "%s\n", output);
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
/* close the file */
|
||||
fclose(f);
|
||||
@ -1603,7 +1603,7 @@ static void execute_dump(running_machine *machine, int ref, int params, const ch
|
||||
|
||||
static void execute_find(running_machine *machine, int ref, int params, const char *param[])
|
||||
{
|
||||
UINT64 offset, endoffset, length, cpunum = cpu_getactivecpu();
|
||||
UINT64 offset, endoffset, length, cpunum = cpunum_get_active();
|
||||
const debug_cpu_info *info;
|
||||
UINT64 data_to_find[256];
|
||||
UINT8 data_size[256];
|
||||
@ -1668,7 +1668,7 @@ static void execute_find(running_machine *machine, int ref, int params, const ch
|
||||
}
|
||||
|
||||
/* now search */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
for (i = offset; i <= endoffset; i += data_size[0])
|
||||
{
|
||||
int suboffset = 0;
|
||||
@ -1695,7 +1695,7 @@ static void execute_find(running_machine *machine, int ref, int params, const ch
|
||||
debug_console_printf("Found at %*X\n", info->space[spacenum].logchars, (UINT32)BYTE2ADDR(i, info, spacenum));
|
||||
}
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
/* print something if not found */
|
||||
if (found == 0)
|
||||
@ -1709,7 +1709,7 @@ static void execute_find(running_machine *machine, int ref, int params, const ch
|
||||
|
||||
static void execute_dasm(running_machine *machine, int ref, int params, const char *param[])
|
||||
{
|
||||
UINT64 offset, length, bytes = 1, cpunum = cpu_getactivecpu();
|
||||
UINT64 offset, length, bytes = 1, cpunum = cpunum_get_active();
|
||||
const debug_cpu_info *info;
|
||||
int minbytes, maxbytes, byteswidth;
|
||||
FILE *f = NULL;
|
||||
@ -1734,8 +1734,8 @@ static void execute_dasm(running_machine *machine, int ref, int params, const ch
|
||||
info = debug_get_cpu_info(cpunum);
|
||||
|
||||
/* determine the width of the bytes */
|
||||
minbytes = cpunum_min_instruction_bytes(cpunum);
|
||||
maxbytes = cpunum_max_instruction_bytes(cpunum);
|
||||
minbytes = cpu_get_min_opcode_bytes(machine->cpu[cpunum]);
|
||||
maxbytes = cpu_get_max_opcode_bytes(machine->cpu[cpunum]);
|
||||
byteswidth = 0;
|
||||
if (bytes)
|
||||
{
|
||||
@ -1752,7 +1752,7 @@ static void execute_dasm(running_machine *machine, int ref, int params, const ch
|
||||
}
|
||||
|
||||
/* now write the data out */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
for (i = 0; i < length; )
|
||||
{
|
||||
int pcbyte = ADDR2BYTE_MASKED(offset + i, info, ADDRESS_SPACE_PROGRAM);
|
||||
@ -1779,7 +1779,7 @@ static void execute_dasm(running_machine *machine, int ref, int params, const ch
|
||||
}
|
||||
|
||||
/* disassemble the result */
|
||||
i += numbytes = activecpu_dasm(disasm, offset + i, opbuf, argbuf) & DASMFLAG_LENGTHMASK;
|
||||
i += numbytes = cpu_dasm(machine->activecpu, disasm, offset + i, opbuf, argbuf) & DASMFLAG_LENGTHMASK;
|
||||
}
|
||||
|
||||
/* print the bytes */
|
||||
@ -1841,7 +1841,7 @@ static void execute_dasm(running_machine *machine, int ref, int params, const ch
|
||||
/* output the result */
|
||||
fprintf(f, "%s\n", output);
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
/* close the file */
|
||||
fclose(f);
|
||||
@ -1861,7 +1861,7 @@ static void execute_trace_internal(running_machine *machine, int ref, int params
|
||||
const char *mode;
|
||||
UINT64 cpunum;
|
||||
|
||||
cpunum = cpu_getactivecpu();
|
||||
cpunum = cpunum_get_active();
|
||||
|
||||
/* validate parameters */
|
||||
if (params > 1 && !debug_command_parameter_number(param[1], &cpunum))
|
||||
@ -1948,7 +1948,7 @@ static void execute_history(running_machine *machine, int ref, int params, const
|
||||
UINT64 cpunum;
|
||||
int i;
|
||||
|
||||
cpunum = cpu_getactivecpu();
|
||||
cpunum = cpunum_get_active();
|
||||
|
||||
/* validate parameters */
|
||||
if (params > 0 && !debug_command_parameter_number(param[0], &cpunum))
|
||||
@ -1968,11 +1968,11 @@ static void execute_history(running_machine *machine, int ref, int params, const
|
||||
info = debug_get_cpu_info(cpunum);
|
||||
|
||||
/* loop over lines */
|
||||
cpuintrf_push_context(cpunum);
|
||||
cpu_push_context(machine->cpu[cpunum]);
|
||||
for (i = 0; i < count; i++)
|
||||
{
|
||||
offs_t pc = info->pc_history[(info->pc_history_index + DEBUG_HISTORY_SIZE - count + i) % DEBUG_HISTORY_SIZE];
|
||||
int maxbytes = activecpu_max_instruction_bytes();
|
||||
int maxbytes = cpu_get_max_opcode_bytes(machine->activecpu);
|
||||
UINT8 opbuf[64], argbuf[64];
|
||||
char buffer[200];
|
||||
offs_t pcbyte;
|
||||
@ -1986,11 +1986,11 @@ static void execute_history(running_machine *machine, int ref, int params, const
|
||||
argbuf[numbytes] = debug_read_opcode(pcbyte + numbytes, 1, TRUE);
|
||||
}
|
||||
|
||||
activecpu_dasm(buffer, pc, opbuf, argbuf);
|
||||
cpu_dasm(machine->activecpu, buffer, pc, opbuf, argbuf);
|
||||
|
||||
debug_console_printf("%0*X: %s\n", info->space[ADDRESS_SPACE_PROGRAM].logchars, pc, buffer);
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
@ -2059,7 +2059,7 @@ static void execute_source(running_machine *machine, int ref, int params, const
|
||||
|
||||
static void execute_map(running_machine *machine, int ref, int params, const char *param[])
|
||||
{
|
||||
UINT64 address, cpunum = cpu_getactivecpu();
|
||||
UINT64 address, cpunum = cpunum_get_active();
|
||||
const debug_cpu_info *info;
|
||||
int spacenum = ref;
|
||||
offs_t taddress;
|
||||
|
@ -21,6 +21,7 @@
|
||||
***************************************************************************/
|
||||
|
||||
#include "driver.h"
|
||||
#include "deprecat.h"
|
||||
#include "xmlfile.h"
|
||||
#include "debugcmt.h"
|
||||
#include "debugcpu.h"
|
||||
@ -300,14 +301,14 @@ UINT32 debug_comment_all_change_count(void)
|
||||
|
||||
UINT32 debug_comment_get_opcode_crc32(offs_t address)
|
||||
{
|
||||
const debug_cpu_info *info = debug_get_cpu_info(cpu_getactivecpu());
|
||||
const debug_cpu_info *info = debug_get_cpu_info(cpunum_get_active());
|
||||
int i;
|
||||
UINT32 crc;
|
||||
UINT8 opbuf[64], argbuf[64];
|
||||
char buff[256];
|
||||
offs_t numbytes;
|
||||
int maxbytes = activecpu_max_instruction_bytes();
|
||||
UINT32 addrmask = (debug_get_cpu_info(cpu_getactivecpu()))->space[ADDRESS_SPACE_PROGRAM].logaddrmask;
|
||||
int maxbytes = cpu_get_max_opcode_bytes(Machine->activecpu);
|
||||
UINT32 addrmask = (debug_get_cpu_info(cpunum_get_active()))->space[ADDRESS_SPACE_PROGRAM].logaddrmask;
|
||||
|
||||
memset(opbuf, 0x00, sizeof(opbuf));
|
||||
memset(argbuf, 0x00, sizeof(argbuf));
|
||||
@ -319,7 +320,7 @@ UINT32 debug_comment_get_opcode_crc32(offs_t address)
|
||||
argbuf[i] = debug_read_opcode(address + i, 1, TRUE);
|
||||
}
|
||||
|
||||
numbytes = activecpu_dasm(buff, address & addrmask, opbuf, argbuf) & DASMFLAG_LENGTHMASK;
|
||||
numbytes = cpu_dasm(Machine->activecpu, buff, address & addrmask, opbuf, argbuf) & DASMFLAG_LENGTHMASK;
|
||||
numbytes = ADDR2BYTE(numbytes, info, ADDRESS_SPACE_PROGRAM);
|
||||
|
||||
crc = crc32(0, argbuf, numbytes);
|
||||
|
@ -328,7 +328,7 @@ static CMDERR internal_parse_command(running_machine *machine, const char *origi
|
||||
if (isexpr && paramcount == 1)
|
||||
{
|
||||
UINT64 expresult;
|
||||
EXPRERR exprerr = expression_evaluate(command_start, debug_get_cpu_info(cpu_getactivecpu())->symtable, &debug_expression_callbacks, &expresult);
|
||||
EXPRERR exprerr = expression_evaluate(command_start, debug_get_cpu_info(cpunum_get_active())->symtable, &debug_expression_callbacks, &expresult);
|
||||
if (exprerr != EXPRERR_NONE)
|
||||
return MAKE_CMDERR_EXPRESSION_ERROR(EXPRERR_ERROR_OFFSET(exprerr));
|
||||
}
|
||||
|
@ -93,11 +93,11 @@ static debugger_private global;
|
||||
|
||||
static void debug_cpu_exit(running_machine *machine);
|
||||
static void perform_trace(running_machine *machine, debug_cpu_info *info);
|
||||
static void prepare_for_step_overout(debug_cpu_info *info);
|
||||
static void prepare_for_step_overout(running_machine *machine, debug_cpu_info *info);
|
||||
static void process_source_file(running_machine *machine);
|
||||
static void breakpoint_check(running_machine *machine, debug_cpu_info *info, offs_t pc);
|
||||
static void watchpoint_check(running_machine *machine, int cpunum, int spacenum, int type, offs_t address, UINT64 value_to_write, UINT64 mem_mask);
|
||||
static void check_hotspots(int cpunum, int spacenum, offs_t address);
|
||||
static void check_hotspots(running_machine *machine, int cpunum, int spacenum, offs_t address);
|
||||
|
||||
/* expression handlers */
|
||||
static UINT64 expression_read_memory(const char *name, int space, UINT32 address, int size);
|
||||
@ -226,25 +226,25 @@ void debug_cpu_init(running_machine *machine)
|
||||
/* reset the PC data */
|
||||
info->valid = TRUE;
|
||||
info->flags = DEBUG_FLAG_OBSERVING | DEBUG_FLAG_HISTORY;
|
||||
info->endianness = cpunum_endianness(cpunum);
|
||||
info->opwidth = cpunum_min_instruction_bytes(cpunum);
|
||||
info->endianness = cpu_get_endianness(machine->cpu[cpunum]);
|
||||
info->opwidth = cpu_get_min_opcode_bytes(machine->cpu[cpunum]);
|
||||
|
||||
/* fetch the memory accessors */
|
||||
info->translate = (cpu_translate_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_TRANSLATE);
|
||||
info->read = (cpu_read_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_READ);
|
||||
info->write = (cpu_write_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_WRITE);
|
||||
info->readop = (cpu_readop_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_READOP);
|
||||
info->translate = (cpu_translate_func)cpu_get_info_fct(machine->cpu[cpunum], CPUINFO_PTR_TRANSLATE);
|
||||
info->read = (cpu_read_func)cpu_get_info_fct(machine->cpu[cpunum], CPUINFO_PTR_READ);
|
||||
info->write = (cpu_write_func)cpu_get_info_fct(machine->cpu[cpunum], CPUINFO_PTR_WRITE);
|
||||
info->readop = (cpu_readop_func)cpu_get_info_fct(machine->cpu[cpunum], CPUINFO_PTR_READOP);
|
||||
|
||||
/* allocate a symbol table */
|
||||
info->symtable = symtable_alloc(global_symtable);
|
||||
|
||||
/* add a global symbol for the current instruction pointer */
|
||||
symtable_add_register(info->symtable, "curpc", NULL, get_current_pc, 0);
|
||||
symtable_add_register(info->symtable, "curpc", machine, get_current_pc, 0);
|
||||
|
||||
/* add all registers into it */
|
||||
for (regnum = 0; regnum < MAX_REGS; regnum++)
|
||||
{
|
||||
const char *str = cpunum_reg_string(cpunum, regnum);
|
||||
const char *str = cpu_get_reg_string(machine->cpu[cpunum], regnum);
|
||||
const char *colon;
|
||||
char symname[256];
|
||||
int charnum;
|
||||
@ -272,11 +272,11 @@ void debug_cpu_init(running_machine *machine)
|
||||
for (spacenum = 0; spacenum < ADDRESS_SPACES; spacenum++)
|
||||
{
|
||||
debug_space_info *spaceinfo = &info->space[spacenum];
|
||||
int datawidth = cpunum_databus_width(cpunum, spacenum);
|
||||
int logwidth = cpunum_logaddr_width(cpunum, spacenum);
|
||||
int physwidth = cpunum_addrbus_width(cpunum, spacenum);
|
||||
int addrshift = cpunum_addrbus_shift(cpunum, spacenum);
|
||||
int pageshift = cpunum_page_shift(cpunum, spacenum);
|
||||
int datawidth = cpu_get_databus_width(machine->cpu[cpunum], spacenum);
|
||||
int logwidth = cpu_get_logaddr_width(machine->cpu[cpunum], spacenum);
|
||||
int physwidth = cpu_get_addrbus_width(machine->cpu[cpunum], spacenum);
|
||||
int addrshift = cpu_get_addrbus_shift(machine->cpu[cpunum], spacenum);
|
||||
int pageshift = cpu_get_page_shift(machine->cpu[cpunum], spacenum);
|
||||
|
||||
if (logwidth == 0)
|
||||
logwidth = physwidth;
|
||||
@ -639,7 +639,7 @@ void debug_cpu_instruction_hook(running_machine *machine, offs_t curpc)
|
||||
|
||||
/* handle step out/over on the instruction we are about to execute */
|
||||
if ((info->flags & (DEBUG_FLAG_STEPPING_OVER | DEBUG_FLAG_STEPPING_OUT)) != 0 && info->stepaddr == ~0)
|
||||
prepare_for_step_overout(info);
|
||||
prepare_for_step_overout(machine, info);
|
||||
|
||||
/* no longer in debugger code */
|
||||
global.within_instruction_hook = FALSE;
|
||||
@ -662,7 +662,7 @@ void debug_cpu_memory_read_hook(running_machine *machine, int cpunum, int spacen
|
||||
|
||||
/* check hotspots */
|
||||
if (info->hotspots != NULL)
|
||||
check_hotspots(cpunum, spacenum, address);
|
||||
check_hotspots(machine, cpunum, spacenum, address);
|
||||
}
|
||||
|
||||
|
||||
@ -988,10 +988,10 @@ int debug_cpu_is_stopped(running_machine *machine)
|
||||
data for a given instruction
|
||||
-------------------------------------------------*/
|
||||
|
||||
static UINT32 dasm_wrapped(char *buffer, offs_t pc)
|
||||
static UINT32 dasm_wrapped(running_machine *machine, char *buffer, offs_t pc)
|
||||
{
|
||||
const debug_cpu_info *cpuinfo = debug_get_cpu_info(cpu_getactivecpu());
|
||||
int maxbytes = activecpu_max_instruction_bytes();
|
||||
const debug_cpu_info *cpuinfo = debug_get_cpu_info(cpunum_get_active());
|
||||
int maxbytes = cpu_get_max_opcode_bytes(machine->activecpu);
|
||||
UINT8 opbuf[64], argbuf[64];
|
||||
offs_t pcbyte;
|
||||
int numbytes;
|
||||
@ -1004,13 +1004,13 @@ static UINT32 dasm_wrapped(char *buffer, offs_t pc)
|
||||
argbuf[numbytes] = debug_read_opcode(pcbyte + numbytes, 1, TRUE);
|
||||
}
|
||||
|
||||
return activecpu_dasm(buffer, pc, opbuf, argbuf);
|
||||
return cpu_dasm(machine->activecpu, buffer, pc, opbuf, argbuf);
|
||||
}
|
||||
|
||||
|
||||
static void perform_trace(running_machine *machine, debug_cpu_info *info)
|
||||
{
|
||||
offs_t pc = activecpu_get_pc();
|
||||
offs_t pc = cpu_get_pc(machine->activecpu);
|
||||
int offset, count, i;
|
||||
char buffer[100];
|
||||
offs_t dasmresult;
|
||||
@ -1044,7 +1044,7 @@ static void perform_trace(running_machine *machine, debug_cpu_info *info)
|
||||
offset = sprintf(buffer, "%0*X: ", info->space[ADDRESS_SPACE_PROGRAM].logchars, pc);
|
||||
|
||||
/* print the disassembly */
|
||||
dasmresult = dasm_wrapped(&buffer[offset], pc);
|
||||
dasmresult = dasm_wrapped(machine, &buffer[offset], pc);
|
||||
|
||||
/* output the result */
|
||||
fprintf(info->trace.file, "%s\n", buffer);
|
||||
@ -1057,7 +1057,7 @@ static void perform_trace(running_machine *machine, debug_cpu_info *info)
|
||||
|
||||
/* if we need to skip additional instructions, advance as requested */
|
||||
while (extraskip-- > 0)
|
||||
trace_over_target += dasm_wrapped(buffer, trace_over_target) & DASMFLAG_LENGTHMASK;
|
||||
trace_over_target += dasm_wrapped(machine, buffer, trace_over_target) & DASMFLAG_LENGTHMASK;
|
||||
|
||||
info->trace.trace_over_target = trace_over_target;
|
||||
}
|
||||
@ -1078,14 +1078,14 @@ static void perform_trace(running_machine *machine, debug_cpu_info *info)
|
||||
stepping over an instruction
|
||||
-------------------------------------------------*/
|
||||
|
||||
static void prepare_for_step_overout(debug_cpu_info *info)
|
||||
static void prepare_for_step_overout(running_machine *machine, debug_cpu_info *info)
|
||||
{
|
||||
offs_t pc = activecpu_get_pc();
|
||||
offs_t pc = cpu_get_pc(machine->activecpu);
|
||||
char dasmbuffer[100];
|
||||
offs_t dasmresult;
|
||||
|
||||
/* disassemble the current instruction and get the flags */
|
||||
dasmresult = dasm_wrapped(dasmbuffer, pc);
|
||||
dasmresult = dasm_wrapped(machine, dasmbuffer, pc);
|
||||
|
||||
/* if flags are supported and it's a call-style opcode, set a temp breakpoint after that instruction */
|
||||
if ((dasmresult & DASMFLAG_SUPPORTED) != 0 && (dasmresult & DASMFLAG_STEP_OVER) != 0)
|
||||
@ -1095,7 +1095,7 @@ static void prepare_for_step_overout(debug_cpu_info *info)
|
||||
|
||||
/* if we need to skip additional instructions, advance as requested */
|
||||
while (extraskip-- > 0)
|
||||
pc += dasm_wrapped(dasmbuffer, pc) & DASMFLAG_LENGTHMASK;
|
||||
pc += dasm_wrapped(machine, dasmbuffer, pc) & DASMFLAG_LENGTHMASK;
|
||||
info->stepaddr = pc;
|
||||
}
|
||||
|
||||
@ -1454,14 +1454,14 @@ static void watchpoint_check(running_machine *machine, int cpunum, int spacenum,
|
||||
|
||||
if (type & WATCHPOINT_WRITE)
|
||||
{
|
||||
sprintf(buffer, "Stopped at watchpoint %X writing %s to %08X (PC=%X)", wp->index, sizes[size], BYTE2ADDR(address, &global.cpuinfo[cpunum], spacenum), activecpu_get_pc());
|
||||
sprintf(buffer, "Stopped at watchpoint %X writing %s to %08X (PC=%X)", wp->index, sizes[size], BYTE2ADDR(address, &global.cpuinfo[cpunum], spacenum), cpu_get_pc(machine->activecpu));
|
||||
if (value_to_write >> 32)
|
||||
sprintf(&buffer[strlen(buffer)], " (data=%X%08X)", (UINT32)(value_to_write >> 32), (UINT32)value_to_write);
|
||||
else
|
||||
sprintf(&buffer[strlen(buffer)], " (data=%X)", (UINT32)value_to_write);
|
||||
}
|
||||
else
|
||||
sprintf(buffer, "Stopped at watchpoint %X reading %s from %08X (PC=%X)", wp->index, sizes[size], BYTE2ADDR(address, &global.cpuinfo[cpunum], spacenum), activecpu_get_pc());
|
||||
sprintf(buffer, "Stopped at watchpoint %X reading %s from %08X (PC=%X)", wp->index, sizes[size], BYTE2ADDR(address, &global.cpuinfo[cpunum], spacenum), cpu_get_pc(machine->activecpu));
|
||||
debug_console_printf("%s\n", buffer);
|
||||
compute_debug_flags(machine, info);
|
||||
}
|
||||
@ -1615,10 +1615,10 @@ int debug_cpu_hotspot_track(running_machine *machine, int cpunum, int numspots,
|
||||
hotspots on a memory read access
|
||||
-------------------------------------------------*/
|
||||
|
||||
static void check_hotspots(int cpunum, int spacenum, offs_t address)
|
||||
static void check_hotspots(running_machine *machine, int cpunum, int spacenum, offs_t address)
|
||||
{
|
||||
debug_cpu_info *info = &global.cpuinfo[cpunum];
|
||||
offs_t pc = activecpu_get_pc();
|
||||
offs_t pc = cpu_get_pc(machine->activecpu);
|
||||
int hotindex;
|
||||
|
||||
/* see if we have a match in our list */
|
||||
@ -1667,7 +1667,7 @@ static void check_hotspots(int cpunum, int spacenum, offs_t address)
|
||||
|
||||
UINT8 debug_read_byte(int spacenum, offs_t address, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
UINT64 custom;
|
||||
UINT8 result;
|
||||
|
||||
@ -1702,7 +1702,7 @@ UINT8 debug_read_byte(int spacenum, offs_t address, int apply_translation)
|
||||
|
||||
UINT16 debug_read_word(int spacenum, offs_t address, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
UINT64 custom;
|
||||
UINT16 result;
|
||||
|
||||
@ -1716,7 +1716,7 @@ UINT16 debug_read_word(int spacenum, offs_t address, int apply_translation)
|
||||
UINT8 byte1 = debug_read_byte(spacenum, address + 1, apply_translation);
|
||||
|
||||
/* based on the endianness, the result is assembled differently */
|
||||
if (global.cpuinfo[cpu_getactivecpu()].endianness == CPU_IS_LE)
|
||||
if (global.cpuinfo[cpunum_get_active()].endianness == CPU_IS_LE)
|
||||
result = byte0 | (byte1 << 8);
|
||||
else
|
||||
result = byte1 | (byte0 << 8);
|
||||
@ -1755,7 +1755,7 @@ UINT16 debug_read_word(int spacenum, offs_t address, int apply_translation)
|
||||
|
||||
UINT32 debug_read_dword(int spacenum, offs_t address, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
UINT64 custom;
|
||||
UINT32 result;
|
||||
|
||||
@ -1769,7 +1769,7 @@ UINT32 debug_read_dword(int spacenum, offs_t address, int apply_translation)
|
||||
UINT16 word1 = debug_read_word(spacenum, address + 2, apply_translation);
|
||||
|
||||
/* based on the endianness, the result is assembled differently */
|
||||
if (global.cpuinfo[cpu_getactivecpu()].endianness == CPU_IS_LE)
|
||||
if (global.cpuinfo[cpunum_get_active()].endianness == CPU_IS_LE)
|
||||
result = word0 | (word1 << 16);
|
||||
else
|
||||
result = word1 | (word0 << 16);
|
||||
@ -1808,7 +1808,7 @@ UINT32 debug_read_dword(int spacenum, offs_t address, int apply_translation)
|
||||
|
||||
UINT64 debug_read_qword(int spacenum, offs_t address, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
UINT64 custom;
|
||||
UINT64 result;
|
||||
|
||||
@ -1822,7 +1822,7 @@ UINT64 debug_read_qword(int spacenum, offs_t address, int apply_translation)
|
||||
UINT32 dword1 = debug_read_dword(spacenum, address + 4, apply_translation);
|
||||
|
||||
/* based on the endianness, the result is assembled differently */
|
||||
if (global.cpuinfo[cpu_getactivecpu()].endianness == CPU_IS_LE)
|
||||
if (global.cpuinfo[cpunum_get_active()].endianness == CPU_IS_LE)
|
||||
result = dword0 | ((UINT64)dword1 << 32);
|
||||
else
|
||||
result = dword1 | ((UINT64)dword0 << 32);
|
||||
@ -1861,7 +1861,7 @@ UINT64 debug_read_qword(int spacenum, offs_t address, int apply_translation)
|
||||
|
||||
void debug_write_byte(int spacenum, offs_t address, UINT8 data, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
|
||||
/* mask against the logical byte mask */
|
||||
address &= info->space[spacenum].logbytemask;
|
||||
@ -1894,7 +1894,7 @@ void debug_write_byte(int spacenum, offs_t address, UINT8 data, int apply_transl
|
||||
|
||||
void debug_write_word(int spacenum, offs_t address, UINT16 data, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
|
||||
/* mask against the logical byte mask */
|
||||
address &= info->space[spacenum].logbytemask;
|
||||
@ -1902,7 +1902,7 @@ void debug_write_word(int spacenum, offs_t address, UINT16 data, int apply_trans
|
||||
/* if this is a misaligned write, or if there are no word writers, just read two bytes */
|
||||
if ((address & 1) || !active_address_space[spacenum].accessors->write_word)
|
||||
{
|
||||
if (global.cpuinfo[cpu_getactivecpu()].endianness == CPU_IS_LE)
|
||||
if (global.cpuinfo[cpunum_get_active()].endianness == CPU_IS_LE)
|
||||
{
|
||||
debug_write_byte(spacenum, address + 0, data >> 0, apply_translation);
|
||||
debug_write_byte(spacenum, address + 1, data >> 8, apply_translation);
|
||||
@ -1946,7 +1946,7 @@ void debug_write_word(int spacenum, offs_t address, UINT16 data, int apply_trans
|
||||
|
||||
void debug_write_dword(int spacenum, offs_t address, UINT32 data, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
|
||||
/* mask against the logical byte mask */
|
||||
address &= info->space[spacenum].logbytemask;
|
||||
@ -1954,7 +1954,7 @@ void debug_write_dword(int spacenum, offs_t address, UINT32 data, int apply_tran
|
||||
/* if this is a misaligned write, or if there are no dword writers, just read two words */
|
||||
if ((address & 3) || !active_address_space[spacenum].accessors->write_dword)
|
||||
{
|
||||
if (global.cpuinfo[cpu_getactivecpu()].endianness == CPU_IS_LE)
|
||||
if (global.cpuinfo[cpunum_get_active()].endianness == CPU_IS_LE)
|
||||
{
|
||||
debug_write_word(spacenum, address + 0, data >> 0, apply_translation);
|
||||
debug_write_word(spacenum, address + 2, data >> 16, apply_translation);
|
||||
@ -1998,7 +1998,7 @@ void debug_write_dword(int spacenum, offs_t address, UINT32 data, int apply_tran
|
||||
|
||||
void debug_write_qword(int spacenum, offs_t address, UINT64 data, int apply_translation)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
|
||||
/* mask against the logical byte mask */
|
||||
address &= info->space[spacenum].logbytemask;
|
||||
@ -2006,7 +2006,7 @@ void debug_write_qword(int spacenum, offs_t address, UINT64 data, int apply_tran
|
||||
/* if this is a misaligned write, or if there are no qword writers, just read two dwords */
|
||||
if ((address & 7) || !active_address_space[spacenum].accessors->write_qword)
|
||||
{
|
||||
if (global.cpuinfo[cpu_getactivecpu()].endianness == CPU_IS_LE)
|
||||
if (global.cpuinfo[cpunum_get_active()].endianness == CPU_IS_LE)
|
||||
{
|
||||
debug_write_dword(spacenum, address + 0, data >> 0, apply_translation);
|
||||
debug_write_dword(spacenum, address + 4, data >> 32, apply_translation);
|
||||
@ -2049,7 +2049,7 @@ void debug_write_qword(int spacenum, offs_t address, UINT64 data, int apply_tran
|
||||
|
||||
UINT64 debug_read_opcode(offs_t address, int size, int arg)
|
||||
{
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpu_getactivecpu()];
|
||||
const debug_cpu_info *info = &global.cpuinfo[cpunum_get_active()];
|
||||
offs_t lowbits_mask;
|
||||
const void *ptr;
|
||||
|
||||
@ -2143,14 +2143,14 @@ UINT64 debug_read_opcode(offs_t address, int size, int arg)
|
||||
/* get pointer to data */
|
||||
/* note that we query aligned to the bus width, and then add back the low bits */
|
||||
lowbits_mask = info->space[ADDRESS_SPACE_PROGRAM].databytes - 1;
|
||||
ptr = memory_get_op_ptr(Machine, cpu_getactivecpu(), address & ~lowbits_mask, arg);
|
||||
ptr = memory_get_op_ptr(Machine, cpunum_get_active(), address & ~lowbits_mask, arg);
|
||||
if (!ptr)
|
||||
return ~(UINT64)0 & (~(UINT64)0 >> (64 - 8*size));
|
||||
ptr = (UINT8 *)ptr + (address & lowbits_mask);
|
||||
|
||||
/* gross! */
|
||||
// if (osd_is_bad_read_ptr(ptr, size))
|
||||
// fatalerror("debug_read_opcode: cpu %d address %x mapped to invalid memory %p", cpu_getactivecpu(), address, ptr);
|
||||
// fatalerror("debug_read_opcode: cpu %d address %x mapped to invalid memory %p", cpunum_get_active(), address, ptr);
|
||||
|
||||
/* return based on the size */
|
||||
switch (size)
|
||||
@ -2197,18 +2197,18 @@ static UINT64 expression_read_memory(const char *name, int space, UINT32 address
|
||||
case EXPSPACE_PROGRAM:
|
||||
case EXPSPACE_DATA:
|
||||
case EXPSPACE_IO:
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpu_getactivecpu();
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpunum_get_active();
|
||||
if (cpuindex < 0)
|
||||
break;
|
||||
return expression_read_address_space(cpuindex, ADDRESS_SPACE_PROGRAM + (space - EXPSPACE_PROGRAM), address, size);
|
||||
|
||||
case EXPSPACE_OPCODE:
|
||||
case EXPSPACE_RAMWRITE:
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpu_getactivecpu();
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpunum_get_active();
|
||||
if (cpuindex < 0)
|
||||
break;
|
||||
if (name == NULL)
|
||||
name = Machine->config->cpu[cpu_getactivecpu()].tag;
|
||||
name = Machine->config->cpu[cpunum_get_active()].tag;
|
||||
return expression_read_program_direct(cpuindex, (space == EXPSPACE_OPCODE), address, size);
|
||||
|
||||
case EXPSPACE_EEPROM:
|
||||
@ -2240,7 +2240,7 @@ static UINT64 expression_read_address_space(int cpuindex, int space, offs_t addr
|
||||
address = ADDR2BYTE(address, info, space);
|
||||
|
||||
/* switch contexts and do the read */
|
||||
cpuintrf_push_context(cpuindex);
|
||||
cpu_push_context(Machine->cpu[cpuindex]);
|
||||
switch (size)
|
||||
{
|
||||
case 1: result = debug_read_byte(space, address, TRUE); break;
|
||||
@ -2248,7 +2248,7 @@ static UINT64 expression_read_address_space(int cpuindex, int space, offs_t addr
|
||||
case 4: result = debug_read_dword(space, address, TRUE); break;
|
||||
case 8: result = debug_read_qword(space, address, TRUE); break;
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
return result;
|
||||
}
|
||||
@ -2406,7 +2406,7 @@ static void expression_write_memory(const char *name, int space, UINT32 address,
|
||||
case EXPSPACE_PROGRAM:
|
||||
case EXPSPACE_DATA:
|
||||
case EXPSPACE_IO:
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpu_getactivecpu();
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpunum_get_active();
|
||||
if (cpuindex < 0)
|
||||
break;
|
||||
expression_write_address_space(cpuindex, ADDRESS_SPACE_PROGRAM + (space - EXPSPACE_PROGRAM), address, size, data);
|
||||
@ -2414,7 +2414,7 @@ static void expression_write_memory(const char *name, int space, UINT32 address,
|
||||
|
||||
case EXPSPACE_OPCODE:
|
||||
case EXPSPACE_RAMWRITE:
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpu_getactivecpu();
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpunum_get_active();
|
||||
if (cpuindex < 0)
|
||||
break;
|
||||
expression_write_program_direct(cpuindex, (space == EXPSPACE_OPCODE), address, size, data);
|
||||
@ -2449,7 +2449,7 @@ static void expression_write_address_space(int cpuindex, int space, offs_t addre
|
||||
address = ADDR2BYTE(address, info, space);
|
||||
|
||||
/* switch contexts and do the write */
|
||||
cpuintrf_push_context(cpuindex);
|
||||
cpu_push_context(Machine->cpu[cpuindex]);
|
||||
switch (size)
|
||||
{
|
||||
case 1: debug_write_byte(space, address, data, TRUE); break;
|
||||
@ -2457,7 +2457,7 @@ static void expression_write_address_space(int cpuindex, int space, offs_t addre
|
||||
case 4: debug_write_dword(space, address, data, TRUE); break;
|
||||
case 8: debug_write_qword(space, address, data, TRUE); break;
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
}
|
||||
|
||||
@ -2639,16 +2639,16 @@ static EXPRERR expression_validate(const char *name, int space)
|
||||
case EXPSPACE_PROGRAM:
|
||||
case EXPSPACE_DATA:
|
||||
case EXPSPACE_IO:
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpu_getactivecpu();
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpunum_get_active();
|
||||
if (cpuindex < 0)
|
||||
return (name == NULL) ? EXPRERR_MISSING_MEMORY_NAME : EXPRERR_INVALID_MEMORY_NAME;
|
||||
if (cpunum_addrbus_width(cpuindex, ADDRESS_SPACE_PROGRAM + (space - EXPSPACE_PROGRAM)) == 0)
|
||||
if (cpu_get_addrbus_width(Machine->cpu[cpuindex], ADDRESS_SPACE_PROGRAM + (space - EXPSPACE_PROGRAM)) == 0)
|
||||
return EXPRERR_NO_SUCH_MEMORY_SPACE;
|
||||
break;
|
||||
|
||||
case EXPSPACE_OPCODE:
|
||||
case EXPSPACE_RAMWRITE:
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpu_getactivecpu();
|
||||
cpuindex = (name != NULL) ? expression_cpu_index(Machine, name) : cpunum_get_active();
|
||||
if (cpuindex < 0)
|
||||
return (name == NULL) ? EXPRERR_MISSING_MEMORY_NAME : EXPRERR_INVALID_MEMORY_NAME;
|
||||
break;
|
||||
@ -2778,7 +2778,7 @@ static UINT64 get_cycles(void *ref)
|
||||
|
||||
static UINT64 get_cpunum(void *ref)
|
||||
{
|
||||
return cpu_getactivecpu();
|
||||
return cpunum_get_active();
|
||||
}
|
||||
|
||||
|
||||
@ -2881,7 +2881,8 @@ static void set_logunmap(void *ref, UINT64 value)
|
||||
|
||||
static UINT64 get_current_pc(void *ref)
|
||||
{
|
||||
return activecpu_get_pc();
|
||||
running_machine *machine = ref;
|
||||
return cpu_get_pc(machine->activecpu);
|
||||
}
|
||||
|
||||
|
||||
@ -2892,7 +2893,7 @@ static UINT64 get_current_pc(void *ref)
|
||||
|
||||
static UINT64 get_cpu_reg(void *ref)
|
||||
{
|
||||
return activecpu_get_reg((FPTR)ref);
|
||||
return cpu_get_reg(Machine->activecpu, (FPTR)ref);
|
||||
}
|
||||
|
||||
|
||||
@ -2903,5 +2904,5 @@ static UINT64 get_cpu_reg(void *ref)
|
||||
|
||||
static void set_cpu_reg(void *ref, UINT64 value)
|
||||
{
|
||||
activecpu_set_reg((FPTR)ref, value);
|
||||
cpu_set_reg(Machine->activecpu, (FPTR)ref, value);
|
||||
}
|
||||
|
@ -951,7 +951,7 @@ static void add_register(debug_view *view, int regnum, const char *str)
|
||||
|
||||
/* note the register number and info */
|
||||
regdata->reg[view->total_rows].lastval =
|
||||
regdata->reg[view->total_rows].currval = cpunum_get_reg(regdata->cpunum, regnum);
|
||||
regdata->reg[view->total_rows].currval = cpu_get_reg(Machine->cpu[regdata->cpunum], regnum);
|
||||
regdata->reg[view->total_rows].regnum = regnum;
|
||||
regdata->reg[view->total_rows].tagstart = tagstart;
|
||||
regdata->reg[view->total_rows].taglen = taglen;
|
||||
@ -973,7 +973,7 @@ static void add_register(debug_view *view, int regnum, const char *str)
|
||||
static void registers_recompute(debug_view *view)
|
||||
{
|
||||
debug_view_registers *regdata = view->extra_data;
|
||||
const int *list = cpunum_debug_register_list(regdata->cpunum);
|
||||
const int *list = cpu_get_debug_register_list(Machine->cpu[regdata->cpunum]);
|
||||
int regnum, maxtaglen, maxvallen;
|
||||
|
||||
/* reset the view parameters */
|
||||
@ -1026,7 +1026,7 @@ static void registers_recompute(debug_view *view)
|
||||
regdata->reg[view->total_rows].tagstart = 0;
|
||||
regdata->reg[view->total_rows].taglen = 5;
|
||||
regdata->reg[view->total_rows].valstart = 6;
|
||||
regdata->reg[view->total_rows].vallen = (UINT32)strlen(cpunum_flags(regdata->cpunum));
|
||||
regdata->reg[view->total_rows].vallen = (UINT32)strlen(cpu_get_flags_string(Machine->cpu[regdata->cpunum]));
|
||||
maxtaglen = MAX(maxtaglen, regdata->reg[view->total_rows].taglen);
|
||||
maxvallen = MAX(maxvallen, regdata->reg[view->total_rows].vallen);
|
||||
view->total_rows++;
|
||||
@ -1053,7 +1053,7 @@ static void registers_recompute(debug_view *view)
|
||||
break;
|
||||
|
||||
/* retrieve the string for this register */
|
||||
str = cpunum_reg_string(regdata->cpunum, regid);
|
||||
str = cpu_get_reg_string(Machine->cpu[regdata->cpunum], regid);
|
||||
|
||||
/* did we get a string? */
|
||||
if (str && str[0] != '\0' && str[0] != '~')
|
||||
@ -1079,7 +1079,7 @@ static void registers_update(debug_view *view)
|
||||
const device_config *screen = Machine->primary_screen;
|
||||
|
||||
/* cannot update if no active CPU */
|
||||
if (cpu_getactivecpu() < 0)
|
||||
if (cpunum_get_active() < 0)
|
||||
return;
|
||||
total_cycles = activecpu_gettotalcycles();
|
||||
|
||||
@ -1134,16 +1134,16 @@ static void registers_update(debug_view *view)
|
||||
break;
|
||||
|
||||
case MAX_REGS + 4:
|
||||
sprintf(dummy, "flags:%s", activecpu_flags());
|
||||
sprintf(dummy, "flags:%s", cpu_get_flags_string(Machine->activecpu));
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
data = (char *)cpunum_reg_string(regdata->cpunum, reg->regnum);
|
||||
data = (char *)cpu_get_reg_string(Machine->cpu[regdata->cpunum], reg->regnum);
|
||||
if (regdata->last_update != total_cycles)
|
||||
reg->lastval = reg->currval;
|
||||
reg->currval = cpunum_get_reg(regdata->cpunum, reg->regnum);
|
||||
reg->currval = cpu_get_reg(Machine->cpu[regdata->cpunum], reg->regnum);
|
||||
}
|
||||
|
||||
/* see if we changed */
|
||||
@ -1324,8 +1324,8 @@ static void disasm_free(debug_view *view)
|
||||
|
||||
static offs_t disasm_back_up(int cpunum, const debug_cpu_info *cpuinfo, offs_t startpc, int numinstrs)
|
||||
{
|
||||
int minlen = BYTE2ADDR(activecpu_min_instruction_bytes(), cpuinfo, ADDRESS_SPACE_PROGRAM);
|
||||
int maxlen = BYTE2ADDR(activecpu_max_instruction_bytes(), cpuinfo, ADDRESS_SPACE_PROGRAM);
|
||||
int minlen = BYTE2ADDR(cpu_get_min_opcode_bytes(Machine->activecpu), cpuinfo, ADDRESS_SPACE_PROGRAM);
|
||||
int maxlen = BYTE2ADDR(cpu_get_max_opcode_bytes(Machine->activecpu), cpuinfo, ADDRESS_SPACE_PROGRAM);
|
||||
UINT32 addrmask = cpuinfo->space[ADDRESS_SPACE_PROGRAM].logaddrmask;
|
||||
offs_t curpc, lastgoodpc = startpc, temppc;
|
||||
UINT8 opbuf[1024], argbuf[1024];
|
||||
@ -1361,7 +1361,7 @@ static offs_t disasm_back_up(int cpunum, const debug_cpu_info *cpuinfo, offs_t s
|
||||
/* get the disassembly, but only if mapped */
|
||||
instlen = 1;
|
||||
if (cpuinfo->translate == NULL || (*cpuinfo->translate)(ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH_DEBUG, &pcbyte))
|
||||
instlen = activecpu_dasm(dasmbuffer, testpc & addrmask, &opbuf[1000 + testpc - startpc], &argbuf[1000 + testpc - startpc]) & DASMFLAG_LENGTHMASK;
|
||||
instlen = cpu_dasm(Machine->activecpu, dasmbuffer, testpc & addrmask, &opbuf[1000 + testpc - startpc], &argbuf[1000 + testpc - startpc]) & DASMFLAG_LENGTHMASK;
|
||||
|
||||
/* count this one */
|
||||
instcount++;
|
||||
@ -1480,13 +1480,13 @@ static int disasm_recompute(debug_view *view, offs_t pc, int startline, int line
|
||||
dasmdata->divider2 = dasmdata->divider1 + 1 + dasmdata->dasm_width + 1;
|
||||
|
||||
/* determine how many bytes we might need to display */
|
||||
minbytes = activecpu_min_instruction_bytes();
|
||||
maxbytes = activecpu_max_instruction_bytes();
|
||||
minbytes = cpu_get_min_opcode_bytes(Machine->activecpu);
|
||||
maxbytes = cpu_get_max_opcode_bytes(Machine->activecpu);
|
||||
|
||||
/* set the width of the third column according to display mode */
|
||||
if (dasmdata->right_column == DVP_DASM_RIGHTCOL_RAW || dasmdata->right_column == DVP_DASM_RIGHTCOL_ENCRYPTED)
|
||||
{
|
||||
chunksize = activecpu_databus_width(ADDRESS_SPACE_PROGRAM) / 8;
|
||||
chunksize = cpu_get_databus_width(Machine->activecpu, ADDRESS_SPACE_PROGRAM) / 8;
|
||||
maxbytes_clamped = maxbytes;
|
||||
if (maxbytes_clamped > DASM_MAX_BYTES)
|
||||
maxbytes_clamped = DASM_MAX_BYTES;
|
||||
@ -1550,7 +1550,7 @@ static int disasm_recompute(debug_view *view, offs_t pc, int startline, int line
|
||||
}
|
||||
|
||||
/* disassemble the result */
|
||||
pc += numbytes = activecpu_dasm(buffer, pc & addrmask, opbuf, argbuf) & DASMFLAG_LENGTHMASK;
|
||||
pc += numbytes = cpu_dasm(Machine->activecpu, buffer, pc & addrmask, opbuf, argbuf) & DASMFLAG_LENGTHMASK;
|
||||
}
|
||||
else
|
||||
sprintf(buffer, "<unmapped>");
|
||||
@ -1568,7 +1568,7 @@ static int disasm_recompute(debug_view *view, offs_t pc, int startline, int line
|
||||
offs_t comment_address = BYTE2ADDR(dasmdata->address[instr], cpuinfo, ADDRESS_SPACE_PROGRAM) ;
|
||||
|
||||
/* get and add the comment */
|
||||
if (debug_comment_get_text(cpu_getactivecpu(), comment_address, debug_comment_get_opcode_crc32(comment_address)) != 0x00)
|
||||
if (debug_comment_get_text(cpunum_get_active(), comment_address, debug_comment_get_opcode_crc32(comment_address)) != 0x00)
|
||||
{
|
||||
int i ;
|
||||
char bob[DEBUG_COMMENT_MAX_LINE_LENGTH] ;
|
||||
@ -1580,7 +1580,7 @@ static int disasm_recompute(debug_view *view, offs_t pc, int startline, int line
|
||||
destbuf[dasmdata->divider2+i] = pre[i] ;
|
||||
|
||||
// Stick in the comment itself
|
||||
strcpy(bob, debug_comment_get_text(cpu_getactivecpu(), comment_address, debug_comment_get_opcode_crc32(comment_address))) ;
|
||||
strcpy(bob, debug_comment_get_text(cpunum_get_active(), comment_address, debug_comment_get_opcode_crc32(comment_address))) ;
|
||||
for (i = 0; i < (dasmdata->allocated_cols - dasmdata->divider2 - strlen(pre) - 1); i++)
|
||||
destbuf[dasmdata->divider2+i+strlen(pre)] = bob[i] ;
|
||||
}
|
||||
@ -1595,7 +1595,7 @@ static int disasm_recompute(debug_view *view, offs_t pc, int startline, int line
|
||||
|
||||
/* reset the opcode base */
|
||||
if (dasmdata->cpunum == original_cpunum)
|
||||
memory_set_opbase(activecpu_get_physical_pc_byte());
|
||||
memory_set_opbase(cpu_get_physical_pc_byte(Machine->activecpu));
|
||||
|
||||
/* update opcode base information */
|
||||
dasmdata->last_opbase_rom = opbase.rom;
|
||||
@ -1618,16 +1618,16 @@ static void disasm_update(debug_view *view)
|
||||
extern opbase_data opbase;
|
||||
debug_view_disasm *dasmdata = view->extra_data;
|
||||
const debug_cpu_info *cpuinfo = debug_get_cpu_info(dasmdata->cpunum);
|
||||
offs_t pc = cpunum_get_reg(dasmdata->cpunum, REG_PC);
|
||||
offs_t pc = cpu_get_reg(Machine->cpu[dasmdata->cpunum], REG_PC);
|
||||
offs_t pcbyte = ADDR2BYTE_MASKED(pc, cpuinfo, ADDRESS_SPACE_PROGRAM);
|
||||
debug_view_char *dest = view->viewdata;
|
||||
int original_cpunum = cpu_getactivecpu();
|
||||
int original_cpunum = cpunum_get_active();
|
||||
int recomputed_this_time = FALSE;
|
||||
EXPRERR exprerr;
|
||||
UINT32 row;
|
||||
|
||||
/* switch to the CPU's context */
|
||||
cpuintrf_push_context(dasmdata->cpunum);
|
||||
cpu_push_context(Machine->cpu[dasmdata->cpunum]);
|
||||
|
||||
/* if our expression is dirty, fix it */
|
||||
if (dasmdata->expression_dirty && dasmdata->expression_string)
|
||||
@ -1803,7 +1803,7 @@ recompute:
|
||||
}
|
||||
|
||||
/* restore the original CPU context */
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
@ -1851,7 +1851,7 @@ static void disasm_handle_char(debug_view *view, char chval)
|
||||
case DCH_HOME: /* set the active column to the PC */
|
||||
{
|
||||
const debug_cpu_info *cpuinfo = debug_get_cpu_info(dasmdata->cpunum);
|
||||
offs_t pc = cpunum_get_reg(dasmdata->cpunum, REG_PC);
|
||||
offs_t pc = cpu_get_reg(Machine->cpu[dasmdata->cpunum], REG_PC);
|
||||
int i;
|
||||
|
||||
pc = ADDR2BYTE_MASKED(pc, cpuinfo, ADDRESS_SPACE_PROGRAM);
|
||||
@ -2380,7 +2380,7 @@ static void memory_write_byte(debug_view_memory *memdata, offs_t offs, UINT8 dat
|
||||
|
||||
/* hack for FD1094 editing */
|
||||
#ifdef FD1094_HACK
|
||||
if (memdata->raw_base == memory_region(machine, "user2"))
|
||||
if (memdata->raw_base == memory_region(Machine, "user2"))
|
||||
{
|
||||
extern void fd1094_regenerate_key(void);
|
||||
fd1094_regenerate_key();
|
||||
@ -2558,7 +2558,7 @@ static void memory_handle_char(debug_view *view, char chval)
|
||||
}
|
||||
|
||||
/* switch off of the current chunk size */
|
||||
cpuintrf_push_context(memdata->cpunum);
|
||||
cpu_push_context(Machine->cpu[memdata->cpunum]);
|
||||
switch (memdata->bytes_per_chunk)
|
||||
{
|
||||
default:
|
||||
@ -2622,7 +2622,7 @@ static void memory_handle_char(debug_view *view, char chval)
|
||||
}
|
||||
break;
|
||||
}
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
|
||||
/* set a new position */
|
||||
memory_set_cursor_pos(view, address, shift);
|
||||
@ -2650,7 +2650,7 @@ static void memory_update(debug_view *view)
|
||||
|
||||
/* switch to the CPU's context */
|
||||
if (memdata->raw_base == NULL)
|
||||
cpuintrf_push_context(memdata->cpunum);
|
||||
cpu_push_context(Machine->cpu[memdata->cpunum]);
|
||||
|
||||
/* determine maximum address and number of characters for that */
|
||||
if (memdata->raw_base != NULL)
|
||||
@ -2949,7 +2949,7 @@ static void memory_update(debug_view *view)
|
||||
|
||||
/* restore the context */
|
||||
if (memdata->raw_base == NULL)
|
||||
cpuintrf_pop_context();
|
||||
cpu_pop_context();
|
||||
}
|
||||
|
||||
|
||||
|
@ -82,7 +82,7 @@ INLINE void debugger_stop_cpu_hook(running_machine *machine, int cpunum)
|
||||
INLINE void debugger_break(running_machine *machine)
|
||||
{
|
||||
if ((machine->debug_flags & DEBUG_FLAG_ENABLED) != 0)
|
||||
debug_cpu_halt_on_next_instruction(machine, cpu_getactivecpu(), "Internal breakpoint\n");
|
||||
debug_cpu_halt_on_next_instruction(machine, cpunum_get_active(), "Internal breakpoint\n");
|
||||
}
|
||||
|
||||
|
||||
|
@ -193,6 +193,7 @@ struct _device_config
|
||||
/* these fields are only valid if the device is live */
|
||||
UINT8 started; /* TRUE if the start function has succeeded */
|
||||
void * token; /* token if device is live */
|
||||
void * classtoken; /* class token if device is live */
|
||||
running_machine * machine; /* machine if device is live */
|
||||
UINT8 * region; /* pointer to region with the device's tag, or NULL */
|
||||
UINT32 regionbytes; /* size of the region, in bytes */
|
||||
|
@ -446,7 +446,7 @@ static void dma_exec(void)
|
||||
|
||||
READ8_HANDLER( lsi53c810_reg_r )
|
||||
{
|
||||
logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, activecpu_get_pc());
|
||||
logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, cpu_get_pc(machine->activecpu));
|
||||
switch(offset)
|
||||
{
|
||||
case 0x00: /* SCNTL0 */
|
||||
@ -527,7 +527,7 @@ READ8_HANDLER( lsi53c810_reg_r )
|
||||
|
||||
WRITE8_HANDLER( lsi53c810_reg_w )
|
||||
{
|
||||
logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, activecpu_get_pc());
|
||||
logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, cpu_get_pc(machine->activecpu));
|
||||
switch(offset)
|
||||
{
|
||||
case 0x00: /* SCNTL0 */
|
||||
|
@ -177,7 +177,7 @@ static void via_set_int (running_machine *machine, int which, int data)
|
||||
|
||||
v->ifr |= data;
|
||||
#ifdef TRACE_VIA
|
||||
logerror("6522VIA chip %d: IFR = %02X. PC: %08X\n", which, v->ifr, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: IFR = %02X. PC: %08X\n", which, v->ifr, safe_cpu_get_pc(machine->activecpu));
|
||||
#endif
|
||||
|
||||
if (v->ier & v->ifr)
|
||||
@ -186,7 +186,7 @@ logerror("6522VIA chip %d: IFR = %02X. PC: %08X\n", which, v->ifr, safe_activec
|
||||
if (v->intf->irq_func)
|
||||
(*v->intf->irq_func)(machine, ASSERT_LINE);
|
||||
else
|
||||
logerror("6522VIA chip %d: Interrupt is asserted but there is no callback function. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Interrupt is asserted but there is no callback function. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
}
|
||||
|
||||
@ -197,7 +197,7 @@ static void via_clear_int (running_machine *machine, int which, int data)
|
||||
|
||||
v->ifr = (v->ifr & ~data) & 0x7f;
|
||||
#ifdef TRACE_VIA
|
||||
logerror("6522VIA chip %d: IFR = %02X. PC: %08X\n", which, v->ifr, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: IFR = %02X. PC: %08X\n", which, v->ifr, safe_cpu_get_pc(machine->activecpu));
|
||||
#endif
|
||||
|
||||
if (v->ifr & v->ier)
|
||||
@ -207,7 +207,7 @@ logerror("6522VIA chip %d: IFR = %02X. PC: %08X\n", which, v->ifr, safe_activec
|
||||
if (v->intf->irq_func)
|
||||
(*v->intf->irq_func)(machine, CLEAR_LINE);
|
||||
// else
|
||||
// logerror("6522VIA chip %d: Interrupt is cleared but there is no callback function. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
// logerror("6522VIA chip %d: Interrupt is cleared but there is no callback function. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
}
|
||||
|
||||
@ -338,7 +338,7 @@ static TIMER_CALLBACK( via_t1_timeout )
|
||||
if (v->intf->out_b_func)
|
||||
v->intf->out_b_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
|
||||
if (!(v->ifr & INT_T1))
|
||||
@ -404,7 +404,7 @@ int via_read(running_machine *machine, int which, int offset)
|
||||
if (v->intf->in_b_func)
|
||||
v->in_b = v->intf->in_b_func(machine, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port B is being read but has no handler. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Port B is being read but has no handler. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
|
||||
CLR_PB_INT(v, which);
|
||||
@ -423,7 +423,7 @@ int via_read(running_machine *machine, int which, int offset)
|
||||
if (v->intf->in_a_func)
|
||||
v->in_a = v->intf->in_a_func(machine, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port A is being read but has no handler. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Port A is being read but has no handler. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
|
||||
/* combine input and output values */
|
||||
@ -444,7 +444,7 @@ int via_read(running_machine *machine, int which, int offset)
|
||||
if (v->intf->out_ca2_func)
|
||||
v->intf->out_ca2_func(machine, 0, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), 0);
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -457,7 +457,7 @@ int via_read(running_machine *machine, int which, int offset)
|
||||
if (v->intf->in_a_func)
|
||||
v->in_a = v->intf->in_a_func(machine, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port A is being read but has no handler. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Port A is being read but has no handler. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
|
||||
/* combine input and output values */
|
||||
@ -567,7 +567,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_b_func)
|
||||
v->intf->out_b_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
|
||||
CLR_PB_INT(v, which);
|
||||
@ -585,7 +585,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_cb2_func)
|
||||
v->intf->out_cb2_func(machine, 0, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CB2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), 0);
|
||||
logerror("6522VIA chip %d: Port CB2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), 0);
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -600,7 +600,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_a_func)
|
||||
v->intf->out_a_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port A is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port A is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
|
||||
CLR_PA_INT(v, which);
|
||||
@ -616,7 +616,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
v->intf->out_ca2_func(machine, 0, 1);
|
||||
}
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CA2 is being pulsed but has no handler. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Port CA2 is being pulsed but has no handler. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
|
||||
/* set CA2 (shouldn't be needed) */
|
||||
v->out_ca2 = 1;
|
||||
@ -632,7 +632,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_ca2_func)
|
||||
v->intf->out_ca2_func(machine, 0, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), 0);
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -648,7 +648,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_a_func)
|
||||
v->intf->out_a_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port A is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port A is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
|
||||
break;
|
||||
@ -666,7 +666,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_b_func)
|
||||
v->intf->out_b_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -684,7 +684,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_a_func)
|
||||
v->intf->out_a_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port A is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port A is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -716,7 +716,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
if (v->intf->out_b_func)
|
||||
v->intf->out_b_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
}
|
||||
timer_adjust_oneshot(v->t1, v_cycles_to_time(v, TIMER1_VALUE(v) + IFR_DELAY), which);
|
||||
@ -757,7 +757,7 @@ void via_write(running_machine *machine, int which, int offset, int data)
|
||||
case VIA_PCR:
|
||||
v->pcr = data;
|
||||
#ifdef TRACE_VIA
|
||||
logerror("6522VIA chip %d: PCR = %02X. PC: %08X\n", which, data, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: PCR = %02X. PC: %08X\n", which, data, safe_cpu_get_pc(machine->activecpu));
|
||||
#endif
|
||||
|
||||
if (CA2_FIX_OUTPUT(data) && CA2_OUTPUT_LEVEL(data) ^ v->out_ca2)
|
||||
@ -766,7 +766,7 @@ logerror("6522VIA chip %d: PCR = %02X. PC: %08X\n", which, data, safe_activecpu
|
||||
if (v->intf->out_ca2_func)
|
||||
v->intf->out_ca2_func(machine, 0, v->out_ca2);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), v->out_ca2);
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), v->out_ca2);
|
||||
}
|
||||
|
||||
if (CB2_FIX_OUTPUT(data) && CB2_OUTPUT_LEVEL(data) ^ v->out_cb2)
|
||||
@ -775,7 +775,7 @@ logerror("6522VIA chip %d: PCR = %02X. PC: %08X\n", which, data, safe_activecpu
|
||||
if (v->intf->out_cb2_func)
|
||||
v->intf->out_cb2_func(machine, 0, v->out_cb2);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CB2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), v->out_cb2);
|
||||
logerror("6522VIA chip %d: Port CB2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), v->out_cb2);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -797,7 +797,7 @@ logerror("6522VIA chip %d: PCR = %02X. PC: %08X\n", which, data, safe_activecpu
|
||||
if (v->intf->out_b_func)
|
||||
v->intf->out_b_func(machine, 0, write_data);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), write_data);
|
||||
logerror("6522VIA chip %d: Port B is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), write_data);
|
||||
}
|
||||
}
|
||||
if (T1_CONTINUOUS(data))
|
||||
@ -822,7 +822,7 @@ logerror("6522VIA chip %d: PCR = %02X. PC: %08X\n", which, data, safe_activecpu
|
||||
if (v->intf->irq_func)
|
||||
(*v->intf->irq_func)(machine, CLEAR_LINE);
|
||||
// else
|
||||
// logerror("6522VIA chip %d: Interrupt is cleared but there is no callback function. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
// logerror("6522VIA chip %d: Interrupt is cleared but there is no callback function. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -833,7 +833,7 @@ logerror("6522VIA chip %d: PCR = %02X. PC: %08X\n", which, data, safe_activecpu
|
||||
if (v->intf->irq_func)
|
||||
(*v->intf->irq_func)(machine, ASSERT_LINE);
|
||||
else
|
||||
logerror("6522VIA chip %d: Interrupt is asserted but there is no callback function. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Interrupt is asserted but there is no callback function. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -869,7 +869,7 @@ void via_set_input_ca1(running_machine *machine, int which, int data)
|
||||
if (data != v->in_ca1)
|
||||
{
|
||||
#ifdef TRACE_VIA
|
||||
logerror("6522VIA chip %d: CA1 = %02X. PC: %08X\n", which, data, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: CA1 = %02X. PC: %08X\n", which, data, safe_cpu_get_pc(machine->activecpu));
|
||||
#endif
|
||||
if ((CA1_LOW_TO_HIGH(v->pcr) && data) || (CA1_HIGH_TO_LOW(v->pcr) && !data))
|
||||
{
|
||||
@ -878,7 +878,7 @@ logerror("6522VIA chip %d: CA1 = %02X. PC: %08X\n", which, data, safe_activecpu
|
||||
if (v->intf->in_a_func)
|
||||
v->in_a = v->intf->in_a_func(machine, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port A is being read but has no handler. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Port A is being read but has no handler. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
|
||||
via_set_int (machine, which, INT_CA1);
|
||||
@ -896,7 +896,7 @@ logerror("6522VIA chip %d: CA1 = %02X. PC: %08X\n", which, data, safe_activecpu
|
||||
if (v->intf->out_ca2_func)
|
||||
v->intf->out_ca2_func(machine, 0, 1);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), 1);
|
||||
logerror("6522VIA chip %d: Port CA2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -965,7 +965,7 @@ void via_set_input_cb1(running_machine *machine, int which, int data)
|
||||
if (v->intf->in_b_func)
|
||||
v->in_b = v->intf->in_b_func(machine, 0);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port B is being read but has no handler. PC: %08X\n", which, safe_activecpu_get_pc());
|
||||
logerror("6522VIA chip %d: Port B is being read but has no handler. PC: %08X\n", which, safe_cpu_get_pc(machine->activecpu));
|
||||
}
|
||||
if (SO_EXT_CONTROL(v->acr) || SI_EXT_CONTROL(v->acr))
|
||||
via_shift (machine, which);
|
||||
@ -985,7 +985,7 @@ void via_set_input_cb1(running_machine *machine, int which, int data)
|
||||
if (v->intf->out_cb2_func)
|
||||
v->intf->out_cb2_func(machine, 0, 1);
|
||||
else
|
||||
logerror("6522VIA chip %d: Port CB2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_activecpu_get_pc(), 1);
|
||||
logerror("6522VIA chip %d: Port CB2 is being written to but has no handler. PC: %08X - %02X\n", which, safe_cpu_get_pc(machine->activecpu), 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -100,7 +100,7 @@ INLINE void update_irqstate(const device_config *device)
|
||||
if (riot->intf->irq_func != NULL)
|
||||
(*riot->intf->irq_func)(device, (state != 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
else
|
||||
logerror("6532RIOT chip #%d: no irq callback function. PC: %08X\n", riot->index, safe_activecpu_get_pc());
|
||||
logerror("6532RIOT chip #%d: no irq callback function. PC: %08X\n", riot->index, safe_cpu_get_pc(device->machine->activecpu));
|
||||
}
|
||||
|
||||
|
||||
@ -263,7 +263,7 @@ WRITE8_DEVICE_HANDLER( riot6532_w )
|
||||
if (port->out_func != NULL)
|
||||
(*port->out_func)(device, data, olddata);
|
||||
else
|
||||
logerror("6532RIOT chip %s: Port %c is being written to but has no handler. PC: %08X - %02X\n", device->tag, 'A' + (offset & 1), safe_activecpu_get_pc(), data);
|
||||
logerror("6532RIOT chip %s: Port %c is being written to but has no handler. PC: %08X - %02X\n", device->tag, 'A' + (offset & 1), safe_cpu_get_pc(device->machine->activecpu), data);
|
||||
}
|
||||
|
||||
/* writes to port A need to update the PA7 state */
|
||||
@ -332,7 +332,7 @@ READ8_DEVICE_HANDLER( riot6532_r )
|
||||
update_pa7_state(device);
|
||||
}
|
||||
else
|
||||
logerror("6532RIOT chip %s: Port %c is being read but has no handler. PC: %08X\n", device->tag, 'A' + (offset & 1), safe_activecpu_get_pc());
|
||||
logerror("6532RIOT chip %s: Port %c is being read but has no handler. PC: %08X\n", device->tag, 'A' + (offset & 1), safe_cpu_get_pc(device->machine->activecpu));
|
||||
|
||||
/* apply the DDR to the result */
|
||||
val = apply_ddr(port);
|
||||
|
@ -261,7 +261,7 @@ static UINT8 get_in_a_value(running_machine *machine, int which)
|
||||
|
||||
if (!p->logged_port_a_not_connected && (p->ddr_a != 0xff))
|
||||
{
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port A read handler. Assuming pins 0x%02X not connected\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, p->ddr_a ^ 0xff);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port A read handler. Assuming pins 0x%02X not connected\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, p->ddr_a ^ 0xff);
|
||||
p->logged_port_a_not_connected = TRUE;
|
||||
}
|
||||
}
|
||||
@ -301,7 +301,7 @@ static UINT8 get_in_b_value(running_machine *machine, int which)
|
||||
{
|
||||
if (!p->logged_port_b_not_connected && (p->ddr_b != 0xff))
|
||||
{
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Error! No port B read handler. Three-state pins 0x%02X are undefined\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, p->ddr_b ^ 0xff);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Error! No port B read handler. Three-state pins 0x%02X are undefined\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, p->ddr_b ^ 0xff);
|
||||
p->logged_port_b_not_connected = TRUE;
|
||||
}
|
||||
|
||||
@ -372,7 +372,7 @@ static void set_out_ca2(running_machine *machine, int which, int data)
|
||||
else
|
||||
{
|
||||
if (p->out_ca2_needs_pulled)
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port CA2 write handler. Previous value has been lost!\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port CA2 write handler. Previous value has been lost!\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
|
||||
p->out_ca2_needs_pulled = TRUE;
|
||||
}
|
||||
@ -397,7 +397,7 @@ static void set_out_cb2(running_machine *machine, int which, int data)
|
||||
else
|
||||
{
|
||||
if (p->out_cb2_needs_pulled)
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port CB2 write handler. Previous value has been lost!\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port CB2 write handler. Previous value has been lost!\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
|
||||
p->out_cb2_needs_pulled = TRUE;
|
||||
}
|
||||
@ -434,19 +434,19 @@ static UINT8 port_a_r(running_machine *machine, int which)
|
||||
set_out_ca2(machine, which, TRUE);
|
||||
}
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: port A read = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, ret));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: port A read = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static UINT8 ddr_a_r(int which)
|
||||
static UINT8 ddr_a_r(running_machine *machine, int which)
|
||||
{
|
||||
pia6821 *p = &pias[which];
|
||||
|
||||
UINT8 ret = p->ddr_a;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A read = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, ret));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A read = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -470,19 +470,19 @@ static UINT8 port_b_r(running_machine *machine, int which)
|
||||
p->irq_b2 = FALSE;
|
||||
update_interrupts(machine, p);
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: port B read = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, ret));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: port B read = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static UINT8 ddr_b_r(int which)
|
||||
static UINT8 ddr_b_r(running_machine *machine, int which)
|
||||
{
|
||||
pia6821 *p = &pias[which];
|
||||
|
||||
UINT8 ret = p->ddr_b;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B read = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, ret));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B read = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -498,7 +498,7 @@ static UINT8 control_a_r(running_machine *machine, int which)
|
||||
pia_set_input_ca1(which, p->intf->in_ca1_func(machine, 0));
|
||||
else if (!p->logged_ca1_not_connected && (!p->in_ca1_pushed))
|
||||
{
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No CA1 read handler. Assuming pin not connected\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No CA1 read handler. Assuming pin not connected\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
p->logged_ca1_not_connected = TRUE;
|
||||
}
|
||||
|
||||
@ -506,7 +506,7 @@ static UINT8 control_a_r(running_machine *machine, int which)
|
||||
pia_set_input_ca2(which, p->intf->in_ca2_func(machine, 0));
|
||||
else if ( !p->logged_ca2_not_connected && C2_INPUT(p->ctl_a) && !p->in_ca2_pushed)
|
||||
{
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No CA2 read handler. Assuming pin not connected\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No CA2 read handler. Assuming pin not connected\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
p->logged_ca2_not_connected = TRUE;
|
||||
}
|
||||
|
||||
@ -520,7 +520,7 @@ static UINT8 control_a_r(running_machine *machine, int which)
|
||||
if (p->irq_a2 && C2_INPUT(p->ctl_a))
|
||||
ret |= PIA_IRQ2;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control A read = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, ret));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control A read = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -536,7 +536,7 @@ static UINT8 control_b_r(running_machine *machine, int which)
|
||||
pia_set_input_cb1(which, p->intf->in_cb1_func(machine, 0));
|
||||
else if (!p->logged_cb1_not_connected && !p->in_cb1_pushed)
|
||||
{
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Error! no CB1 read handler. Three-state pin is undefined\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Error! no CB1 read handler. Three-state pin is undefined\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
p->logged_cb1_not_connected = TRUE;
|
||||
}
|
||||
|
||||
@ -544,7 +544,7 @@ static UINT8 control_b_r(running_machine *machine, int which)
|
||||
pia_set_input_cb2(which, p->intf->in_cb2_func(machine, 0));
|
||||
else if (!p->logged_cb2_not_connected && C2_INPUT(p->ctl_b) && !p->in_cb2_pushed)
|
||||
{
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Error! No CB2 read handler. Three-state pin is undefined\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Error! No CB2 read handler. Three-state pin is undefined\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
p->logged_cb2_not_connected = TRUE;
|
||||
}
|
||||
|
||||
@ -558,7 +558,7 @@ static UINT8 control_b_r(running_machine *machine, int which)
|
||||
if (p->irq_b2 && C2_INPUT(p->ctl_b))
|
||||
ret |= PIA_IRQ2;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control B read = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, ret));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control B read = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -576,7 +576,7 @@ UINT8 pia_read(int which, offs_t offset)
|
||||
if (OUTPUT_SELECTED(p->ctl_a))
|
||||
ret = port_a_r(Machine, which);
|
||||
else
|
||||
ret = ddr_a_r(which);
|
||||
ret = ddr_a_r(Machine, which);
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
@ -587,7 +587,7 @@ UINT8 pia_read(int which, offs_t offset)
|
||||
if (OUTPUT_SELECTED(p->ctl_b))
|
||||
ret = port_b_r(Machine, which);
|
||||
else
|
||||
ret = ddr_b_r(which);
|
||||
ret = ddr_b_r(Machine, which);
|
||||
break;
|
||||
|
||||
case 0x03:
|
||||
@ -627,14 +627,14 @@ static void send_to_out_a_func(running_machine *machine, int which, const char*
|
||||
/* input pins are pulled high */
|
||||
UINT8 data = get_out_a_value(machine, which);
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: %s = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, message, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: %s = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, message, data));
|
||||
|
||||
if (p->intf->out_a_func)
|
||||
p->intf->out_a_func(machine, 0, data);
|
||||
else
|
||||
{
|
||||
if (p->out_a_needs_pulled)
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port A write handler. Previous value has been lost!\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port A write handler. Previous value has been lost!\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
|
||||
p->out_a_needs_pulled = TRUE;
|
||||
}
|
||||
@ -648,14 +648,14 @@ static void send_to_out_b_func(running_machine *machine, int which, const char*
|
||||
/* input pins are high-impedance - we just send them as zeros for backwards compatibility */
|
||||
UINT8 data = get_out_b_value(which);
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: %s = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, message, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: %s = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, message, data));
|
||||
|
||||
if (p->intf->out_b_func)
|
||||
p->intf->out_b_func(machine, 0, data);
|
||||
else
|
||||
{
|
||||
if (p->out_b_needs_pulled)
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port B write handler. Previous value has been lost!\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which);
|
||||
logerror("cpu #%d (PC=%08X): PIA #%d: Warning! No port B write handler. Previous value has been lost!\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which);
|
||||
|
||||
p->out_b_needs_pulled = TRUE;
|
||||
}
|
||||
@ -678,11 +678,11 @@ static void ddr_a_w(running_machine *machine, int which, UINT8 data)
|
||||
pia6821 *p = &pias[which];
|
||||
|
||||
if (data == 0x00)
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A write = %02X (input mode)\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A write = %02X (input mode)\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
else if (data == 0xff)
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A write = %02X (output mode)\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A write = %02X (output mode)\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
else
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A write = %02X (mixed mode)\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR A write = %02X (mixed mode)\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
|
||||
if (p->ddr_a != data)
|
||||
{
|
||||
@ -721,11 +721,11 @@ static void ddr_b_w(running_machine *machine, int which, UINT8 data)
|
||||
pia6821 *p = &pias[which];
|
||||
|
||||
if (data == 0x00)
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B write = %02X (input mode)\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B write = %02X (input mode)\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
else if (data == 0xff)
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B write = %02X (output mode)\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B write = %02X (output mode)\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
else
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B write = %02X (mixed mode)\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: DDR B write = %02X (mixed mode)\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
|
||||
if (p->ddr_b != data)
|
||||
{
|
||||
@ -744,7 +744,7 @@ static void control_a_w(running_machine *machine, int which, UINT8 data)
|
||||
/* bit 7 and 6 are read only */
|
||||
data &= 0x3f;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control A write = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control A write = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
|
||||
/* update the control register */
|
||||
p->ctl_a = data;
|
||||
@ -777,7 +777,7 @@ static void control_b_w(running_machine *machine, int which, UINT8 data)
|
||||
/* bit 7 and 6 are read only */
|
||||
data &= 0x3f;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control B write = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: control B write = %02X\n", cpunum_get_active(), safe_cpu_get_pc(machine->activecpu), which, data));
|
||||
|
||||
/* update the control register */
|
||||
p->ctl_b = data;
|
||||
@ -863,7 +863,7 @@ void pia_set_input_a(int which, UINT8 data, UINT8 z_mask)
|
||||
|
||||
assert_always(p->intf->in_a_func == NULL, "pia_set_input_a() called when in_a_func implemented");
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input port A = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input port A = %02X\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which, data));
|
||||
|
||||
p->in_a = data;
|
||||
p->port_a_z_mask = z_mask;
|
||||
@ -903,13 +903,13 @@ void pia_set_input_ca1(int which, int data)
|
||||
/* limit the data to 0 or 1 */
|
||||
data = data ? TRUE : FALSE;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CA1 = %d\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CA1 = %d\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which, data));
|
||||
|
||||
/* the new state has caused a transition */
|
||||
if ((p->in_ca1 != data) &&
|
||||
((data && C1_LOW_TO_HIGH(p->ctl_a)) || (!data && C1_HIGH_TO_LOW(p->ctl_a))))
|
||||
{
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CA1 triggering\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CA1 triggering\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which));
|
||||
|
||||
/* mark the IRQ */
|
||||
p->irq_a1 = TRUE;
|
||||
@ -950,14 +950,14 @@ void pia_set_input_ca2(int which, int data)
|
||||
/* limit the data to 0 or 1 */
|
||||
data = data ? 1 : 0;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CA2 = %d\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CA2 = %d\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which, data));
|
||||
|
||||
/* if input mode and the new state has caused a transition */
|
||||
if (C2_INPUT(p->ctl_a) &&
|
||||
(p->in_ca2 != data) &&
|
||||
((data && C2_LOW_TO_HIGH(p->ctl_a)) || (!data && C2_HIGH_TO_LOW(p->ctl_a))))
|
||||
{
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CA2 triggering\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CA2 triggering\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which));
|
||||
|
||||
/* mark the IRQ */
|
||||
p->irq_a2 = TRUE;
|
||||
@ -1016,7 +1016,7 @@ void pia_set_input_b(int which, UINT8 data)
|
||||
|
||||
assert_always(p->intf->in_b_func == NULL, "pia_set_input_b() called when in_b_func implemented");
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input port B = %02X\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input port B = %02X\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which, data));
|
||||
|
||||
p->in_b = data;
|
||||
p->in_b_pushed = TRUE;
|
||||
@ -1056,13 +1056,13 @@ void pia_set_input_cb1(int which, int data)
|
||||
/* limit the data to 0 or 1 */
|
||||
data = data ? 1 : 0;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CB1 = %d\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CB1 = %d\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which, data));
|
||||
|
||||
/* the new state has caused a transition */
|
||||
if ((p->in_cb1 != data) &&
|
||||
((data && C1_LOW_TO_HIGH(p->ctl_b)) || (!data && C1_HIGH_TO_LOW(p->ctl_b))))
|
||||
{
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CB1 triggering\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CB1 triggering\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which));
|
||||
|
||||
/* mark the IRQ */
|
||||
p->irq_b1 = 1;
|
||||
@ -1104,14 +1104,14 @@ void pia_set_input_cb2(int which, int data)
|
||||
/* limit the data to 0 or 1 */
|
||||
data = data ? 1 : 0;
|
||||
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CB2 = %d\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which, data));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: set input CB2 = %d\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which, data));
|
||||
|
||||
/* if input mode and the new state has caused a transition */
|
||||
if (C2_INPUT(p->ctl_b) &&
|
||||
(p->in_cb2 != data) &&
|
||||
((data && C2_LOW_TO_HIGH(p->ctl_b)) || (!data && C2_HIGH_TO_LOW(p->ctl_b))))
|
||||
{
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CB2 triggering\n", cpu_getactivecpu(), safe_activecpu_get_pc(), which));
|
||||
LOG(("cpu #%d (PC=%08X): PIA #%d: CB2 triggering\n", cpunum_get_active(), safe_cpu_get_pc(Machine->activecpu), which));
|
||||
|
||||
/* mark the IRQ */
|
||||
p->irq_b2 = 1;
|
||||
|
@ -471,7 +471,7 @@ int ptm6840_read(running_machine *machine, int which, int offset)
|
||||
|
||||
case PTM_6840_STATUS:
|
||||
{
|
||||
PLOG(("%06X: MC6840 #%d: Status read = %04X\n", activecpu_get_previouspc(), which, currptr->status_reg));
|
||||
PLOG(("%06X: MC6840 #%d: Status read = %04X\n", cpu_get_previouspc(machine->activecpu), which, currptr->status_reg));
|
||||
currptr->status_read_since_int |= currptr->status_reg & 0x07;
|
||||
val = currptr->status_reg;
|
||||
break;
|
||||
@ -493,7 +493,7 @@ int ptm6840_read(running_machine *machine, int which, int offset)
|
||||
|
||||
currptr->lsb_buffer = result & 0xff;
|
||||
|
||||
PLOG(("%06X: MC6840 #%d: Counter %d read = %04X\n", activecpu_get_previouspc(), which, idx, result >> 8));
|
||||
PLOG(("%06X: MC6840 #%d: Counter %d read = %04X\n", cpu_get_previouspc(machine->activecpu), which, idx, result >> 8));
|
||||
val = result >> 8;
|
||||
break;
|
||||
}
|
||||
@ -609,7 +609,7 @@ void ptm6840_write (running_machine *machine, int which, int offset, int data)
|
||||
if (!(currptr->control_reg[idx] & 0x10))
|
||||
reload_count(machine, which,idx);
|
||||
|
||||
PLOG(("%06X:MC6840 #%d: Counter %d latch = %04X\n", activecpu_get_previouspc(), which, idx, currptr->latch[idx]));
|
||||
PLOG(("%06X:MC6840 #%d: Counter %d latch = %04X\n", cpu_get_previouspc(machine->activecpu), which, idx, currptr->latch[idx]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -354,7 +354,7 @@ static void acia6850_check_interrupts(int which)
|
||||
/*
|
||||
Write transmit register
|
||||
*/
|
||||
static void acia6850_data_w(int which, UINT8 data)
|
||||
static void acia6850_data_w(running_machine *machine, int which, UINT8 data)
|
||||
{
|
||||
acia_6850 *acia_p = &acia[which];
|
||||
|
||||
@ -366,7 +366,7 @@ static void acia6850_data_w(int which, UINT8 data)
|
||||
}
|
||||
else
|
||||
{
|
||||
logerror("ACIA %d: Data write while in reset! (%x)\n", which, activecpu_get_previouspc());
|
||||
logerror("ACIA %d: Data write while in reset! (%x)\n", which, cpu_get_previouspc(machine->activecpu));
|
||||
}
|
||||
}
|
||||
|
||||
@ -752,10 +752,10 @@ WRITE8_HANDLER( acia6850_1_ctrl_w ) { acia6850_ctrl_w(1, data); }
|
||||
WRITE8_HANDLER( acia6850_2_ctrl_w ) { acia6850_ctrl_w(2, data); }
|
||||
WRITE8_HANDLER( acia6850_3_ctrl_w ) { acia6850_ctrl_w(3, data); }
|
||||
|
||||
WRITE8_HANDLER( acia6850_0_data_w ) { acia6850_data_w(0, data); }
|
||||
WRITE8_HANDLER( acia6850_1_data_w ) { acia6850_data_w(1, data); }
|
||||
WRITE8_HANDLER( acia6850_2_data_w ) { acia6850_data_w(2, data); }
|
||||
WRITE8_HANDLER( acia6850_3_data_w ) { acia6850_data_w(3, data); }
|
||||
WRITE8_HANDLER( acia6850_0_data_w ) { acia6850_data_w(machine, 0, data); }
|
||||
WRITE8_HANDLER( acia6850_1_data_w ) { acia6850_data_w(machine, 1, data); }
|
||||
WRITE8_HANDLER( acia6850_2_data_w ) { acia6850_data_w(machine, 2, data); }
|
||||
WRITE8_HANDLER( acia6850_3_data_w ) { acia6850_data_w(machine, 3, data); }
|
||||
|
||||
READ8_HANDLER( acia6850_0_stat_r ) { return acia6850_stat_r(0); }
|
||||
READ8_HANDLER( acia6850_1_stat_r ) { return acia6850_stat_r(1); }
|
||||
@ -797,12 +797,12 @@ WRITE16_HANDLER( acia6850_1_ctrl_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_ctrl
|
||||
WRITE16_HANDLER( acia6850_2_ctrl_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_ctrl_w(2, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_3_ctrl_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_ctrl_w(3, data & 0xff); }
|
||||
|
||||
WRITE16_HANDLER( acia6850_0_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(0, (data >> 8) & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_1_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(1, (data >> 8) & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_2_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(2, (data >> 8) & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_3_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(3, (data >> 8) & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_0_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(machine, 0, (data >> 8) & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_1_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(machine, 1, (data >> 8) & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_2_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(machine, 2, (data >> 8) & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_3_data_msb_w ) { if (ACCESSING_BITS_8_15) acia6850_data_w(machine, 3, (data >> 8) & 0xff); }
|
||||
|
||||
WRITE16_HANDLER( acia6850_0_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(0, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_1_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(1, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_2_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(2, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_3_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(3, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_0_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(machine, 0, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_1_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(machine, 1, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_2_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(machine, 2, data & 0xff); }
|
||||
WRITE16_HANDLER( acia6850_3_data_lsb_w ) { if (ACCESSING_BITS_0_7) acia6850_data_w(machine, 3, data & 0xff); }
|
||||
|
@ -7,6 +7,7 @@
|
||||
|
||||
#include <stdarg.h>
|
||||
#include "driver.h"
|
||||
#include "deprecat.h"
|
||||
#include "machine/adc083x.h"
|
||||
|
||||
#define VERBOSE_LEVEL ( 0 )
|
||||
@ -20,9 +21,9 @@ INLINE void ATTR_PRINTF(2,3) verboselog( int n_level, const char *s_fmt, ... )
|
||||
va_start( v, s_fmt );
|
||||
vsprintf( buf, s_fmt, v );
|
||||
va_end( v );
|
||||
if( cpu_getactivecpu() != -1 )
|
||||
if( cpunum_get_active() != -1 )
|
||||
{
|
||||
logerror( "%08x: %s", activecpu_get_pc(), buf );
|
||||
logerror( "%08x: %s", cpu_get_pc(Machine->activecpu), buf );
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -69,11 +69,11 @@ READ32_HANDLER( am53cf96_r )
|
||||
|
||||
if (reg == REG_FIFO)
|
||||
{
|
||||
// mame_printf_debug("53cf96: read FIFO PC=%x\n", activecpu_get_pc());
|
||||
// mame_printf_debug("53cf96: read FIFO PC=%x\n", cpu_get_pc(machine->activecpu));
|
||||
return 0;
|
||||
}
|
||||
|
||||
// logerror("53cf96: read reg %d = %x (PC=%x)\n", reg, rv>>shift, activecpu_get_pc());
|
||||
// logerror("53cf96: read reg %d = %x (PC=%x)\n", reg, rv>>shift, cpu_get_pc(machine->activecpu));
|
||||
|
||||
if (reg == REG_IRQSTATE)
|
||||
{
|
||||
@ -106,7 +106,7 @@ WRITE32_HANDLER( am53cf96_w )
|
||||
}
|
||||
val &= 0xff;
|
||||
|
||||
// logerror("53cf96: w %x to reg %d (ofs %02x data %08x mask %08x PC=%x)\n", val, reg, offset, data, mem_mask, activecpu_get_pc());
|
||||
// logerror("53cf96: w %x to reg %d (ofs %02x data %08x mask %08x PC=%x)\n", val, reg, offset, data, mem_mask, cpu_get_pc(machine->activecpu));
|
||||
|
||||
// if writing to the target ID, cache it off for later
|
||||
if (reg == REG_STATUS)
|
||||
@ -144,7 +144,7 @@ WRITE32_HANDLER( am53cf96_w )
|
||||
case 2: // reset device
|
||||
scsi_regs[REG_IRQSTATE] = 8; // indicate success
|
||||
|
||||
logerror("53cf96: reset target ID = %d (PC = %x)\n", last_id, activecpu_get_pc());
|
||||
logerror("53cf96: reset target ID = %d (PC = %x)\n", last_id, cpu_get_pc(machine->activecpu));
|
||||
if (devices[last_id])
|
||||
{
|
||||
SCSIReset( devices[last_id] );
|
||||
@ -172,7 +172,7 @@ WRITE32_HANDLER( am53cf96_w )
|
||||
scsi_regs[REG_INTSTATE] = 4;
|
||||
}
|
||||
|
||||
logerror("53cf96: command %x exec. target ID = %d (PC = %x)\n", fifo[1], last_id, activecpu_get_pc());
|
||||
logerror("53cf96: command %x exec. target ID = %d (PC = %x)\n", fifo[1], last_id, cpu_get_pc(machine->activecpu));
|
||||
if (devices[last_id])
|
||||
{
|
||||
int length;
|
||||
|
@ -50,11 +50,11 @@ WRITE8_DEVICE_HANDLER( at28c16_w )
|
||||
|
||||
if( c->last_write >= 0 )
|
||||
{
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) busy\n", activecpu_get_pc(), chip, offset, data );
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) busy\n", cpu_get_pc(machine->activecpu), chip, offset, data );
|
||||
}
|
||||
else if( c->oe_12v )
|
||||
{
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) erase\n", activecpu_get_pc(), chip, offset, data );
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) erase\n", cpu_get_pc(machine->activecpu), chip, offset, data );
|
||||
memset( c->data, 0xff, SIZE_DATA );
|
||||
memset( c->id, 0xff, SIZE_ID );
|
||||
c->last_write = 0xff;
|
||||
@ -62,14 +62,14 @@ WRITE8_DEVICE_HANDLER( at28c16_w )
|
||||
}
|
||||
else if( offset >= OFFSET_ID && c->a9_12v )
|
||||
{
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) id\n", activecpu_get_pc(), chip, offset, data );
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) id\n", cpu_get_pc(machine->activecpu), chip, offset, data );
|
||||
c->id[ offset - OFFSET_ID ] = data;
|
||||
c->last_write = data;
|
||||
timer_adjust_oneshot( c->write_timer, ATTOTIME_IN_USEC( 200 ), 0 );
|
||||
}
|
||||
else
|
||||
{
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) data\n", activecpu_get_pc(), chip, offset, data );
|
||||
// logerror( "%08x: at28c16_write( %d, %04x, %02x ) data\n", cpu_get_pc(machine->activecpu), chip, offset, data );
|
||||
c->data[ offset ] = data;
|
||||
c->last_write = data;
|
||||
timer_adjust_oneshot( c->write_timer, ATTOTIME_IN_USEC( 200 ), 0 );
|
||||
@ -93,7 +93,7 @@ READ8_DEVICE_HANDLER( at28c16_r )
|
||||
}
|
||||
else
|
||||
{
|
||||
// logerror( "%08x: at28c16_read( %d, %04x ) %02x data\n", activecpu_get_pc(), chip, offset, c->data[ offset ] );
|
||||
// logerror( "%08x: at28c16_read( %d, %04x ) %02x data\n", cpu_get_pc(machine->activecpu), chip, offset, c->data[ offset ] );
|
||||
return c->data[ offset ];
|
||||
}
|
||||
}
|
||||
|
@ -8,6 +8,7 @@
|
||||
|
||||
#include <stdarg.h>
|
||||
#include "driver.h"
|
||||
#include "deprecat.h"
|
||||
#include "state.h"
|
||||
#include "machine/ds2401.h"
|
||||
|
||||
@ -22,9 +23,9 @@ INLINE void ATTR_PRINTF(2,3) verboselog( int n_level, const char *s_fmt, ... )
|
||||
va_start( v, s_fmt );
|
||||
vsprintf( buf, s_fmt, v );
|
||||
va_end( v );
|
||||
if( cpu_getactivecpu() != -1 )
|
||||
if( cpunum_get_active() != -1 )
|
||||
{
|
||||
logerror( "%08x: %s", activecpu_get_pc(), buf );
|
||||
logerror( "%08x: %s", cpu_get_pc(Machine->activecpu), buf );
|
||||
}
|
||||
else
|
||||
{
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user