Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-06-02 02:49:44 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

segas24.cpp: Further cleanups (nw)

Browse Source
This commit is contained in:
AJR 2018-06-05 11:58:19 -04:00
parent cb1e35223f
commit 92f5d2591b
2 changed files with 255 additions and 255 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

385
src/mame/drivers/segas24.cpp
View File

@ -346,6 +346,7 @@ Notes:
#include "machine/nvram.h"
#include "machine/upd4701.h"
#include "machine/315_5296.h"
#include "sound/dac.h"
#include "sound/volt_reg.h"
#include "sound/ym2151.h"
#include "video/segaic24.h"
@ -375,43 +376,43 @@ enum {
void segas24_state::fdc_init()
{
fdc_status = 0;
fdc_track = 0;
fdc_sector = 0;
fdc_data = 0;
fdc_phys_track = 0;
fdc_irq = 0;
fdc_drq = 0;
fdc_index_count = 0;
m_fdc_status = 0;
m_fdc_track = 0;
m_fdc_sector = 0;
m_fdc_data = 0;
m_fdc_phys_track = 0;
m_fdc_irq = false;
m_fdc_drq = false;
m_fdc_index_count = 0;
}
READ16_MEMBER( segas24_state::fdc_r )
{
if(!track_size)
if(!m_track_size)
return 0xffff;
switch(offset) {
case 0:
fdc_irq = 0;
return fdc_status;
m_fdc_irq = false;
return m_fdc_status;
case 1:
return fdc_track;
return m_fdc_track;
case 2:
return fdc_sector;
return m_fdc_sector;
case 3:
default: {
int res = fdc_data;
if(fdc_drq) {
fdc_span--;
// FDC_LOG(("Read %02x (%d)\n", res, fdc_span));
if(fdc_span) {
fdc_pt++;
fdc_data = *fdc_pt;
int res = m_fdc_data;
if(m_fdc_drq) {
m_fdc_span--;
// FDC_LOG(("Read %02x (%d)\n", res, m_fdc_span));
if(m_fdc_span) {
m_fdc_pt++;
m_fdc_data = *m_fdc_pt;
} else {
FDC_LOG(("FDC: transfert complete\n"));
fdc_drq = 0;
fdc_status = 0;
fdc_irq = 1;
m_fdc_drq = false;
m_fdc_status = 0;
m_fdc_irq = true;
}
} else
FDC_LOG(("FDC: data read with drq down\n"));
@ -422,54 +423,54 @@ READ16_MEMBER( segas24_state::fdc_r )
WRITE16_MEMBER( segas24_state::fdc_w )
{
if(!track_size)
if(!m_track_size)
return;
if(ACCESSING_BITS_0_7) {
data &= 0xff;
switch(offset) {
case 0:
fdc_irq = 0;
m_fdc_irq = false;
switch(data >> 4) {
case 0x0:
FDC_LOG(("FDC: Restore\n"));
fdc_phys_track = fdc_track = 0;
fdc_irq = 1;
fdc_status = 4;
m_fdc_phys_track = m_fdc_track = 0;
m_fdc_irq = true;
m_fdc_status = 4;
break;
case 0x1:
FDC_LOG(("FDC: Seek %d\n", fdc_data));
fdc_phys_track = fdc_track = fdc_data;
fdc_irq = 1;
fdc_status = fdc_track ? 0 : 4;
FDC_LOG(("FDC: Seek %d\n", m_fdc_data));
m_fdc_phys_track = m_fdc_track = m_fdc_data;
m_fdc_irq = true;
m_fdc_status = m_fdc_track ? 0 : 4;
break;
case 0x9:
FDC_LOG(("Read multiple [%02x] %d..%d side %d track %d\n", data, fdc_sector, fdc_sector+fdc_data-1, data & 8 ? 1 : 0, fdc_phys_track));
fdc_pt = memregion("floppy")->base() + track_size*(2*fdc_phys_track+(data & 8 ? 1 : 0));
fdc_span = track_size;
fdc_status = 3;
fdc_drq = 1;
fdc_data = *fdc_pt;
FDC_LOG(("Read multiple [%02x] %d..%d side %d track %d\n", data, m_fdc_sector, m_fdc_sector+m_fdc_data-1, data & 8 ? 1 : 0, m_fdc_phys_track));
m_fdc_pt = &m_floppy[m_track_size*(2*m_fdc_phys_track+(data & 8 ? 1 : 0))];
m_fdc_span = m_track_size;
m_fdc_status = 3;
m_fdc_drq = true;
m_fdc_data = *m_fdc_pt;
break;
case 0xb:
FDC_LOG(("Write multiple [%02x] %d..%d side %d track %d\n", data, fdc_sector, fdc_sector+fdc_data-1, data & 8 ? 1 : 0, fdc_phys_track));
fdc_pt = memregion("floppy")->base() + track_size*(2*fdc_phys_track+(data & 8 ? 1 : 0));
fdc_span = track_size;
fdc_status = 3;
fdc_drq = 1;
FDC_LOG(("Write multiple [%02x] %d..%d side %d track %d\n", data, m_fdc_sector, m_fdc_sector+m_fdc_data-1, data & 8 ? 1 : 0, m_fdc_phys_track));
m_fdc_pt = &m_floppy[m_track_size*(2*m_fdc_phys_track+(data & 8 ? 1 : 0))];
m_fdc_span = m_track_size;
m_fdc_status = 3;
m_fdc_drq = true;
break;
case 0xd:
FDC_LOG(("FDC: Forced interrupt\n"));
fdc_span = 0;
fdc_drq = 0;
fdc_irq = data & 1;
fdc_status = 0;
m_fdc_span = 0;
m_fdc_drq = false;
m_fdc_irq = BIT(data, 0);
m_fdc_status = 0;
break;
case 0xf:
if(data == 0xfe)
FDC_LOG(("FDC: Assign mode %02x\n", fdc_data));
FDC_LOG(("FDC: Assign mode %02x\n", m_fdc_data));
else if(data == 0xfd)
FDC_LOG(("FDC: Assign parameter %02x\n", fdc_data));
FDC_LOG(("FDC: Assign parameter %02x\n", m_fdc_data));
else
FDC_LOG(("FDC: Unknown command %02x\n", data));
break;
@ -480,26 +481,26 @@ WRITE16_MEMBER( segas24_state::fdc_w )
break;
case 1:
FDC_LOG(("FDC: Track register %02x\n", data));
fdc_track = data;
m_fdc_track = data;
break;
case 2:
FDC_LOG(("FDC: Sector register %02x\n", data));
fdc_sector = data;
m_fdc_sector = data;
break;
case 3:
if(fdc_drq) {
// FDC_LOG("Write %02x (%d)\n", data, fdc_span);
*fdc_pt++ = data;
fdc_span--;
if(!fdc_span) {
if(m_fdc_drq) {
// FDC_LOG("Write %02x (%d)\n", data, m_fdc_span);
*m_fdc_pt++ = data;
m_fdc_span--;
if(!m_fdc_span) {
FDC_LOG(("FDC: transfert complete\n"));
fdc_drq = 0;
fdc_status = 0;
fdc_irq = 1;
m_fdc_drq = false;
m_fdc_status = 0;
m_fdc_irq = true;
}
} else
FDC_LOG(("FDC: Data register %02x\n", data));
fdc_data = data;
m_fdc_data = data;
break;
}
}
@ -507,10 +508,10 @@ WRITE16_MEMBER( segas24_state::fdc_w )
READ16_MEMBER( segas24_state::fdc_status_r )
{
if(!track_size)
if(!m_track_size)
return 0xffff;
return 0x90 | (fdc_irq ? 2 : 0) | (fdc_drq ? 1 : 0) | (fdc_phys_track ? 0x40 : 0) | (fdc_index_count ? 0x20 : 0);
return 0x90 | (m_fdc_irq ? 2 : 0) | (m_fdc_drq ? 1 : 0) | (m_fdc_phys_track ? 0x40 : 0) | (m_fdc_index_count ? 0x20 : 0);
}
WRITE16_MEMBER( segas24_state::fdc_ctrl_w )
@ -537,18 +538,18 @@ READ8_MEMBER(segas24_state::dcclub_p3_r)
READ8_MEMBER(segas24_state::mahmajn_input_line_r)
{
return ~(1 << cur_input_line);
return ~(1 << m_cur_input_line);
}
READ8_MEMBER(segas24_state::mahmajn_inputs_r)
{
return m_mj_inputs[cur_input_line].read_safe(0xff);
return m_mj_inputs[m_cur_input_line].read_safe(0xff);
}
WRITE8_MEMBER(segas24_state::mahmajn_mux_w)
{
if(data & 4)
cur_input_line = (cur_input_line + 1) & 7;
m_cur_input_line = (m_cur_input_line + 1) & 7;
}
WRITE8_MEMBER(segas24_state::hotrod_lamps_w)
@ -660,41 +661,41 @@ void segas24_state::reset_bank()
{
if (m_romboard != nullptr)
{
membank("bank1")->set_entry(curbank & 15);
membank("bank2")->set_entry(curbank & 15);
membank("bank1")->set_entry(m_curbank & 15);
membank("bank2")->set_entry(m_curbank & 15);
}
}
READ16_MEMBER( segas24_state::curbank_r )
{
return curbank;
return m_curbank;
}
WRITE16_MEMBER( segas24_state::curbank_w )
{
if(ACCESSING_BITS_0_7) {
curbank = data & 0xff;
m_curbank = data & 0xff;
reset_bank();
}
}
READ8_MEMBER( segas24_state::frc_mode_r )
{
return frc_mode & 1;
return m_frc_mode & 1;
}
WRITE8_MEMBER( segas24_state::frc_mode_w )
{
/* reset frc if a write happens here */
m_frc_cnt_timer->reset();
frc_mode = data & 1;
m_frc_mode = data & 1;
}
READ8_MEMBER( segas24_state::frc_r )
{
int32_t result = (m_frc_cnt_timer->time_elapsed() * (frc_mode ? FRC_CLOCK_MODE1 : FRC_CLOCK_MODE0).dvalue()).as_double();
int32_t result = (m_frc_cnt_timer->time_elapsed() * (m_frc_mode ? FRC_CLOCK_MODE1 : FRC_CLOCK_MODE0).dvalue()).as_double();
result %= ((frc_mode) ? 0x67 : 0x100);
result %= ((m_frc_mode) ? 0x67 : 0x100);
return result;
}
@ -709,18 +710,18 @@ WRITE8_MEMBER( segas24_state::frc_w )
// Protection magic latch
const uint8_t segas24_state::mahmajn_mlt[8] = { 5, 1, 6, 2, 3, 7, 4, 0 };
const uint8_t segas24_state::mahmajn2_mlt[8] = { 6, 0, 5, 3, 1, 4, 2, 7 };
const uint8_t segas24_state::qgh_mlt[8] = { 3, 7, 4, 0, 2, 6, 5, 1 };
const uint8_t segas24_state::bnzabros_mlt[8] = { 2, 4, 0, 5, 7, 3, 1, 6 };
const uint8_t segas24_state::qrouka_mlt[8] = { 1, 6, 4, 7, 0, 5, 3, 2 };
const uint8_t segas24_state::quizmeku_mlt[8] = { 0, 3, 2, 4, 6, 1, 7, 5 };
const uint8_t segas24_state::dcclub_mlt[8] = { 4, 7, 3, 0, 2, 6, 5, 1 };
const uint8_t segas24_state::s_mahmajn_mlt[8] = { 5, 1, 6, 2, 3, 7, 4, 0 };
const uint8_t segas24_state::s_mahmajn2_mlt[8] = { 6, 0, 5, 3, 1, 4, 2, 7 };
const uint8_t segas24_state::s_qgh_mlt[8] = { 3, 7, 4, 0, 2, 6, 5, 1 };
const uint8_t segas24_state::s_bnzabros_mlt[8] = { 2, 4, 0, 5, 7, 3, 1, 6 };
const uint8_t segas24_state::s_qrouka_mlt[8] = { 1, 6, 4, 7, 0, 5, 3, 2 };
const uint8_t segas24_state::s_quizmeku_mlt[8] = { 0, 3, 2, 4, 6, 1, 7, 5 };
const uint8_t segas24_state::s_dcclub_mlt[8] = { 4, 7, 3, 0, 2, 6, 5, 1 };
READ16_MEMBER( segas24_state::mlatch_r )
{
return mlatch;
return m_mlatch;
}
WRITE16_MEMBER( segas24_state::mlatch_w )
@ -728,7 +729,7 @@ WRITE16_MEMBER( segas24_state::mlatch_w )
if(ACCESSING_BITS_0_7) {
int i;
uint8_t mxor = 0;
if(!mlatch_table) {
if(!m_mlatch_table) {
logerror("Protection: magic latch accessed but no table loaded %s\n", machine().describe_context());
return;
}
@ -737,13 +738,13 @@ WRITE16_MEMBER( segas24_state::mlatch_w )
if(data != 0xff) {
for(i=0; i<8; i++)
if(mlatch & (1<<i))
mxor |= 1 << mlatch_table[i];
mlatch = data ^ mxor;
logerror("Magic latching %02x ^ %02x as %02x %s\n", data & 0xff, mxor, mlatch, machine().describe_context());
if(m_mlatch & (1<<i))
mxor |= 1 << m_mlatch_table[i];
m_mlatch = data ^ mxor;
logerror("Magic latching %02x ^ %02x as %02x %s\n", data & 0xff, mxor, m_mlatch, machine().describe_context());
} else {
logerror("Magic latch reset %s\n", machine().describe_context());
mlatch = 0x00;
m_mlatch = 0x00;
}
}
}
@ -755,51 +756,51 @@ void segas24_state::irq_timer_sync()
{
attotime ctime = machine().time();
switch(irq_tmode) {
switch(m_irq_tmode) {
case 0:
break;
case 1: {
// Don't remove the floor(), the value may be slightly negative
int ppos = floor((irq_synctime - irq_vsynctime).as_double() * HSYNC_CLOCK.dvalue());
int cpos = floor((ctime - irq_vsynctime).as_double() * HSYNC_CLOCK.dvalue());
irq_tval += cpos-ppos;
int ppos = floor((m_irq_synctime - m_irq_vsynctime).as_double() * HSYNC_CLOCK.dvalue());
int cpos = floor((ctime - m_irq_vsynctime).as_double() * HSYNC_CLOCK.dvalue());
m_irq_tval += cpos-ppos;
break;
}
case 2: {
fatalerror("segas24_state::irq_timer_sync - case 2\n");
}
case 3: {
int ppos = floor((irq_synctime - irq_vsynctime).as_double() * TIMER_CLOCK.dvalue());
int cpos = floor((ctime - irq_vsynctime).as_double() * TIMER_CLOCK.dvalue());
irq_tval += cpos-ppos;
int ppos = floor((m_irq_synctime - m_irq_vsynctime).as_double() * TIMER_CLOCK.dvalue());
int cpos = floor((ctime - m_irq_vsynctime).as_double() * TIMER_CLOCK.dvalue());
m_irq_tval += cpos-ppos;
break;
}
}
irq_synctime = ctime;
m_irq_synctime = ctime;
}
void segas24_state::irq_timer_start(int old_tmode)
{
switch(irq_tmode) {
switch(m_irq_tmode) {
case 0:
if(old_tmode) {
irq_tval++;
if(irq_tval == 0x1000)
m_irq_tval++;
if(m_irq_tval == 0x1000)
m_irq_timer->adjust(attotime::zero);
else
m_irq_timer->enable(false);
}
break;
case 1: {
int count = 0x1000 - irq_tval;
int count = 0x1000 - m_irq_tval;
m_irq_timer->adjust(attotime::from_hz(HSYNC_CLOCK)*count);
break;
}
case 2:
fatalerror("segas24_state::irq_timer_start - case 2\n");
case 3: {
int count = 0x1000 - irq_tval;
int count = 0x1000 - m_irq_tval;
m_irq_timer->adjust(attotime::from_hz(TIMER_CLOCK)*count);
break;
}
@ -810,19 +811,19 @@ TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_timer_cb)
{
irq_timer_sync();
if(irq_tval != 0x1000)
fprintf(stderr, "Error: timer desync %x != 1000\n", irq_tval);
if(m_irq_tval != 0x1000)
fprintf(stderr, "Error: timer desync %x != 1000\n", m_irq_tval);
irq_tval = irq_tdata;
irq_timer_start(irq_tmode);
m_irq_tval = m_irq_tdata;
irq_timer_start(m_irq_tmode);
irq_timer_pend0 = irq_timer_pend1 = 1;
if(irq_allow0 & (1 << IRQ_TIMER))
m_irq_timer_pend0 = m_irq_timer_pend1 = true;
if(m_irq_allow0 & (1 << IRQ_TIMER))
m_maincpu->set_input_line(IRQ_TIMER+1, ASSERT_LINE);
if(irq_allow1 & (1 << IRQ_TIMER))
if(m_irq_allow1 & (1 << IRQ_TIMER))
m_subcpu->set_input_line(IRQ_TIMER+1, ASSERT_LINE);
if (irq_tmode == 1 || irq_tmode == 2)
if (m_irq_tmode == 1 || m_irq_tmode == 2)
{
// m_screen->update_now();
m_screen->update_partial(m_screen->vpos());
@ -831,7 +832,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_timer_cb)
TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_timer_clear_cb)
{
irq_sprite = irq_vblank = 0;
m_irq_sprite = m_irq_vblank = false;
m_maincpu->set_input_line(IRQ_VBLANK+1, CLEAR_LINE);
m_maincpu->set_input_line(IRQ_SPRITE+1, CLEAR_LINE);
m_subcpu->set_input_line(IRQ_VBLANK+1, CLEAR_LINE);
@ -840,26 +841,26 @@ TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_timer_clear_cb)
TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_frc_cb)
{
if(irq_allow0 & (1 << IRQ_FRC) && frc_mode == 1)
if(m_irq_allow0 & (1 << IRQ_FRC) && m_frc_mode == 1)
m_maincpu->set_input_line(IRQ_FRC+1, ASSERT_LINE);
if(irq_allow1 & (1 << IRQ_FRC) && frc_mode == 1)
if(m_irq_allow1 & (1 << IRQ_FRC) && m_frc_mode == 1)
m_subcpu->set_input_line(IRQ_FRC+1, ASSERT_LINE);
}
void segas24_state::irq_init()
{
irq_tdata = 0;
irq_tmode = 0;
irq_allow0 = 0;
irq_allow1 = 0;
irq_timer_pend0 = 0;
irq_timer_pend1 = 0;
irq_vblank = 0;
irq_sprite = 0;
irq_tval = 0;
irq_synctime = attotime::zero;
irq_vsynctime = attotime::zero;
m_irq_tdata = 0;
m_irq_tmode = 0;
m_irq_allow0 = 0;
m_irq_allow1 = 0;
m_irq_timer_pend0 = false;
m_irq_timer_pend1 = false;
m_irq_vblank = false;
m_irq_sprite = false;
m_irq_tval = 0;
m_irq_synctime = attotime::zero;
m_irq_vsynctime = attotime::zero;
}
WRITE16_MEMBER(segas24_state::irq_w)
@ -867,36 +868,36 @@ WRITE16_MEMBER(segas24_state::irq_w)
switch(offset) {
case 0: {
irq_timer_sync();
COMBINE_DATA(&irq_tdata);
irq_tdata &= 0xfff;
irq_timer_start(irq_tmode);
COMBINE_DATA(&m_irq_tdata);
m_irq_tdata &= 0xfff;
irq_timer_start(m_irq_tmode);
break;
}
case 1:
if(ACCESSING_BITS_0_7) {
uint8_t old_tmode = irq_tmode;
uint8_t old_tmode = m_irq_tmode;
irq_timer_sync();
irq_tmode = data & 3;
m_irq_tmode = data & 3;
irq_timer_start(old_tmode);
}
break;
case 2:
irq_allow0 = data & 0x3f;
irq_timer_pend0 = 0;
m_irq_allow0 = data & 0x3f;
m_irq_timer_pend0 = false;
m_maincpu->set_input_line(IRQ_TIMER+1, CLEAR_LINE);
m_maincpu->set_input_line(IRQ_YM2151+1, irq_yms && (irq_allow0 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(IRQ_VBLANK+1, irq_vblank && (irq_allow0 & (1 << IRQ_VBLANK)) ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(IRQ_SPRITE+1, irq_sprite && (irq_allow0 & (1 << IRQ_SPRITE)) ? ASSERT_LINE : CLEAR_LINE);
//m_maincpu->set_input_line(IRQ_FRC+1, irq_frc && (irq_allow0 & (1 << IRQ_FRC)) ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(IRQ_YM2151+1, m_irq_yms && (m_irq_allow0 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(IRQ_VBLANK+1, m_irq_vblank && (m_irq_allow0 & (1 << IRQ_VBLANK)) ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(IRQ_SPRITE+1, m_irq_sprite && (m_irq_allow0 & (1 << IRQ_SPRITE)) ? ASSERT_LINE : CLEAR_LINE);
//m_maincpu->set_input_line(IRQ_FRC+1, m_irq_frc && (m_irq_allow0 & (1 << IRQ_FRC)) ? ASSERT_LINE : CLEAR_LINE);
break;
case 3:
irq_allow1 = data & 0x3f;
irq_timer_pend1 = 0;
m_irq_allow1 = data & 0x3f;
m_irq_timer_pend1 = false;
m_subcpu->set_input_line(IRQ_TIMER+1, CLEAR_LINE);
m_subcpu->set_input_line(IRQ_YM2151+1, irq_yms && (irq_allow1 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
m_subcpu->set_input_line(IRQ_VBLANK+1, irq_vblank && (irq_allow1 & (1 << IRQ_VBLANK)) ? ASSERT_LINE : CLEAR_LINE);
m_subcpu->set_input_line(IRQ_SPRITE+1, irq_sprite && (irq_allow1 & (1 << IRQ_SPRITE)) ? ASSERT_LINE : CLEAR_LINE);
//m_subcpu->set_input_line(IRQ_FRC+1, irq_frc && (irq_allow1 & (1 << IRQ_FRC)) ? ASSERT_LINE : CLEAR_LINE);
m_subcpu->set_input_line(IRQ_YM2151+1, m_irq_yms && (m_irq_allow1 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
m_subcpu->set_input_line(IRQ_VBLANK+1, m_irq_vblank && (m_irq_allow1 & (1 << IRQ_VBLANK)) ? ASSERT_LINE : CLEAR_LINE);
m_subcpu->set_input_line(IRQ_SPRITE+1, m_irq_sprite && (m_irq_allow1 & (1 << IRQ_SPRITE)) ? ASSERT_LINE : CLEAR_LINE);
//m_subcpu->set_input_line(IRQ_FRC+1, m_irq_frc && (m_irq_allow1 & (1 << IRQ_FRC)) ? ASSERT_LINE : CLEAR_LINE);
break;
}
}
@ -915,16 +916,16 @@ READ16_MEMBER(segas24_state::irq_r)
{
switch(offset) {
case 2:
irq_timer_pend0 = 0;
m_irq_timer_pend0 = false;
m_maincpu->set_input_line(IRQ_TIMER+1, CLEAR_LINE);
break;
case 3:
irq_timer_pend1 = 0;
m_irq_timer_pend1 = false;
m_subcpu->set_input_line(IRQ_TIMER+1, CLEAR_LINE);
break;
}
irq_timer_sync();
return irq_tval & 0xfff;
return m_irq_tval & 0xfff;
}
TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_vbl)
@ -933,8 +934,8 @@ TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_vbl)
int scanline = param;
/* TODO: perhaps vblank irq happens at 400, sprite IRQ certainly don't at 0! */
if(scanline == 0) { irq = IRQ_SPRITE; irq_sprite = 1; }
else if(scanline == 384) { irq = IRQ_VBLANK; irq_vblank = 1; }
if(scanline == 0) { irq = IRQ_SPRITE; m_irq_sprite = true; }
else if(scanline == 384) { irq = IRQ_VBLANK; m_irq_vblank = true; }
else
return;
@ -942,30 +943,30 @@ TIMER_DEVICE_CALLBACK_MEMBER(segas24_state::irq_vbl)
mask = 1 << irq;
if(irq_allow0 & mask)
if(m_irq_allow0 & mask)
m_maincpu->set_input_line(1+irq, ASSERT_LINE);
if(irq_allow1 & mask)
if(m_irq_allow1 & mask)
m_subcpu->set_input_line(1+irq, ASSERT_LINE);
if(scanline == 384) {
// Ensure one index pulse every 20 frames
// The is some code in bnzabros at 0x852 that makes it crash
// if the pulse train is too fast
fdc_index_count++;
if(fdc_index_count >= 20)
fdc_index_count = 0;
m_fdc_index_count++;
if(m_fdc_index_count >= 20)
m_fdc_index_count = 0;
}
irq_timer_sync();
irq_vsynctime = machine().time();
m_irq_vsynctime = machine().time();
}
WRITE_LINE_MEMBER(segas24_state::irq_ym)
{
irq_yms = state;
m_maincpu->set_input_line(IRQ_YM2151+1, irq_yms && (irq_allow0 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
m_subcpu->set_input_line(IRQ_YM2151+1, irq_yms && (irq_allow1 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
m_irq_yms = state;
m_maincpu->set_input_line(IRQ_YM2151+1, m_irq_yms && (m_irq_allow0 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
m_subcpu->set_input_line(IRQ_YM2151+1, m_irq_yms && (m_irq_allow1 & (1 << IRQ_YM2151)) ? ASSERT_LINE : CLEAR_LINE);
}
@ -1181,8 +1182,8 @@ void segas24_state::decrypted_opcodes_map(address_map &map)
void segas24_state::machine_start()
{
if (track_size)
subdevice<nvram_device>("floppy_nvram")->set_base(memregion("floppy")->base(), 2*track_size);
if (m_track_size)
subdevice<nvram_device>("floppy_nvram")->set_base(&m_floppy[0], 2*m_track_size);
if (m_romboard != nullptr)
{
@ -1197,11 +1198,11 @@ void segas24_state::machine_reset()
m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
m_cnt1 = true;
fdc_init();
curbank = 0;
m_curbank = 0;
reset_bank();
irq_init();
mlatch = 0x00;
frc_mode = 0;
m_mlatch = 0x00;
m_frc_mode = 0;
m_frc_cnt_timer->reset();
}
@ -2336,45 +2337,45 @@ ROM_END
void segas24_state::init_qgh()
{
mlatch_table = segas24_state::qgh_mlt;
track_size = 0;
m_mlatch_table = s_qgh_mlt;
m_track_size = 0;
}
void segas24_state::init_dcclub()
{
mlatch_table = segas24_state::dcclub_mlt;
track_size = 0;
m_mlatch_table = s_dcclub_mlt;
m_track_size = 0;
}
void segas24_state::init_qrouka()
{
mlatch_table = segas24_state::qrouka_mlt;
track_size = 0;
m_mlatch_table = s_qrouka_mlt;
m_track_size = 0;
}
void segas24_state::init_quizmeku()
{
mlatch_table = segas24_state::quizmeku_mlt;
track_size = 0;
m_mlatch_table = s_quizmeku_mlt;
m_track_size = 0;
}
void segas24_state::init_mahmajn()
{
mlatch_table = segas24_state::mahmajn_mlt;
track_size = 0;
cur_input_line = 0;
m_mlatch_table = s_mahmajn_mlt;
m_track_size = 0;
m_cur_input_line = 0;
}
void segas24_state::init_mahmajn2()
{
mlatch_table = segas24_state::mahmajn2_mlt;
track_size = 0;
cur_input_line = 0;
m_mlatch_table = s_mahmajn2_mlt;
m_track_size = 0;
m_cur_input_line = 0;
}
void segas24_state::init_hotrod()
{
mlatch_table = nullptr;
m_mlatch_table = nullptr;
// Sector Size
// 1 8192
@ -2384,12 +2385,12 @@ void segas24_state::init_hotrod()
// 5 512
// 6 256
track_size = 0x2f00;
m_track_size = 0x2f00;
}
void segas24_state::init_bnzabros()
{
mlatch_table = segas24_state::bnzabros_mlt;
m_mlatch_table = s_bnzabros_mlt;
// Sector Size
// 1 2048
@ -2400,58 +2401,58 @@ void segas24_state::init_bnzabros()
// 6 1024
// 7 256
track_size = 0x2d00;
m_track_size = 0x2d00;
}
void segas24_state::init_sspirits()
{
mlatch_table = nullptr;
track_size = 0x2d00;
m_mlatch_table = nullptr;
m_track_size = 0x2d00;
}
void segas24_state::init_sspiritj()
{
mlatch_table = nullptr;
track_size = 0x2f00;
m_mlatch_table = nullptr;
m_track_size = 0x2f00;
}
void segas24_state::init_dcclubfd()
{
mlatch_table = segas24_state::dcclub_mlt;
track_size = 0x2d00;
m_mlatch_table = s_dcclub_mlt;
m_track_size = 0x2d00;
}
void segas24_state::init_sgmast()
{
mlatch_table = nullptr;
track_size = 0x2d00;
m_mlatch_table = nullptr;
m_track_size = 0x2d00;
}
void segas24_state::init_qsww()
{
mlatch_table = nullptr;
track_size = 0x2d00;
m_mlatch_table = nullptr;
m_track_size = 0x2d00;
}
void segas24_state::init_gground()
{
mlatch_table = nullptr;
track_size = 0x2d00;
m_mlatch_table = nullptr;
m_track_size = 0x2d00;
m_gground_hack_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(segas24_state::gground_hack_timer_callback), this));
}
void segas24_state::init_crkdown()
{
mlatch_table = nullptr;
track_size = 0x2d00;
m_mlatch_table = nullptr;
m_track_size = 0x2d00;
}
void segas24_state::init_roughrac()
{
mlatch_table = nullptr;
track_size = 0x2d00;
m_mlatch_table = nullptr;
m_track_size = 0x2d00;
}

125
src/mame/includes/segas24.h
View File

@ -7,7 +7,6 @@
#include "machine/timer.h"
#include "video/segaic24.h"
#include "sound/dac.h"
#include "screen.h"
class segas24_state : public driver_device
@ -17,11 +16,11 @@ public:
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_subcpu(*this, "subcpu")
, m_dac(*this, "dac")
, m_screen(*this, "screen")
, m_palette(*this, "palette")
, m_generic_paletteram_16(*this, "paletteram")
, m_romboard(*this, "romboard")
, m_floppy(*this, "floppy")
, m_irq_timer(*this, "irq_timer")
, m_irq_timer_clear(*this, "irq_timer_clear")
, m_frc_cnt_timer(*this, "frc_timer")
@ -33,61 +32,85 @@ public:
, m_p2(*this, "P2")
, m_p3(*this, "P3")
, m_paddle(*this, "PADDLE")
, m_dials(*this, {"DIAL1", "DIAL2", "DIAL3", "DIAL4"})
, m_mj_inputs(*this, {"MJ0", "MJ1", "MJ2", "MJ3", "MJ4", "MJ5", "P1", "P2"})
{
}
void init_crkdown();
void init_quizmeku();
void init_qrouka();
void init_roughrac();
void init_qgh();
void init_gground();
void init_mahmajn2();
void init_sspiritj();
void init_mahmajn();
void init_hotrod();
void init_sspirits();
void init_dcclub();
void init_bnzabros();
void init_dcclubfd();
void init_qsww();
void init_sgmast();
void mahmajn(machine_config &config);
void system24_floppy_fd_upd(machine_config &config);
void system24_floppy(machine_config &config);
void system24_floppy_fd1094(machine_config &config);
void dcclub(machine_config &config);
void system24_floppy_dcclub(machine_config &config);
void system24_floppy_hotrod(machine_config &config);
void system24(machine_config &config);
private:
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_subcpu;
required_device<dac_byte_interface> m_dac;
required_device<screen_device> m_screen;
required_device<palette_device> m_palette;
required_shared_ptr<uint16_t> m_generic_paletteram_16;
optional_memory_region m_romboard;
optional_region_ptr<uint8_t> m_floppy;
static const uint8_t mahmajn_mlt[8];
static const uint8_t mahmajn2_mlt[8];
static const uint8_t qgh_mlt[8];
static const uint8_t bnzabros_mlt[8];
static const uint8_t qrouka_mlt[8];
static const uint8_t quizmeku_mlt[8];
static const uint8_t dcclub_mlt[8];
static const uint8_t s_mahmajn_mlt[8];
static const uint8_t s_mahmajn2_mlt[8];
static const uint8_t s_qgh_mlt[8];
static const uint8_t s_bnzabros_mlt[8];
static const uint8_t s_qrouka_mlt[8];
static const uint8_t s_quizmeku_mlt[8];
static const uint8_t s_dcclub_mlt[8];
int fdc_status;
int fdc_track;
int fdc_sector;
int fdc_data;
int fdc_phys_track;
int fdc_irq;
int fdc_drq;
int fdc_span;
int fdc_index_count;
uint8_t *fdc_pt;
int track_size;
int cur_input_line;
uint8_t curbank;
uint8_t mlatch;
const uint8_t *mlatch_table;
int m_fdc_status;
int m_fdc_track;
int m_fdc_sector;
int m_fdc_data;
int m_fdc_phys_track;
bool m_fdc_irq;
bool m_fdc_drq;
int m_fdc_span;
int m_fdc_index_count;
uint8_t *m_fdc_pt;
int m_track_size;
int m_cur_input_line;
uint8_t m_curbank;
uint8_t m_mlatch;
const uint8_t *m_mlatch_table;
uint16_t irq_tdata, irq_tval;
uint8_t irq_tmode, irq_allow0, irq_allow1;
int irq_timer_pend0;
int irq_timer_pend1;
int irq_yms;
int irq_vblank;
int irq_sprite;
attotime irq_synctime, irq_vsynctime;
uint16_t m_irq_tdata, m_irq_tval;
uint8_t m_irq_tmode, m_irq_allow0, m_irq_allow1;
bool m_irq_timer_pend0;
bool m_irq_timer_pend1;
bool m_irq_yms;
bool m_irq_vblank;
bool m_irq_sprite;
attotime m_irq_synctime, m_irq_vsynctime;
required_device<timer_device> m_irq_timer;
required_device<timer_device> m_irq_timer_clear;
//timer_device *irq_frc;
//timer_device *m_irq_frc;
required_device<timer_device> m_frc_cnt_timer;
uint8_t frc_mode;
uint8_t m_frc_mode;
bool m_cnt1;
uint16_t *shared_ram;
required_device<segas24_tile_device> m_vtile;
required_device<segas24_sprite_device> m_vsprite;
required_device<segas24_mixer_device> m_vmixer;
@ -127,22 +150,6 @@ public:
void irq_timer_sync();
void irq_timer_start(int old_tmode);
WRITE_LINE_MEMBER(cnt1);
void init_crkdown();
void init_quizmeku();
void init_qrouka();
void init_roughrac();
void init_qgh();
void init_gground();
void init_mahmajn2();
void init_sspiritj();
void init_mahmajn();
void init_hotrod();
void init_sspirits();
void init_dcclub();
void init_bnzabros();
void init_dcclubfd();
void init_qsww();
void init_sgmast();
virtual void machine_start() override;
virtual void machine_reset() override;
uint32_t screen_update_system24(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
@ -158,16 +165,8 @@ public:
required_ioport m_p2;
required_ioport m_p3;
optional_ioport m_paddle;
optional_ioport_array<4> m_dials;
optional_ioport_array<8> m_mj_inputs;
void mahmajn(machine_config &config);
void system24_floppy_fd_upd(machine_config &config);
void system24_floppy(machine_config &config);
void system24_floppy_fd1094(machine_config &config);
void dcclub(machine_config &config);
void system24_floppy_dcclub(machine_config &config);
void system24_floppy_hotrod(machine_config &config);
void system24(machine_config &config);
void decrypted_opcodes_map(address_map &map);
void hotrod_cpu1_map(address_map &map);
void hotrod_cpu2_map(address_map &map);