From 93060c917e31472b68a66f7513965785e223c951 Mon Sep 17 00:00:00 2001 From: hap Date: Mon, 27 May 2019 19:19:43 +0200 Subject: [PATCH] New NOT_WORKING software list additions --------------------------------------- ibm5170: The ChessMachine (Installer V3.0) [hap] ibm5170: The ChessMachine (Installer V2.2) [hap] --- hash/ibm5170.xml | 53 +++++++++- scripts/src/bus.lua | 2 + src/devices/bus/isa/chessm.cpp | 167 ++++++++++++++++++++++++++++++ src/devices/bus/isa/chessm.h | 56 ++++++++++ src/devices/bus/isa/finalchs.cpp | 12 ++- src/devices/bus/isa/isa_cards.cpp | 5 +- 6 files changed, 289 insertions(+), 6 deletions(-) create mode 100644 src/devices/bus/isa/chessm.cpp create mode 100644 src/devices/bus/isa/chessm.h diff --git a/hash/ibm5170.xml b/hash/ibm5170.xml index cf6ffb3e97c..9f01c2ab392 100644 --- a/hash/ibm5170.xml +++ b/hash/ibm5170.xml @@ -8543,6 +8543,56 @@ + + + The ChessMachine (Installer V3.0) + 1991 + Tasc + + + + + + + + + + + + + + + + + + + + + + + + + + The ChessMachine (Installer V2.2) + 1991 + Tasc + + + + + + + + + + + + + + + + + Cisco Heat - All American Police Car Race @@ -9560,10 +9610,11 @@ - + The Final ChessCard 1989 Tasc + diff --git a/scripts/src/bus.lua b/scripts/src/bus.lua index 673553ed3bd..20b8abf0144 100644 --- a/scripts/src/bus.lua +++ b/scripts/src/bus.lua @@ -1231,6 +1231,8 @@ if (BUSES["ISA"]~=null) then MAME_DIR .. "src/devices/bus/isa/wdxt_gen.h", MAME_DIR .. "src/devices/bus/isa/adlib.cpp", MAME_DIR .. "src/devices/bus/isa/adlib.h", + MAME_DIR .. "src/devices/bus/isa/chessm.cpp", + MAME_DIR .. "src/devices/bus/isa/chessm.h", MAME_DIR .. "src/devices/bus/isa/com.cpp", MAME_DIR .. "src/devices/bus/isa/com.h", MAME_DIR .. "src/devices/bus/isa/fdc.cpp", diff --git a/src/devices/bus/isa/chessm.cpp b/src/devices/bus/isa/chessm.cpp new file mode 100644 index 00000000000..3facd5636f8 --- /dev/null +++ b/src/devices/bus/isa/chessm.cpp @@ -0,0 +1,167 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + +The ChessMachine by Tasc + +8-bit ISA card, successor of The Final ChessCard. +No ROM on the card this time, the chess program is sent to RAM instead. + +VLSI VY86C010-12QC (ARM2), seen with 30MHz XTAL, but XTAL label usually scratched off. +128KB, 512KB, or 1MB RAM. 512KB version probably the most common. +Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare or prototype. + +TODO: +- It doesn't work. Card detection routine works, comms test works, RAM test works, + program checksum works. But after it's done with tests and needs to start the chess + game, it doesn't acknowledge IRQ and locks up. +- add RAM/CPU configuration + +*/ + +#include "emu.h" +#include "chessm.h" + + +DEFINE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device, "isa_chessm", "ChessMachine") + +//------------------------------------------------- +// constructor +//------------------------------------------------- + +isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + device_t(mconfig, ISA8_CHESSM, tag, owner, clock), + device_isa8_card_interface(mconfig, *this), + m_maincpu(*this, "maincpu"), + m_mainlatch(*this, "mainlatch"), + m_sublatch(*this, "sublatch") +{ } + + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void isa8_chessm_device::device_start() +{ + set_isa_device(); + m_installed = false; +} + + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void isa8_chessm_device::device_reset() +{ + if (!m_installed) + { + // MAME doesn't allow reading ioport at device_start + u16 port = ioport("DSW")->read() * 0x40 + 0x10; + m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessm_device::chessm_r), this), write8_delegate(FUNC(isa8_chessm_device::chessm_w), this)); + + m_installed = true; + } +} + +void isa8_chessm_device::device_reset_after_children() +{ + // hold ARM CPU in reset state + chessm_w(machine().dummy_space(), 1, 0); +} + + + +//------------------------------------------------- +// input_ports - device-specific input ports +//------------------------------------------------- + +static INPUT_PORTS_START( chessm ) + PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x390 + PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4") + PORT_DIPSETTING( 0x00, "0x010 (Invalid)" ) + PORT_DIPSETTING( 0x01, "0x050 (Invalid)" ) + PORT_DIPSETTING( 0x02, "0x090 (Invalid)" ) + PORT_DIPSETTING( 0x03, "0x0D0 (Invalid)" ) + PORT_DIPSETTING( 0x04, "0x110" ) + PORT_DIPSETTING( 0x05, "0x150" ) + PORT_DIPSETTING( 0x06, "0x190" ) + PORT_DIPSETTING( 0x07, "0x1D0" ) + PORT_DIPSETTING( 0x08, "0x210" ) + PORT_DIPSETTING( 0x09, "0x250" ) + PORT_DIPSETTING( 0x0a, "0x290" ) + PORT_DIPSETTING( 0x0b, "0x2D0" ) + PORT_DIPSETTING( 0x0c, "0x310" ) + PORT_DIPSETTING( 0x0d, "0x350" ) + PORT_DIPSETTING( 0x0e, "0x390" ) + PORT_DIPSETTING( 0x0f, "0x3D0 (Invalid)" ) +INPUT_PORTS_END + +ioport_constructor isa8_chessm_device::device_input_ports() const +{ + return INPUT_PORTS_NAME(chessm); +} + + + +//------------------------------------------------- +// device_add_mconfig - add device configuration +//------------------------------------------------- + +void isa8_chessm_device::device_add_mconfig(machine_config &config) +{ + ARM(config, m_maincpu, 30_MHz_XTAL/2); + m_maincpu->set_addrmap(AS_PROGRAM, &isa8_chessm_device::chessm_mem); + m_maincpu->set_copro_type(arm_cpu_device::copro_type::VL86C020); + + GENERIC_LATCH_8(config, m_mainlatch); + GENERIC_LATCH_8(config, m_sublatch); + m_sublatch->data_pending_callback().set_inputline(m_maincpu, ARM_FIRQ_LINE); +} + + + +/****************************************************************************** + I/O +******************************************************************************/ + +// External handlers + +READ8_MEMBER(isa8_chessm_device::chessm_r) +{ + if (offset == 0) + return m_mainlatch->read(); + else + return m_mainlatch->pending_r() ? 0 : 2; +} + +WRITE8_MEMBER(isa8_chessm_device::chessm_w) +{ + if (offset == 0) + { + if (m_suspended) + m_maincpu->space(AS_PROGRAM).write_byte(m_ram_offset++, data); + else + m_sublatch->write(data); + } + else + { + // disable CPU, PC side can write to first 256-byte block of RAM when in this state + m_suspended = bool(~data & 1); + m_maincpu->set_input_line(INPUT_LINE_RESET, m_suspended ? ASSERT_LINE : CLEAR_LINE); + m_sublatch->read(); // clear IRQ + m_ram_offset = 0xff; + } +} + + +// Internal (on-card CPU) + +void isa8_chessm_device::chessm_mem(address_map &map) +{ + map(0x00000000, 0x0007ffff).ram(); + map(0x00380000, 0x00380000).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write)); +} diff --git a/src/devices/bus/isa/chessm.h b/src/devices/bus/isa/chessm.h new file mode 100644 index 00000000000..b514fdfe63d --- /dev/null +++ b/src/devices/bus/isa/chessm.h @@ -0,0 +1,56 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + + The ChessMachine by Tasc + +*/ + +#ifndef MAME_BUS_ISA_CHESSM_H +#define MAME_BUS_ISA_CHESSM_H + +#pragma once + +#include "isa.h" +#include "cpu/arm/arm.h" +#include "machine/gen_latch.h" + + +class isa8_chessm_device : + public device_t, + public device_isa8_card_interface +{ +public: + // construction/destruction + isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_reset_after_children() override; + + // optional information overrides + virtual void device_add_mconfig(machine_config &config) override; + virtual ioport_constructor device_input_ports() const override; + +private: + required_device m_maincpu; + required_device m_mainlatch; + required_device m_sublatch; + + u8 m_ram_offset; + bool m_suspended; + bool m_installed; + + DECLARE_READ8_MEMBER(chessm_r); + DECLARE_WRITE8_MEMBER(chessm_w); + + void chessm_mem(address_map &map); +}; + + +DECLARE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device) + + +#endif // MAME_BUS_ISA_CHESSM_H diff --git a/src/devices/bus/isa/finalchs.cpp b/src/devices/bus/isa/finalchs.cpp index ef0cb69ca9b..baefba6823e 100644 --- a/src/devices/bus/isa/finalchs.cpp +++ b/src/devices/bus/isa/finalchs.cpp @@ -8,7 +8,11 @@ The Final ChessCard by Tasc It is similar to the C64 version, actually not as impressive since a PC from around 1989 should be able to run a good chess game by itself. -Tasc later released The ChessMachine ISA card, not emulated yet. +Tasc later released The ChessMachine ISA card, see chessm.cpp. + +TODO: +- ChessMachine software(which claims to support this card too) does not detect it, + maybe it expects a newer ROM revision? */ @@ -84,7 +88,7 @@ const tiny_rom_entry *isa8_finalchs_device::device_rom_region() const static INPUT_PORTS_START( finalchs ) PORT_START("DSW") // DIP switch on the ISA card PCB - PORT_DIPNAME( 0x0f, 0x07, "I/O Port Address" ) PORT_DIPLOCATION("SW1:!1,!2,!3,!4") + PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("FCC_SW1:1,2,3,4") PORT_DIPSETTING( 0x00, "0x100" ) PORT_DIPSETTING( 0x01, "0x110" ) PORT_DIPSETTING( 0x02, "0x120" ) @@ -137,7 +141,7 @@ READ8_MEMBER(isa8_finalchs_device::finalchs_r) if (offset == 0) return m_mainlatch->read(); else - return !m_mainlatch->pending_r(); + return m_mainlatch->pending_r() ? 0 : 1; } WRITE8_MEMBER(isa8_finalchs_device::finalchs_w) @@ -147,7 +151,7 @@ WRITE8_MEMBER(isa8_finalchs_device::finalchs_w) } -// internal (on-card CPU) +// Internal (on-card CPU) void isa8_finalchs_device::finalchs_mem(address_map &map) { diff --git a/src/devices/bus/isa/isa_cards.cpp b/src/devices/bus/isa/isa_cards.cpp index 1c03f93cd95..d2eabd9d547 100644 --- a/src/devices/bus/isa/isa_cards.cpp +++ b/src/devices/bus/isa/isa_cards.cpp @@ -73,6 +73,7 @@ #include "pds.h" // other +#include "chessm.h" #include "finalchs.h" @@ -101,7 +102,6 @@ void pc_isa8_cards(device_slot_interface &device) device.option_add("fdc344", ISA8_FDC344); device.option_add("fdcmag", ISA8_FDCMAG); device.option_add("wdxt_gen", ISA8_WDXT_GEN); - device.option_add("finalchs", ISA8_FINALCHS); device.option_add("xtide", ISA8_XTIDE); device.option_add("side116", ISA8_SIDE116); device.option_add("hdc", ISA8_HDC); @@ -122,6 +122,8 @@ void pc_isa8_cards(device_slot_interface &device) device.option_add("pds", ISA8_PDS); device.option_add("lba_enhancer", ISA8_LBA_ENHANCER); device.option_add("asc88", ASC88); + device.option_add("chessm", ISA8_CHESSM); + device.option_add("finalchs", ISA8_FINALCHS); } void pc_isa16_cards(device_slot_interface &device) @@ -159,6 +161,7 @@ void pc_isa16_cards(device_slot_interface &device) device.option_add("dectalk", ISA8_DECTALK); device.option_add("pds", ISA8_PDS); device.option_add("lba_enhancer", ISA8_LBA_ENHANCER); + device.option_add("chessm", ISA8_CHESSM); device.option_add("finalchs", ISA8_FINALCHS); // 16-bit device.option_add("ide", ISA16_IDE);