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Fixed BADCOP exception handling in the MIPS III interpreter. [MooglyGuy]
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4f9b4ae380
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@ -101,6 +101,7 @@ typedef struct
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int interrupt_cycles;
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UINT32 ll_value;
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UINT64 lld_value;
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UINT32 badcop_value;
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const vtlb_entry *tlb_table;
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/* endian-dependent load/store */
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@ -201,6 +202,12 @@ INLINE void generate_exception(int exception, int backup)
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/* put the cause in the low 8 bits and clear the branch delay flag */
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CAUSE = (CAUSE & ~0x800000ff) | (exception << 2);
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/* set the appropriate bits for coprocessor exceptions */
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if(exception == EXCEPTION_BADCOP)
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{
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CAUSE |= mips3.badcop_value << 28;
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}
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/* if we were in a branch delay slot, adjust */
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if (mips3.nextpc != ~0)
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{
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@ -585,7 +592,10 @@ INLINE void set_cop0_creg(int idx, UINT64 val)
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INLINE void handle_cop0(UINT32 op)
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{
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if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0))
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{
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mips3.badcop_value = 0;
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generate_exception(EXCEPTION_BADCOP, 1);
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}
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switch (RSREG)
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{
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@ -721,7 +731,10 @@ INLINE void handle_cop1_fr0(UINT32 op)
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/* note: additional condition codes available on R5000 only */
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if (!(SR & SR_COP1))
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{
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mips3.badcop_value = 1;
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generate_exception(EXCEPTION_BADCOP, 1);
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}
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switch (RSREG)
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{
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@ -1077,7 +1090,10 @@ INLINE void handle_cop1_fr1(UINT32 op)
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/* note: additional condition codes available on R5000 only */
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if (!(SR & SR_COP1))
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{
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mips3.badcop_value = 1;
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generate_exception(EXCEPTION_BADCOP, 1);
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}
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switch (RSREG)
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{
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@ -1437,7 +1453,10 @@ INLINE void handle_cop1x_fr0(UINT32 op)
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UINT32 temp;
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if (!(SR & SR_COP1))
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{
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mips3.badcop_value = 1;
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generate_exception(EXCEPTION_BADCOP, 1);
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}
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switch (op & 0x3f)
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{
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@ -1513,7 +1532,10 @@ INLINE void handle_cop1x_fr1(UINT32 op)
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UINT32 temp;
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if (!(SR & SR_COP1))
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{
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mips3.badcop_value = 1;
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generate_exception(EXCEPTION_BADCOP, 1);
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}
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switch (op & 0x3f)
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{
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@ -1611,7 +1633,10 @@ INLINE void set_cop2_creg(int idx, UINT64 val)
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INLINE void handle_cop2(UINT32 op)
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{
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if (!(SR & SR_COP2))
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{
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mips3.badcop_value = 2;
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generate_exception(EXCEPTION_BADCOP, 1);
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}
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switch (RSREG)
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{
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