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Pointer-ified the apexc core (whatever that is :)
This commit is contained in:
Aaron Giles
parent
b99f7aef26
commit
942a56edb9
@ -1,5 +1,5 @@
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/*
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cpu/apexc/apexc.c: APE(X)C CPU emulation
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cpu/apexc/cpustate->c: APE(X)C CPU emulation
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By Raphael Nabet
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@ -40,7 +40,7 @@
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be accessed at a time (the 16 first ones, plus 16 others chosen by the programmer),
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and the rotation rate is 3750rpm (62.5 rotations per second).
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* two I/O units: tape reader and tape puncher. A teletyper was designed to read
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specially-encoded punched tapes and print decoded text. (See /systems/apexc.c)
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specially-encoded punched tapes and print decoded text. (See /systems/cpustate->c)
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* machine code has 15 instructions (!), including add, substract, shift, multiply (!),
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test and branch, input and punch. A so-called vector mode allow to repeat the same
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operation 32 times with 32 successive memory locations. Note the lack of bitwise
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@ -49,7 +49,7 @@
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time: 16ms, which would allow about 60IPS when no optimization is made)
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* there is no indirect addressing whatever, although dynamic modification of opcodes (!)
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allows to simulate it...
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* a control panel allows operation and debugging of the machine. (See /systems/apexc.c)
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* a control panel allows operation and debugging of the machine. (See /systems/cpustate->c)
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Conventions:
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Bits are numbered in big-endian order, starting with 1: bit #1 is the
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@ -327,7 +327,24 @@ field: X address D Function Y address D (part 2)
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#include "debugger.h"
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#include "apexc.h"
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typedef struct
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#ifndef SUPPORT_ODD_WORD_SIZES
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#define apexc_readmem(address) memory_read_dword_32be(cpustate->program, (address)<<2)
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#define apexc_writemem(address, data) memory_write_dword_32be(cpustate->program, (address)<<2, (data))
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/* eewww ! - Fortunately, there is no memory mapped I/O, so we can simulate masked write
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without danger */
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#define apexc_writemem_masked(address, data, mask) \
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apexc_writemem((address), (apexc_readmem(address) & ~(mask)) | ((data) & (mask)))
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#else
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#define apexc_readmem(address) cpu_readmem13_32(address)
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#define apexc_writemem(address, data) cpu_writemem13_32((address), (data))
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#define apexc_writemem_masked(address, data, mask) cpu_writemem13_32masked((address), (data), (mask))
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#endif
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#define apexc_readop(address) apexc_readmem(address)
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typedef struct _apexc_state apexc_state;
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struct _apexc_state
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{
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UINT32 a; /* accumulator */
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UINT32 r; /* register */
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@ -343,14 +360,11 @@ typedef struct
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const device_config *device;
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const address_space *program;
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const address_space *io;
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} apexc_regs;
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static apexc_regs apexc;
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static int apexc_ICount;
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int icount;
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};
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/* decrement ICount by n */
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#define DELAY(n) {apexc_ICount -= (n); apexc.current_word = (apexc.current_word + (n)) & 0x1f;}
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#define DELAY(n) {cpustate->icount -= (n); cpustate->current_word = (cpustate->current_word + (n)) & 0x1f;}
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/*
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@ -369,33 +383,33 @@ static int apexc_ICount;
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/* compute complete word address (i.e. translate a logical track address (expressed
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in current working store) to an absolute track address) */
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static int effective_address(int address)
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static int effective_address(apexc_state *cpustate, int address)
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{
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if (address & 0x200)
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{
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address = (address & 0x1FF) | (apexc.working_store) << 9;
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address = (address & 0x1FF) | (cpustate->working_store) << 9;
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}
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return address;
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}
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/* read word */
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static UINT32 word_read(int address, int special)
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static UINT32 word_read(apexc_state *cpustate, int address, int special)
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{
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UINT32 result;
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/* compute absolute track address */
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address = effective_address(address);
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address = effective_address(cpustate, address);
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if (special)
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{
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/* ignore word position in x - use current position instead */
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address = (address & ~ 0x1f) | apexc.current_word;
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address = (address & ~ 0x1f) | cpustate->current_word;
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}
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else
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{
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/* wait for requested word to appear under the heads */
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DELAY(((address /*& 0x1f*/) - apexc.current_word) & 0x1f);
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DELAY(((address /*& 0x1f*/) - cpustate->current_word) & 0x1f);
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}
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/* read 32 bits */
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@ -418,13 +432,13 @@ static UINT32 word_read(int address, int special)
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}
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/* write word (or part of a word, according to mask) */
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static void word_write(int address, UINT32 data, UINT32 mask)
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static void word_write(apexc_state *cpustate, int address, UINT32 data, UINT32 mask)
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{
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/* compute absolute track address */
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address = effective_address(address);
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address = effective_address(cpustate, address);
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/* wait for requested word to appear under the heads */
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DELAY(((address /*& 0x1f*/) - apexc.current_word) & 0x1f);
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DELAY(((address /*& 0x1f*/) - cpustate->current_word) & 0x1f);
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/* write 32 bits according to mask */
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#if 0
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@ -449,14 +463,14 @@ static void word_write(int address, UINT32 data, UINT32 mask)
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no address is used, these functions just punch or read 5 bits
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*/
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static int papertape_read(void)
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static int papertape_read(apexc_state *cpustate)
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{
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return memory_read_byte_8be(apexc.io, 0) & 0x1f;
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return memory_read_byte_8be(cpustate->io, 0) & 0x1f;
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}
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static void papertape_punch(int data)
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static void papertape_punch(apexc_state *cpustate, int data)
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{
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memory_write_byte_8be(apexc.io, 0, data);
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memory_write_byte_8be(cpustate->io, 0, data);
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}
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/*
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@ -466,17 +480,17 @@ static void papertape_punch(int data)
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/*
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set the memory location (i.e. address) register, and compute the associated delay
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*/
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INLINE int load_ml(int address, int vector)
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INLINE int load_ml(apexc_state *cpustate, int address, int vector)
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{
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int delay;
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/* additionnal delay appears if we switch tracks */
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if (((apexc.ml & 0x3E0) != (address & 0x3E0)) /*|| vector*/)
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if (((cpustate->ml & 0x3E0) != (address & 0x3E0)) /*|| vector*/)
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delay = 6; /* if tracks are different, delay to allow for track switching */
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else
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delay = 0; /* else, no problem */
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apexc.ml = address; /* save ml */
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cpustate->ml = address; /* save ml */
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return delay;
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}
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@ -496,7 +510,7 @@ INLINE int load_ml(int address, int vector)
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execute it.
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This solution makes timing simulation much simpler, too.
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*/
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static void execute(void)
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static void execute(apexc_state *cpustate)
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{
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int x, y, function, c6, vector; /* instruction fields */
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int i = 0; /* misc counter */
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@ -511,11 +525,11 @@ static void execute(void)
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int delay3; /* pre-operand-fetch delay */
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/* first isolate the instruction fields */
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x = (apexc.cr >> 22) & 0x3FF;
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y = (apexc.cr >> 12) & 0x3FF;
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function = (apexc.cr >> 7) & 0x1F;
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c6 = (apexc.cr >> 1) & 0x3F;
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vector = apexc.cr & 1;
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x = (cpustate->cr >> 22) & 0x3FF;
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y = (cpustate->cr >> 12) & 0x3FF;
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function = (cpustate->cr >> 7) & 0x1F;
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c6 = (cpustate->cr >> 1) & 0x3F;
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vector = cpustate->cr & 1;
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function &= 0x1E; /* this is a mere guess - the LSBit is reserved for future additions */
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@ -525,7 +539,7 @@ static void execute(void)
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if (has_operand)
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{
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/* load ml with X */
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delay1 = load_ml(x, vector);
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delay1 = load_ml(cpustate, x, vector);
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/* burn pre-operand-access delay if needed */
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if (delay1)
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{
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@ -542,7 +556,7 @@ static void execute(void)
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case 0:
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/* stop */
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apexc.running = FALSE;
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cpustate->running = FALSE;
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/* BTW, I don't know whether stop loads y into ml or not, and whether
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subsequent fetch is done */
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@ -552,14 +566,14 @@ static void execute(void)
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/* I */
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/* I do not know whether the CPU does an OR or whatever, but since docs say that
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the 5 bits must be cleared initially, an OR kind of makes sense */
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apexc.r |= papertape_read() << 27;
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cpustate->r |= papertape_read(cpustate) << 27;
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delay2 = 32; /* no idea whether this should be counted as an absolute delay
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or as a value in delay2 */
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break;
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case 4:
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/* P */
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papertape_punch((apexc.r >> 27) & 0x1f);
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papertape_punch(cpustate, (cpustate->r >> 27) & 0x1f);
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delay2 = 32; /* no idea whether this should be counted as an absolute delay
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or as a value in delay2 */
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break;
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@ -567,10 +581,10 @@ static void execute(void)
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case 6:
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/* B<(x)>=(y) */
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/* I have no idea what we should do if the vector bit is set */
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if (apexc.a & 0x80000000UL)
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if (cpustate->a & 0x80000000UL)
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{
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/* load ml with X */
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delay1 = load_ml(x, vector);
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delay1 = load_ml(cpustate, x, vector);
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/* burn pre-fetch delay if needed */
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if (delay1)
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{
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@ -592,13 +606,13 @@ static void execute(void)
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int shifted_bit = 0;
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/* shift and increment c6 */
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shifted_bit = apexc.r & 1;
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apexc.r >>= 1;
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if (apexc.a & 1)
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apexc.r |= 0x80000000UL;
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apexc.a >>= 1;
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shifted_bit = cpustate->r & 1;
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cpustate->r >>= 1;
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if (cpustate->a & 1)
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cpustate->r |= 0x80000000UL;
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cpustate->a >>= 1;
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if (shifted_bit)
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apexc.a |= 0x80000000UL;
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cpustate->a |= 0x80000000UL;
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c6 = (c6+1) & 0x3f;
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}
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@ -613,10 +627,10 @@ static void execute(void)
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while (c6 != 0)
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{
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/* shift and increment c6 */
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apexc.r >>= 1;
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if (apexc.a & 1)
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apexc.r |= 0x80000000UL;
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apexc.a = ((INT32) apexc.a) >> 1;
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cpustate->r >>= 1;
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if (cpustate->a & 1)
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cpustate->r |= 0x80000000UL;
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cpustate->a = ((INT32) cpustate->a) >> 1;
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c6 = (c6+1) & 0x3f;
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}
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@ -637,15 +651,15 @@ static void execute(void)
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{
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int shifted_bit;
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apexc.a = 0;
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cpustate->a = 0;
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shifted_bit = 0;
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while (1)
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{
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/* note we read word at current word position */
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if (shifted_bit && ! (apexc.r & 1))
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apexc.a += word_read(x, 1);
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else if ((! shifted_bit) && (apexc.r & 1))
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apexc.a -= word_read(x, 1);
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if (shifted_bit && ! (cpustate->r & 1))
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cpustate->a += word_read(cpustate, x, 1);
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else if ((! shifted_bit) && (cpustate->r & 1))
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cpustate->a -= word_read(cpustate, x, 1);
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else
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/* Even if we do not read anything, the loop still takes 1 cycle of
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the memory word clock. */
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@ -661,11 +675,11 @@ static void execute(void)
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c6 = (c6+1) & 0x3f;
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/* shift */
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shifted_bit = apexc.r & 1;
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apexc.r >>= 1;
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if (apexc.a & 1)
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apexc.r |= 0x80000000UL;
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apexc.a = ((INT32) apexc.a) >> 1;
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shifted_bit = cpustate->r & 1;
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cpustate->r >>= 1;
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if (cpustate->a & 1)
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cpustate->r |= 0x80000000UL;
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cpustate->a = ((INT32) cpustate->a) >> 1;
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}
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}
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@ -677,27 +691,27 @@ static void execute(void)
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case 16:
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/* +c(x) */
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apexc.a = + word_read(apexc.ml, 0);
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cpustate->a = + word_read(cpustate, cpustate->ml, 0);
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break;
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case 18:
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/* -c(x) */
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apexc.a = - word_read(apexc.ml, 0);
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cpustate->a = - word_read(cpustate, cpustate->ml, 0);
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break;
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case 20:
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/* +(x) */
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apexc.a += word_read(apexc.ml, 0);
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cpustate->a += word_read(cpustate, cpustate->ml, 0);
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break;
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case 22:
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/* -(x) */
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apexc.a -= word_read(apexc.ml, 0);
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cpustate->a -= word_read(cpustate, cpustate->ml, 0);
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break;
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case 24:
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/* T(x) */
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apexc.r = word_read(apexc.ml, 0);
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cpustate->r = word_read(cpustate, cpustate->ml, 0);
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break;
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case 26:
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@ -711,10 +725,10 @@ static void execute(void)
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else
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mask = 0xFFFFFFFFUL >> c6;
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word_write(apexc.ml, apexc.r, mask);
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word_write(cpustate, cpustate->ml, cpustate->r, mask);
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}
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apexc.r = (apexc.r & 0x80000000UL) ? 0xFFFFFFFFUL : 0;
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cpustate->r = (cpustate->r & 0x80000000UL) ? 0xFFFFFFFFUL : 0;
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delay2 = 1;
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break;
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@ -730,7 +744,7 @@ static void execute(void)
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else
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mask = 0xFFFFFFFFUL >> c6;
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word_write(apexc.ml, apexc.a, mask);
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word_write(cpustate, cpustate->ml, cpustate->a, mask);
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}
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delay2 = 1;
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@ -738,19 +752,19 @@ static void execute(void)
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case 30:
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/* S(x) */
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apexc.working_store = (x >> 5) & 0xf; /* or is it (x >> 6)? */
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cpustate->working_store = (x >> 5) & 0xf; /* or is it (x >> 6)? */
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DELAY(32); /* no idea what the value is... All I know is that it takes much
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more time than track switching (which takes 6 cycles) */
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break;
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}
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if (vector)
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/* increment word position in vector operations */
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apexc.ml = (apexc.ml & 0x3E0) | ((apexc.ml + 1) & 0x1F);
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cpustate->ml = (cpustate->ml & 0x3E0) | ((cpustate->ml + 1) & 0x1F);
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} while (vector && has_operand && (++i < 32)); /* iterate 32 times if vector bit is set */
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/* the has_operand is a mere guess */
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/* load ml with Y */
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delay3 = load_ml(y, 0);
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delay3 = load_ml(cpustate, y, 0);
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/* compute max(delay2, delay3) */
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if (delay2 > delay3)
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@ -767,63 +781,59 @@ static void execute(void)
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special_fetch:
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/* fetch current instruction into control register */
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apexc.cr = word_read(apexc.ml, 0);
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cpustate->cr = word_read(cpustate, cpustate->ml, 0);
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}
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static CPU_INIT( apexc )
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{
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apexc.device = device;
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apexc.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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apexc.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
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apexc_state *cpustate = device->token;
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cpustate->device = device;
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cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
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}
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static CPU_RESET( apexc )
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{
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apexc_state *cpustate = device->token;
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/* mmmh... I don't know what happens on reset with an actual APEXC. */
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apexc.working_store = 1; /* mere guess */
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apexc.current_word = 0; /* well, we do have to start somewhere... */
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cpustate->working_store = 1; /* mere guess */
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cpustate->current_word = 0; /* well, we do have to start somewhere... */
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/* next two lines are just the product of my bold fantasy */
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apexc.cr = 0; /* first instruction executed will be a stop */
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apexc.running = TRUE; /* this causes the CPU to load the instruction at 0/0,
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cpustate->cr = 0; /* first instruction executed will be a stop */
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cpustate->running = TRUE; /* this causes the CPU to load the instruction at 0/0,
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which enables easy booting (just press run on the panel) */
|
||||
}
|
||||
|
||||
static CPU_GET_CONTEXT( apexc )
|
||||
{
|
||||
if (dst)
|
||||
* ((apexc_regs*) dst) = apexc;
|
||||
}
|
||||
|
||||
static CPU_SET_CONTEXT( apexc )
|
||||
{
|
||||
if (src)
|
||||
apexc = * ((apexc_regs*)src);
|
||||
}
|
||||
|
||||
static CPU_EXECUTE( apexc )
|
||||
{
|
||||
apexc_ICount = cycles;
|
||||
apexc_state *cpustate = device->token;
|
||||
|
||||
cpustate->icount = cycles;
|
||||
|
||||
do
|
||||
{
|
||||
debugger_instruction_hook(device, effective_address(apexc.ml));
|
||||
debugger_instruction_hook(device, effective_address(cpustate, cpustate->ml));
|
||||
|
||||
if (apexc.running)
|
||||
execute();
|
||||
if (cpustate->running)
|
||||
execute(cpustate);
|
||||
else
|
||||
{
|
||||
DELAY(apexc_ICount); /* burn cycles once for all */
|
||||
DELAY(cpustate->icount); /* burn cycles once for all */
|
||||
}
|
||||
} while (apexc_ICount > 0);
|
||||
} while (cpustate->icount > 0);
|
||||
|
||||
return cycles - apexc_ICount;
|
||||
return cycles - cpustate->icount;
|
||||
}
|
||||
|
||||
static CPU_SET_INFO( apexc )
|
||||
{
|
||||
apexc_state *cpustate = device->token;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are set as 64-bit signed integers --- */
|
||||
@ -832,34 +842,36 @@ static CPU_SET_INFO( apexc )
|
||||
case CPUINFO_INT_PC:
|
||||
/* keep address 9 LSBits - 10th bit depends on whether we are accessing the permanent
|
||||
track group or a switchable one */
|
||||
apexc.ml = info->i & 0x1ff;
|
||||
cpustate->ml = info->i & 0x1ff;
|
||||
if (info->i & 0x1e00)
|
||||
{ /* we are accessing a switchable track group */
|
||||
apexc.ml |= 0x200; /* set 10th bit */
|
||||
cpustate->ml |= 0x200; /* set 10th bit */
|
||||
|
||||
if (((info->i >> 9) & 0xf) != apexc.working_store)
|
||||
if (((info->i >> 9) & 0xf) != cpustate->working_store)
|
||||
{ /* we need to do a store switch */
|
||||
apexc.working_store = ((info->i >> 9) & 0xf);
|
||||
cpustate->working_store = ((info->i >> 9) & 0xf);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case CPUINFO_INT_SP: (void) info->i; /* no SP */ break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + APEXC_CR: apexc.cr = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_A: apexc.a = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_R: apexc.r = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_ML: apexc.ml = info->i & 0x3ff; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_WS: apexc.working_store = info->i & 0xf; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_STATE: apexc.running = info->i ? TRUE : FALSE; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_CR: cpustate->cr = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_A: cpustate->a = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_R: cpustate->r = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_ML: cpustate->ml = info->i & 0x3ff; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_WS: cpustate->working_store = info->i & 0xf; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_STATE: cpustate->running = info->i ? TRUE : FALSE; break;
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( apexc )
|
||||
{
|
||||
apexc_state *cpustate = (device != NULL) ? device->token : NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(apexc); break;
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(apexc_state); break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 0; break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; /*don't care*/ break;
|
||||
@ -884,29 +896,29 @@ CPU_GET_INFO( apexc )
|
||||
case CPUINFO_INT_PC:
|
||||
/* no PC - return memory location register instead, this should be
|
||||
equivalent unless executed in the midst of an instruction */
|
||||
info->i = effective_address(apexc.ml);
|
||||
info->i = effective_address(cpustate, cpustate->ml);
|
||||
break;
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* no PC */ break;
|
||||
|
||||
/*case CPUINFO_INT_INPUT_STATE + ...:*/ /* no interrupts */
|
||||
|
||||
case CPUINFO_INT_REGISTER + APEXC_CR: info->i = apexc.cr; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_A: info->i = apexc.a; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_R: info->i = apexc.r; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_ML: info->i = apexc.ml; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_WS: info->i = apexc.working_store; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_STATE: info->i = apexc.running; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_ML_FULL: info->i = effective_address(apexc.ml); break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_CR: info->i = cpustate->cr; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_A: info->i = cpustate->a; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_R: info->i = cpustate->r; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_ML: info->i = cpustate->ml; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_WS: info->i = cpustate->working_store; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_STATE: info->i = cpustate->running; break;
|
||||
case CPUINFO_INT_REGISTER + APEXC_ML_FULL: info->i = effective_address(cpustate, cpustate->ml); break;
|
||||
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(apexc); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(apexc); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(apexc); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(apexc); break;
|
||||
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(apexc); break;
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(apexc); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(apexc); break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &apexc_ICount; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "APEXC"); break;
|
||||
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "APEC"); break;
|
||||
@ -914,14 +926,14 @@ CPU_GET_INFO( apexc )
|
||||
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
||||
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Raphael Nabet"); break;
|
||||
|
||||
case CPUINFO_STR_FLAGS: sprintf(info->s, "%c", (apexc.running) ? 'R' : 'S'); break;
|
||||
case CPUINFO_STR_FLAGS: sprintf(info->s, "%c", (cpustate->running) ? 'R' : 'S'); break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + APEXC_CR: sprintf(info->s, "CR:%08X", apexc.cr); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_A: sprintf(info->s, "A :%08X", apexc.a); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_R: sprintf(info->s, "R :%08X", apexc.r); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_ML: sprintf(info->s, "ML:%03X", apexc.ml); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_WS: sprintf(info->s, "WS:%01X", apexc.working_store); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_CR: sprintf(info->s, "CR:%08X", cpustate->cr); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_A: sprintf(info->s, "A :%08X", cpustate->a); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_R: sprintf(info->s, "R :%08X", cpustate->r); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_ML: sprintf(info->s, "ML:%03X", cpustate->ml); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_WS: sprintf(info->s, "WS:%01X", cpustate->working_store); break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + APEXC_STATE: sprintf(info->s, "CPU state:%01X", apexc.running ? TRUE : FALSE); break;
|
||||
case CPUINFO_STR_REGISTER + APEXC_STATE: sprintf(info->s, "CPU state:%01X", cpustate->running ? TRUE : FALSE); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -20,21 +20,6 @@ enum
|
||||
|
||||
CPU_GET_INFO( apexc );
|
||||
|
||||
#ifndef SUPPORT_ODD_WORD_SIZES
|
||||
#define apexc_readmem(address) memory_read_dword_32be(apexc.program, (address)<<2)
|
||||
#define apexc_writemem(address, data) memory_write_dword_32be(apexc.program, (address)<<2, (data))
|
||||
/* eewww ! - Fortunately, there is no memory mapped I/O, so we can simulate masked write
|
||||
without danger */
|
||||
#define apexc_writemem_masked(address, data, mask) \
|
||||
apexc_writemem((address), (apexc_readmem(address) & ~(mask)) | ((data) & (mask)))
|
||||
#else
|
||||
#define apexc_readmem(address) cpu_readmem13_32(address)
|
||||
#define apexc_writemem(address, data) cpu_writemem13_32((address), (data))
|
||||
#define apexc_writemem_masked(address, data, mask) cpu_writemem13_32masked((address), (data), (mask))
|
||||
#endif
|
||||
|
||||
CPU_DISASSEMBLE( apexc );
|
||||
|
||||
#define apexc_readop(address) apexc_readmem(address)
|
||||
|
||||
#endif /* __APEXC_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user