mirror of
https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
hec2hrp and arcompact fix (nw)
This commit is contained in:
Miodrag Milanovic
parent
58c42b6993
commit
949fddaaa8
@ -73,7 +73,7 @@ end
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--------------------------------------------------
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-- ARcompact (ARCtangent-A5, ARC 600, ARC 700)
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--@src/devices/cpu/arc/arc.h,CPUS["ARCOMPACT"] = true
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--@src/devices/cpu/arcompact/arcompact.h,CPUS["ARCOMPACT"] = true
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--------------------------------------------------
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if (CPUS["ARCOMPACT"]~=null) then
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@ -1841,8 +1841,7 @@ files {
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MAME_DIR .. "src/mame/drivers/hec2hrp.cpp",
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MAME_DIR .. "src/mame/includes/hec2hrp.h",
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MAME_DIR .. "src/mame/machine/hec2hrp.cpp",
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MAME_DIR .. "src/mame/machine/hecdisk2.cpp",
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MAME_DIR .. "src/mame/video/hec2video.cpp",
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MAME_DIR .. "src/mame/video/hec2hrp.cpp",
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MAME_DIR .. "src/mame/drivers/interact.cpp",
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}
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@ -1,7 +1,6 @@
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// license:BSD-3-Clause
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// copyright-holders:JJ Stacino
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/////////////////////////////////////////////////////////////////////////
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// HEC2HRP.C in machine
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/* Hector 2HR+
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Victor
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Hector 2HR
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@ -49,6 +48,8 @@
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#include "formats/hect_tap.h"
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#include "includes/hec2hrp.h"
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#include "formats/hect_dsk.h"
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#include "cpu/z80/z80.h"
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#ifndef DEBUG_TRACE_COM_HECTOR
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//#define DEBUG_TRACE_COM_HECTOR 1
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@ -820,3 +821,136 @@ MACHINE_CONFIG_FRAGMENT( hector_audio )
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MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
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MACHINE_CONFIG_END
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/* Lecteur de disquette DISK II pour les machines :
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Hector HRX
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Hector MX40c
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Hector MX80c
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JJStacino jj.stacino@aliceadsl.fr
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15/02/2010 : Start of the disc2 project! JJStacino
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26/09/2010 : first sending with bug2 (the first "dir" command finih with a crash of the Z80 disc II proc) JJStacino
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01/11/2010 : first time ending boot sequence, probleme on the CP/M lauch JJStacino
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20/11/2010 : synchronization between uPD765 and Z80 are now OK, CP/M runnig! JJStacino
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28/11/2010 : Found at Bratislava that the disk writing with TRANS X: is NOT WORKING (the exchange Hector=>Disc2 ok)
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*/
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/* Callback uPD request */
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/* How uPD765 works:
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* First we send at uPD the string of command (p.e. 9 bytes for read starting by 0x46) on port 60h
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between each byte, check the authorization of the uPD by reading the status register
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* When the command is finish, the data arrive with DMA interrupt, then:
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If read: in port 70 to retrieve the data,
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If write: in port 70 send the data
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* When all data had been send the uPD launch an INT
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* The Z80 Disc2 writes in FF12 a flag
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* if the flag is set, end of DMA function,
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* At this point the Z80 can read the RESULT in port 61h
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*/
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/*****************************************************************************/
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/**** Management of the interrupts (NMI and INT)between uPD765 and Z80 ******/
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/*****************************************************************************/
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/* upd765 INT is connected to interrupt of Z80 within a RNMI hardware authorization */
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WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_interrupt )
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{
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m_IRQ_current_state = state;
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m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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}
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/* upd765 DRQ is connected to NMI of Z80 within a RNMI hardware authorization */
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WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_dma_irq )
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{
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m_NMI_current_state = state;
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m_disc2cpu->set_input_line(INPUT_LINE_NMI, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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}
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// RESET the disc2 Unit !
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void hec2hrp_state::hector_disc2_reset()
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{
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// Initialization Disc2 unit
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m_disc2cpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
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machine().device<upd765a_device>("upd765")->reset();
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// Select ROM memory to cold restart
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membank("bank3")->set_entry(DISCII_BANK_ROM);
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// Clear the Hardware's buffers
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m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */
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m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */
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m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */
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m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */
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m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */
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m_IRQ_current_state=0; /* Clear the IRQ active request */
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m_NMI_current_state=0; /* Clear the DMA active request */
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}
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/*****************************************************************************/
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/******************** Port handling of the Z80 Disc II unit *****************/
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/*****************************************************************************/
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READ8_MEMBER( hec2hrp_state::hector_disc2_io00_port_r)
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{
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/* Switch Disc 2 to RAM to let full RAM acces */
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membank("bank3")->set_entry(DISCII_BANK_RAM);
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return 0;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io00_port_w)
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{
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/* Switch Disc 2 to RAM to let full RAM acces */
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membank("bank3")->set_entry(DISCII_BANK_RAM);
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io20_port_r)
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{
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// You can implemente the 8251 chip communication here !
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return 0;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io20_port_w)
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{
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// You can implemente the 8251 chip communication here !
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io30_port_r)
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{
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return m_hector_disc2_data_r_ready;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io30_port_w)
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{
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// Nothing here !
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io40_port_r)
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{
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/* Read data send by Hector, by Disc2*/
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m_hector_disc2_data_r_ready = 0x00; /* Clear memory info read ready*/
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return m_hector_disc2_data_read; /* send the data !*/
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io40_port_w) /* Write data send by Disc2, to Hector*/
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{
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m_hector_disc2_data_write = data; /* Memorization data*/
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m_hector_disc2_data_w_ready = 0x80; /* Memorization data write ready in D7*/
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io50_port_r) /*Read memory info write ready*/
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{
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return m_hector_disc2_data_w_ready;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io50_port_w) /* I/O Port to the stuff of Disc2*/
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{
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upd765a_device *fdc = machine().device<upd765a_device>("upd765");
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/* FDC Motor Control - Bit 0/1 defines the state of the FDD 0/1 motor */
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machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // Moteur floppy A:
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machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Moteur floppy B:
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/* Write bit TC uPD765 on D4 of port I/O 50 */
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fdc->tc_w(BIT(data, 4));
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/* Authorization interrupt and NMI with RNMI signal*/
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m_hector_disc2_RNMI = BIT(data, 5);
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m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, m_IRQ_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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m_disc2cpu->set_input_line(INPUT_LINE_NMI, m_NMI_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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}
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@ -1,148 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:JJ Stacino
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/*******************************************************/
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/************ HECDISK2.C in machine ******************/
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/*******************************************************/
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/* Lecteur de disquette DISK II pour les machines :
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Hector HRX
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Hector MX40c
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Hector MX80c
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JJStacino jj.stacino@aliceadsl.fr
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15/02/2010 : Start of the disc2 project! JJStacino
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26/09/2010 : first sending with bug2 (the first "dir" command finih with a crash of the Z80 disc II proc) JJStacino
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01/11/2010 : first time ending boot sequence, probleme on the CP/M lauch JJStacino
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20/11/2010 : synchronization between uPD765 and Z80 are now OK, CP/M runnig! JJStacino
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28/11/2010 : Found at Bratislava that the disk writing with TRANS X: is NOT WORKING (the exchange Hector=>Disc2 ok)
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*/
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#include "emu.h"
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#include "sound/wave.h" /* for K7 sound*/
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#include "sound/discrete.h" /* for 1 Bit sound*/
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#include "machine/upd765.h" /* for floppy disc controller */
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#include "formats/hect_dsk.h"
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#include "cpu/z80/z80.h"
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#include "includes/hec2hrp.h"
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/* Callback uPD request */
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/* How uPD765 works:
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* First we send at uPD the string of command (p.e. 9 bytes for read starting by 0x46) on port 60h
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between each byte, check the authorization of the uPD by reading the status register
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* When the command is finish, the data arrive with DMA interrupt, then:
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If read: in port 70 to retrieve the data,
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If write: in port 70 send the data
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* When all data had been send the uPD launch an INT
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* The Z80 Disc2 writes in FF12 a flag
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* if the flag is set, end of DMA function,
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* At this point the Z80 can read the RESULT in port 61h
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*/
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/*****************************************************************************/
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/**** Management of the interrupts (NMI and INT)between uPD765 and Z80 ******/
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/*****************************************************************************/
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/* upd765 INT is connected to interrupt of Z80 within a RNMI hardware authorization */
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WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_interrupt )
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{
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m_IRQ_current_state = state;
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m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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}
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/* upd765 DRQ is connected to NMI of Z80 within a RNMI hardware authorization */
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WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_dma_irq )
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{
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m_NMI_current_state = state;
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m_disc2cpu->set_input_line(INPUT_LINE_NMI, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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}
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// RESET the disc2 Unit !
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void hec2hrp_state::hector_disc2_reset()
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{
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// Initialization Disc2 unit
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m_disc2cpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
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machine().device<upd765a_device>("upd765")->reset();
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// Select ROM memory to cold restart
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membank("bank3")->set_entry(DISCII_BANK_ROM);
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// Clear the Hardware's buffers
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m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */
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m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */
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m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */
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m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */
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m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */
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m_IRQ_current_state=0; /* Clear the IRQ active request */
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m_NMI_current_state=0; /* Clear the DMA active request */
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}
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/*****************************************************************************/
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/******************** Port handling of the Z80 Disc II unit *****************/
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/*****************************************************************************/
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READ8_MEMBER( hec2hrp_state::hector_disc2_io00_port_r)
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{
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/* Switch Disc 2 to RAM to let full RAM acces */
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membank("bank3")->set_entry(DISCII_BANK_RAM);
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return 0;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io00_port_w)
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{
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/* Switch Disc 2 to RAM to let full RAM acces */
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membank("bank3")->set_entry(DISCII_BANK_RAM);
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io20_port_r)
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{
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// You can implemente the 8251 chip communication here !
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return 0;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io20_port_w)
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{
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// You can implemente the 8251 chip communication here !
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io30_port_r)
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{
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return m_hector_disc2_data_r_ready;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io30_port_w)
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{
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// Nothing here !
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io40_port_r)
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{
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/* Read data send by Hector, by Disc2*/
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m_hector_disc2_data_r_ready = 0x00; /* Clear memory info read ready*/
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return m_hector_disc2_data_read; /* send the data !*/
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io40_port_w) /* Write data send by Disc2, to Hector*/
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{
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m_hector_disc2_data_write = data; /* Memorization data*/
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m_hector_disc2_data_w_ready = 0x80; /* Memorization data write ready in D7*/
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}
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READ8_MEMBER( hec2hrp_state::hector_disc2_io50_port_r) /*Read memory info write ready*/
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{
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return m_hector_disc2_data_w_ready;
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}
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WRITE8_MEMBER( hec2hrp_state::hector_disc2_io50_port_w) /* I/O Port to the stuff of Disc2*/
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{
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upd765a_device *fdc = machine().device<upd765a_device>("upd765");
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/* FDC Motor Control - Bit 0/1 defines the state of the FDD 0/1 motor */
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machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // Moteur floppy A:
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machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Moteur floppy B:
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/* Write bit TC uPD765 on D4 of port I/O 50 */
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fdc->tc_w(BIT(data, 4));
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/* Authorization interrupt and NMI with RNMI signal*/
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m_hector_disc2_RNMI = BIT(data, 5);
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m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, m_IRQ_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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m_disc2cpu->set_input_line(INPUT_LINE_NMI, m_NMI_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE);
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}
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