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Very preliminary sound DMA hooked up. Born to be Wild!

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This commit is contained in:
Angelo Salese 2013-02-20 00:16:36 +00:00
parent ced04f06a0
commit 954c801a0a
1 changed files with 78 additions and 10 deletions
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88
src/mame/drivers/coolridr.c
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@ -323,7 +323,7 @@ public:
UINT8 m_vblank;
int m_scsp_last_line;
UINT8 an_mux_data;
UINT8 sound_data;
DECLARE_READ32_MEMBER(sysh1_unk_r);
DECLARE_WRITE32_MEMBER(sysh1_unk_w);
@ -343,6 +343,7 @@ public:
DECLARE_WRITE8_MEMBER(analog_mux_w);
DECLARE_WRITE8_MEMBER(lamps_w);
DECLARE_WRITE_LINE_MEMBER(scsp_to_main_irq);
DECLARE_WRITE8_MEMBER(sound_to_sh1_w);
DECLARE_DRIVER_INIT(coolridr);
virtual void machine_start();
virtual void machine_reset();
@ -469,14 +470,78 @@ UINT32 coolridr_state::screen_update_coolridr2(screen_device &screen, bitmap_rgb
/* unknown purpose */
READ32_MEMBER(coolridr_state::sysh1_unk_r)
{
if(offset == 8)
return sound_data;
if(offset == 2 || offset == 6) // DMA status
return 0;
printf("%08x\n",offset);
return m_h1_unk[offset];
}
WRITE32_MEMBER(coolridr_state::sysh1_unk_w)
{
address_space &main_space = m_maincpu->space(AS_PROGRAM);
address_space &sound_space = m_soundcpu->space(AS_PROGRAM);
if(offset == 8)
{
//bit 16 probably halts m68k
return;
}
if(offset == 2)
{
if(!(data & 1) && (m_h1_unk[2] & 1)) // 1 -> 0 transition enables DMA
{
UINT32 src = m_h1_unk[0];
UINT32 dst = m_h1_unk[1];
UINT32 size = 0x200; // TODO
if(src == 0x100000) // DMA for m68k program, TODO
return;
//printf("%08x %08x %08x\n",src,dst,size);
for(int i = 0;i < size; i+=2)
{
sound_space.write_word(dst,main_space.read_word(src));
src+=2;
dst+=2;
}
}
}
if(offset == 6)
{
if(!(data & 1) && (m_h1_unk[6] & 1)) // 1 -> 0 transition enables DMA
{
UINT32 src = m_h1_unk[4];
UINT32 dst = m_h1_unk[5];
UINT32 size = 0x200; // TODO
if(src == 0x100000) // DMA for m68k program, TODO
return;
//printf("%08x %08x %08x\n",src,dst,size);
for(int i = 0;i < size; i+=2)
{
sound_space.write_word(dst,main_space.read_word(src));
src+=2;
dst+=2;
}
}
}
COMBINE_DATA(&m_h1_unk[offset]);
//printf("%08x %08x\n",offset*4,m_h1_unk[offset]);
}
/* According to Guru, this is actually the same I/O chip of Sega Model 2 HW */
#if 0
READ32_MEMBER(coolridr_state::sysh1_ioga_r)
@ -754,7 +819,7 @@ WRITE32_MEMBER(coolridr_state::sysh1_txt_blit_w)
// it writes the palette for the bgs here, with fade effects?
// is this the only way for the tile colours to be actually used, or does this just go to memory somewhere too?
//printf("blit mode %02x %02x %08x\n", m_blitterMode, m_blitterSerialCount, data);
sysh1_pal_w(space,m_textOffset,data,0xffffffff);
m_textOffset++;
@ -972,9 +1037,9 @@ static ADDRESS_MAP_START( coolridr_submap, AS_PROGRAM, 32, coolridr_state )
AM_RANGE(0x03200000, 0x0327ffff) AM_READWRITE16(h1_soundram2_r, h1_soundram2_w,0xffffffff) //AM_SHARE("soundram2")
AM_RANGE(0x03300000, 0x03300fff) AM_DEVREADWRITE16_LEGACY("scsp2", scsp_r, scsp_w, 0xffffffff)
AM_RANGE(0x04000000, 0x0400001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xffffffff)
AM_RANGE(0x04000020, 0x0400003f) AM_READWRITE(sysh1_unk_r,sysh1_unk_w) AM_SHARE("h1_unk")
AM_RANGE(0x04200000, 0x0420003f) AM_RAM /* hi-word for DMA? */
// AM_RANGE(0x04000000, 0x0400001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xffffffff)
AM_RANGE(0x04000000, 0x0400003f) AM_READWRITE(sysh1_unk_r,sysh1_unk_w) AM_SHARE("h1_unk")
// AM_RANGE(0x04200000, 0x0420003f) AM_RAM /* hi-word for DMA? */
AM_RANGE(0x05000000, 0x05000fff) AM_RAM
AM_RANGE(0x05200000, 0x052001ff) AM_RAM
@ -995,16 +1060,18 @@ static ADDRESS_MAP_START( coolridr_submap, AS_PROGRAM, 32, coolridr_state )
AM_RANGE(0x60000000, 0x600003ff) AM_WRITENOP
ADDRESS_MAP_END
// SH-1 or SH-2 almost certainly copies the program down to here: the ROM containing the program is 32-bit wide and the 68000 is 16-bit
// the SCSP is believed to be hardcoded to decode the first 4 MB like this for a master/slave config
// (see also Model 3):
WRITE8_MEMBER(coolridr_state::sound_to_sh1_w)
{
sound_data = data;
}
static ADDRESS_MAP_START( system_h1_sound_map, AS_PROGRAM, 16, coolridr_state )
AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_REGION("scsp1",0) AM_SHARE("soundram")
AM_RANGE(0x100000, 0x100fff) AM_DEVREADWRITE_LEGACY("scsp1", scsp_r, scsp_w)
AM_RANGE(0x200000, 0x27ffff) AM_RAM AM_REGION("scsp2",0) AM_SHARE("soundram2")
AM_RANGE(0x300000, 0x300fff) AM_DEVREADWRITE_LEGACY("scsp2", scsp_r, scsp_w)
AM_RANGE(0x800000, 0x80ffff) AM_RAM
AM_RANGE(0x900000, 0x900001) AM_WRITENOP
AM_RANGE(0x900000, 0x900001) AM_WRITE8(sound_to_sh1_w,0x00ff)
ADDRESS_MAP_END
@ -1469,7 +1536,8 @@ static const scsp_interface scsp_config =
static const scsp_interface scsp2_interface =
{
0,
NULL
NULL,
DEVCB_DRIVER_LINE_MEMBER(coolridr_state, scsp_to_main_irq)
};
#define MAIN_CLOCK XTAL_28_63636MHz