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https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
i386.cpp: add virtual methods for cpuid and msr instructions (nw)
- add virtual methods opcode_cpuid opcode_rdmsr opcode_wrmsr - default implementations in class i386_device log an error message - derive Pentium MMX, Pentium II, Pentium III classes from pentium_pro_device - remove pentium_msr_* p6_msr_* piv_msr_* MSR_READ MSR_WRITE routines and call virtual methods instead - the routine pentium_rdmsr modifies the registers only if the msr is valid
This commit is contained in:
yz70s
parent
99e50b3d41
commit
95c50fed36
@ -99,26 +99,31 @@ mediagx_device::mediagx_device(const machine_config &mconfig, const char *tag, d
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}
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pentium_pro_device::pentium_pro_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pentium_device(mconfig, PENTIUM_PRO, tag, owner, clock)
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: pentium_pro_device(mconfig, PENTIUM_PRO, tag, owner, clock)
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{
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}
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pentium_pro_device::pentium_pro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
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: pentium_device(mconfig, type, tag, owner, clock)
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{
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}
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pentium_mmx_device::pentium_mmx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pentium_device(mconfig, PENTIUM_MMX, tag, owner, clock)
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: pentium_pro_device(mconfig, PENTIUM_MMX, tag, owner, clock)
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{
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// 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
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set_vtlb_dynamic_entries(96);
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}
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pentium2_device::pentium2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pentium_device(mconfig, PENTIUM2, tag, owner, clock)
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: pentium_pro_device(mconfig, PENTIUM2, tag, owner, clock)
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{
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// 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
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set_vtlb_dynamic_entries(96);
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}
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pentium3_device::pentium3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pentium_device(mconfig, PENTIUM3, tag, owner, clock)
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: pentium_pro_device(mconfig, PENTIUM3, tag, owner, clock)
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{
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// 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
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set_vtlb_dynamic_entries(96);
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@ -4039,6 +4044,24 @@ std::unique_ptr<util::disasm_interface> i386_device::create_disassembler()
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return std::make_unique<i386_disassembler>(this);
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}
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void i386_device::opcode_cpuid()
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{
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logerror("CPUID called with unsupported EAX=%08x at %08x!\n", REG32(EAX), m_eip);
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}
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uint64_t i386_device::opcode_rdmsr(bool &valid_msr)
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{
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valid_msr = false;
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logerror("RDMSR called with unsupported ECX=%08x at %08x!\n", REG32(ECX), m_eip);
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return -1;
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}
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void i386_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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{
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valid_msr = false;
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logerror("WRMSR called with unsupported ECX=%08x (%08x%08x) at %08x!\n", REG32(ECX), (uint32_t)(data >> 32), (uint32_t)data, m_eip);
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}
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/*****************************************************************************/
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/* Intel 486 */
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@ -4177,6 +4200,98 @@ void pentium_device::device_reset()
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CHANGE_PC(m_eip);
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}
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uint64_t pentium_device::opcode_rdmsr(bool &valid_msr)
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{
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uint32_t offset = REG32(ECX);
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switch (offset)
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{
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// Machine Check Exception (TODO)
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case 0x00:
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valid_msr = true;
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popmessage("RDMSR: Reading P5_MC_ADDR");
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return 0;
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case 0x01:
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valid_msr = true;
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popmessage("RDMSR: Reading P5_MC_TYPE");
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return 0;
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// Time Stamp Counter
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case 0x10:
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valid_msr = true;
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popmessage("RDMSR: Reading TSC");
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return m_tsc;
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// Event Counters (TODO)
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case 0x11: // CESR
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valid_msr = true;
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popmessage("RDMSR: Reading CESR");
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return 0;
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case 0x12: // CTR0
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valid_msr = true;
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return m_perfctr[0];
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case 0x13: // CTR1
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valid_msr = true;
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return m_perfctr[1];
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default:
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if (!(offset & ~0xf)) // 2-f are test registers
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{
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valid_msr = true;
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logerror("RDMSR: Reading test MSR %x", offset);
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return 0;
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}
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logerror("RDMSR: invalid P5 MSR read %08x at %08x\n", offset, m_pc - 2);
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valid_msr = false;
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return 0;
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}
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return -1;
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}
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void pentium_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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{
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uint32_t offset = REG32(ECX);
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switch (offset)
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{
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// Machine Check Exception (TODO)
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case 0x00:
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popmessage("WRMSR: Writing P5_MC_ADDR");
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valid_msr = true;
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break;
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case 0x01:
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popmessage("WRMSR: Writing P5_MC_TYPE");
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valid_msr = true;
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break;
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// Time Stamp Counter
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case 0x10:
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m_tsc = data;
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popmessage("WRMSR: Writing to TSC");
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valid_msr = true;
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break;
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// Event Counters (TODO)
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case 0x11: // CESR
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popmessage("WRMSR: Writing to CESR");
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valid_msr = true;
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break;
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case 0x12: // CTR0
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m_perfctr[0] = data;
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valid_msr = true;
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break;
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case 0x13: // CTR1
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m_perfctr[1] = data;
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valid_msr = true;
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break;
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default:
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if (!(offset & ~0xf)) // 2-f are test registers
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{
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valid_msr = true;
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logerror("WRMSR: Writing test MSR %x", offset);
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break;
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}
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logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n", offset, (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
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valid_msr = false;
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break;
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}
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}
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/*****************************************************************************/
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/* Cyrix MediaGX */
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@ -4314,6 +4429,69 @@ void pentium_pro_device::device_reset()
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CHANGE_PC(m_eip);
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}
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uint64_t pentium_pro_device::opcode_rdmsr(bool &valid_msr)
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{
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uint32_t offset = REG32(ECX);
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switch (offset)
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{
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// Machine Check Exception (TODO)
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case 0x00:
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valid_msr = true;
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popmessage("RDMSR: Reading P5_MC_ADDR");
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return 0;
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case 0x01:
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valid_msr = true;
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popmessage("RDMSR: Reading P5_MC_TYPE");
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return 0;
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// Time Stamp Counter
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case 0x10:
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valid_msr = true;
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popmessage("RDMSR: Reading TSC");
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return m_tsc;
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// Performance Counters (TODO)
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case 0xc1: // PerfCtr0
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valid_msr = true;
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return m_perfctr[0];
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case 0xc2: // PerfCtr1
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valid_msr = true;
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return m_perfctr[1];
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default:
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logerror("RDMSR: unimplemented register called %08x at %08x\n", offset, m_pc - 2);
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valid_msr = true;
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return 0;
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}
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return -1;
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}
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void pentium_pro_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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{
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uint32_t offset = REG32(ECX);
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switch (offset)
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{
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// Time Stamp Counter
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case 0x10:
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m_tsc = data;
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popmessage("WRMSR: Writing to TSC");
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valid_msr = true;
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break;
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// Performance Counters (TODO)
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case 0xc1: // PerfCtr0
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m_perfctr[0] = data;
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valid_msr = true;
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break;
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case 0xc2: // PerfCtr1
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m_perfctr[1] = data;
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valid_msr = true;
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break;
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default:
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logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n", offset, (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
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valid_msr = true;
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break;
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}
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}
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/*****************************************************************************/
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/* Intel Pentium MMX */
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@ -4655,3 +4833,26 @@ void pentium4_device::device_reset()
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CHANGE_PC(m_eip);
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}
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uint64_t pentium4_device::opcode_rdmsr(bool &valid_msr)
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{
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switch (REG32(ECX))
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{
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default:
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logerror("RDMSR: unimplemented register called %08x at %08x\n", REG32(ECX), m_pc - 2);
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valid_msr = true;
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return 0;
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}
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return -1;
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}
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void pentium4_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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{
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switch (REG32(ECX))
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{
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default:
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logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n", REG32(ECX), (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
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valid_msr = true;
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break;
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}
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}
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@ -77,6 +77,12 @@ protected:
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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virtual int get_mode() const override;
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// routines for opcodes whose operation can vary between cpu models
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// default implementations just log an error message
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virtual void opcode_cpuid();
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virtual uint64_t opcode_rdmsr(bool &valid_msr);
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virtual void opcode_wrmsr(uint64_t data, bool &valid_msr);
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address_space_config m_program_config;
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address_space_config m_io_config;
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@ -425,14 +431,6 @@ protected:
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inline void WRITEPORT16(offs_t port, uint16_t value);
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inline uint32_t READPORT32(offs_t port);
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inline void WRITEPORT32(offs_t port, uint32_t value);
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uint64_t pentium_msr_read(uint32_t offset,uint8_t *valid_msr);
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void pentium_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr);
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uint64_t p6_msr_read(uint32_t offset,uint8_t *valid_msr);
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void p6_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr);
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uint64_t piv_msr_read(uint32_t offset,uint8_t *valid_msr);
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void piv_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr);
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inline uint64_t MSR_READ(uint32_t offset,uint8_t *valid_msr);
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inline void MSR_WRITE(uint32_t offset, uint64_t data, uint8_t *valid_msr);
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uint32_t i386_load_protected_mode_segment(I386_SREG *seg, uint64_t *desc );
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void i386_load_call_gate(I386_CALL_GATE *gate);
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void i386_set_descriptor_accessed(uint16_t selector);
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@ -1542,6 +1540,8 @@ protected:
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virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == INPUT_LINE_NMI || inputnum == INPUT_LINE_SMI; }
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virtual void execute_set_input(int inputnum, int state) override;
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virtual uint64_t opcode_rdmsr(bool &valid_msr) override;
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virtual void opcode_wrmsr(uint64_t data, bool &valid_msr) override;
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virtual void device_start() override;
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virtual void device_reset() override;
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};
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@ -1566,12 +1566,16 @@ public:
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pentium_pro_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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pentium_pro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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virtual uint64_t opcode_rdmsr(bool &valid_msr) override;
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virtual void opcode_wrmsr(uint64_t data, bool &valid_msr) override;
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virtual void device_start() override;
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virtual void device_reset() override;
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};
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class pentium_mmx_device : public pentium_device
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class pentium_mmx_device : public pentium_pro_device
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{
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public:
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// construction/destruction
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@ -1583,7 +1587,7 @@ protected:
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};
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class pentium2_device : public pentium_device
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class pentium2_device : public pentium_pro_device
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{
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public:
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// construction/destruction
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@ -1595,7 +1599,7 @@ protected:
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};
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class pentium3_device : public pentium_device
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class pentium3_device : public pentium_pro_device
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{
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public:
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// construction/destruction
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@ -1626,6 +1630,8 @@ public:
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pentium4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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virtual uint64_t opcode_rdmsr(bool &valid_msr) override;
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virtual void opcode_wrmsr(uint64_t data, bool &valid_msr) override;
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virtual void device_start() override;
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virtual void device_reset() override;
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};
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@ -1200,227 +1200,4 @@ void i386_device::WRITEPORT32(offs_t port, uint32_t value)
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}
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}
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/***********************************************************************************
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MSR ACCESS
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***********************************************************************************/
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// Pentium MSR handling
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uint64_t i386_device::pentium_msr_read(uint32_t offset,uint8_t *valid_msr)
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{
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switch(offset)
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{
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// Machine Check Exception (TODO)
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case 0x00:
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*valid_msr = 1;
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popmessage("RDMSR: Reading P5_MC_ADDR");
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return 0;
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case 0x01:
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*valid_msr = 1;
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popmessage("RDMSR: Reading P5_MC_TYPE");
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return 0;
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// Time Stamp Counter
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case 0x10:
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*valid_msr = 1;
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popmessage("RDMSR: Reading TSC");
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return m_tsc;
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// Event Counters (TODO)
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case 0x11: // CESR
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*valid_msr = 1;
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popmessage("RDMSR: Reading CESR");
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return 0;
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case 0x12: // CTR0
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*valid_msr = 1;
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return m_perfctr[0];
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case 0x13: // CTR1
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*valid_msr = 1;
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return m_perfctr[1];
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default:
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if(!(offset & ~0xf)) // 2-f are test registers
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{
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*valid_msr = 1;
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logerror("RDMSR: Reading test MSR %x", offset);
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return 0;
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}
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logerror("RDMSR: invalid P5 MSR read %08x at %08x\n",offset,m_pc-2);
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*valid_msr = 0;
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return 0;
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}
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return -1;
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}
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void i386_device::pentium_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr)
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{
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switch(offset)
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{
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// Machine Check Exception (TODO)
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case 0x00:
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popmessage("WRMSR: Writing P5_MC_ADDR");
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*valid_msr = 1;
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break;
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case 0x01:
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popmessage("WRMSR: Writing P5_MC_TYPE");
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*valid_msr = 1;
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break;
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// Time Stamp Counter
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case 0x10:
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m_tsc = data;
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popmessage("WRMSR: Writing to TSC");
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*valid_msr = 1;
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break;
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// Event Counters (TODO)
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case 0x11: // CESR
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popmessage("WRMSR: Writing to CESR");
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*valid_msr = 1;
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break;
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case 0x12: // CTR0
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m_perfctr[0] = data;
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*valid_msr = 1;
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break;
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case 0x13: // CTR1
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m_perfctr[1] = data;
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*valid_msr = 1;
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break;
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default:
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if(!(offset & ~0xf)) // 2-f are test registers
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{
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*valid_msr = 1;
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logerror("WRMSR: Writing test MSR %x", offset);
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break;
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}
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logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n",offset,(uint32_t)(data >> 32),(uint32_t)data,m_pc-2);
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*valid_msr = 0;
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break;
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}
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}
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// P6 (Pentium Pro, Pentium II, Pentium III) MSR handling
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uint64_t i386_device::p6_msr_read(uint32_t offset,uint8_t *valid_msr)
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{
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switch(offset)
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||||
{
|
||||
// Machine Check Exception (TODO)
|
||||
case 0x00:
|
||||
*valid_msr = 1;
|
||||
popmessage("RDMSR: Reading P5_MC_ADDR");
|
||||
return 0;
|
||||
case 0x01:
|
||||
*valid_msr = 1;
|
||||
popmessage("RDMSR: Reading P5_MC_TYPE");
|
||||
return 0;
|
||||
// Time Stamp Counter
|
||||
case 0x10:
|
||||
*valid_msr = 1;
|
||||
popmessage("RDMSR: Reading TSC");
|
||||
return m_tsc;
|
||||
// Performance Counters (TODO)
|
||||
case 0xc1: // PerfCtr0
|
||||
*valid_msr = 1;
|
||||
return m_perfctr[0];
|
||||
case 0xc2: // PerfCtr1
|
||||
*valid_msr = 1;
|
||||
return m_perfctr[1];
|
||||
default:
|
||||
logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,m_pc-2);
|
||||
*valid_msr = 1;
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
void i386_device::p6_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
// Time Stamp Counter
|
||||
case 0x10:
|
||||
m_tsc = data;
|
||||
popmessage("WRMSR: Writing to TSC");
|
||||
*valid_msr = 1;
|
||||
break;
|
||||
// Performance Counters (TODO)
|
||||
case 0xc1: // PerfCtr0
|
||||
m_perfctr[0] = data;
|
||||
*valid_msr = 1;
|
||||
break;
|
||||
case 0xc2: // PerfCtr1
|
||||
m_perfctr[1] = data;
|
||||
*valid_msr = 1;
|
||||
break;
|
||||
default:
|
||||
logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(uint32_t)(data >> 32),(uint32_t)data,m_pc-2);
|
||||
*valid_msr = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// PIV (Pentium 4+)
|
||||
uint64_t i386_device::piv_msr_read(uint32_t offset,uint8_t *valid_msr)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
default:
|
||||
logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,m_pc-2);
|
||||
*valid_msr = 1;
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
void i386_device::piv_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
default:
|
||||
logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(uint32_t)(data >> 32),(uint32_t)data,m_pc-2);
|
||||
*valid_msr = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t i386_device::MSR_READ(uint32_t offset,uint8_t *valid_msr)
|
||||
{
|
||||
uint64_t res;
|
||||
uint8_t cpu_type = (m_cpu_version >> 8) & 0x0f;
|
||||
|
||||
*valid_msr = 0;
|
||||
|
||||
switch(cpu_type)
|
||||
{
|
||||
case 5: // Pentium
|
||||
res = pentium_msr_read(offset,valid_msr);
|
||||
break;
|
||||
case 6: // Pentium Pro, Pentium II, Pentium III
|
||||
res = p6_msr_read(offset,valid_msr);
|
||||
break;
|
||||
case 15: // Pentium 4+
|
||||
res = piv_msr_read(offset,valid_msr);
|
||||
break;
|
||||
default:
|
||||
res = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
void i386_device::MSR_WRITE(uint32_t offset, uint64_t data, uint8_t *valid_msr)
|
||||
{
|
||||
*valid_msr = 0;
|
||||
uint8_t cpu_type = (m_cpu_version >> 8) & 0x0f;
|
||||
|
||||
switch(cpu_type)
|
||||
{
|
||||
case 5: // Pentium
|
||||
pentium_msr_write(offset,data,valid_msr);
|
||||
break;
|
||||
case 6: // Pentium Pro, Pentium II, Pentium III
|
||||
p6_msr_write(offset,data,valid_msr);
|
||||
break;
|
||||
case 15: // Pentium 4+
|
||||
piv_msr_write(offset,data,valid_msr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __I386_H__ */
|
||||
|
||||
@ -34,7 +34,8 @@ void i386_device::i486_cpuid() // Opcode 0x0F A2
|
||||
|
||||
default:
|
||||
{
|
||||
logerror("CPUID called with unsupported EAX=%08x at %08x!\n", REG32(EAX), m_eip);
|
||||
// call the model specific implementation
|
||||
opcode_cpuid();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -56,14 +56,17 @@ void i386_device::WRITEXMM_HI64(uint32_t ea,i386_device::XMM_REG &r)
|
||||
void i386_device::pentium_rdmsr() // Opcode 0x0f 32
|
||||
{
|
||||
uint64_t data;
|
||||
uint8_t valid_msr = 0;
|
||||
bool valid_msr = false;
|
||||
|
||||
data = MSR_READ(REG32(ECX),&valid_msr);
|
||||
REG32(EDX) = data >> 32;
|
||||
REG32(EAX) = data & 0xffffffff;
|
||||
|
||||
if(m_CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized ...
|
||||
FAULT(FAULT_GP,0) // ... throw a general exception fault
|
||||
// call the model specific implementation
|
||||
data = opcode_rdmsr(valid_msr);
|
||||
if (m_CPL != 0 || valid_msr == false) // if current privilege level isn't 0 or the register isn't recognized ...
|
||||
FAULT(FAULT_GP, 0) // ... throw a general exception fault
|
||||
else
|
||||
{
|
||||
REG32(EDX) = data >> 32;
|
||||
REG32(EAX) = data & 0xffffffff;
|
||||
}
|
||||
|
||||
CYCLES(CYCLES_RDMSR);
|
||||
}
|
||||
@ -71,12 +74,13 @@ void i386_device::pentium_rdmsr() // Opcode 0x0f 32
|
||||
void i386_device::pentium_wrmsr() // Opcode 0x0f 30
|
||||
{
|
||||
uint64_t data;
|
||||
uint8_t valid_msr = 0;
|
||||
bool valid_msr = false;
|
||||
|
||||
data = (uint64_t)REG32(EAX);
|
||||
data |= (uint64_t)(REG32(EDX)) << 32;
|
||||
|
||||
MSR_WRITE(REG32(ECX),data,&valid_msr);
|
||||
// call the model specific implementation
|
||||
opcode_wrmsr(data, valid_msr);
|
||||
|
||||
if(m_CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized
|
||||
FAULT(FAULT_GP,0) // ... throw a general exception fault
|
||||
|
||||
Loading…
Reference in New Issue
Block a user