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Cleanups and version bump

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This commit is contained in:
Miodrag Milanovic 2013-09-17 06:47:03 +00:00
parent a7d12daf5b
commit 96aa5e1c08
437 changed files with 16715 additions and 16831 deletions
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16
hash/a800_flop.xml
View File

@ -2,12 +2,12 @@
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<!--
Atari 400 / 800 floppies
(skeleton list)
note: many 'original' floppy images are in .atx format, whereas cracked / unprotected ones are .atr format
.atx is unsupported, although apparently has been reverse engineered (insert info link here)
There are also images in .xex format?
Atari 400 / 800 floppies
(skeleton list)
note: many 'original' floppy images are in .atx format, whereas cracked / unprotected ones are .atr format
.atx is unsupported, although apparently has been reverse engineered (insert info link here)
There are also images in .xex format?
-->
@ -23,6 +23,6 @@
</dataarea>
</part>
</software>
</softwarelist>

2
hash/amigaocs_flop.xml
View File

@ -20935,7 +20935,7 @@
<dataarea name="flop" size="1049612">
<rom name="hugo - pa nye eventyr 2 (denmark) (disk 1 of 6).ipf" size="1049612" crc="47ebcd60" sha1="e7689d9fab1d1eabb204121633ad0fad87100e86" offset="0"/>
</dataarea>
</part>
</part>
<part name="flop2" interface="floppy_3_5">
<feature name="part_id" value="Disk 2" />
<dataarea name="flop" size="1049612">

2
hash/apple2.xml
View File

@ -2766,7 +2766,7 @@
<software name="breakout">
<description>Breakout</description>
<year>19??</year>
<publisher>Apple Computer, Inc.</publisher> <!-- programmed by Steve Wozniak -->
<publisher>Apple Computer, Inc.</publisher> <!-- programmed by Steve Wozniak -->
<part name="flop11" interface="floppy_5_25">
<dataarea name="flop1" size="143360">

4
hash/c64_cart.xml
View File

@ -6903,11 +6903,11 @@
<publisher>Commodore</publisher>
<info name="serial" value="C-64320" />
<sharedfeat name="compatibility" value="NTSC,PAL"/>
<part name="cart" interface="c64_cart">
<feature name="game" value="0" />
<feature name="exrom" value="0" />
<dataarea name="roml" size="0x4000">
<rom name="a-bee-c.rom" size="0x4000" crc="5cfe999c" sha1="57202c3829f1d668c445ae7e792ae80245682a99" offset="0" />
</dataarea>

2
hash/c64_flop.xml
View File

@ -1085,7 +1085,7 @@
<rom name="cmk49.d64" size="174848" crc="5ef6645a" sha1="c9afd892731ebd68bc67bd8c6c84cbb1aa5e874d" offset="0" />
</dataarea>
</part>
</software>
</software>
<!-- Test -->

16
hash/copera.xml
View File

@ -1,7 +1,7 @@
<?xml version="1.0"?>
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<!--
<!--
Games for the MIXT BOOK PLAYER COPERA
* メロディランド - Melody Land (Yamaha - 199312xx - MMGS-1)
@ -16,9 +16,9 @@ not dumped?
* コペラのちきゅうだいすき - Copera no Chikyuu Daisuki (Yamaha - ???? - MMGS-9)
* 冒険!メロリン島 - Bouken! Merorin Shima (Yamaha - ???? - MMGS-10)
-->
<softwarelist name="copera" description="Yamaha / Sega Copera cartridges">
-->
<softwarelist name="copera" description="Yamaha / Sega Copera cartridges">
<software name="melody">
@ -68,7 +68,7 @@ not dumped?
</dataarea>
</part>
</software>
<software name="outacanv">
<description>Outa no Canvas (Jpn)</description>
<year>1994</year>
@ -83,8 +83,8 @@ not dumped?
</dataarea>
</part>
</software>
<software name="copekono">
<software name="copekono">
<description>Copera no Kono Otonaani (Jpn)</description>
<year>1994</year>
<publisher>Yamaha</publisher>
@ -98,7 +98,7 @@ not dumped?
</dataarea>
</part>
</software>
<software name="mikeatmw">
<description>Mike to Asobou Tobidase Milky Way (Jpn)</description>
<year>1994</year>

2
hash/famicom_cass.xml
View File

@ -2,7 +2,7 @@
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<softwarelist name="famicom_cass" description="Nintendo Famicom Family BASIC cassettes">
<!--
<!--
This list is a bit peculiar, since it contains cassette images obtained on a FC
by saving BASIC programs typed in from magazines, books, or homebrew

2
hash/ibm5140.xml
View File

@ -52,5 +52,5 @@
</dataarea>
</part>
</software>
</softwarelist>

2
hash/ibm5170.xml
View File

@ -13,7 +13,7 @@ Missing files come here
<description>Advanced Diagnostics for the IBM AT (v2.07)</description>
<year>1985</year>
<publisher>IBM</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="368640">
<rom name="atad_207.img" size="368640" crc="43d0783b" sha1="63a48f7dd92382356222ed2030cd4b900d09de3d" offset="0" />

38
hash/megadriv.xml
View File

@ -31027,16 +31027,16 @@ This dump is either a bad dump or a wrongly patched one.
-->
<!-- Software below is test / demo software for the purpose of validating our emulation
where possible any information / additional files provided with the software has been included in extra data areas
in order to mirror the original release packages and possibly provide useful references
If no additional materials are listed then the results of a successful run should be mentioned here for future reference.
-->
<!-- most effects currently fail -->
<!-- titan-overdrivemegademo.zip -->
<!-- http://www.pouet.net/prod.php?which=61724 -->
<!-- Software below is test / demo software for the purpose of validating our emulation
where possible any information / additional files provided with the software has been included in extra data areas
in order to mirror the original release packages and possibly provide useful references
If no additional materials are listed then the results of a successful run should be mentioned here for future reference.
-->
<!-- most effects currently fail -->
<!-- titan-overdrivemegademo.zip -->
<!-- http://www.pouet.net/prod.php?which=61724 -->
<software name="d_titovr">
<description>Overdrive (Demo) (Euro)</description>
<year>2013</year>
@ -31045,19 +31045,19 @@ This dump is either a bad dump or a wrongly patched one.
<dataarea name="rom" size="0x400000">
<rom name="titan-overdrivemegademo.bin" size="0x3f01be" crc="3deb19a9" sha1="6085182099d6a9ad2c8242eae263507e42269b66" offset="0x000000" loadflag="load16_word_swap"/>
</dataarea>
<!-- non-rom extras (should be marked as optional?) -->
<dataarea name="misc" size="0x7af9">
<!-- non-rom extras (should be marked as optional?) -->
<dataarea name="misc" size="0x7af9">
<rom name="titan-overdrivemegademo.nfo" size="0x7af9" crc="d560530a" sha1="f3a130881878e95a1db6e32268e7b1b001965c1a" offset="0x000000"/>
</dataarea>
<dataarea name="misc2" size="0x13489c0">
<rom name="titan-overdrivemegademo_inlay.pdf" size="0x13489c0" crc="ae55e12d" sha1="620fcba1600563b87543b027c42687da7d876b03" offset="0x000000"/>
<dataarea name="misc2" size="0x13489c0">
<rom name="titan-overdrivemegademo_inlay.pdf" size="0x13489c0" crc="ae55e12d" sha1="620fcba1600563b87543b027c42687da7d876b03" offset="0x000000"/>
</dataarea>
<dataarea name="misc3" size="0xa68cf">
<rom name="titan-overdrivemegademo_label.pdf" size="0xa68cf" crc="a527c826" sha1="449c945a0ddcbb145c7c92bc01fac543fc1352da" offset="0x000000"/>
<dataarea name="misc3" size="0xa68cf">
<rom name="titan-overdrivemegademo_label.pdf" size="0xa68cf" crc="a527c826" sha1="449c945a0ddcbb145c7c92bc01fac543fc1352da" offset="0x000000"/>
</dataarea>
<dataarea name="misc4" size="0x1c985d">
<rom name="titan-overdrivemegademo_poster.png" size="0x1c985d" crc="0dfeac10" sha1="cdfd4ff93e199da66cab3ef49d39828f3eb6040c" offset="0x000000"/>
</dataarea>
<dataarea name="misc4" size="0x1c985d">
<rom name="titan-overdrivemegademo_poster.png" size="0x1c985d" crc="0dfeac10" sha1="cdfd4ff93e199da66cab3ef49d39828f3eb6040c" offset="0x000000"/>
</dataarea>
</part>
</software>

10
hash/megaduck.xml
View File

@ -193,7 +193,7 @@
</dataarea>
</part>
</software>
<software name="2ndspace">
<description>2nd Space</description>
<year>1993</year>
@ -206,7 +206,7 @@
</dataarea>
</part>
</software>
<software name="trapturn">
<description>Trap &amp; Turn</description>
<year>1993</year>
@ -219,7 +219,7 @@
</dataarea>
</part>
</software>
<software name="bombdisp">
<description>Bomb Disposer</description>
<year>1993</year>
@ -232,7 +232,7 @@
</dataarea>
</part>
</software>
<software name="mmaze">
<description>Magic Maze</description>
<year>1993</year>
@ -245,7 +245,7 @@
</dataarea>
</part>
</software>
<software name="vex">
<description>Vex</description>
<year>1993</year>

390
hash/pc98.xml
View File

@ -1,6 +1,6 @@
<?xml version="1.0"?>
<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
<softwarelist name="pc98" description="NEC PC-9801 disk images">
<softwarelist name="pc98" description="NEC PC-9801 disk images">
<software name="pc98dosd">
<description>PC-98DO+ System Disk</description>
@ -98,7 +98,7 @@ only have some part of Windows file and a Video driver(CLGD?).
<!--
PC-98xx NEW (as per 31 July 2013) software list starts here.
TODO:
- Manually parse the list, add publisher / year where possible, fix floppy order (i.e. if a floppy is labeled opening.fdi or system.fdi is the one
- Manually parse the list, add publisher / year where possible, fix floppy order (i.e. if a floppy is labeled opening.fdi or system.fdi is the one
required at PC-98xx boot), label ALL userX.fdi images as bad dump, test all games and double check support status, fix zipnames (most sucks right now),
identify anything that has a size different than 1265664 (== 3'5" floppy image), document any unorthodox way for running a given sw.
@ -145,12 +145,12 @@ TODO:
<dataarea name="flop" size="1265664">
<rom name="2069ad_b.fdi" size="1265664" crc="3e596802" sha1="05633e7847be623f1fdc8e4c4cbaa91dd7ac8a68" offset="0" />
</dataarea>
</part>
</part>
<part name="flop3" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="2069ad_c.fdi" size="1265664" crc="25c601a5" sha1="a6b6b7096fedf6a0536fee0b380e976ebd0eb63b" offset="0" />
</dataarea>
</part>
</part>
</software>
<software name="31iwayu" supported="yes">
@ -162,7 +162,7 @@ TODO:
<rom name="disk a.fdi" size="1265664" crc="7131e56e" sha1="2070ebdd0acb1a50d77cc73368b448fe05096a3e" offset="0" />
</dataarea>
</part>
<part name="flop2" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="disk b.fdi" size="1265664" crc="54ed018b" sha1="69aaf92e5545a26fe62e4acd5334249173b0e06b" offset="0" />
@ -209,7 +209,7 @@ TODO:
</dataarea>
</part>
<!--
Note: all of these are expansions (and have no clue about how to load them either)
Note: all of these are expansions (and have no clue about how to load them either)
-->
<part name="flop2" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
@ -833,24 +833,24 @@ TODO:
<software name="add_pdrk">
<description>AD&amp;D Pools of Darkness</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="diska.fdi" size="1265664" crc="a40becba" sha1="3c65e5ab1f95d5f9863681c472b8c73927e0a2c2" offset="0" />
</dataarea>
</part>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="diska.fdi" size="1265664" crc="a40becba" sha1="3c65e5ab1f95d5f9863681c472b8c73927e0a2c2" offset="0" />
</dataarea>
</part>
<part name="flop2" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="diskb.fdi" size="1265664" crc="2fb75bcb" sha1="78df14162d4fbd9e6c8f6a67e00d3aed3dd02bc7" offset="0" />
</dataarea>
</part>
<dataarea name="flop" size="1265664">
<rom name="diskb.fdi" size="1265664" crc="2fb75bcb" sha1="78df14162d4fbd9e6c8f6a67e00d3aed3dd02bc7" offset="0" />
</dataarea>
</part>
<part name="flop3" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="opening.fdi" size="1265664" crc="11cf2229" sha1="abf3bed693797d9bfecb1b7dc42eadcfb8a14641" offset="0" />
</dataarea>
</part>
</software>
<dataarea name="flop" size="1265664">
<rom name="opening.fdi" size="1265664" crc="11cf2229" sha1="abf3bed693797d9bfecb1b7dc42eadcfb8a14641" offset="0" />
</dataarea>
</part>
</software>
<software name="add_ssil" supported="no">
<description>AD&amp;D Secret of the Silver Blades</description>
@ -882,7 +882,7 @@ TODO:
<rom name="user.d88" size="0x138fb0" crc="efd89d91" sha1="c243ec20af65ea9f612926c2c8ce868750a076e4" offset="0" status="baddump" />
</dataarea>
</part>
</software>
</software>
<software name="advanp2p">
<description>Advanced Power Dolls 2 Premium Disk</description>
@ -912,9 +912,9 @@ TODO:
</part>
<!-- hacked (and working since it's 2hd floppy) set, not going to be supported however
<part name="flop3" interface="floppy_5_25">
<dataarea name="flop" size="0x1093f0">
<rom name="adventureland 2hd.d88" size="0x1093f0" crc="dfe46669" sha1="ee0e6fae3553f8b60d515ba5c0bfdbe56cb7df16" offset="0" />
</dataarea>
<dataarea name="flop" size="0x1093f0">
<rom name="adventureland 2hd.d88" size="0x1093f0" crc="dfe46669" sha1="ee0e6fae3553f8b60d515ba5c0bfdbe56cb7df16" offset="0" />
</dataarea>
</part>
-->
</software>
@ -1645,16 +1645,16 @@ TODO:
</part>
</software>
<!--
<software name="applec4">
<description> Apple Club - Data Shuu #04 - Tonari no Oneesan Hen</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="?pc98????????1 ????#4.fdi" size="1265664" crc=" ***" sha1="20e87b43 ?CRC32*Apple Club 1\aplclub1.FD" offset="0" />
</dataarea>
</part>
</software>
<software name="applec4">
<description> Apple Club - Data Shuu #04 - Tonari no Oneesan Hen</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="?pc98????????1 ????#4.fdi" size="1265664" crc=" ***" sha1="20e87b43 ?CRC32*Apple Club 1\aplclub1.FD" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="applecl">
<description>Apple Club 1 - Kinjirareta Asobi Series</description>
@ -2041,7 +2041,7 @@ TODO:
</dataarea>
</part>
</software>
<software name="asokono">
<description>Asoko no Koufuku - Yamamoto-san-chi no Baai ni Okeru Asoko no Fukou ni Tsuite</description>
<year>19??</year>
@ -2638,7 +2638,7 @@ TODO:
</dataarea>
</part>
</software>
<software name="bodyins">
<description>Body Inspection in Belloncho</description>
<year>19??</year>
@ -2664,7 +2664,7 @@ TODO:
<rom name="bokosuka.d88" size="0x10f760" crc="d5da4869" sha1="1fd6124180be8f20acd188702e3b9f9c2d128428" offset="0" />
</dataarea>
</part>
</software>
</software>
<software name="bomberq">
<description>Bomber Quest</description>
@ -3093,7 +3093,7 @@ TODO:
</dataarea>
</part>
</software>
<software name="burningd">
<description>Burning Dragon</description>
<year>19??</year>
@ -3257,7 +3257,7 @@ TODO:
</dataarea>
</part>
</software>
<software name="carata" cloneof="carat">
<description>Carat - Magical Blocks(another)</description>
<year>19??</year>
@ -4275,7 +4275,7 @@ TODO:
</part>
</software>
<!--
<!--
Presumably copy protection floppy, to be used with CD-Rom
-->
<software name="debut">
@ -5098,7 +5098,7 @@ Presumably copy protection floppy, to be used with CD-Rom
</part>
</software>
<software name="dragone">
<description>Dragon Egg</description>
<year>19??</year>
@ -5527,16 +5527,16 @@ Presumably copy protection floppy, to be used with CD-Rom
<!--
TODO: missing install disks
<software name="eveber">
<description>Eve - Burst Error</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="dos62.fdi" size="1265664" crc="678b88a7" sha1="480dee4a4df0c588416b0895057caeba862eea7f" offset="0" />
</dataarea>
</part>
</software>
<software name="eveber">
<description>Eve - Burst Error</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="dos62.fdi" size="1265664" crc="678b88a7" sha1="480dee4a4df0c588416b0895057caeba862eea7f" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="f14fd">
@ -5873,30 +5873,30 @@ TODO: missing install disks
<!-- same as all bishoujo extra disk 2 -->
<!--
<software name="floppyb2">
<description>Floppy Bunko 17 - All Bishoujo Art Graphics Vol. 2</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="disk_2.fdi" size="1265664" crc="ee12585b" sha1="941abd888e3ce84c072a28f4cd73b15cb6c8945b" offset="0" />
</dataarea>
</part>
</software>
<software name="floppyb2">
<description>Floppy Bunko 17 - All Bishoujo Art Graphics Vol. 2</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="disk_2.fdi" size="1265664" crc="ee12585b" sha1="941abd888e3ce84c072a28f4cd73b15cb6c8945b" offset="0" />
</dataarea>
</part>
</software>
-->
<!-- same as all bishoujo extra disk 3 -->
<!--
<software name="floppyb3">
<description>Floppy Bunko 20 - All Bishoujo Art Graphics Vol. 3</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="disk_3.fdi" size="1265664" crc="30ae9567" sha1="e46a1cd8fa82a99a497048001b2e6d0268c4a5d6" offset="0" />
</dataarea>
</part>
</software>
<software name="floppyb3">
<description>Floppy Bunko 20 - All Bishoujo Art Graphics Vol. 3</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="disk_3.fdi" size="1265664" crc="30ae9567" sha1="e46a1cd8fa82a99a497048001b2e6d0268c4a5d6" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="foxy">
@ -6429,16 +6429,16 @@ TODO: missing install disks
<!--
Fake disk?
<software name="golflin">
<description>Golf Links 386 Pro</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="golf links 386 pro anex86 cd & hd boot disk.fdi" size="1265664" crc="05559a9e" sha1="77510219ec879af55a90da092e268c5fa4b0257c" offset="0" />
</dataarea>
</part>
</software>
<software name="golflin">
<description>Golf Links 386 Pro</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="golf links 386 pro anex86 cd & hd boot disk.fdi" size="1265664" crc="05559a9e" sha1="77510219ec879af55a90da092e268c5fa4b0257c" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="golflpr">
<description>Golf Links Champion Course Pinehurst Resort and Country Ciub</description>
@ -6814,7 +6814,7 @@ Fake disk?
</software>
<!--
Game is named "image", with lowercase i on title screen
Game is named "image", with lowercase i on title screen
-->
<software name="image">
<description>image</description>
@ -7310,16 +7310,16 @@ Game is named "image", with lowercase i on title screen
<!--
TODO: other two disks, in .nfd format
<software name="kawaisou">
<description>Kawaisou Monogatari</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="user.fdi" size="1265664" crc="6c424c81" sha1="5feb465c5178534a575b555eeeabacae36b9f650" offset="0" status="baddump" />
</dataarea>
</part>
</software>
<software name="kawaisou">
<description>Kawaisou Monogatari</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="user.fdi" size="1265664" crc="6c424c81" sha1="5feb465c5178534a575b555eeeabacae36b9f650" offset="0" status="baddump" />
</dataarea>
</part>
</software>
-->
<software name="kerakera">
<description>Kerakera-sei</description>
@ -8279,7 +8279,7 @@ TODO: other two disks, in .nfd format
</dataarea>
</part>
</software>
<software name="madouars">
<description>Madou Monogatari A-R-S</description>
<year>19??</year>
@ -8465,16 +8465,16 @@ TODO: other two disks, in .nfd format
</software>
<!-- TODO: another .nfd floppy used
<software name="mtaikai">
<description>Mahjong Taikai</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="user.fdi" size="1265664" crc="fca4122d" sha1="6797330e0237af84f1f4f112704034281834c97b" offset="0" status="baddump" />
</dataarea>
</part>
</software>
<software name="mtaikai">
<description>Mahjong Taikai</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="user.fdi" size="1265664" crc="fca4122d" sha1="6797330e0237af84f1f4f112704034281834c97b" offset="0" status="baddump" />
</dataarea>
</part>
</software>
-->
<software name="mahoush">
<description>Mahou Shoujo Rina</description>
@ -8736,16 +8736,16 @@ TODO: other two disks, in .nfd format
</software>
<!-- same as disk 02 fugasel1
<software name="mazeque">
<description>Maze Quest</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="maze quest.fdi" size="1265664" crc="3949e01a" sha1="9ee3c3dac883036375c69192fd98af11695ffea8" offset="0" />
</dataarea>
</part>
</software>
<software name="mazeque">
<description>Maze Quest</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="maze quest.fdi" size="1265664" crc="3949e01a" sha1="9ee3c3dac883036375c69192fd98af11695ffea8" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="meikyuu">
@ -9072,16 +9072,16 @@ TODO: other two disks, in .nfd format
<!--
Omake disk?
<software name="mime">
<description>Mime</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="special.fdi" size="1265664" crc="7a3b8749" sha1="2ed561501500af290bd09e09e523d934c9ba7b5c" offset="0" />
</dataarea>
</part>
</software>
<software name="mime">
<description>Mime</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="special.fdi" size="1265664" crc="7a3b8749" sha1="2ed561501500af290bd09e09e523d934c9ba7b5c" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="mink01">
@ -9222,7 +9222,7 @@ Omake disk?
</part>
</software>
<!--
<!--
Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
-->
<software name="gundamao" supported="no">
@ -9753,18 +9753,18 @@ Requires MS-DOS 5.00H plus an unknown procedure (HDD install?)
</part>
</software>
<!--
<!--
Other three disks, in nfd format
<software name="n88bas61">
<description>N88 BASIC v6.1</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="rx_train.fdi" size="1265664" crc="607b85f8" sha1="0d2fdf6f0550e50127b27b42b470ba25b305239c" offset="0" />
</dataarea>
</part>
</software>
<software name="n88bas61">
<description>N88 BASIC v6.1</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="rx_train.fdi" size="1265664" crc="607b85f8" sha1="0d2fdf6f0550e50127b27b42b470ba25b305239c" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="nadiamw">
@ -9780,16 +9780,16 @@ Other three disks, in nfd format
<!--
other two disks
<software name="narumah">
<description>Naru Mahjong</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="disk01.fdi" size="1265664" crc="d2db97c6" sha1="06910b3812d6efbac4f0b6adb9767397f2b590d7" offset="0" />
</dataarea>
</part>
</software>
<software name="narumah">
<description>Naru Mahjong</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="disk01.fdi" size="1265664" crc="d2db97c6" sha1="06910b3812d6efbac4f0b6adb9767397f2b590d7" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="natsudam">
@ -9834,7 +9834,7 @@ other two disks
</dataarea>
</part>
</software>
<software name="nazopds7">
<description>Nazo Puyo (off DS7)</description>
<year>19??</year>
@ -12152,16 +12152,16 @@ other two disks
</part>
</software>
<!--
<software name="rougeno">
<description>Rouge no Densetsu (hdi)</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="kidou.fdi" size="1265664" crc="e0b52ce7" sha1="00ed12fdff1986986e347343d9176f6205d5d87c" offset="0" />
</dataarea>
</part>
</software>
<software name="rougeno">
<description>Rouge no Densetsu (hdi)</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="kidou.fdi" size="1265664" crc="e0b52ce7" sha1="00ed12fdff1986986e347343d9176f6205d5d87c" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="roundwar">
<description>Round Warrior</description>
@ -12763,41 +12763,41 @@ other two disks
<!--
Same as Police Quest 2 - Quest for Glory stand-alone disks
<software name="sierradp">
<description>Sierra 3D AVG Double Pack - Quest for Glory &amp; Police Quest 2</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="police quest ii disk 01.fdi" size="1265664" crc="18f51678" sha1="49b137412230d20df0dec0c1236866003a3f1f15" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="police quest ii disk 02.fdi" size="1265664" crc="3fd79ed8" sha1="6893264fd7ecdbf8ceb14d2e62d76bb548fb344e" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="police quest ii disk 03.fdi" size="1265664" crc="4c6f0d6a" sha1="442e4f2074087b5d8401f808153a12ffef9a6e7c" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="quest for glory disk 01.fdi" size="1265664" crc="695c079e" sha1="93195094944af1d88338c4a2ce82f9188a7f3898" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="quest for glory disk 02.fdi" size="1265664" crc="b8cdbf73" sha1="d6048c691963d159ce29c9e90b0f33a60e71c29d" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="quest for glory disk 03.fdi" size="1265664" crc="10f50bfa" sha1="7aab2821b8a18ef3ec4811d6c8e50767f96f0108" offset="0" />
</dataarea>
</part>
</software>
<software name="sierradp">
<description>Sierra 3D AVG Double Pack - Quest for Glory &amp; Police Quest 2</description>
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="police quest ii disk 01.fdi" size="1265664" crc="18f51678" sha1="49b137412230d20df0dec0c1236866003a3f1f15" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="police quest ii disk 02.fdi" size="1265664" crc="3fd79ed8" sha1="6893264fd7ecdbf8ceb14d2e62d76bb548fb344e" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="police quest ii disk 03.fdi" size="1265664" crc="4c6f0d6a" sha1="442e4f2074087b5d8401f808153a12ffef9a6e7c" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="quest for glory disk 01.fdi" size="1265664" crc="695c079e" sha1="93195094944af1d88338c4a2ce82f9188a7f3898" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="quest for glory disk 02.fdi" size="1265664" crc="b8cdbf73" sha1="d6048c691963d159ce29c9e90b0f33a60e71c29d" offset="0" />
</dataarea>
</part>
<part name="flop1" interface="floppy_5_25">
<dataarea name="flop" size="1265664">
<rom name="quest for glory disk 03.fdi" size="1265664" crc="10f50bfa" sha1="7aab2821b8a18ef3ec4811d6c8e50767f96f0108" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="simcity">
@ -14988,7 +14988,7 @@ Same as Police Quest 2 - Quest for Glory stand-alone disks
</dataarea>
</part>
</software>
<software name="vg2">
<description>Variable Geo 2 - The Bout of Cabalistic Goddess</description>
<year>19??</year>
@ -16508,7 +16508,7 @@ Same as Police Quest 2 - Quest for Glory stand-alone disks
</dataarea>
</part>
</software>
<software name="artemis">
<description>Artemis</description>
<year>19??</year>

2
hash/visicom.xml
View File

@ -8,7 +8,7 @@ _________________________________________________________________
CAS-110 Arithmetic Drill (Math Fun & Fun with Numbers) no 算数ドリル
CAS-130 Sports Fan (Baseball & Sumo Wrestling) yes スポーツファン
CAS-140 Gambler I (Blackjack) no ギャンブラーI
CAS-140 Gambler I (Blackjack) no ギャンブラーI
CAS-141 Gambler II (Slot Machine and Dice) no ギャンブラーII
CAS-160 Space Command (Space War) no スペースコマンド
CAS-190 Inspiration (Bagua and Biorhythm) no 霊感

4
src/emu/clifront.c
View File

@ -619,7 +619,7 @@ void cli_frontend::listdevices(const char *gamename)
// sort them by tag
qsort(&device_list[0], device_list.count(), sizeof(device_list[0]), compare_devices);
// dump the results
for (int index = 0; index < device_list.count(); index++)
{
@ -629,7 +629,7 @@ void cli_frontend::listdevices(const char *gamename)
const char *tag = device->tag();
if (*tag == ':')
tag++;
// determine the depth
int depth = 1;
if (*tag == 0)

4
src/emu/cpu/cpu.mak
View File

@ -726,8 +726,8 @@ $(CPUOBJ)/i8085/i8085.o: $(CPUSRC)/i8085/i8085.c \
ifneq ($(filter I8089,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/i8089
CPUOBJS += $(CPUOBJ)/i8089/i8089.o \
$(CPUOBJ)/i8089/i8089_channel.o \
$(CPUOBJ)/i8089/i8089_ops.o
$(CPUOBJ)/i8089/i8089_channel.o \
$(CPUOBJ)/i8089/i8089_ops.o
DASMOBJS += $(CPUOBJ)/i8089/i8089_dasm.o
endif

15
src/emu/cpu/cubeqcpu/cubeqcpu.c
View File

@ -111,8 +111,8 @@ offs_t cquestrot_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const U
cquestlin_cpu_device::cquestlin_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, CQUESTLIN, "Cube Quest Line CPU", tag, owner, clock, "cquestlin", __FILE__)
, m_program_config("program", ENDIANNESS_BIG, 64, 8, -3)
: cpu_device(mconfig, CQUESTLIN, "Cube Quest Line CPU", tag, owner, clock, "cquestlin", __FILE__)
, m_program_config("program", ENDIANNESS_BIG, 64, 8, -3)
, m_linedata_r(*this)
, m_flags(0)
, m_curpc(0)
@ -358,8 +358,8 @@ void cquestrot_cpu_device::state_string_export(const device_state_entry &entry,
{
case STATE_GENFLAGS:
string.printf( "%c%c%c", m_cflag ? 'C' : '.',
m_vflag ? 'V' : '.',
m_f ? '.' : 'Z');
m_vflag ? 'V' : '.',
m_f ? '.' : 'Z');
break;
}
}
@ -488,9 +488,9 @@ void cquestlin_cpu_device::state_string_export(const device_state_entry &entry,
{
case STATE_GENFLAGS:
string.printf( "%c%c%c|%cG", m_cflag ? 'C' : '.',
m_vflag ? 'V' : '.',
m_f ? '.' : 'Z',
( m_clkcnt & 3 ) ? 'B' : 'F');
m_vflag ? 'V' : '.',
m_f ? '.' : 'Z',
( m_clkcnt & 3 ) ? 'B' : 'F');
break;
}
}
@ -1551,4 +1551,3 @@ void cquestlin_cpu_device::execute_run()
m_clkcnt++;
} while (m_icount > 0);
}

12
src/emu/cpu/es5510/es5510.c
View File

@ -168,7 +168,7 @@ es5510_device::es5510_device(const machine_config &mconfig, const char *tag, dev
instr_latch = 0;
ram_sel = 0;
host_control = 0;
pc = 0;
memset(&alu, 0, sizeof(alu));
memset(&mulacc, 0, sizeof(mulacc));
@ -606,7 +606,7 @@ void es5510_device::list_program(void(p)(const char *, ...)) {
is_written[i] = is_read[i] = false;
name[i][0] = '\0';
}
for (addr = 0; addr < 0xa0; addr++) {
DESCRIBE_INSTR(buf, instr[addr], gpr[addr], NULL, NULL, NULL, NULL);
UINT64 inst = instr[addr];
@ -621,7 +621,7 @@ void es5510_device::list_program(void(p)(const char *, ...)) {
}
UINT8 operandSelect = (UINT8)((inst >> 8) & 0x0f);
const op_select_t &opSelect = OPERAND_SELECT[operandSelect];
const op_select_t &opSelect = OPERAND_SELECT[operandSelect];
if (opSelect.mac_src == SRC_DST_REG) {
is_read[cReg] = true;
@ -630,7 +630,7 @@ void es5510_device::list_program(void(p)(const char *, ...)) {
if (opSelect.mac_dst != SRC_DST_DELAY) { // either REG or BOTH
is_written[cReg] = true;
}
alu_op_t aluOp = ALU_OPS[alu_op];
if (aluOp.operands == 1) {
if (opSelect.alu_src == SRC_DST_REG) {
@ -663,7 +663,7 @@ void es5510_device::list_program(void(p)(const char *, ...)) {
for (int i = 0xc0; i < 0x100; i++) {
name[i][0] = 0;
}
for (addr = 0; addr < 0xa0; addr++) {
UINT8 aReg = (UINT8)((instr[addr] >> 16) & 0xff);
UINT8 bReg = (UINT8)((instr[addr] >> 24) & 0xff);
@ -830,7 +830,7 @@ void es5510_device::execute_run() {
// *** T2, clock high
LOG_EXEC(("- T2.1\n"));
// --- Write ALU Result N-1
LOG_EXEC((". write ALU:\n"));
if (alu.write_result) {

8
src/emu/cpu/es5510/es5510.h
View File

@ -152,8 +152,8 @@ private:
INT16 ser2l;
INT16 ser3r;
INT16 ser3l;
INT64 machl; // 48 bits, right justified and sign extended
bool mac_overflow; // whether reading the MAC register should return a saturated replacement value
INT64 machl; // 48 bits, right justified and sign extended
bool mac_overflow; // whether reading the MAC register should return a saturated replacement value
INT32 dil;
INT32 memsiz;
INT32 memmask;
@ -165,8 +165,8 @@ private:
INT32 dbase;
INT32 sigreg;
int mulshift;
INT8 ccr; // really, 5 bits, left justified
INT8 cmr; // really, 6 bits, left justified
INT8 ccr; // really, 5 bits, left justified
INT8 cmr; // really, 6 bits, left justified
INT32 dol[2];
int dol_count;

14
src/emu/cpu/f8/f8.c
View File

@ -1601,7 +1601,7 @@ void f8_cpu_device::device_reset()
m_irq_vector = 0;
memset(m_r, 0, sizeof(m_r));
m_irq_request = 0;
m_w&=~I;
/* save PC0 to PC1 and reset PC0 */
@ -2054,11 +2054,11 @@ void f8_cpu_device::state_string_export(const device_state_entry &entry, astring
{
case STATE_GENFLAGS:
string.printf("%c%c%c%c%c",
m_w & 0x10 ? 'I':'.',
m_w & 0x08 ? 'O':'.',
m_w & 0x04 ? 'Z':'.',
m_w & 0x02 ? 'C':'.',
m_w & 0x01 ? 'S':'.');
m_w & 0x10 ? 'I':'.',
m_w & 0x08 ? 'O':'.',
m_w & 0x04 ? 'Z':'.',
m_w & 0x02 ? 'C':'.',
m_w & 0x01 ? 'S':'.');
break;
}
}
@ -2075,5 +2075,3 @@ void f8_cpu_device::execute_set_input( int inptnum, int state )
{
m_irq_request = state;
}

1
src/emu/cpu/i8085/i8085.c
View File

@ -1133,4 +1133,3 @@ offs_t i8085a_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT
extern CPU_DISASSEMBLE( i8085 );
return CPU_DISASSEMBLE_NAME(i8085)(this, buffer, pc, oprom, opram, options);
}

14
src/emu/cpu/i8089/i8089.h
View File

@ -121,14 +121,14 @@ private:
SOC,
DIVIDER1,
CH1_GA, CH1_GB, CH1_GC,
CH1_TP, CH1_BC, CH1_IX,
CH1_CC, CH1_MC, CH1_CP,
CH1_PP, CH1_PSW,
CH1_TP, CH1_BC, CH1_IX,
CH1_CC, CH1_MC, CH1_CP,
CH1_PP, CH1_PSW,
DIVIDER2,
CH2_GA, CH2_GB, CH2_GC,
CH2_TP, CH2_BC, CH2_IX,
CH2_CC, CH2_MC, CH2_CP,
CH2_PP, CH2_PSW
CH2_GA, CH2_GB, CH2_GC,
CH2_TP, CH2_BC, CH2_IX,
CH2_CC, CH2_MC, CH2_CP,
CH2_PP, CH2_PSW
};
// system configuration

20
src/emu/cpu/i8089/i8089_channel.c
View File

@ -19,16 +19,16 @@
#define VERBOSE_DMA 1
// channel control register fields
#define CC_TMC ((m_r[CC].w >> 0) & 0x07) // terminate on masked compare
#define CC_TBC ((m_r[CC].w >> 3) & 0x03) // terminate on byte count
#define CC_TX ((m_r[CC].w >> 5) & 0x03) // terminate on external signal
#define CC_TS ((m_r[CC].w >> 7) & 0x01) // terminate on single transfer
#define CC_CHAIN ((m_r[CC].w >> 8) & 0x01) // chaining
#define CC_LOCK ((m_r[CC].w >> 9) & 0x01) // actuate lock
#define CC_SOURCE ((m_r[CC].w >> 10) & 0x01) // source register
#define CC_SYNC ((m_r[CC].w >> 11) & 0x03) // synchronization
#define CC_TRANS ((m_r[CC].w >> 13) & 0x01) // translation
#define CC_FUNC ((m_r[CC].w >> 14) & 0x03) // function
#define CC_TMC ((m_r[CC].w >> 0) & 0x07) // terminate on masked compare
#define CC_TBC ((m_r[CC].w >> 3) & 0x03) // terminate on byte count
#define CC_TX ((m_r[CC].w >> 5) & 0x03) // terminate on external signal
#define CC_TS ((m_r[CC].w >> 7) & 0x01) // terminate on single transfer
#define CC_CHAIN ((m_r[CC].w >> 8) & 0x01) // chaining
#define CC_LOCK ((m_r[CC].w >> 9) & 0x01) // actuate lock
#define CC_SOURCE ((m_r[CC].w >> 10) & 0x01) // source register
#define CC_SYNC ((m_r[CC].w >> 11) & 0x03) // synchronization
#define CC_TRANS ((m_r[CC].w >> 13) & 0x01) // translation
#define CC_FUNC ((m_r[CC].w >> 14) & 0x03) // function
//**************************************************************************

2
src/emu/cpu/i8089/i8089_ops.c
View File

@ -2,7 +2,7 @@
Intel 8089 I/O Processor
Opcode implementations
Opcode implementations
***************************************************************************/

4
src/emu/cpu/i86/i186.c
View File

@ -1284,8 +1284,8 @@ void i80186_cpu_device::drq_callback(int which)
update_interrupt_state();
}
// dma->finish_timer->adjust(attotime::from_hz(clock()/8), 0);
// dma->drq_delay = true;
// dma->finish_timer->adjust(attotime::from_hz(clock()/8), 0);
// dma->drq_delay = true;
}
READ16_MEMBER(i80186_cpu_device::internal_port_r)

1
src/emu/cpu/i86/i286.c
View File

@ -1956,4 +1956,3 @@ void i80286_cpu_device::check_permission(UINT8 check_seg, UINT32 offset, UINT16
throw TRAP(trap, 0);
}
}

2
src/emu/cpu/i86/i286.h
View File

@ -7,7 +7,7 @@
extern const device_type I80286;
enum
{ // same order as I8086 registers
{ // same order as I8086 registers
I286_PC = 0,
I286_IP,

7
src/emu/cpu/i860/i860.c
View File

@ -139,9 +139,9 @@ void i860_cpu_device::device_start()
void i860_cpu_device::state_import(const device_state_entry &entry)
{
#define I860_SET_INFO_F(fnum) m_frg[0+(4*fnum)] = (m_freg[fnum] & 0x000000ff); \
m_frg[1+(4*fnum)] = (m_freg[fnum] & 0x0000ff00) >> 8; \
m_frg[2+(4*fnum)] = (m_freg[fnum] & 0x00ff0000) >> 16; \
m_frg[3+(4*fnum)] = (m_freg[fnum] & 0xff000000) >> 24;
m_frg[1+(4*fnum)] = (m_freg[fnum] & 0x0000ff00) >> 8; \
m_frg[2+(4*fnum)] = (m_freg[fnum] & 0x00ff0000) >> 16; \
m_frg[3+(4*fnum)] = (m_freg[fnum] & 0xff000000) >> 24;
switch (entry.index())
{
@ -238,4 +238,3 @@ offs_t i860_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
* The actual decode and execute code.
**************************************************************************/
#include "i860dec.c"

10
src/emu/cpu/i860/i860dec.c
View File

@ -285,11 +285,11 @@ void i860_cpu_device::set_fregval_d (int fr, double d)
int i860_cpu_device::has_delay_slot(UINT32 insn)
{
int opc = (insn >> 26) & 0x3f;
if (opc == 0x10 || opc == 0x1a || opc == 0x1b || opc == 0x1d ||
opc == 0x1f || opc == 0x2d || (opc == 0x13 && (insn & 3) == 2))
return 1;
return 0;
int opc = (insn >> 26) & 0x3f;
if (opc == 0x10 || opc == 0x1a || opc == 0x1b || opc == 0x1d ||
opc == 0x1f || opc == 0x2d || (opc == 0x13 && (insn & 3) == 2))
return 1;
return 0;
}
/* This is the external interface for asserting/deasserting pins on

2
src/emu/cpu/i960/i960.c
View File

@ -2077,7 +2077,6 @@ void i960_cpu_device::device_start()
void i960_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
{
static const char *const conditions[8] =
{
"no", "g", "e", "ge", "l", "ne", "le", "o"
@ -2116,4 +2115,3 @@ offs_t i960_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
extern CPU_DISASSEMBLE( i960 );
return CPU_DISASSEMBLE_NAME(i960)(this, buffer, pc, oprom, opram, options);
}

3
src/emu/cpu/jaguar/jaguar.c
View File

@ -416,7 +416,7 @@ void jaguar_cpu_device::state_string_export(const device_state_entry &entry, ast
FLAGS & 0x0008 ? 'I':'.',
FLAGS & 0x0004 ? 'N':'.',
FLAGS & 0x0002 ? 'C':'.',
FLAGS & 0x0001 ? 'Z':'.');
FLAGS & 0x0001 ? 'Z':'.');
break;
}
}
@ -1447,4 +1447,3 @@ offs_t jaguardsp_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const U
extern CPU_DISASSEMBLE( jaguardsp );
return CPU_DISASSEMBLE_NAME(jaguardsp)(this, buffer, pc, oprom, opram, options);
}

1
src/emu/cpu/lh5801/lh5801.c
View File

@ -264,4 +264,3 @@ offs_t lh5801_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT
extern CPU_DISASSEMBLE( lh5801 );
return CPU_DISASSEMBLE_NAME(lh5801)(this, buffer, pc, oprom, opram, options);
}

2
src/emu/cpu/m37710/m37710.h
View File

@ -161,7 +161,7 @@ private:
address_space *m_program;
address_space *m_io;
UINT32 m_stopped; /* Sets how the CPU is stopped */
// on-board peripheral stuff
UINT8 m_m37710_regs[128];
attotime m_reload[8];

15
src/emu/cpu/m6800/m6800.c
View File

@ -1708,17 +1708,17 @@ WRITE8_MEMBER( m6800_cpu_device::m6801_io_w )
}
}
void m6801_cpu_device::m6801_clock_serial()
{
void m6801_cpu_device::m6801_clock_serial()
{
if (m_use_ext_serclock)
{
m_ext_serclock++;
m_ext_serclock++;
if (m_ext_serclock >= 8)
{
m_ext_serclock = 0;
serial_transmit();
serial_receive();
{
m_ext_serclock = 0;
serial_transmit();
serial_receive();
}
}
}
@ -1777,4 +1777,3 @@ offs_t nsc8105_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UIN
extern CPU_DISASSEMBLE( nsc8105 );
return CPU_DISASSEMBLE_NAME(nsc8105)(this, buffer, pc, oprom, opram, options);
}

2
src/emu/cpu/m6800/m6800.h
View File

@ -139,7 +139,7 @@ protected:
int m_clock_divider;
UINT8 m_trcsr, m_rmcr, m_rdr, m_tdr, m_rsr, m_tsr;
int m_rxbits, m_txbits, m_txstate, m_trcsr_read_tdre, m_trcsr_read_orfe, m_trcsr_read_rdrf, m_tx, m_ext_serclock;
bool m_use_ext_serclock;
bool m_use_ext_serclock;
int m_port2_written;
int m_icount;

12
src/emu/cpu/m68000/m68k_in.c
View File

@ -3897,9 +3897,9 @@ M68KMAKE_OP(clr, 8, ., .)
{
UINT32 ea = M68KMAKE_GET_EA_AY_8;
if(CPU_TYPE_IS_010_LESS((mc68kcpu)->cpu_type))
if(CPU_TYPE_IS_010_LESS((mc68kcpu)->cpu_type))
{
m68ki_read_8((mc68kcpu), ea); /* the 68000 (and 010?) does a dummy read, the value is discarded */
m68ki_read_8((mc68kcpu), ea); /* the 68000 (and 010?) does a dummy read, the value is discarded */
}
m68ki_write_8((mc68kcpu), ea, 0);
@ -3926,9 +3926,9 @@ M68KMAKE_OP(clr, 16, ., .)
{
UINT32 ea = M68KMAKE_GET_EA_AY_16;
if(CPU_TYPE_IS_010_LESS((mc68kcpu)->cpu_type))
if(CPU_TYPE_IS_010_LESS((mc68kcpu)->cpu_type))
{
m68ki_read_16((mc68kcpu), ea); /* the 68000 (and 010?) does a dummy read, the value is discarded */
m68ki_read_16((mc68kcpu), ea); /* the 68000 (and 010?) does a dummy read, the value is discarded */
}
m68ki_write_16((mc68kcpu), ea, 0);
@ -3955,9 +3955,9 @@ M68KMAKE_OP(clr, 32, ., .)
{
UINT32 ea = M68KMAKE_GET_EA_AY_32;
if(CPU_TYPE_IS_010_LESS((mc68kcpu)->cpu_type))
if(CPU_TYPE_IS_010_LESS((mc68kcpu)->cpu_type))
{
m68ki_read_32((mc68kcpu), ea); /* the 68000 (and 010?) does a dummy read, the value is discarded */
m68ki_read_32((mc68kcpu), ea); /* the 68000 (and 010?) does a dummy read, the value is discarded */
}
m68ki_write_32((mc68kcpu), ea, 0);

3
src/emu/cpu/mb86233/mb86233.c
View File

@ -96,7 +96,7 @@ void mb86233_cpu_device::device_start()
m_fifo_read_cb.resolve_safe(0);
m_fifo_read_ok_cb.resolve_safe(0);
m_fifo_write_cb.resolve_safe();
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
@ -1582,4 +1582,3 @@ void mb86233_cpu_device::execute_run()
}
}
}

9
src/emu/cpu/mb88xx/mb88xx.c
View File

@ -114,25 +114,25 @@ mb88_cpu_device::mb88_cpu_device(const machine_config &mconfig, device_type type
mb8841_cpu_device::mb8841_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: mb88_cpu_device(mconfig, MB8841, "MB8841", tag, owner, clock, "mb8841", __FILE__, 11, 7)
: mb88_cpu_device(mconfig, MB8841, "MB8841", tag, owner, clock, "mb8841", __FILE__, 11, 7)
{
}
mb8842_cpu_device::mb8842_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: mb88_cpu_device(mconfig, MB8842, "MB8842", tag, owner, clock, "mb8842", __FILE__, 11, 7)
: mb88_cpu_device(mconfig, MB8842, "MB8842", tag, owner, clock, "mb8842", __FILE__, 11, 7)
{
}
mb8843_cpu_device::mb8843_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: mb88_cpu_device(mconfig, MB8843, "MB8843", tag, owner, clock, "mb8843", __FILE__, 10, 6)
: mb88_cpu_device(mconfig, MB8843, "MB8843", tag, owner, clock, "mb8843", __FILE__, 10, 6)
{
}
mb8844_cpu_device::mb8844_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: mb88_cpu_device(mconfig, MB8844, "MB8844", tag, owner, clock, "mb8844", __FILE__, 10, 6)
: mb88_cpu_device(mconfig, MB8844, "MB8844", tag, owner, clock, "mb8844", __FILE__, 10, 6)
{
}
@ -946,4 +946,3 @@ void mb88_cpu_device::execute_run()
update_pio(oc);
}
}

16
src/emu/cpu/mb88xx/mb88xx.h
View File

@ -158,32 +158,32 @@ private:
class mb8841_cpu_device : public mb88_cpu_device
{
public:
// construction/destruction
mb8841_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// construction/destruction
mb8841_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class mb8842_cpu_device : public mb88_cpu_device
{
public:
// construction/destruction
mb8842_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// construction/destruction
mb8842_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class mb8843_cpu_device : public mb88_cpu_device
{
public:
// construction/destruction
mb8843_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// construction/destruction
mb8843_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class mb8844_cpu_device : public mb88_cpu_device
{
public:
// construction/destruction
mb8844_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// construction/destruction
mb8844_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};

1
src/emu/cpu/mc68hc11/mc68hc11.c
View File

@ -595,4 +595,3 @@ void mc68hc11_cpu_device::execute_run()
(this->*hc11_optable[op])();
}
}

1
src/emu/cpu/mcs48/mcs48.c
View File

@ -1330,4 +1330,3 @@ void mcs48_cpu_device::execute_set_input(int inputnum, int state)
break;
}
}

12
src/emu/cpu/mcs48/mcs48.h
View File

@ -484,9 +484,9 @@ public:
i8021_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
// device_execute_interface overrides
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); }
// device_execute_interface overrides
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); }
};
class i8022_device : public mcs48_cpu_device
@ -496,9 +496,9 @@ public:
i8022_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
// device_execute_interface overrides
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); }
// device_execute_interface overrides
virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 30 - 1) / 30; }
virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 30); }
};
class i8035_device : public mcs48_cpu_device

1
src/emu/cpu/mcs51/mcs51.c
View File

@ -2506,4 +2506,3 @@ offs_t ds5002fp_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
extern CPU_DISASSEMBLE( ds5002fp );
return CPU_DISASSEMBLE_NAME(ds5002fp)(this, buffer, pc, oprom, opram, options);
}

1
src/emu/cpu/minx/minx.c
View File

@ -236,4 +236,3 @@ offs_t minx_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
extern CPU_DISASSEMBLE( minx );
return CPU_DISASSEMBLE_NAME(minx)(this, buffer, pc, oprom, opram, options);
}

4
src/emu/cpu/minx/minx.h
View File

@ -880,8 +880,8 @@ private:
static const op_func insnminx_CE[256];
static const int insnminx_cycles_CE[256];
static const op_func insnminx_CF[256];
static const int insnminx_cycles_CF[256];
static const op_func insnminx_CF[256];
static const int insnminx_cycles_CF[256];
};

3
src/emu/cpu/mips/mips3drc.c
View File

@ -3934,7 +3934,7 @@ CPU_GET_INFO( r4700le_drc )
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "R4700 (little) DRC"); break;
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4700le_drc"); break;
/* --- everything else is handled generically --- */
default: CPU_GET_INFO_CALL(mips3); break;
}
@ -4124,4 +4124,3 @@ DEFINE_LEGACY_CPU_DEVICE(QED5271LE_DRC, qed5271le_drc);
DEFINE_LEGACY_CPU_DEVICE(RM7000BE_DRC, rm7000be_drc);
DEFINE_LEGACY_CPU_DEVICE(RM7000LE_DRC, rm7000le_drc);

2
src/emu/cpu/mn10200/mn10200.c
View File

@ -2436,5 +2436,3 @@ offs_t mn10200_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *
extern CPU_DISASSEMBLE( mn10200 );
return CPU_DISASSEMBLE_NAME(mn10200)(this, buffer, pc, oprom, opram, options);
}

2
src/emu/cpu/nec/v25.c
View File

@ -711,7 +711,7 @@ static CPU_GET_INFO( v25v35 )
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &nec_state->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "NEC"); break;
case CPUINFO_STR_NAME: strcpy(info->s, "NEC"); break;
case CPUINFO_STR_FAMILY: strcpy(info->s, "NEC V-Series"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "2.0"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;

69
src/emu/cpu/pic16c5x/pic16c5x.c
View File

@ -703,78 +703,78 @@ void pic16c5x_device::xorwf()
const pic16c5x_device::pic16c5x_opcode pic16c5x_device::s_opcode_main[256]=
{
/*00*/ {1, &pic16c5x_device::nop },{0, &pic16c5x_device::illegal },{1, &pic16c5x_device::movwf },{1, &pic16c5x_device::movwf },
{1, &pic16c5x_device::clrw },{0, &pic16c5x_device::illegal },{1, &pic16c5x_device::clrf },{1, &pic16c5x_device::clrf },
{1, &pic16c5x_device::clrw },{0, &pic16c5x_device::illegal },{1, &pic16c5x_device::clrf },{1, &pic16c5x_device::clrf },
/*08*/ {1, &pic16c5x_device::subwf },{1, &pic16c5x_device::subwf },{1, &pic16c5x_device::subwf },{1, &pic16c5x_device::subwf },
{1, &pic16c5x_device::decf },{1, &pic16c5x_device::decf },{1, &pic16c5x_device::decf },{1, &pic16c5x_device::decf },
{1, &pic16c5x_device::decf },{1, &pic16c5x_device::decf },{1, &pic16c5x_device::decf },{1, &pic16c5x_device::decf },
/*10*/ {1, &pic16c5x_device::iorwf },{1, &pic16c5x_device::iorwf },{1, &pic16c5x_device::iorwf },{1, &pic16c5x_device::iorwf },
{1, &pic16c5x_device::andwf },{1, &pic16c5x_device::andwf },{1, &pic16c5x_device::andwf },{1, &pic16c5x_device::andwf },
{1, &pic16c5x_device::andwf },{1, &pic16c5x_device::andwf },{1, &pic16c5x_device::andwf },{1, &pic16c5x_device::andwf },
/*18*/ {1, &pic16c5x_device::xorwf },{1, &pic16c5x_device::xorwf },{1, &pic16c5x_device::xorwf },{1, &pic16c5x_device::xorwf },
{1, &pic16c5x_device::addwf },{1, &pic16c5x_device::addwf },{1, &pic16c5x_device::addwf },{1, &pic16c5x_device::addwf },
{1, &pic16c5x_device::addwf },{1, &pic16c5x_device::addwf },{1, &pic16c5x_device::addwf },{1, &pic16c5x_device::addwf },
/*20*/ {1, &pic16c5x_device::movf },{1, &pic16c5x_device::movf },{1, &pic16c5x_device::movf },{1, &pic16c5x_device::movf },
{1, &pic16c5x_device::comf },{1, &pic16c5x_device::comf },{1, &pic16c5x_device::comf },{1, &pic16c5x_device::comf },
{1, &pic16c5x_device::comf },{1, &pic16c5x_device::comf },{1, &pic16c5x_device::comf },{1, &pic16c5x_device::comf },
/*28*/ {1, &pic16c5x_device::incf },{1, &pic16c5x_device::incf },{1, &pic16c5x_device::incf },{1, &pic16c5x_device::incf },
{1, &pic16c5x_device::decfsz },{1, &pic16c5x_device::decfsz },{1, &pic16c5x_device::decfsz },{1, &pic16c5x_device::decfsz },
{1, &pic16c5x_device::decfsz },{1, &pic16c5x_device::decfsz },{1, &pic16c5x_device::decfsz },{1, &pic16c5x_device::decfsz },
/*30*/ {1, &pic16c5x_device::rrf },{1, &pic16c5x_device::rrf },{1, &pic16c5x_device::rrf },{1, &pic16c5x_device::rrf },
{1, &pic16c5x_device::rlf },{1, &pic16c5x_device::rlf },{1, &pic16c5x_device::rlf },{1, &pic16c5x_device::rlf },
{1, &pic16c5x_device::rlf },{1, &pic16c5x_device::rlf },{1, &pic16c5x_device::rlf },{1, &pic16c5x_device::rlf },
/*38*/ {1, &pic16c5x_device::swapf },{1, &pic16c5x_device::swapf },{1, &pic16c5x_device::swapf },{1, &pic16c5x_device::swapf },
{1, &pic16c5x_device::incfsz },{1, &pic16c5x_device::incfsz },{1, &pic16c5x_device::incfsz },{1, &pic16c5x_device::incfsz },
{1, &pic16c5x_device::incfsz },{1, &pic16c5x_device::incfsz },{1, &pic16c5x_device::incfsz },{1, &pic16c5x_device::incfsz },
/*40*/ {1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },
{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },
{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },
/*48*/ {1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },
{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },
{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },{1, &pic16c5x_device::bcf },
/*50*/ {1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },
{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },
{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },
/*58*/ {1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },
{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },
{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },{1, &pic16c5x_device::bsf },
/*60*/ {1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },
{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },
{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },
/*68*/ {1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },
{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },
{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },{1, &pic16c5x_device::btfsc },
/*70*/ {1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },
{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },
{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },
/*78*/ {1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },
{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },
{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },{1, &pic16c5x_device::btfss },
/*80*/ {2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },
{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },
{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },
/*88*/ {2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },
{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },
{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },{2, &pic16c5x_device::retlw },
/*90*/ {2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },
{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },
{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },
/*98*/ {2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },
{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },
{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },{2, &pic16c5x_device::call },
/*A0*/ {2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
/*A8*/ {2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
/*B0*/ {2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
/*B8*/ {2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },{2, &pic16c5x_device::goto_op },
/*C0*/ {1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },
{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },
{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },
/*C8*/ {1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },
{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },
{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },{1, &pic16c5x_device::movlw },
/*D0*/ {1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },
{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },
{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },
/*D8*/ {1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },
{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },
{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },{1, &pic16c5x_device::iorlw },
/*E0*/ {1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },
{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },
{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },
/*E8*/ {1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },
{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },
{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },{1, &pic16c5x_device::andlw },
/*F0*/ {1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },
{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },
{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },
/*F8*/ {1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },
{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw }
{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw },{1, &pic16c5x_device::xorlw }
};
const pic16c5x_device::pic16c5x_opcode pic16c5x_device::s_opcode_00x[16]=
{
/*00*/ {1, &pic16c5x_device::nop },{0, &pic16c5x_device::illegal },{1, &pic16c5x_device::option },{1, &pic16c5x_device::sleepic },
{1, &pic16c5x_device::clrwdt },{1, &pic16c5x_device::tris },{1, &pic16c5x_device::tris },{1, &pic16c5x_device::tris },
{1, &pic16c5x_device::clrwdt },{1, &pic16c5x_device::tris },{1, &pic16c5x_device::tris },{1, &pic16c5x_device::tris },
/*08*/ {0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal },
{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal }
{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal },{0, &pic16c5x_device::illegal }
};
@ -1102,4 +1102,3 @@ void pic16c5x_device::execute_run()
} while (m_icount > 0);
}

1
src/emu/cpu/pic16c62x/pic16c62x.c
View File

@ -1176,4 +1176,3 @@ void pic16c62x_device::device_reset()
pic16c62x_reset_regs();
SET(STATUS, (TO_FLAG | PD_FLAG));
}

4
src/emu/cpu/pic16c62x/pic16c62x.h
View File

@ -227,8 +227,8 @@ public:
class pic16cr620a_device : public pic16c62x_device
{
public:
// construction/destruction
pic16cr620a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// construction/destruction
pic16cr620a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
}*/;
class pic16c621_device : public pic16c62x_device

1
src/emu/cpu/pps4/pps4.c
View File

@ -367,4 +367,3 @@ void pps4_device::device_reset()
m_SB.d = 0;
m_B.d = 0;
}

2
src/emu/cpu/psx/rcnt.h
View File

@ -65,7 +65,7 @@ private:
UINT16 root_current( int n_counter );
int root_target( int n_counter );
void root_timer_adjust( int n_counter );
devcb2_write_line m_irq0_handler;
devcb2_write_line m_irq1_handler;
devcb2_write_line m_irq2_handler;

1
src/emu/cpu/rsp/rspdrc.c
View File

@ -6167,4 +6167,3 @@ CPU_GET_INFO( rsp_drc )
}
DEFINE_LEGACY_CPU_DEVICE(RSP_DRC, rsp_drc);

1
src/emu/cpu/s2650/s2650.c
View File

@ -1564,4 +1564,3 @@ void s2650_device::execute_run()
}
} while( m_icount > 0 );
}

8
src/emu/cpu/sh2/sh2comn.c
View File

@ -17,11 +17,11 @@
INLINE sh2_state *GET_SH2(device_t *dev)
{
if (dev->machine().options().drc()) {
if (dev->machine().options().drc()) {
return *(sh2_state **)downcast<legacy_cpu_device *>(dev)->token();
} else {
} else {
return (sh2_state *)downcast<legacy_cpu_device *>(dev)->token();
}
}
}
static const int div_tab[4] = { 3, 5, 7, 0 };
@ -844,7 +844,7 @@ void sh2_set_irq_line(sh2_state *sh2, int irqline, int state)
sh2_exception(sh2, "Set IRQ line", 16);
if (sh2->isdrc)
sh2->pending_nmi = 1;
sh2->pending_nmi = 1;
}
}
else

2
src/emu/cpu/sh2/sh2comn.h
View File

@ -117,7 +117,7 @@ struct sh2_state
UINT32 irqsr; // IRQ-time old SR for DRC
UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
irq_entry irq_queue[16];
bool isdrc;
int pcfsel; // last pcflush entry set

1
src/emu/cpu/sh2/sh2fe.c
View File

@ -760,4 +760,3 @@ bool sh2_frontend::describe_group_12(opcode_desc &desc, const opcode_desc *prev,
return false;
}

1
src/emu/cpu/tlcs900/tlcs900.c
View File

@ -2168,4 +2168,3 @@ void tmp95c063_device::execute_set_input(int input, int level)
}
m_check_irqs = 1;
}

228
src/emu/cpu/tms32082/dis_mp.c
View File

@ -16,10 +16,10 @@ static const char *BCND_CONDITION[32] =
static const char *BITNUM_CONDITION[32] =
{
"eq.b", "ne.b", "gt.b", "le.b", "lt.b", "ge.b", "hi.b", "ls.b",
"lo.b", "hs.b", "eq.h", "ne.h", "gt.h", "le.h", "lt.h", "ge.h",
"hi.h", "ls.h", "lo.h", "hs.h", "eq.w", "ne.w", "gt.w", "le.w",
"lt.w", "ge.w", "hi.w", "ls.w", "lo.w", "hs.w", "?", "?",
"eq.b", "ne.b", "gt.b", "le.b", "lt.b", "ge.b", "hi.b", "ls.b",
"lo.b", "hs.b", "eq.h", "ne.h", "gt.h", "le.h", "lt.h", "ge.h",
"hi.h", "ls.h", "lo.h", "hs.h", "eq.w", "ne.w", "gt.w", "le.w",
"lt.w", "ge.w", "hi.w", "ls.w", "lo.w", "hs.w", "?", "?",
};
static const char *MEMOP_S[2] =
@ -156,8 +156,8 @@ static char* format_vector_op(UINT32 op, UINT32 imm32)
b += sprintf(b, "vrnd.%s%s 0x%08X, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd4], imm32, rs);
break;
case 0xca: b += sprintf(b, "vrnd.%s%s R%d, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2],src1, rs); break;
case 0xcb: b += sprintf(b, "vrnd.%s%s 0x%08X, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2], imm32, rs); break;
case 0xca: b += sprintf(b, "vrnd.%s%s R%d, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2],src1, rs); break;
case 0xcb: b += sprintf(b, "vrnd.%s%s 0x%08X, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2], imm32, rs); break;
case 0xcc: case 0xdc:
b += sprintf(b, "vmac.ss%s R%d, R%d, %s, %s", FLOATOP_PRECISION[(op >> 9) & 1], src1, rs, z ? "0" : ACC_SEL[acc], (regdest && rd == 0) ? ACC_SEL[acc] : dest);
@ -172,7 +172,7 @@ static char* format_vector_op(UINT32 op, UINT32 imm32)
b += sprintf(b, "vmsc.ss%s 0x%08X, R%d, %s, %s", FLOATOP_PRECISION[(op >> 9) & 1], imm32, rs, z ? "0" : ACC_SEL[acc], (regdest && rd == 0) ? ACC_SEL[acc] : dest);
break;
default: b += sprintf(b, "?"); break;
default: b += sprintf(b, "?"); break;
}
// align the line end
@ -183,17 +183,17 @@ static char* format_vector_op(UINT32 op, UINT32 imm32)
{
b += sprintf(b, " ");
}
}
}
// optional load/store op
switch (vector_ls_bits)
{
case 0x01: b += sprintf(b, "|| vst.s R%d", rd); break;
case 0x03: b += sprintf(b, "|| vst.d R%d", rd); break;
case 0x04: b += sprintf(b, "|| vld0.s R%d", rd); break;
case 0x05: b += sprintf(b, "|| vld1.s R%d", rd); break;
case 0x06: b += sprintf(b, "|| vld0.d R%d", rd); break;
case 0x07: b += sprintf(b, "|| vld1.d R%d", rd); break;
case 0x01: b += sprintf(b, "|| vst.s R%d", rd); break;
case 0x03: b += sprintf(b, "|| vst.d R%d", rd); break;
case 0x04: b += sprintf(b, "|| vld0.s R%d", rd); break;
case 0x05: b += sprintf(b, "|| vld1.s R%d", rd); break;
case 0x06: b += sprintf(b, "|| vld0.d R%d", rd); break;
case 0x07: b += sprintf(b, "|| vld1.d R%d", rd); break;
}
return buffer;
@ -226,30 +226,30 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
switch (subop)
{
case 0x00: print("illop0 "); break;
case 0x01: print("trap %d", UIMM15(uimm15)); break;
case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break;
case 0x04: print("rdcr %s, R%d", get_creg_name(UIMM15(uimm15)), rd); break;
case 0x05: print("swcr R%d, %s, R%d", rd, get_creg_name(UIMM15(uimm15)), rs); break;
case 0x06: print("brcr %s", get_creg_name(UIMM15(uimm15))); break;
case 0x08: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x09: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0a: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0b: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0c: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0d: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0e: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0f: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x11: print("and 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x12: print("and.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x14: print("and.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x16: print("xor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x17: print("or 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x18: print("and.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x19: print("xnor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1b: print("or.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1d: print("or.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1e: print("or.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x00: print("illop0 "); break;
case 0x01: print("trap %d", UIMM15(uimm15)); break;
case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break;
case 0x04: print("rdcr %s, R%d", get_creg_name(UIMM15(uimm15)), rd); break;
case 0x05: print("swcr R%d, %s, R%d", rd, get_creg_name(UIMM15(uimm15)), rs); break;
case 0x06: print("brcr %s", get_creg_name(UIMM15(uimm15))); break;
case 0x08: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x09: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0a: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0b: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0c: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0d: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0e: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x0f: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x11: print("and 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x12: print("and.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x14: print("and.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x16: print("xor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x17: print("or 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x18: print("and.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x19: print("xnor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1b: print("or.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1d: print("or.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1e: print("or.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x24: case 0x20:
print("ld.b 0x%04X(R%d%s), R%d", UIMM15(uimm15), rs, MEMOP_M[m], rd);
@ -283,23 +283,23 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
print("st.d R%d, 0x%04X(R%d%s)", rd, UIMM15(uimm15), rs, MEMOP_M[m]);
break;
case 0x40: print("bsr 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
case 0x41: print("bsr.a 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
case 0x44: print("jsr 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
case 0x45: print("jsr.a 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
case 0x48: print("bbz 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x49: print("bbz.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x4a: print("bbo 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x4b: print("bbo.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x4c: print("bcnd 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
case 0x4d: print("bcnd.a 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
case 0x50: print("cmp 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x58: print("add 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x59: print("addu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x5a: print("sub 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x5b: print("subu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x40: print("bsr 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
case 0x41: print("bsr.a 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
case 0x44: print("jsr 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
case 0x45: print("jsr.a 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
case 0x48: print("bbz 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x49: print("bbz.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x4a: print("bbo 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x4b: print("bbo.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x4c: print("bcnd 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
case 0x4d: print("bcnd.a 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
case 0x50: print("cmp 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x58: print("add 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x59: print("addu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x5a: print("sub 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x5b: print("subu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
default: print("?"); break;
default: print("?"); break;
}
break;
}
@ -324,16 +324,16 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
switch (subop)
{
case 0x02: print("trap %d", src1); break;
case 0x03: print("trap %d", imm32); break;
case 0x04: print("cmnd R%d", src1); break;
case 0x05: print("cmnd 0x%08X", imm32); break;
case 0x08: print("rdcr R%d, R%d,", src1, rd); break;
case 0x09: print("rdcr %s, R%d", get_creg_name(imm32), rd); break;
case 0x0a: print("swcr R%d, R%d, R%d", rd, src1, rs); break;
case 0x0b: print("swcr R%d, %s, R%d", rd, get_creg_name(imm32), rs); break;
case 0x0c: print("brcr R%d", src1); break;
case 0x0d: print("brcr %s", get_creg_name(imm32)); break;
case 0x02: print("trap %d", src1); break;
case 0x03: print("trap %d", imm32); break;
case 0x04: print("cmnd R%d", src1); break;
case 0x05: print("cmnd 0x%08X", imm32); break;
case 0x08: print("rdcr R%d, R%d,", src1, rd); break;
case 0x09: print("rdcr %s, R%d", get_creg_name(imm32), rd); break;
case 0x0a: print("swcr R%d, R%d, R%d", rd, src1, rs); break;
case 0x0b: print("swcr R%d, %s, R%d", rd, get_creg_name(imm32), rs); break;
case 0x0c: print("brcr R%d", src1); break;
case 0x0d: print("brcr %s", get_creg_name(imm32)); break;
case 0x10: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
case 0x12: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
@ -434,69 +434,69 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
print("dcache 0x%08X(R%d)", imm32, rs);
break;
case 0x80: print("bsr R%d, R%d", src1, link); break;
case 0x81: print("bsr 0x%08X, R%d", imm32, link); break;
case 0x82: print("bsr.a R%d, R%d", src1, rd); break;
case 0x83: print("bsr.a 0x%08X, R%d", imm32, link); break;
case 0x88: print("jsr R%d, R%d", src1, link); break;
case 0x89: print("jsr 0x%08X, R%d", imm32, link); break;
case 0x8a: print("jsr.a R%d, R%d", src1, link); break;
case 0x8b: print("jsr.a 0x%08X, R%d", imm32, link); break;
case 0x90: print("bbz R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x91: print("bbz 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x92: print("bbz.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x93: print("bbz.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x94: print("bbo R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x95: print("bbo 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x96: print("bbo.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x97: print("bbo.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x98: print("bcnd R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
case 0x99: print("bcnd 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
case 0x9a: print("bcnd.a R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
case 0x9b: print("bcnd.a 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
case 0xa0: print("cmp R%d, R%d, R%d", src1, rs, rd); break;
case 0xa1: print("cmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb0: print("add R%d, R%d, R%d", src1, rs, rd); break;
case 0xb1: print("add 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb2: print("addu R%d, R%d, R%d", src1, rs, rd); break;
case 0xb3: print("addu 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb4: print("sub R%d, R%d, R%d", src1, rs, rd); break;
case 0xb5: print("sub 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb6: print("subu R%d, R%d, R%d", src1, rs, rd); break;
case 0xb7: print("subu 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x80: print("bsr R%d, R%d", src1, link); break;
case 0x81: print("bsr 0x%08X, R%d", imm32, link); break;
case 0x82: print("bsr.a R%d, R%d", src1, rd); break;
case 0x83: print("bsr.a 0x%08X, R%d", imm32, link); break;
case 0x88: print("jsr R%d, R%d", src1, link); break;
case 0x89: print("jsr 0x%08X, R%d", imm32, link); break;
case 0x8a: print("jsr.a R%d, R%d", src1, link); break;
case 0x8b: print("jsr.a 0x%08X, R%d", imm32, link); break;
case 0x90: print("bbz R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x91: print("bbz 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x92: print("bbz.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x93: print("bbz.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x94: print("bbo R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x95: print("bbo 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x96: print("bbo.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x97: print("bbo.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break;
case 0x98: print("bcnd R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
case 0x99: print("bcnd 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
case 0x9a: print("bcnd.a R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
case 0x9b: print("bcnd.a 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
case 0xa0: print("cmp R%d, R%d, R%d", src1, rs, rd); break;
case 0xa1: print("cmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb0: print("add R%d, R%d, R%d", src1, rs, rd); break;
case 0xb1: print("add 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb2: print("addu R%d, R%d, R%d", src1, rs, rd); break;
case 0xb3: print("addu 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb4: print("sub R%d, R%d, R%d", src1, rs, rd); break;
case 0xb5: print("sub 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb6: print("subu R%d, R%d, R%d", src1, rs, rd); break;
case 0xb7: print("subu 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5:
case 0xc6: case 0xd6: case 0xc7: case 0xd7: case 0xc8: case 0xd8: case 0xc9: case 0xd9:
case 0xca: case 0xcb: case 0xcc: case 0xdc: case 0xcd: case 0xdd: case 0xce: case 0xde:
case 0xca: case 0xcb: case 0xcc: case 0xdc: case 0xcd: case 0xdd: case 0xce: case 0xde:
case 0xcf: case 0xdf:
{
print("%s", format_vector_op(op, imm32));
break;
}
case 0xe0: print("fadd.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe1: print("fadd.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe2: print("fsub.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe3: print("fsub.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe4: print("fmpy.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe5: print("fmpy.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe6: print("fdiv.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe7: print("fdiv.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe8: print("frnd%s.%s%s R%d, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], src1, rd); break;
case 0xe9: print("frnd%s.%s%s 0x%08X, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], imm32, rd); break;
case 0xea: print("fcmp R%d, R%d, R%d", src1, rs, rd); break;
case 0xeb: print("fcmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xee: print("fsqrt R%d, R%d", src1, rd); break;
case 0xef: print("fsqrt 0x%08X, R%d", imm32, rd); break;
case 0xf0: print("lmo R%d, R%d", rs, rd); break;
case 0xf2: print("rmo R%d, R%d", rs, rd); break;
case 0xfc: print("estop "); break;
case 0xe0: print("fadd.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe1: print("fadd.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe2: print("fsub.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe3: print("fsub.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe4: print("fmpy.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe5: print("fmpy.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe6: print("fdiv.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break;
case 0xe7: print("fdiv.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break;
case 0xe8: print("frnd%s.%s%s R%d, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], src1, rd); break;
case 0xe9: print("frnd%s.%s%s 0x%08X, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], imm32, rd); break;
case 0xea: print("fcmp R%d, R%d, R%d", src1, rs, rd); break;
case 0xeb: print("fcmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xee: print("fsqrt R%d, R%d", src1, rd); break;
case 0xef: print("fsqrt 0x%08X, R%d", imm32, rd); break;
case 0xf0: print("lmo R%d, R%d", rs, rd); break;
case 0xf2: print("rmo R%d, R%d", rs, rd); break;
case 0xfc: print("estop "); break;
case 0xfe: case 0xff:
print("illopF ");
break;
default: print("?"); break;
default: print("?"); break;
}
break;
}

142
src/emu/cpu/tms32082/dis_pp.c
View File

@ -6,37 +6,37 @@
static const char *REG_NAMES[128] =
{
// 0 - 15
"a0", "a1", "a2", "a3", "a4", "???", "a6", "a7",
"a8", "a9", "a10", "a11", "a12", "???", "a14", "a15",
"a0", "a1", "a2", "a3", "a4", "???", "a6", "a7",
"a8", "a9", "a10", "a11", "a12", "???", "a14", "a15",
// 16 - 31
"x0", "x1", "x2", "???", "???", "???", "???", "???",
"x8", "x9", "x10", "???", "???", "???", "???", "???",
"x0", "x1", "x2", "???", "???", "???", "???", "???",
"x8", "x9", "x10", "???", "???", "???", "???", "???",
// 32 - 47
"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
"???", "sr", "mf", "???", "???", "???", "???", "???",
"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
"???", "sr", "mf", "???", "???", "???", "???", "???",
// 48 - 63
"???", "???", "???", "???", "???", "???", "???", "???",
"pc/call", "ipa/br", "ipe", "iprs", "inten", "intflg", "comm", "lctl",
"???", "???", "???", "???", "???", "???", "???", "???",
"pc/call", "ipa/br", "ipe", "iprs", "inten", "intflg", "comm", "lctl",
// 64 - 79
"???", "???", "???", "???", "???", "???", "???", "???",
"???", "???", "???", "???", "???", "???", "???", "???",
"???", "???", "???", "???", "???", "???", "???", "???",
"???", "???", "???", "???", "???", "???", "???", "???",
// 80 - 95
"???", "???", "???", "???", "???", "???", "???", "???",
"???", "???", "???", "???", "???", "???", "???", "???",
"???", "???", "???", "???", "???", "???", "???", "???",
"???", "???", "???", "???", "???", "???", "???", "???",
// 96 - 111
"lc0", "lc1", "lc2", "???", "lr0", "lr1", "lr2", "???",
"lrse0", "lrse1", "lrse2", "???", "lrs0", "lrs1", "lrs2", "???",
"lc0", "lc1", "lc2", "???", "lr0", "lr1", "lr2", "???",
"lrse0", "lrse1", "lrse2", "???", "lrs0", "lrs1", "lrs2", "???",
// 112 - 127
"ls0", "ls1", "ls2", "???", "le0", "le1", "le2", "???",
"???", "???", "???", "???", "tag0", "tag1", "tag2", "tag3"
"ls0", "ls1", "ls2", "???", "le0", "le1", "le2", "???",
"???", "???", "???", "???", "tag0", "tag1", "tag2", "tag3"
};
static const char *CONDITION_CODES[16] =
{
"", "[p] ", "[ls] ", "[hi] ",
"[lt] ", "[le] ", "[ge] ", "[gt] ",
"[hs] ", "[lo] ", "[eq] ", "[ne] ",
"[v] ", "[nv] ", "[n] ", "[nn] "
"", "[p] ", "[ls] ", "[hi] ",
"[lt] ", "[le] ", "[ge] ", "[gt] ",
"[hs] ", "[lo] ", "[eq] ", "[ne] ",
"[v] ", "[nv] ", "[n] ", "[nn] "
};
static const char *TRANSFER_SIZE[4] =
@ -103,7 +103,7 @@ static void format_transfer(UINT64 op)
switch (gmode)
{
case 0x00: // Format 7: Conditional DU || Conditional Move
case 0x00: // Format 7: Conditional DU || Conditional Move
{
int dstbank = (op >> 18) & 0xf;
int srcbank = (op >> 6) & 0xf;
@ -117,14 +117,14 @@ static void format_transfer(UINT64 op)
b += sprintf(b, "%s = %s", REG_NAMES[dreg], REG_NAMES[sreg]);
break;
}
case 0x01: // Format 8: Conditional DU ||Conditional Field Move
case 0x01: // Format 8: Conditional DU ||Conditional Field Move
{
int dstbank = (op >> 18) & 0xf;
int src = (op >> 10) & 0x7;
int dst = (op >> 3) & 0x7;
int itm = (op >> 22) & 0x3;
int size = (op >> 7) & 0x3;
// int e = (op & (1 << 9));
// int e = (op & (1 << 9));
int dreg = (dstbank << 3) | dst;
int sreg = (4 << 3) | src;
@ -133,7 +133,7 @@ static void format_transfer(UINT64 op)
b += sprintf(b, "%s = [%s%d]%s", REG_NAMES[dreg], TRANSFER_SIZE[size], itm, REG_NAMES[sreg]);
break;
}
case 0x02: case 0x03: // Format 10: Conditional Non-D Data Unit
case 0x02: case 0x03: // Format 10: Conditional Non-D Data Unit
{
int as1bank = (op >> 6) & 0xf;
int adstbank = (op >> 18) & 0xf;
@ -156,7 +156,7 @@ static void format_transfer(UINT64 op)
}
default:
{
if (op & 0x4) // Format 9: Conditional DU || Conditional Global
if (op & 0x4) // Format 9: Conditional DU || Conditional Global
{
int bank = (op >> 18) & 0xf;
int le = ((op >> 16) & 2) | ((op >> 9) & 1);
@ -178,7 +178,7 @@ static void format_transfer(UINT64 op)
case 3: b += sprintf(b, "%s = &%s%s", REG_NAMES[greg], TRANSFER_SIZE[size], format_address_mode(gmode, ga, s, gimx)); break;
}
}
else // Format 5: Global (Long Offset)
else // Format 5: Global (Long Offset)
{
int bank = (op >> 18) & 0xf;
int le = ((op >> 16) & 2) | ((op >> 9) & 1);
@ -194,7 +194,7 @@ static void format_transfer(UINT64 op)
// sign extend offset
if (s && (offset & 0x4000))
offset |= 0xffffc000;
switch (le)
{
case 0: b += sprintf(b, "&%s%s = %s", TRANSFER_SIZE[size], format_address_mode(gmode, ga, s, offset), REG_NAMES[greg]); break;
@ -215,17 +215,17 @@ static void format_transfer(UINT64 op)
switch (mode)
{
case 0x00: // Format 2: Move || Local
case 0x00: // Format 2: Move || Local
{
b += sprintf(b, "move||local <TODO>");
break;
}
case 0x01: // Format 3: Field Move || Local
case 0x01: // Format 3: Field Move || Local
{
b += sprintf(b, "field move||local <TODO>");
break;
}
case 0x02: case 0x03: // Format 6: Non-D DU || Local
case 0x02: case 0x03: // Format 6: Non-D DU || Local
{
int d = (op >> 32) & 0x7;
int s = (op & (1 << 28));
@ -245,7 +245,7 @@ static void format_transfer(UINT64 op)
}
break;
}
case 0x10: case 0x11: case 0x12: case 0x13: // Format 4: Local (Long Offset)
case 0x10: case 0x11: case 0x12: case 0x13: // Format 4: Local (Long Offset)
{
int d = (op >> 32) & 0x7;
int bank = (op >> 18) & 0xf;
@ -277,7 +277,7 @@ static void format_transfer(UINT64 op)
}
break;
}
case 0x14: case 0x15: case 0x16: case 0x17: // Format 1: Double Parallel
case 0x14: case 0x15: case 0x16: case 0x17: // Format 1: Double Parallel
case 0x18: case 0x19: case 0x1a: case 0x1b:
case 0x1c: case 0x1d: case 0x1e: case 0x1f:
{
@ -329,83 +329,83 @@ static void format_transfer(UINT64 op)
static void format_alu_op(int aluop, int a, const char *dst_text, const char *a_text, const char *b_text, const char *c_text)
{
if (a) // arithmetic
if (a) // arithmetic
{
int bits = (aluop & 1) | ((aluop >> 1) & 2) | ((aluop >> 2) & 4) | ((aluop >> 3) & 8);
switch (bits)
{
case 1: print("%s = %s - %s<1<", dst_text, a_text, b_text); break;
case 2: print("%s = %s + %s<0<", dst_text, a_text, b_text); break;
case 3: print("%s = %s - %s", dst_text, a_text, c_text); break;
case 4: print("%s = %s - %s>1>", dst_text, a_text, b_text); break;
case 5: print("%s = %s - %s", dst_text, a_text, b_text); break;
case 6: print("?"); break;
case 7: print("%s = %s - %s>0>", dst_text, a_text, b_text); break;
case 8: print("%s = %s + %s>0>", dst_text, a_text, b_text); break;
case 9: print("?"); break;
case 10: print("%s = %s + %s", dst_text, a_text, b_text); break;
case 11: print("%s = %s + %s>1>", dst_text, a_text, b_text); break;
case 12: print("%s = %s + %s", dst_text, a_text, c_text); break;
case 13: print("%s = %s - %s<0<", dst_text, a_text, b_text); break;
case 14: print("%s = %s + %s<1<", dst_text, a_text, b_text); break;
case 15: print("%s = field %s + %s", dst_text, a_text, b_text); break;
case 1: print("%s = %s - %s<1<", dst_text, a_text, b_text); break;
case 2: print("%s = %s + %s<0<", dst_text, a_text, b_text); break;
case 3: print("%s = %s - %s", dst_text, a_text, c_text); break;
case 4: print("%s = %s - %s>1>", dst_text, a_text, b_text); break;
case 5: print("%s = %s - %s", dst_text, a_text, b_text); break;
case 6: print("?"); break;
case 7: print("%s = %s - %s>0>", dst_text, a_text, b_text); break;
case 8: print("%s = %s + %s>0>", dst_text, a_text, b_text); break;
case 9: print("?"); break;
case 10: print("%s = %s + %s", dst_text, a_text, b_text); break;
case 11: print("%s = %s + %s>1>", dst_text, a_text, b_text); break;
case 12: print("%s = %s + %s", dst_text, a_text, c_text); break;
case 13: print("%s = %s - %s<0<", dst_text, a_text, b_text); break;
case 14: print("%s = %s + %s<1<", dst_text, a_text, b_text); break;
case 15: print("%s = field %s + %s", dst_text, a_text, b_text); break;
}
}
else // boolean
else // boolean
{
switch (aluop)
{
case 0xaa: // A & B & C | A & ~B & C | A & B & ~C | A & ~B & ~C = A
case 0xaa: // A & B & C | A & ~B & C | A & B & ~C | A & ~B & ~C = A
print("%s = %s", dst_text, a_text);
break;
case 0x55: // ~A & B & C | ~A & ~B & C | ~A & B & ~C | ~A & ~B & ~C = ~A
case 0x55: // ~A & B & C | ~A & ~B & C | ~A & B & ~C | ~A & ~B & ~C = ~A
print("%s = ~%s", dst_text, a_text);
break;
case 0xcc: // A & B & C | ~A & B & C | A & B & ~C | ~A & B & ~C = B
case 0xcc: // A & B & C | ~A & B & C | A & B & ~C | ~A & B & ~C = B
print("%s = %s", dst_text, b_text);
break;
case 0x33: // A & ~B & C | ~A & ~B & C | A & ~B & ~C | ~A & ~B & ~C = ~B
case 0x33: // A & ~B & C | ~A & ~B & C | A & ~B & ~C | ~A & ~B & ~C = ~B
print("%s = %s", dst_text, b_text);
break;
case 0xf0: // A & B & C | ~A & B & C | A & ~B & C | ~A & ~B & C = C
case 0xf0: // A & B & C | ~A & B & C | A & ~B & C | ~A & ~B & C = C
print("%s = %s", dst_text, c_text);
break;
case 0x0f: // A & B & ~C | ~A & B & ~C | A & ~B & ~C | ~A & ~B & ~C = ~C
case 0x0f: // A & B & ~C | ~A & B & ~C | A & ~B & ~C | ~A & ~B & ~C = ~C
print("%s = ~%s", dst_text, c_text);
break;
case 0x80: // A & B & C
case 0x80: // A & B & C
print("%s = %s & %s & %s", dst_text, a_text, b_text, c_text);
break;
case 0x88: // A & B & C | A & B & ~C = A & B
case 0x88: // A & B & C | A & B & ~C = A & B
print("%s = %s & %s", dst_text, a_text, b_text);
break;
case 0xa0: // A & B & C | A & ~B & C = A & C
case 0xa0: // A & B & C | A & ~B & C = A & C
print("%s = %s & %s", dst_text, a_text, c_text);
break;
case 0xc0: // A & B & C | ~A & B & C = B & C
case 0xc0: // A & B & C | ~A & B & C = B & C
print("%s = %s & %s", dst_text, b_text, c_text);
break;
case 0xea: // A & B & C | ~A & B & C | A & ~B & C |
case 0xea: // A & B & C | ~A & B & C | A & ~B & C |
// A & B & ~C | A & ~B & ~C = A | C
print("%s = %s | %s", dst_text, a_text, c_text);
break;
case 0xee: // A & B & C | ~A & B & C | A & ~B & C |
case 0xee: // A & B & C | ~A & B & C | A & ~B & C |
// A & B & ~C | ~A & B & ~C | A & ~B & ~C = A | B
print("%s = %s | %s", dst_text, a_text, b_text);
break;
case 0x44: // ~A & B & C | ~A & B & ~C = ~A & B
case 0x44: // ~A & B & C | ~A & B & ~C = ~A & B
print("%s = ~%s & %s", dst_text, a_text, b_text);
break;
@ -420,14 +420,14 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom)
{
output = buffer;
UINT32 flags = 0;
UINT64 op = ((UINT64)(oprom[0]) << 56) | ((UINT64)(oprom[1]) << 48) | ((UINT64)(oprom[2]) << 40) | ((UINT64)(oprom[3]) << 32) |
((UINT64)(oprom[4]) << 24) | ((UINT64)(oprom[5]) << 16) | ((UINT64)(oprom[6]) << 8) | ((UINT64)(oprom[7]));
switch (op >> 60)
{
case 0x6:
case 0x7: // Six-operand
case 0x7: // Six-operand
{
print("A: six operand <TODO>");
break;
@ -452,7 +452,7 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom)
case 0x00: print("nop"); break;
case 0x02: print("eint"); break;
case 0x03: print("dint"); break;
default: print("<reserved>"); break;
default: print("<reserved>"); break;
}
format_transfer(parallel_xfer);
@ -467,7 +467,7 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom)
switch ((op >> 43) & 3)
{
case 0:
case 1: // Base set ALU (5-bit immediate)
case 1: // Base set ALU (5-bit immediate)
{
UINT64 parallel_xfer = (op & U64(0x0000007fffffffff));
@ -545,8 +545,8 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom)
format_transfer(parallel_xfer);
break;
}
case 2: // Base set ALU (reg src2)
case 2: // Base set ALU (reg src2)
{
UINT64 parallel_xfer = (op & U64(0x0000007fffffffff));
@ -625,8 +625,8 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom)
format_transfer(parallel_xfer);
break;
}
case 3: // Base set ALU (32-bit immediate)
case 3: // Base set ALU (32-bit immediate)
{
int dst = (op >> 48) & 7;
int src1 = (op >> 45) & 7;
@ -709,4 +709,4 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom)
CPU_DISASSEMBLE(tms32082_pp)
{
return tms32082_disasm_pp(buffer, pc, oprom);
}
}

264
src/emu/cpu/tms32082/mp_ops.c
View File

@ -32,7 +32,7 @@
#define SIGN16(x) (((x) & 0x8000) ? 1 : 0)
#define SIGN8(x) (((x) & 0x80) ? 1 : 0)
#define SIGN_EXTEND(x, r) ((x) | (((x) & (0x80000000 >> r)) ? ((INT32)(0x80000000) >> r) : 0))
#define SIGN_EXTEND(x, r) ((x) | (((x) & (0x80000000 >> r)) ? ((INT32)(0x80000000) >> r) : 0))
@ -95,38 +95,38 @@ UINT32 tms32082_mp_device::calculate_cmp(UINT32 src1, UINT32 src2)
UINT32 flags = 0;
// 32-bits (bits 20-29)
flags |= ((~c32) & 1) << 29; // higher than or same (C)
flags |= ((c32) & 1) << 28; // lower than (~C)
flags |= ((c32|z32) & 1) << 27; // lower than or same (~C|Z)
flags |= ((~c32&~z32) & 1) << 26; // higher than (C&~Z)
flags |= (((n32&v32)|(~n32&~v32)) & 1) << 25; // greater than or equal (N&V)|(~N&~V)
flags |= (((n32&~v32)|(~n32&v32)) & 1) << 24; // less than (N&~V)|(~N&V)
flags |= (((n32&~v32)|(~n32&v32)|(z32)) & 1) << 23; // less than or equal (N&~V)|(~N&V)|Z
flags |= (((n32&v32&~z32)|(~n32&~v32&~z32)) & 1) << 22; // greater than (N&V&~Z)|(~N&~V&~Z)
flags |= ((~z32) & 1) << 21; // not equal (~Z)
flags |= ((z32) & 1) << 20; // equal (Z)
flags |= ((~c32) & 1) << 29; // higher than or same (C)
flags |= ((c32) & 1) << 28; // lower than (~C)
flags |= ((c32|z32) & 1) << 27; // lower than or same (~C|Z)
flags |= ((~c32&~z32) & 1) << 26; // higher than (C&~Z)
flags |= (((n32&v32)|(~n32&~v32)) & 1) << 25; // greater than or equal (N&V)|(~N&~V)
flags |= (((n32&~v32)|(~n32&v32)) & 1) << 24; // less than (N&~V)|(~N&V)
flags |= (((n32&~v32)|(~n32&v32)|(z32)) & 1) << 23; // less than or equal (N&~V)|(~N&V)|Z
flags |= (((n32&v32&~z32)|(~n32&~v32&~z32)) & 1) << 22; // greater than (N&V&~Z)|(~N&~V&~Z)
flags |= ((~z32) & 1) << 21; // not equal (~Z)
flags |= ((z32) & 1) << 20; // equal (Z)
// 16-bits (bits 10-19)
flags |= ((~c16) & 1) << 19; // higher than or same (C)
flags |= ((c16) & 1) << 18; // lower than (~C)
flags |= ((c16|z16) & 1) << 17; // lower than or same (~C|Z)
flags |= ((~c16&~z16) & 1) << 16; // higher than (C&~Z)
flags |= (((n16&v16)|(~n16&~v16)) & 1) << 15; // greater than or equal (N&V)|(~N&~V)
flags |= (((n16&~v16)|(~n16&v16)) & 1) << 14; // less than (N&~V)|(~N&V)
flags |= (((n16&~v16)|(~n16&v16)|(z16)) & 1) << 13; // less than or equal (N&~V)|(~N&V)|Z
flags |= (((n16&v16&~z16)|(~n16&~v16&~z16)) & 1) << 12; // greater than (N&V&~Z)|(~N&~V&~Z)
flags |= ((~z16) & 1) << 11; // not equal (~Z)
flags |= ((z16) & 1) << 10; // equal (Z)
flags |= ((~c16) & 1) << 19; // higher than or same (C)
flags |= ((c16) & 1) << 18; // lower than (~C)
flags |= ((c16|z16) & 1) << 17; // lower than or same (~C|Z)
flags |= ((~c16&~z16) & 1) << 16; // higher than (C&~Z)
flags |= (((n16&v16)|(~n16&~v16)) & 1) << 15; // greater than or equal (N&V)|(~N&~V)
flags |= (((n16&~v16)|(~n16&v16)) & 1) << 14; // less than (N&~V)|(~N&V)
flags |= (((n16&~v16)|(~n16&v16)|(z16)) & 1) << 13; // less than or equal (N&~V)|(~N&V)|Z
flags |= (((n16&v16&~z16)|(~n16&~v16&~z16)) & 1) << 12; // greater than (N&V&~Z)|(~N&~V&~Z)
flags |= ((~z16) & 1) << 11; // not equal (~Z)
flags |= ((z16) & 1) << 10; // equal (Z)
// 8-bits (bits 0-9)
flags |= ((~c8) & 1) << 9; // higher than or same (C)
flags |= ((c8) & 1) << 8; // lower than (~C)
flags |= ((c8|z8) & 1) << 7; // lower than or same (~C|Z)
flags |= ((~c8&~z8) & 1) << 6; // higher than (C&~Z)
flags |= (((n8&v8)|(~n8&~v8)) & 1) << 5; // greater than or equal (N&V)|(~N&~V)
flags |= (((n8&~v8)|(~n8&v8)) & 1) << 4; // less than (N&~V)|(~N&V)
flags |= (((n8&~v8)|(~n8&v8)|(z8)) & 1) << 3; // less than or equal (N&~V)|(~N&V)|Z
flags |= (((n8&v8&~z8)|(~n8&~v8&~z8)) & 1) << 2; // greater than (N&V&~Z)|(~N&~V&~Z)
flags |= ((~z8) & 1) << 1; // not equal (~Z)
flags |= ((z8) & 1) << 0; // equal (Z)
flags |= ((~c8) & 1) << 9; // higher than or same (C)
flags |= ((c8) & 1) << 8; // lower than (~C)
flags |= ((c8|z8) & 1) << 7; // lower than or same (~C|Z)
flags |= ((~c8&~z8) & 1) << 6; // higher than (C&~Z)
flags |= (((n8&v8)|(~n8&~v8)) & 1) << 5; // greater than or equal (N&V)|(~N&~V)
flags |= (((n8&~v8)|(~n8&v8)) & 1) << 4; // less than (N&~V)|(~N&V)
flags |= (((n8&~v8)|(~n8&v8)|(z8)) & 1) << 3; // less than or equal (N&~V)|(~N&V)|Z
flags |= (((n8&v8&~z8)|(~n8&~v8&~z8)) & 1) << 2; // greater than (N&V&~Z)|(~N&~V&~Z)
flags |= ((~z8) & 1) << 1; // not equal (~Z)
flags |= ((z8) & 1) << 0; // equal (Z)
return flags;
}
@ -138,38 +138,38 @@ void tms32082_mp_device::vector_loadstore()
switch (vector_ls_bits)
{
case 0x01: // vst.s
case 0x01: // vst.s
{
m_program->write_dword(m_outp, m_reg[rd]);
m_outp += 4;
break;
}
case 0x03: // vst.d
case 0x03: // vst.d
{
UINT64 data = m_fpair[rd >> 1];
m_program->write_qword(m_outp, data);
m_outp += 8;
break;
}
case 0x04: // vld0.s
case 0x04: // vld0.s
{
m_reg[rd] = m_program->read_dword(m_in0p);
m_in0p += 4;
break;
}
case 0x05: // vld1.s
case 0x05: // vld1.s
{
m_reg[rd] = m_program->read_dword(m_in1p);
m_in1p += 4;
break;
}
case 0x06: // vld0.d
case 0x06: // vld0.d
{
m_fpair[rd >> 1] = m_program->read_qword(m_in0p);
m_in0p += 8;
break;
}
case 0x07: // vld1.d
case 0x07: // vld1.d
{
m_fpair[rd >> 1] = m_program->read_qword(m_in1p);
m_in1p += 8;
@ -186,7 +186,7 @@ void tms32082_mp_device::execute_short_imm()
{
switch ((m_ir >> 15) & 0x7f)
{
case 0x02: // cmnd
case 0x02: // cmnd
{
UINT32 data = OP_UIMM15();
@ -220,7 +220,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x06: // brcr
case 0x06: // brcr
{
int cr = OP_UIMM15();
@ -233,13 +233,13 @@ void tms32082_mp_device::execute_short_imm()
UINT32 data = read_creg(cr);
m_fetchpc = data & ~3;
m_ie = (m_ie & ~1) | (data & 1); // global interrupt mask from creg
m_ie = (m_ie & ~1) | (data & 1); // global interrupt mask from creg
// TODO: user/supervisor latch from creg
}
break;
}
case 0x08: // shift.dz
case 0x08: // shift.dz
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -251,14 +251,14 @@ void tms32082_mp_device::execute_short_imm()
UINT32 endmask = SHIFT_MASK[end ? end : 32];
if (inv) endmask = ~endmask;
UINT32 compmask = endmask; // shiftmask == 0xffffffff
UINT32 compmask = endmask; // shiftmask == 0xffffffff
UINT32 res = 0;
if (r) // right
if (r) // right
{
res = ROTATE_R(source, rot) & compmask;
}
else // left
else // left
{
res = ROTATE_L(source, rot) & compmask;
}
@ -268,7 +268,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x0a: // shift.ds
case 0x0a: // shift.ds
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -280,15 +280,15 @@ void tms32082_mp_device::execute_short_imm()
UINT32 endmask = SHIFT_MASK[end ? end : 32];
if (inv) endmask = ~endmask;
UINT32 compmask = endmask; // shiftmask == 0xffffffff
UINT32 compmask = endmask; // shiftmask == 0xffffffff
UINT32 res = 0;
if (r) // right
if (r) // right
{
res = ROTATE_R(source, rot) & compmask;
res = SIGN_EXTEND(res, rot);
}
else // left
else // left
{
res = ROTATE_L(source, rot) & compmask;
// sign extend makes no sense to left..
@ -299,7 +299,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x0b: // shift.ez
case 0x0b: // shift.ez
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -330,7 +330,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x0c: // shift.em
case 0x0c: // shift.em
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -346,11 +346,11 @@ void tms32082_mp_device::execute_short_imm()
UINT32 compmask = endmask & shiftmask;
UINT32 res = 0;
if (r) // right
if (r) // right
{
res = (ROTATE_R(source, rot) & compmask) | (m_reg[rd] & ~compmask);
}
else // left
else // left
{
res = (ROTATE_L(source, rot) & compmask) | (m_reg[rd] & ~compmask);
}
@ -360,7 +360,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x0d: // shift.es
case 0x0d: // shift.es
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -371,18 +371,18 @@ void tms32082_mp_device::execute_short_imm()
UINT32 endmask = SHIFT_MASK[end ? end : 32];
if (inv) endmask = ~endmask;
int shift = r ? 32-rot : rot;
UINT32 shiftmask = SHIFT_MASK[shift ? shift : 32];
UINT32 compmask = endmask & shiftmask;
UINT32 res = 0;
if (r) // right
if (r) // right
{
res = ROTATE_R(source, rot) & compmask;
res = SIGN_EXTEND(res, rot);
}
else // left
else // left
{
res = ROTATE_L(source, rot) & compmask;
// sign extend makes no sense to left..
@ -393,7 +393,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x0e: // shift.iz
case 0x0e: // shift.iz
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -423,7 +423,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x0f: // shift.im
case 0x0f: // shift.im
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -439,11 +439,11 @@ void tms32082_mp_device::execute_short_imm()
UINT32 compmask = endmask & ~shiftmask;
UINT32 res = 0;
if (r) // right
if (r) // right
{
res = (ROTATE_R(source, rot) & compmask) | (m_reg[rd] & ~compmask);
}
else // left
else // left
{
res = (ROTATE_L(source, rot) & compmask) | (m_reg[rd] & ~compmask);
}
@ -453,7 +453,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x11: // and
case 0x11: // and
{
int rd = OP_RD();
int rs = OP_RS();
@ -464,7 +464,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x14: // and.ft
case 0x14: // and.ft
{
int rd = OP_RD();
int rs = OP_RS();
@ -475,7 +475,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x17: // or
case 0x17: // or
{
int rd = OP_RD();
int rs = OP_RS();
@ -486,7 +486,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x1d: // or.ft
case 0x1d: // or.ft
{
int rd = OP_RD();
int rs = OP_RS();
@ -498,7 +498,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x24:
case 0x20: // ld.b
case 0x20: // ld.b
{
int rd = OP_RD();
int base = OP_BASE();
@ -517,7 +517,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x25:
case 0x21: // ld.h
case 0x21: // ld.h
{
int rd = OP_RD();
int base = OP_BASE();
@ -536,7 +536,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x26:
case 0x22: // ld
case 0x22: // ld
{
int rd = OP_RD();
int base = OP_BASE();
@ -554,7 +554,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x27:
case 0x23: // ld.d
case 0x23: // ld.d
{
int rd = OP_RD();
int base = OP_BASE();
@ -576,7 +576,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x28:
case 0x2c: // ld.ub
case 0x2c: // ld.ub
{
int rd = OP_RD();
int base = OP_BASE();
@ -594,7 +594,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x2d:
case 0x29: // ld.uh
case 0x29: // ld.uh
{
int rd = OP_RD();
int base = OP_BASE();
@ -612,7 +612,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x34:
case 0x30: // st.b
case 0x30: // st.b
{
int rd = OP_RD();
int base = OP_BASE();
@ -629,7 +629,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x35:
case 0x31: // st.h
case 0x31: // st.h
{
int rd = OP_RD();
int base = OP_BASE();
@ -663,7 +663,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x37:
case 0x33: // st.d
case 0x33: // st.d
{
int rd = OP_RD();
int base = OP_BASE();
@ -679,8 +679,8 @@ void tms32082_mp_device::execute_short_imm()
m_reg[base] = address;
break;
}
case 0x48: // bbz
case 0x48: // bbz
{
int bitnum = OP_BITNUM() ^ 0x1f;
INT32 offset = OP_SIMM15();
@ -698,7 +698,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x49: // bbz.a
case 0x49: // bbz.a
{
int bitnum = OP_BITNUM() ^ 0x1f;
INT32 offset = OP_SIMM15();
@ -711,7 +711,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x4a: // bbo
case 0x4a: // bbo
{
int bitnum = OP_BITNUM() ^ 0x1f;
INT32 offset = OP_SIMM15();
@ -742,7 +742,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x4c: // bcnd
case 0x4c: // bcnd
{
INT32 offset = OP_SIMM15();
int code = OP_RD();
@ -760,7 +760,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x4d: // bcnd.a
case 0x4d: // bcnd.a
{
INT32 offset = OP_SIMM15();
int code = OP_RD();
@ -784,7 +784,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x58: // add
case 0x58: // add
{
INT32 imm = OP_SIMM15();
int rd = OP_RD();
@ -808,7 +808,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x5a: // sub
case 0x5a: // sub
{
INT32 imm = OP_SIMM15();
int rd = OP_RD();
@ -821,7 +821,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
case 0x5b: // subu
case 0x5b: // subu
{
INT32 imm = OP_SIMM15();
int rd = OP_RD();
@ -887,7 +887,7 @@ void tms32082_mp_device::execute_reg_long_imm()
break;
}
case 0x1c: // shift.iz
case 0x1c: // shift.iz
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@ -919,7 +919,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0x22:
case 0x23: // and
case 0x23: // and
{
int rd = OP_RD();
int rs = OP_RS();
@ -943,7 +943,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0x2c:
case 0x2d: // xor
case 0x2d: // xor
{
int rd = OP_RD();
int rs = OP_RS();
@ -967,7 +967,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x40:
case 0x41:
case 0x48:
case 0x49: // ld.b
case 0x49: // ld.b
{
int m = m_ir & (1 << 15);
@ -977,7 +977,7 @@ void tms32082_mp_device::execute_reg_long_imm()
UINT32 address = m_reg[base] + (has_imm ? imm32 : m_reg[OP_SRC1()]);
UINT32 r = m_program->read_byte(address);
if (r & 0x80) r |= 0xffffff00;
if (rd)
m_reg[rd] = r;
@ -989,7 +989,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x42:
case 0x4a:
case 0x43:
case 0x4b: // ld.h
case 0x4b: // ld.h
{
int shift = (m_ir & (1 << 11)) ? 1 : 0;
int m = m_ir & (1 << 15);
@ -1012,7 +1012,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x4c:
case 0x44:
case 0x4d:
case 0x45: // ld
case 0x45: // ld
{
int shift = (m_ir & (1 << 11)) ? 2 : 0;
int m = m_ir & (1 << 15);
@ -1033,7 +1033,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x4e:
case 0x4f:
case 0x46:
case 0x47: // ld.d
case 0x47: // ld.d
{
int shift = (m_ir & (1 << 11)) ? 3 : 0;
int m = m_ir & (1 << 15);
@ -1054,7 +1054,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x58:
case 0x59:
case 0x50:
case 0x51: // ld.ub
case 0x51: // ld.ub
{
int m = m_ir & (1 << 15);
int base = OP_BASE();
@ -1074,7 +1074,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x5a:
case 0x5b:
case 0x52:
case 0x53: // ld.uh
case 0x53: // ld.uh
{
int shift = (m_ir & (1 << 11)) ? 1 : 0;
int m = m_ir & (1 << 15);
@ -1095,7 +1095,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x60:
case 0x61:
case 0x68:
case 0x69: // st.b
case 0x69: // st.b
{
int m = m_ir & (1 << 15);
@ -1112,7 +1112,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x62:
case 0x63:
case 0x6a:
case 0x6b: // st.h
case 0x6b: // st.h
{
int shift = (m_ir & (1 << 11)) ? 1 : 0;
int m = m_ir & (1 << 15);
@ -1130,7 +1130,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0x6c:
case 0x6d:
case 0x64:
case 0x65: // st
case 0x65: // st
{
int shift = (m_ir & (1 << 11)) ? 2 : 0;
int m = m_ir & (1 << 15);
@ -1177,7 +1177,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xa0:
case 0xa1: // cmp
case 0xa1: // cmp
{
int rd = OP_RD();
UINT32 src1 = has_imm ? imm32 : m_reg[OP_SRC1()];
@ -1200,7 +1200,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xb4:
case 0xb5: // sub
case 0xb5: // sub
{
int rd = OP_RD();
int rs = OP_RS();
@ -1213,7 +1213,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xb6:
case 0xb7: // subu
case 0xb7: // subu
{
int rd = OP_RD();
int rs = OP_RS();
@ -1226,7 +1226,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0xc4:
case 0xd4:
case 0xc5:
case 0xd5: // vmpy
case 0xd5: // vmpy
{
int p1 = m_ir & (1 << 5);
int pd = m_ir & (1 << 7);
@ -1262,7 +1262,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0xc8:
case 0xd8:
case 0xc9:
case 0xd9: // vrnd
case 0xd9: // vrnd
{
int acc = OP_ACC();
int p1 = m_ir & (1 << 5);
@ -1282,7 +1282,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0:
m_reg[rd] = f2u((float)source);
break;
case 1:
case 1:
m_fpair[rd >> 1] = d2u(source);
break;
case 2:
@ -1313,7 +1313,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0xcc:
case 0xdc:
case 0xcd:
case 0xdd: // vmac
case 0xdd: // vmac
{
int acc = OP_ACC();
int z = m_ir & (1 << 8);
@ -1356,7 +1356,7 @@ void tms32082_mp_device::execute_reg_long_imm()
case 0xce:
case 0xde:
case 0xcf:
case 0xdf: // vmsc
case 0xdf: // vmsc
{
int acc = OP_ACC();
int z = m_ir & (1 << 8);
@ -1397,25 +1397,25 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xe0:
case 0xe1: // fadd
case 0xe1: // fadd
{
int rd = OP_RD();
int rs = OP_RS();
int src1 = OP_SRC1();
int precision = (m_ir >> 5) & 0x3f;
if (rd) // only calculate if destination register is valid
if (rd) // only calculate if destination register is valid
{
switch (precision)
{
case 0x00: // SP - SP -> SP
case 0x00: // SP - SP -> SP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
float s2 = u2f(m_reg[rs]);
m_reg[rd] = f2u(s1 + s2);
break;
}
case 0x10: // SP - SP -> DP
case 0x10: // SP - SP -> DP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
float s2 = u2f(m_reg[rs]);
@ -1423,7 +1423,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x14: // SP - DP -> DP
case 0x14: // SP - DP -> DP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
double s2 = u2d(m_fpair[rs >> 1]);
@ -1431,7 +1431,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x11: // DP - SP -> DP
case 0x11: // DP - SP -> DP
{
double s1 = u2d(m_fpair[src1 >> 1]);
float s2 = u2f(m_reg[rs]);
@ -1439,7 +1439,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x15: // DP - DP -> DP
case 0x15: // DP - DP -> DP
{
double s1 = u2d(m_fpair[src1 >> 1]);
double s2 = u2d(m_fpair[rs >> 1]);
@ -1455,25 +1455,25 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xe2:
case 0xe3: // fsub
case 0xe3: // fsub
{
int rd = OP_RD();
int rs = OP_RS();
int src1 = OP_SRC1();
int precision = (m_ir >> 5) & 0x3f;
if (rd) // only calculate if destination register is valid
if (rd) // only calculate if destination register is valid
{
switch (precision)
{
case 0x00: // SP - SP -> SP
case 0x00: // SP - SP -> SP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
float s2 = u2f(m_reg[rs]);
m_reg[rd] = f2u(s1 - s2);
break;
}
case 0x10: // SP - SP -> DP
case 0x10: // SP - SP -> DP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
float s2 = u2f(m_reg[rs]);
@ -1481,7 +1481,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x14: // SP - DP -> DP
case 0x14: // SP - DP -> DP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
double s2 = u2d(m_fpair[rs >> 1]);
@ -1489,7 +1489,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x11: // DP - SP -> DP
case 0x11: // DP - SP -> DP
{
double s1 = u2d(m_fpair[src1 >> 1]);
float s2 = u2f(m_reg[rs]);
@ -1497,7 +1497,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x15: // DP - DP -> DP
case 0x15: // DP - DP -> DP
{
double s1 = u2d(m_fpair[src1 >> 1]);
double s2 = u2d(m_fpair[rs >> 1]);
@ -1513,25 +1513,25 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xe4:
case 0xe5: // fmpy
case 0xe5: // fmpy
{
int rd = OP_RD();
int rs = OP_RS();
int src1 = OP_SRC1();
int precision = (m_ir >> 5) & 0x3f;
if (rd) // only calculate if destination register is valid
if (rd) // only calculate if destination register is valid
{
switch (precision)
{
case 0x00: // SP x SP -> SP
case 0x00: // SP x SP -> SP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
float s2 = u2f(m_reg[rs]);
m_reg[rd] = f2u(s1 * s2);
break;
}
case 0x10: // SP x SP -> DP
case 0x10: // SP x SP -> DP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
float s2 = u2f(m_reg[rs]);
@ -1539,7 +1539,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x14: // SP x DP -> DP
case 0x14: // SP x DP -> DP
{
float s1 = u2f(has_imm ? imm32 : m_reg[src1]);
double s2 = u2d(m_fpair[rs >> 1]);
@ -1547,7 +1547,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x11: // DP x SP -> DP
case 0x11: // DP x SP -> DP
{
double s1 = u2d(m_fpair[src1 >> 1]);
float s2 = u2f(m_reg[rs]);
@ -1555,7 +1555,7 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x15: // DP x DP -> DP
case 0x15: // DP x DP -> DP
{
double s1 = u2d(m_fpair[src1 >> 1]);
double s2 = u2d(m_fpair[rs >> 1]);
@ -1563,12 +1563,12 @@ void tms32082_mp_device::execute_reg_long_imm()
m_fpair[rd >> 1] = res;
break;
}
case 0x2a: // I x I -> I
case 0x2a: // I x I -> I
{
m_reg[rd] = (INT32)(m_reg[rs]) * (INT32)(has_imm ? imm32 : m_reg[OP_SRC1()]);
break;
}
case 0x3f: // U x U -> U
case 0x3f: // U x U -> U
{
m_reg[rd] = (UINT32)(m_reg[rs]) * (UINT32)(has_imm ? imm32 : m_reg[OP_SRC1()]);
break;
@ -1581,7 +1581,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xe6:
case 0xe7: // fdiv
case 0xe7: // fdiv
{
int rd = OP_RD();
int p1 = m_ir & (1 << 5);
@ -1606,7 +1606,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xe8:
case 0xe9: // frnd
case 0xe9: // frnd
{
//int mode = (m_ir >> 7) & 3;
int p1 = (m_ir >> 5) & 3;
@ -1654,9 +1654,9 @@ void tms32082_mp_device::execute_reg_long_imm()
}
break;
}
case 0xea:
case 0xeb: // fcmp
case 0xeb: // fcmp
{
int rd = OP_RD();
int p1 = m_ir & (1 << 5);
@ -1689,7 +1689,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xee:
case 0xef: // fsqrt
case 0xef: // fsqrt
{
int rd = OP_RD();
int src1 = OP_SRC1();
@ -1709,7 +1709,7 @@ void tms32082_mp_device::execute_reg_long_imm()
break;
}
case 0xf2: // rmo
case 0xf2: // rmo
{
UINT32 source = m_reg[OP_RS()];
int rd = OP_RD();

46
src/emu/cpu/tms32082/tms32082.c
View File

@ -22,7 +22,7 @@ const device_type TMS32082_PP = &device_creator<tms32082_pp_device>;
// internal memory map
static ADDRESS_MAP_START(mp_internal_map, AS_PROGRAM, 32, tms32082_mp_device)
AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0")
AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0")
AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("pp1_data0")
AM_RANGE(0x00008000, 0x00008fff) AM_RAM AM_SHARE("pp0_data1")
AM_RANGE(0x00009000, 0x00009fff) AM_RAM AM_SHARE("pp1_data1")
@ -141,7 +141,7 @@ void tms32082_mp_device::device_start()
save_item(NAME(m_fetchpc));
save_item(NAME(m_reg));
save_item(NAME(m_acc));
save_item(NAME(m_in0p));
save_item(NAME(m_in1p));
save_item(NAME(m_outp));
@ -256,7 +256,7 @@ void tms32082_mp_device::processor_command(UINT32 command)
printf("Task ");
if (command & 0x00002000)
printf("Msg ");
printf("to: ");
if (command & 0x00000400)
@ -300,28 +300,28 @@ UINT32 tms32082_mp_device::read_creg(int reg)
{
switch (reg)
{
case 0x0: // EPC
case 0x0: // EPC
return m_epc;
case 0x1: // EIP
case 0x1: // EIP
return m_eip;
case 0x4: // INTPEN
case 0x4: // INTPEN
return m_intpen;
case 0x6: // IE
case 0x6: // IE
return m_ie;
case 0xa: // PPERROR
return 0xe0000;
case 0x4000: // IN0P
case 0x4000: // IN0P
return m_in0p;
case 0x4001: // IN1P
case 0x4001: // IN1P
return m_in1p;
case 0x4002: // OUTP
case 0x4002: // OUTP
return m_outp;
default:
@ -335,15 +335,15 @@ void tms32082_mp_device::write_creg(int reg, UINT32 data)
{
switch (reg)
{
case 0x0: // EPC
case 0x0: // EPC
m_epc = data;
break;
case 0x1: // EIP
case 0x1: // EIP
m_eip = data;
break;
case 0x4: // INTPEN
case 0x4: // INTPEN
{
for (int i=0; i < 32; i++)
{
@ -353,20 +353,20 @@ void tms32082_mp_device::write_creg(int reg, UINT32 data)
break;
}
case 0x6: // IE
case 0x6: // IE
m_ie = data;
printf("IE = %08X\n", data);
break;
case 0x4000: // IN0P
case 0x4000: // IN0P
m_in0p = data;
break;
case 0x4001: // IN1P
case 0x4001: // IN1P
m_in1p = data;
break;
case 0x4002: // OUTP
case 0x4002: // OUTP
m_outp = data;
break;
@ -378,19 +378,19 @@ void tms32082_mp_device::write_creg(int reg, UINT32 data)
void tms32082_mp_device::check_interrupts()
{
if (m_ie & 1) // global interrupt mask
if (m_ie & 1) // global interrupt mask
{
for (int i=1; i < 32; i++)
{
if (m_ie & m_intpen & (1 << i))
{
m_epc = (m_fetchpc & ~3);
m_epc |= (m_ie & 1); // save global interrupt mask
m_epc |= (m_ie & 1); // save global interrupt mask
// TODO: user mode bit to EPC
m_eip = m_pc;
m_ie &= ~1; // clear global interrupt mask
m_ie &= ~1; // clear global interrupt mask
// get new pc from vector table
m_fetchpc = m_pc = m_program->read_dword(0x01010180 + (i * 4));
@ -445,7 +445,7 @@ void tms32082_mp_device::execute_run()
while (m_icount > 0)
{
m_pc = m_fetchpc;
check_interrupts();
debugger_instruction_hook(this, m_pc);
@ -466,7 +466,7 @@ void tms32082_mp_device::execute_run()
// internal memory map
static ADDRESS_MAP_START(pp_internal_map, AS_PROGRAM, 32, tms32082_pp_device)
AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0")
AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0")
AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("pp1_data0")
AM_RANGE(0x00008000, 0x00008fff) AM_RAM AM_SHARE("pp0_data1")
AM_RANGE(0x00009000, 0x00009fff) AM_RAM AM_SHARE("pp1_data1")
@ -528,4 +528,4 @@ void tms32082_pp_device::execute_run()
m_icount = 0;
return;
}
}

8
src/emu/cpu/tms32082/tms32082.h
View File

@ -58,10 +58,10 @@ public:
enum
{
INPUT_X1 = 1,
INPUT_X2 = 2,
INPUT_X3 = 3,
INPUT_X4 = 4,
INPUT_X1 = 1,
INPUT_X2 = 2,
INPUT_X3 = 3,
INPUT_X4 = 4,
};
DECLARE_READ32_MEMBER(mp_param_r);

1
src/emu/cpu/tms34010/tms34010.c
View File

@ -1842,4 +1842,3 @@ tms34020_device::tms34020_device(const machine_config &mconfig, device_type type
}
const device_type TMS34020 = &legacy_device_creator<tms34020_device>;

4
src/emu/cpu/tms34010/tms34010.h
View File

@ -210,10 +210,10 @@ class tms34010_device : public legacy_cpu_device
public:
tms34010_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
tms34010_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func get_info);
UINT32 tms340x0_ind16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
UINT32 tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
};
};
extern const device_type TMS34010;

2
src/emu/cpu/tms9900/99xxcore.h
View File

@ -4781,7 +4781,7 @@ void TMS99XX_GET_INFO(legacy_cpu_device *device, UINT32 state, cpuinfo *info)
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, TMS99XX_device_get_name); break;
case CPUINFO_STR_SHORTNAME: strcpy(info->s, TMS99XX_device_get_shortname); break;
case CPUINFO_STR_FAMILY: strcpy(info->s, "Texas Instruments 9900L"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "2.0"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;

4
src/emu/debug/debugcmd.c
View File

@ -1495,8 +1495,8 @@ static void execute_wplist(running_machine &machine, int ref, int params, const
{
static const char *const types[] = { "unkn ", "read ", "write", "r/w " };
debug_console_printf(machine, "Device '%s' %s space watchpoints:\n", device->tag(),
device->debug()->watchpoint_first(spacenum)->space().name());
debug_console_printf(machine, "Device '%s' %s space watchpoints:\n", device->tag(),
device->debug()->watchpoint_first(spacenum)->space().name());
/* loop over the watchpoints */
for (device_debug::watchpoint *wp = device->debug()->watchpoint_first(spacenum); wp != NULL; wp = wp->next())

58
src/emu/debug/debugcpu.c
View File

@ -3279,18 +3279,18 @@ void device_debug::set_state(symbol_table &table, void *ref, UINT64 value)
//-------------------------------------------------
device_debug::breakpoint::breakpoint(device_debug* debugInterface,
symbol_table &symbols,
int index,
offs_t address,
const char *condition,
const char *action)
symbol_table &symbols,
int index,
offs_t address,
const char *condition,
const char *action)
: m_debugInterface(debugInterface),
m_next(NULL),
m_index(index),
m_enabled(true),
m_address(address),
m_condition(&symbols, (condition != NULL) ? condition : "1"),
m_action((action != NULL) ? action : "")
m_next(NULL),
m_index(index),
m_enabled(true),
m_address(address),
m_condition(&symbols, (condition != NULL) ? condition : "1"),
m_action((action != NULL) ? action : "")
{
}
@ -3335,25 +3335,25 @@ bool device_debug::breakpoint::hit(offs_t pc)
// watchpoint - constructor
//-------------------------------------------------
device_debug::watchpoint::watchpoint(device_debug* debugInterface,
symbol_table &symbols,
int index,
address_space &space,
int type,
offs_t address,
offs_t length,
const char *condition,
const char *action)
device_debug::watchpoint::watchpoint(device_debug* debugInterface,
symbol_table &symbols,
int index,
address_space &space,
int type,
offs_t address,
offs_t length,
const char *condition,
const char *action)
: m_debugInterface(debugInterface),
m_next(NULL),
m_space(space),
m_index(index),
m_enabled(true),
m_type(type),
m_address(space.address_to_byte(address) & space.bytemask()),
m_length(space.address_to_byte(length)),
m_condition(&symbols, (condition != NULL) ? condition : "1"),
m_action((action != NULL) ? action : "")
m_next(NULL),
m_space(space),
m_index(index),
m_enabled(true),
m_type(type),
m_address(space.address_to_byte(address) & space.bytemask()),
m_length(space.address_to_byte(length)),
m_condition(&symbols, (condition != NULL) ? condition : "1"),
m_action((action != NULL) ? action : "")
{
}

26
src/emu/debug/debugcpu.h
View File

@ -80,11 +80,11 @@ public:
public:
// construction/destruction
breakpoint(device_debug* debugInterface,
symbol_table &symbols,
int index,
offs_t address,
const char *condition = NULL,
const char *action = NULL);
symbol_table &symbols,
int index,
offs_t address,
const char *condition = NULL,
const char *action = NULL);
// getters
const device_debug *debugInterface() const { return m_debugInterface; }
@ -119,14 +119,14 @@ public:
public:
// construction/destruction
watchpoint(device_debug* debugInterface,
symbol_table &symbols,
int index,
address_space &space,
int type,
offs_t address,
offs_t length,
const char *condition = NULL,
const char *action = NULL);
symbol_table &symbols,
int index,
address_space &space,
int type,
offs_t address,
offs_t length,
const char *condition = NULL,
const char *action = NULL);
// getters
const device_debug *debugInterface() const { return m_debugInterface; }

6
src/emu/debug/dvwpoints.c
View File

@ -496,9 +496,9 @@ void debug_view_watchpoints::view_update()
pad_astring_to_length(buffer, tableBreaks[2]);
buffer.catprintf("%s", wp->space().name());
pad_astring_to_length(buffer, tableBreaks[3]);
buffer.catprintf("%s-%s",
core_i64_hex_format(wp->space().byte_to_address(wp->address()), wp->space().addrchars()),
core_i64_hex_format(wp->space().byte_to_address_end(wp->address() + wp->length()) - 1, wp->space().addrchars()));
buffer.catprintf("%s-%s",
core_i64_hex_format(wp->space().byte_to_address(wp->address()), wp->space().addrchars()),
core_i64_hex_format(wp->space().byte_to_address_end(wp->address() + wp->length()) - 1, wp->space().addrchars()));
pad_astring_to_length(buffer, tableBreaks[4]);
buffer.catprintf("%s", types[wp->type() & 3]);
pad_astring_to_length(buffer, tableBreaks[5]);

4
src/emu/divideo.c
View File

@ -104,7 +104,7 @@ void device_video_interface::interface_validity_check(validity_checker &valid) c
if (screen == NULL)
mame_printf_error("Screen '%s' not found, explicitly set for device '%s'", m_screen_tag, device().tag());
}
// otherwise, look for a single match
else
{
@ -138,7 +138,7 @@ void device_video_interface::interface_pre_start()
if (m_screen == NULL)
throw emu_fatalerror("Screen '%s' not found, explicitly set for device '%s'", m_screen_tag, device().tag());
}
// otherwise, look for a single match
else
{

8
src/emu/divideo.h
View File

@ -81,13 +81,13 @@ protected:
// optional operation overrides
virtual void interface_validity_check(validity_checker &valid) const;
virtual void interface_pre_start();
// configuration state
bool m_screen_required; // is a screen required?
const char * m_screen_tag; // configured tag for the target screen
bool m_screen_required; // is a screen required?
const char * m_screen_tag; // configured tag for the target screen
// internal state
screen_device * m_screen; // pointer to the screen device
screen_device * m_screen; // pointer to the screen device
};
// iterator

8
src/emu/emuopts.c
View File

@ -189,8 +189,8 @@ const options_entry emu_options::s_option_entries[] =
// misc options
{ NULL, NULL, OPTION_HEADER, "CORE MISC OPTIONS" },
{ OPTION_DRC, "1", OPTION_BOOLEAN, "enable DRC cpu core if available" },
{ OPTION_DRC_USE_C, "0", OPTION_BOOLEAN, "force DRC use C backend" },
{ OPTION_DRC, "1", OPTION_BOOLEAN, "enable DRC cpu core if available" },
{ OPTION_DRC_USE_C, "0", OPTION_BOOLEAN, "force DRC use C backend" },
{ OPTION_BIOS, NULL, OPTION_STRING, "select the system BIOS to use" },
{ OPTION_CHEAT ";c", "0", OPTION_BOOLEAN, "enable cheat subsystem" },
{ OPTION_SKIP_GAMEINFO, "0", OPTION_BOOLEAN, "skip displaying the information screen at startup" },
@ -202,8 +202,8 @@ const options_entry emu_options::s_option_entries[] =
{ OPTION_AUTOBOOT_DELAY, "2", OPTION_INTEGER, "timer delay in sec to trigger command execution on autoboot" },
{ OPTION_AUTOBOOT_SCRIPT ";script", NULL, OPTION_STRING, "lua script to execute after machine boot" },
{ OPTION_HTTP, "0", OPTION_BOOLEAN, "enable local http server" },
{ OPTION_HTTP_PORT, "8080", OPTION_INTEGER, "http server listener port" },
{ OPTION_HTTP_PATH, "web", OPTION_STRING, "path to web files" },
{ OPTION_HTTP_PORT, "8080", OPTION_INTEGER, "http server listener port" },
{ OPTION_HTTP_PATH, "web", OPTION_STRING, "path to web files" },
{ NULL }
};

8
src/emu/emuopts.h
View File

@ -206,9 +206,9 @@ enum
#define OPTION_AUTOBOOT_DELAY "autoboot_delay"
#define OPTION_AUTOBOOT_SCRIPT "autoboot_script"
#define OPTION_HTTP "http"
#define OPTION_HTTP_PORT "http_port"
#define OPTION_HTTP_PATH "http_path"
#define OPTION_HTTP "http"
#define OPTION_HTTP_PORT "http_port"
#define OPTION_HTTP_PATH "http_path"
//**************************************************************************
// TYPE DEFINITIONS
@ -369,7 +369,7 @@ public:
const char *autoboot_command() const { return value(OPTION_AUTOBOOT_COMMAND); }
int autoboot_delay() const { return int_value(OPTION_AUTOBOOT_DELAY); }
const char *autoboot_script() const { return value(OPTION_AUTOBOOT_SCRIPT); }
bool http() const { return bool_value(OPTION_HTTP); }
const char *http_port() const { return value(OPTION_HTTP_PORT); }
const char *http_path() const { return value(OPTION_HTTP_PATH); }

2
src/emu/machine.c
View File

@ -394,7 +394,7 @@ int running_machine::run(bool firstrun)
bool settingsloaded = config_load_settings(*this);
nvram_load(*this);
sound().ui_mute(false);
// initialize ui lists
ui_initialize(*this);

4
src/emu/machine/40105.c
View File

@ -37,8 +37,8 @@ const device_type CMOS_40105 = &device_creator<cmos_40105_device>;
cmos_40105_device::cmos_40105_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, CMOS_40105, "40105", tag, owner, clock, "40105", __FILE__),
m_write_dir(*this),
m_write_dor(*this)
m_write_dir(*this),
m_write_dor(*this)
{
}

2
src/emu/machine/40105.h
View File

@ -48,7 +48,7 @@ public:
DECLARE_WRITE_LINE_MEMBER( si_w );
DECLARE_WRITE_LINE_MEMBER( so_w );
DECLARE_READ_LINE_MEMBER( dir_r );
DECLARE_READ_LINE_MEMBER( dor_r );

5
src/emu/machine/74148.c
View File

@ -70,12 +70,12 @@ void ttl74148_device::device_config_complete()
const ttl74148_config *intf = reinterpret_cast<const ttl74148_config *>(static_config());
if (intf != NULL)
*static_cast<ttl74148_config *>(this) = *intf;
// or initialize to defaults if none provided
else
{
}
}
//-------------------------------------------------
@ -100,7 +100,6 @@ void ttl74148_device::device_start()
void ttl74148_device::device_reset()
{
m_enable_input = 1;
m_input_lines[0] = 1;
m_input_lines[1] = 1;

8
src/emu/machine/74153.c
View File

@ -52,13 +52,13 @@ ttl74153_device::ttl74153_device(const machine_config &mconfig, const char *tag,
m_input_lines[1][1] = 0;
m_input_lines[1][2] = 0;
m_input_lines[1][3] = 0;
for (int i = 0; i < 2; i++)
m_enable[i] = 0;
for (int i = 0; i < 2; i++)
m_output[i] = 0;
for (int i = 0; i < 2; i++)
m_last_output[i] = 0;
}
@ -75,7 +75,7 @@ void ttl74153_device::device_config_complete()
const ttl74153_config *intf = reinterpret_cast<const ttl74153_config *>(static_config());
if (intf != NULL)
*static_cast<ttl74153_config *>(this) = *intf;
// or initialize to defaults if none provided
else
{

4
src/emu/machine/74153.h
View File

@ -59,13 +59,13 @@ public:
void input_line_w(int section, int input_line, int data);
void enable_w(int section, int data);
int output_r(int section);
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
private:
// internal state

3
src/emu/machine/74181.h
View File

@ -19,8 +19,7 @@
//**************************************************************************
#define MCFG_TTL74181_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, TTL74181, 0) \
MCFG_DEVICE_ADD(_tag, TTL74181, 0)
//**************************************************************************
// TYPE DEFINITIONS

6
src/emu/machine/aicartc.c
View File

@ -1,9 +1,9 @@
/***************************************************************************
AICA-RTC sub-device
AICA-RTC sub-device
TODO:
- move this inside AICA sound core once that'll get modernized
TODO:
- move this inside AICA sound core once that'll get modernized
***************************************************************************/

2
src/emu/machine/aicartc.h
View File

@ -25,7 +25,7 @@ Template for skeleton device
// ======================> aicartc_device
class aicartc_device : public device_t,
public device_rtc_interface
public device_rtc_interface
{
public:
// construction/destruction

2
src/emu/machine/atahle.c
View File

@ -239,7 +239,7 @@ bool ata_hle_device::set_dma_mode(int word)
m_identify_buffer[word] |= 0x100 << (m_sector_count & 7);
return true;
}
return false;
}

2
src/emu/machine/ataintf.c
View File

@ -141,7 +141,7 @@ READ16_MEMBER( ata_interface_device::read_cs0 )
if (m_slot[i]->dev() != NULL)
result &= m_slot[i]->dev()->read_cs0(space, offset, mem_mask);
// { static int last_status = -1; if (offset == 7 ) { if( result == last_status ) return last_status; last_status = result; } else last_status = -1; }
// { static int last_status = -1; if (offset == 7 ) { if( result == last_status ) return last_status; last_status = result; } else last_status = -1; }
// printf( "read cs0 %04x %04x %04x\n", offset, result, mem_mask );

18
src/emu/machine/eeprom.c
View File

@ -87,10 +87,10 @@ eeprom_base_device::eeprom_base_device(const machine_config &mconfig, device_typ
m_completion_time(attotime::zero)
{
// a 2ms write time is too long for rfjetsa
m_operation_time[WRITE_TIME] = attotime::from_usec(1750);
m_operation_time[WRITE_ALL_TIME] = attotime::from_usec(8000);
m_operation_time[ERASE_TIME] = attotime::from_usec(1000);
m_operation_time[ERASE_ALL_TIME] = attotime::from_usec(8000);
m_operation_time[WRITE_TIME] = attotime::from_usec(1750);
m_operation_time[WRITE_ALL_TIME] = attotime::from_usec(8000);
m_operation_time[ERASE_TIME] = attotime::from_usec(1000);
m_operation_time[ERASE_ALL_TIME] = attotime::from_usec(8000);
}
@ -195,8 +195,8 @@ void eeprom_base_device::write(offs_t address, UINT32 data)
//-------------------------------------------------
// write_all - write data at all addresses
// (assumes an erase has previously been
// performed)
// (assumes an erase has previously been
// performed)
//-------------------------------------------------
void eeprom_base_device::write_all(UINT32 data)
@ -308,7 +308,7 @@ void eeprom_base_device::nvram_default()
if (m_default_data.u8 != NULL)
{
mame_printf_verbose("Warning: Driver-specific EEPROM defaults are going away soon.\n");
for (offs_t offs = 0; offs < m_default_data_size; offs++)
for (offs_t offs = 0; offs < m_default_data_size; offs++)
{
if (m_data_bits == 8)
m_addrspace[0]->write_byte(offs, m_default_data.u8[offs]);
@ -385,8 +385,8 @@ UINT32 eeprom_base_device::internal_read(offs_t address)
//-------------------------------------------------
// internal_write - write data at the given
// address
// internal_write - write data at the given
// address
//-------------------------------------------------
void eeprom_base_device::internal_write(offs_t address, UINT32 data)

24
src/emu/machine/eeprom.h
View File

@ -72,7 +72,7 @@
// ======================> eeprom_base_device
class eeprom_base_device : public device_t,
class eeprom_base_device : public device_t,
public device_memory_interface,
public device_nvram_interface
{
@ -84,10 +84,10 @@ public:
// timing constants
enum timing_type
{
WRITE_TIME, // default = 2ms
WRITE_ALL_TIME, // default = 8ms
ERASE_TIME, // default = 1ms
ERASE_ALL_TIME, // default = 8ms
WRITE_TIME, // default = 2ms
WRITE_ALL_TIME, // default = 8ms
ERASE_TIME, // default = 1ms
ERASE_ALL_TIME, // default = 8ms
TIMING_COUNT
};
@ -104,10 +104,10 @@ public:
void write_all(UINT32 data);
void erase(offs_t address);
void erase_all();
// status
bool ready() const { return machine().time() >= m_completion_time; }
protected:
// device-level overrides
virtual void device_validity_check(validity_checker &valid) const;
@ -127,18 +127,18 @@ protected:
void internal_write(offs_t address, UINT32 data);
// configuration state
UINT32 m_cells;
UINT8 m_address_bits;
UINT8 m_data_bits;
UINT32 m_cells;
UINT8 m_address_bits;
UINT8 m_data_bits;
address_space_config m_space_config;
generic_ptr m_default_data;
UINT32 m_default_data_size;
UINT32 m_default_value;
bool m_default_value_set;
attotime m_operation_time[TIMING_COUNT];
attotime m_operation_time[TIMING_COUNT];
// live state
attotime m_completion_time;
attotime m_completion_time;
};

55
src/emu/machine/eeprompar.c
View File

@ -37,33 +37,33 @@
****************************************************************************
Parallel EEPROMs are generally simpler than serial EEPROMs, though
they require more pins to provide the full set of address and data
lines necessary. They also require more pins the larger the EEPROM
is, whereas serial EEPROMs all share the same pinout regardless of
size.
At a basic level, there are 5 sets of signals involved:
* /CE = chip enable
* /OE = output enable
* /WE = write enable
* D0-Dn = data lines
* A0-An = address lines
Parallel EEPROMs are generally simpler than serial EEPROMs, though
they require more pins to provide the full set of address and data
lines necessary. They also require more pins the larger the EEPROM
is, whereas serial EEPROMs all share the same pinout regardless of
size.
To access the chip, the various enable states must be asserted or
cleared. Note that these are generally active-low, so asserted means
pulled to GND, and cleared means pulled to Vcc:
/CE /OE /WE Action
ASSERT ASSERT CLEAR Read (D0-Dn contain output data)
ASSERT CLEAR ASSERT Write/Erase (D0-Dn are input data)
Erase is performed by doing a write with D0-Dn all set to 1.
In general, it is slow to write or erase (9ms is quoted in the 2816A
datasheet, for example), and the /WE must be held low for the entire
write/erase duration in order to guarantee the data is written.
At a basic level, there are 5 sets of signals involved:
* /CE = chip enable
* /OE = output enable
* /WE = write enable
* D0-Dn = data lines
* A0-An = address lines
To access the chip, the various enable states must be asserted or
cleared. Note that these are generally active-low, so asserted means
pulled to GND, and cleared means pulled to Vcc:
/CE /OE /WE Action
ASSERT ASSERT CLEAR Read (D0-Dn contain output data)
ASSERT CLEAR ASSERT Write/Erase (D0-Dn are input data)
Erase is performed by doing a write with D0-Dn all set to 1.
In general, it is slow to write or erase (9ms is quoted in the 2816A
datasheet, for example), and the /WE must be held low for the entire
write/erase duration in order to guarantee the data is written.
***************************************************************************/
@ -150,8 +150,7 @@ eeprom_parallel_##_lowercase##_device::eeprom_parallel_##_lowercase##_device(con
{ \
static_set_size(*this, _cells, _bits); \
}; \
const device_type EEPROM_PARALLEL_##_uppercase = &device_creator<eeprom_parallel_##_lowercase##_device>; \
const device_type EEPROM_PARALLEL_##_uppercase = &device_creator<eeprom_parallel_##_lowercase##_device>;
// standard 28XX class of 8-bit EEPROMs
DEFINE_PARALLEL_EEPROM_DEVICE(28xx, 2804, 2804, 8, 512)
DEFINE_PARALLEL_EEPROM_DEVICE(28xx, 2816, 2816, 8, 2048)

3
src/emu/machine/eeprompar.h
View File

@ -120,8 +120,7 @@ class eeprom_parallel_##_lowercase##_device : public eeprom_parallel_##_baseclas
public: \
eeprom_parallel_##_lowercase##_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); \
}; \
extern const device_type EEPROM_PARALLEL_##_uppercase; \
extern const device_type EEPROM_PARALLEL_##_uppercase;
// standard 28XX class of 8-bit EEPROMs
DECLARE_PARALLEL_EEPROM_DEVICE(28xx, 2804, 2804)
DECLARE_PARALLEL_EEPROM_DEVICE(28xx, 2816, 2816)

279
src/emu/machine/eepromser.c
View File

@ -37,95 +37,95 @@
****************************************************************************
Serial EEPROMs generally work the same across manufacturers and models,
varying largely by the size of the EEPROM and the packaging details.
At a basic level, there are 5 signals involved:
* CS = chip select
* CLK = serial data clock
* DI = serial data in
* DO = serial data out
* RDY/BUSY = ready (1) or busy (0) status
Data is read or written via serial commands. A command is begun on a
low-to-high transition of the CS line, following by clocking a start
bit (1) on the DI line. After the start bit, subsequent clocks
assemble one of the following commands:
Start Opcode Address Data
1 01 aaaaaaaaa ddddddd WRITE data
1 10 aaaaaaaaa READ data
1 11 aaaaaaaaa ERASE data
1 00 00xxxxxxx WREN = WRite ENable
1 00 01xxxxxxx ddddddd WRAL = WRite ALl cells
1 00 10xxxxxxx ERAL = ERase ALl cells
1 00 11xxxxxxx WRDS = WRite DiSable
Serial EEPROMs generally work the same across manufacturers and models,
varying largely by the size of the EEPROM and the packaging details.
The number of address bits (a) clocked varies based on the size of the
chip, though it does not always map 1:1 with the size of the chip.
For example, the 93C06 has 16 cells, which only needs 4 address bits;
but commands to the 93C06 require 6 address bits (the top two must
be 0).
The number of data bits (d) clocked varies based on the chip and at
times on the state of a pin on the chip which selects between multiple
sizes (e.g., 8-bit versus 16-bit).
****************************************************************************
At a basic level, there are 5 signals involved:
Most EEPROMs are based on the 93Cxx design (and have similar part
designations):
+--v--+
CS |1 8| Vcc
CLK |2 7| NC
DI |3 6| NC
DO |4 5| GND
+-----+
Note the lack of a READY/BUSY pin. On the 93Cxx series, the DO pin
serves double-duty, returning READY/BUSY during a write/erase cycle,
and outputting data during a read cycle.
Some manufacturers have released "enhanced" versions with additional
features:
* Several manufacturers (ST) map pin 6 to "ORG", specifying the
logical organization of the data. Connecting ORG to ground
makes the EEPROM work as an 8-bit device, while connecting it
to Vcc makes it work as a 16-bit device with one less
address bit.
* Other manufacturers (ST) have enhanced the read operations to
allow serially streaming more than one cell. Essentially, after
reading the first cell, keep CS high and keep clocking, and
data from following cells will be read as well.
* CS = chip select
* CLK = serial data clock
* DI = serial data in
* DO = serial data out
* RDY/BUSY = ready (1) or busy (0) status
The ER5911 is only slightly different:
+--v--+
CS |1 8| Vcc
CLK |2 7| RDY/BUSY
DI |3 6| ORG
DO |4 5| GND
+-----+
Here we have an explicit RDY/BUSY signal, and the ORG flag as described
above.
Data is read or written via serial commands. A command is begun on a
low-to-high transition of the CS line, following by clocking a start
bit (1) on the DI line. After the start bit, subsequent clocks
assemble one of the following commands:
From a command perspective, the ER5911 is also slightly different:
93Cxx has ERASE command; this maps to WRITE on ER5911
93Cxx has WRITEALL command; no equivalent on ER5911
Start Opcode Address Data
1 01 aaaaaaaaa ddddddd WRITE data
1 10 aaaaaaaaa READ data
1 11 aaaaaaaaa ERASE data
1 00 00xxxxxxx WREN = WRite ENable
1 00 01xxxxxxx ddddddd WRAL = WRite ALl cells
1 00 10xxxxxxx ERAL = ERase ALl cells
1 00 11xxxxxxx WRDS = WRite DiSable
The number of address bits (a) clocked varies based on the size of the
chip, though it does not always map 1:1 with the size of the chip.
For example, the 93C06 has 16 cells, which only needs 4 address bits;
but commands to the 93C06 require 6 address bits (the top two must
be 0).
The number of data bits (d) clocked varies based on the chip and at
times on the state of a pin on the chip which selects between multiple
sizes (e.g., 8-bit versus 16-bit).
****************************************************************************
Issues with:
kickgoal.c - code seems wrong, clock logic writes 0-0-0 instead of 0-1-0 as expected
overdriv.c - drops CS, raises CS, keeps DI=1, triggering extraneous start bit
Most EEPROMs are based on the 93Cxx design (and have similar part
designations):
+--v--+
CS |1 8| Vcc
CLK |2 7| NC
DI |3 6| NC
DO |4 5| GND
+-----+
Note the lack of a READY/BUSY pin. On the 93Cxx series, the DO pin
serves double-duty, returning READY/BUSY during a write/erase cycle,
and outputting data during a read cycle.
Some manufacturers have released "enhanced" versions with additional
features:
* Several manufacturers (ST) map pin 6 to "ORG", specifying the
logical organization of the data. Connecting ORG to ground
makes the EEPROM work as an 8-bit device, while connecting it
to Vcc makes it work as a 16-bit device with one less
address bit.
* Other manufacturers (ST) have enhanced the read operations to
allow serially streaming more than one cell. Essentially, after
reading the first cell, keep CS high and keep clocking, and
data from following cells will be read as well.
The ER5911 is only slightly different:
+--v--+
CS |1 8| Vcc
CLK |2 7| RDY/BUSY
DI |3 6| ORG
DO |4 5| GND
+-----+
Here we have an explicit RDY/BUSY signal, and the ORG flag as described
above.
From a command perspective, the ER5911 is also slightly different:
93Cxx has ERASE command; this maps to WRITE on ER5911
93Cxx has WRITEALL command; no equivalent on ER5911
****************************************************************************
Issues with:
kickgoal.c - code seems wrong, clock logic writes 0-0-0 instead of 0-1-0 as expected
overdriv.c - drops CS, raises CS, keeps DI=1, triggering extraneous start bit
***************************************************************************/
#include "emu.h"
@ -138,11 +138,11 @@
//**************************************************************************
// logging levels:
// 0 = errors and warnings only
// 1 = commands
// 2 = state machine
// 3 = DI/DO/READY reads & writes
// 4 = all reads & writes
// 0 = errors and warnings only
// 1 = commands
// 2 = state machine
// 3 = DI/DO/READY reads & writes
// 4 = all reads & writes
#define VERBOSE_PRINTF 0
#define VERBOSE_LOGERROR 0
@ -195,7 +195,7 @@ eeprom_serial_base_device::eeprom_serial_base_device(const machine_config &mconf
//-------------------------------------------------
// static_set_address_bits - configuration helper
// to set the number of address bits in the
// serial commands
// serial commands
//-------------------------------------------------
void eeprom_serial_base_device::static_set_address_bits(device_t &device, int addrbits)
@ -227,7 +227,7 @@ void eeprom_serial_base_device::device_start()
// start the base class
eeprom_base_device::device_start();
// save the current state
save_item(NAME(m_state));
save_item(NAME(m_cs_state));
@ -269,8 +269,8 @@ void eeprom_serial_base_device::device_reset()
//**************************************************************************
//-------------------------------------------------
// base_cs_write - set the state of the chip
// select (CS) line
// base_cs_write - set the state of the chip
// select (CS) line
//-------------------------------------------------
void eeprom_serial_base_device::base_cs_write(int state)
@ -280,10 +280,10 @@ void eeprom_serial_base_device::base_cs_write(int state)
if (state == m_cs_state)
return;
// set the new state
// set the new state
LOG4((" cs_write(%d)\n", state));
m_cs_state = state;
// remember the rising edge time so we don't process CLK signals at the same time
if (state == ASSERT_LINE)
m_last_cs_rising_edge_time = machine().time();
@ -292,7 +292,7 @@ void eeprom_serial_base_device::base_cs_write(int state)
//-------------------------------------------------
// base_clk_write - set the state of the clock
// base_clk_write - set the state of the clock
// (CLK) line
//-------------------------------------------------
@ -303,7 +303,7 @@ void eeprom_serial_base_device::base_clk_write(int state)
if (state == m_clk_state)
return;
// set the new state
// set the new state
LOG4((" clk_write(%d)\n", state));
m_clk_state = state;
handle_event((m_clk_state == ASSERT_LINE) ? EVENT_CLK_RISING_EDGE : EVENT_CLK_FALLING_EDGE);
@ -311,8 +311,8 @@ void eeprom_serial_base_device::base_clk_write(int state)
//-------------------------------------------------
// base_di_write - set the state of the data input
// (DI) line
// base_di_write - set the state of the data input
// (DI) line
//-------------------------------------------------
void eeprom_serial_base_device::base_di_write(int state)
@ -325,7 +325,7 @@ void eeprom_serial_base_device::base_di_write(int state)
//-------------------------------------------------
// base_do_read - read the state of the data
// base_do_read - read the state of the data
// output (DO) line
//-------------------------------------------------
@ -341,7 +341,7 @@ int eeprom_serial_base_device::base_do_read()
//-------------------------------------------------
// base_ready_read - read the state of the
// base_ready_read - read the state of the
// READY/BUSY line
//-------------------------------------------------
@ -390,7 +390,7 @@ void eeprom_serial_base_device::set_state(eeprom_state newstate)
//-------------------------------------------------
// handle_event - handle an event via the state
// machine
// machine
//-------------------------------------------------
void eeprom_serial_base_device::handle_event(eeprom_event event)
@ -421,7 +421,7 @@ void eeprom_serial_base_device::handle_event(eeprom_event event)
if (event == EVENT_CS_RISING_EDGE)
set_state(STATE_WAIT_FOR_START_BIT);
break;
// CS is asserted; wait for rising clock with a 1 start bit; falling CS will reset us
// note that because each bit is written independently, it is possible for us to receive
// a false rising CLK edge at the exact same time as a rising CS edge; it appears we
@ -435,7 +435,7 @@ void eeprom_serial_base_device::handle_event(eeprom_event event)
else if (event == EVENT_CS_FALLING_EDGE)
set_state(STATE_IN_RESET);
break;
// CS is asserted; wait for a command to come through; falling CS will reset us
case STATE_WAIT_FOR_COMMAND:
if (event == EVENT_CLK_RISING_EDGE)
@ -448,13 +448,13 @@ void eeprom_serial_base_device::handle_event(eeprom_event event)
else if (event == EVENT_CS_FALLING_EDGE)
set_state(STATE_IN_RESET);
break;
// CS is asserted; reading data, clock the shift register; falling CS will reset us
case STATE_READING_DATA:
if (event == EVENT_CLK_RISING_EDGE)
{
int bit_index = m_bits_accum++;
// wrapping the address on multi-read is required by pacslot(cave.c)
if (bit_index % m_data_bits == 0 && (bit_index == 0 || m_streaming_enabled))
m_shift_register = read((m_address + m_bits_accum / m_data_bits) & ((1 << m_address_bits) - 1)) << (32 - m_data_bits);
@ -474,7 +474,7 @@ void eeprom_serial_base_device::handle_event(eeprom_event event)
LOG0(("EEPROM: CS deasserted in READING_DATA after %d bits\n", m_bits_accum));
}
break;
// CS is asserted; waiting for data; clock data through until we accumulate enough; falling CS will reset us
case STATE_WAIT_FOR_DATA:
if (event == EVENT_CLK_RISING_EDGE)
@ -489,7 +489,7 @@ void eeprom_serial_base_device::handle_event(eeprom_event event)
LOG0(("EEPROM: CS deasserted in STATE_WAIT_FOR_DATA after %d bits\n", m_bits_accum));
}
break;
// CS is asserted; waiting for completion; watch for CS falling
case STATE_WAIT_FOR_COMPLETION:
if (event == EVENT_CS_FALLING_EDGE)
@ -501,7 +501,7 @@ void eeprom_serial_base_device::handle_event(eeprom_event event)
//-------------------------------------------------
// execute_command - execute a command once we
// have enough bits for one
// have enough bits for one
//-------------------------------------------------
void eeprom_serial_base_device::execute_command()
@ -509,7 +509,7 @@ void eeprom_serial_base_device::execute_command()
// parse into a generic command and reset the accumulator count
parse_command_and_address();
m_bits_accum = 0;
#if (VERBOSE_PRINTF > 0 || VERBOSE_LOGERROR > 0)
// for debugging purposes
static const struct { eeprom_command command; const char *string; } s_command_names[] =
@ -540,14 +540,14 @@ void eeprom_serial_base_device::execute_command()
m_shift_register = 0;
set_state(STATE_READING_DATA);
break;
// reset the shift register and wait for enough data to be clocked through
case COMMAND_WRITE:
case COMMAND_WRITEALL:
m_shift_register = 0;
set_state(STATE_WAIT_FOR_DATA);
break;
// erase the parsed address (unless locked) and wait for it to complete
case COMMAND_ERASE:
if (m_locked)
@ -559,19 +559,19 @@ void eeprom_serial_base_device::execute_command()
erase(m_address);
set_state(STATE_WAIT_FOR_COMPLETION);
break;
// lock the chip; return to IN_RESET state
case COMMAND_LOCK:
m_locked = true;
set_state(STATE_IN_RESET);
break;
// unlock the chip; return to IN_RESET state
case COMMAND_UNLOCK:
m_locked = false;
set_state(STATE_IN_RESET);
break;
// erase the entire chip (unless locked) and wait for it to complete
case COMMAND_ERASEALL:
if (m_locked)
@ -583,7 +583,7 @@ void eeprom_serial_base_device::execute_command()
erase_all();
set_state(STATE_WAIT_FOR_COMPLETION);
break;
default:
throw emu_fatalerror("execute_command called with invalid command %d\n", m_command);
}
@ -591,8 +591,8 @@ void eeprom_serial_base_device::execute_command()
//-------------------------------------------------
// execute_write_command - execute a write
// command after receiving the data bits
// execute_write_command - execute a write
// command after receiving the data bits
//-------------------------------------------------
void eeprom_serial_base_device::execute_write_command()
@ -627,7 +627,7 @@ void eeprom_serial_base_device::execute_write_command()
break;
// write the entire EEPROM with the same data; ERASEALL is required before so we
// AND against the already-present data
// AND against the already-present data
case COMMAND_WRITEALL:
if (m_locked)
{
@ -638,7 +638,7 @@ void eeprom_serial_base_device::execute_write_command()
write_all(m_shift_register);
set_state(STATE_WAIT_FOR_COMPLETION);
break;
default:
throw emu_fatalerror("execute_write_command called with invalid command %d\n", m_command);
}
@ -661,8 +661,8 @@ eeprom_serial_93cxx_device::eeprom_serial_93cxx_device(const machine_config &mco
//-------------------------------------------------
// parse_command_and_address - extract the
// command and address from a bitstream
// parse_command_and_address - extract the
// command and address from a bitstream
//-------------------------------------------------
void eeprom_serial_93cxx_device::parse_command_and_address()
@ -670,7 +670,7 @@ void eeprom_serial_93cxx_device::parse_command_and_address()
// set the defaults
m_command = COMMAND_INVALID;
m_address = m_command_address_accum & ((1 << m_command_address_bits) - 1);
// extract the command portion and handle it
switch (m_command_address_accum >> m_command_address_bits)
{
@ -678,16 +678,16 @@ void eeprom_serial_93cxx_device::parse_command_and_address()
case 0:
switch (m_address >> (m_command_address_bits - 2))
{
case 0: m_command = COMMAND_LOCK; break;
case 1: m_command = COMMAND_WRITEALL; break;
case 2: m_command = COMMAND_ERASEALL; break;
case 3: m_command = COMMAND_UNLOCK; break;
case 0: m_command = COMMAND_LOCK; break;
case 1: m_command = COMMAND_WRITEALL; break;
case 2: m_command = COMMAND_ERASEALL; break;
case 3: m_command = COMMAND_UNLOCK; break;
}
m_address = 0;
break;
case 1: m_command = COMMAND_WRITE; break;
case 2: m_command = COMMAND_READ; break;
case 3: m_command = COMMAND_ERASE; break;
case 1: m_command = COMMAND_WRITE; break;
case 2: m_command = COMMAND_READ; break;
case 3: m_command = COMMAND_ERASE; break;
}
// warn about out-of-range addresses
@ -728,8 +728,8 @@ eeprom_serial_er5911_device::eeprom_serial_er5911_device(const machine_config &m
//-------------------------------------------------
// parse_command_and_address - extract the
// command and address from a bitstream
// parse_command_and_address - extract the
// command and address from a bitstream
//-------------------------------------------------
void eeprom_serial_er5911_device::parse_command_and_address()
@ -737,7 +737,7 @@ void eeprom_serial_er5911_device::parse_command_and_address()
// set the defaults
m_command = COMMAND_INVALID;
m_address = m_command_address_accum & ((1 << m_command_address_bits) - 1);
// extract the command portion and handle it
switch (m_command_address_accum >> m_command_address_bits)
{
@ -745,16 +745,16 @@ void eeprom_serial_er5911_device::parse_command_and_address()
case 0:
switch (m_address >> (m_command_address_bits - 2))
{
case 0: m_command = COMMAND_LOCK; break;
case 1: m_command = COMMAND_INVALID; break; // not on ER5911
case 2: m_command = COMMAND_ERASEALL; break;
case 3: m_command = COMMAND_UNLOCK; break;
case 0: m_command = COMMAND_LOCK; break;
case 1: m_command = COMMAND_INVALID; break; // not on ER5911
case 2: m_command = COMMAND_ERASEALL; break;
case 3: m_command = COMMAND_UNLOCK; break;
}
m_address = 0;
break;
case 1: m_command = COMMAND_WRITE; break;
case 2: m_command = COMMAND_READ; break;
case 3: m_command = COMMAND_WRITE; break; // WRITE instead of ERASE on ER5911
case 1: m_command = COMMAND_WRITE; break;
case 2: m_command = COMMAND_READ; break;
case 3: m_command = COMMAND_WRITE; break; // WRITE instead of ERASE on ER5911
}
// warn about out-of-range addresses
@ -793,8 +793,7 @@ eeprom_serial_##_lowercase##_##_bits##bit_device::eeprom_serial_##_lowercase##_#
static_set_size(*this, _cells, _bits); \
static_set_address_bits(*this, _addrbits); \
}; \
const device_type EEPROM_SERIAL_##_uppercase##_##_bits##BIT = &device_creator<eeprom_serial_##_lowercase##_##_bits##bit_device>; \
const device_type EEPROM_SERIAL_##_uppercase##_##_bits##BIT = &device_creator<eeprom_serial_##_lowercase##_##_bits##bit_device>;
// standard 93CX6 class of 16-bit EEPROMs
DEFINE_SERIAL_EEPROM_DEVICE(93cxx, 93c06, 93C06, 16, 16, 6)
DEFINE_SERIAL_EEPROM_DEVICE(93cxx, 93c46, 93C46, 16, 64, 6)

64
src/emu/machine/eepromser.h
View File

@ -87,8 +87,7 @@
// optional enable for streaming reads
#define MCFG_EEPROM_SERIAL_ENABLE_STREAMING() \
eeprom_serial_base_device::static_enable_streaming(*device); \
eeprom_serial_base_device::static_enable_streaming(*device);
// pass-throughs to the base class for setting default data
#define MCFG_EEPROM_SERIAL_DATA MCFG_EEPROM_DATA
#define MCFG_EEPROM_SERIAL_DEFAULT_VALUE MCFG_EEPROM_DEFAULT_VALUE
@ -112,14 +111,14 @@ public:
// inline configuration helpers
static void static_set_address_bits(device_t &device, int addrbits);
static void static_enable_streaming(device_t &device);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// read interfaces differ between implementations
// commands
enum eeprom_command
{
@ -143,7 +142,7 @@ protected:
STATE_WAIT_FOR_DATA,
STATE_WAIT_FOR_COMPLETION
};
// events
enum eeprom_event
{
@ -158,34 +157,34 @@ protected:
void handle_event(eeprom_event event);
void execute_command();
void execute_write_command();
// subclass helpers
void base_cs_write(int state);
void base_clk_write(int state);
void base_di_write(int state);
int base_do_read();
int base_ready_read();
// subclass overrides
virtual void parse_command_and_address() = 0;
// configuration state
UINT8 m_command_address_bits; // number of address bits in a command
bool m_streaming_enabled; // true if streaming is enabled
UINT8 m_command_address_bits; // number of address bits in a command
bool m_streaming_enabled; // true if streaming is enabled
// runtime state
eeprom_state m_state; // current internal state
UINT8 m_cs_state; // state of the CS line
attotime m_last_cs_rising_edge_time; // time of the last CS rising edge
UINT8 m_oe_state; // state of the OE line
UINT8 m_clk_state; // state of the CLK line
UINT8 m_di_state; // state of the DI line
bool m_locked; // are we locked against writes?
UINT32 m_bits_accum; // number of bits accumulated
UINT32 m_command_address_accum; // accumulator of command+address bits
eeprom_command m_command; // current command
UINT32 m_address; // current address extracted from command
UINT32 m_shift_register; // holds data coming in/going out
eeprom_state m_state; // current internal state
UINT8 m_cs_state; // state of the CS line
attotime m_last_cs_rising_edge_time; // time of the last CS rising edge
UINT8 m_oe_state; // state of the OE line
UINT8 m_clk_state; // state of the CLK line
UINT8 m_di_state; // state of the DI line
bool m_locked; // are we locked against writes?
UINT32 m_bits_accum; // number of bits accumulated
UINT32 m_command_address_accum; // accumulator of command+address bits
eeprom_command m_command; // current command
UINT32 m_address; // current address extracted from command
UINT32 m_shift_register; // holds data coming in/going out
};
@ -200,12 +199,12 @@ protected:
public:
// read handlers
DECLARE_READ_LINE_MEMBER(do_read); // combined DO+READY/BUSY
DECLARE_READ_LINE_MEMBER(do_read); // combined DO+READY/BUSY
// write handlers
DECLARE_WRITE_LINE_MEMBER(cs_write); // CS signal (active high)
DECLARE_WRITE_LINE_MEMBER(clk_write); // CLK signal (active high)
DECLARE_WRITE_LINE_MEMBER(di_write); // DI
DECLARE_WRITE_LINE_MEMBER(cs_write); // CS signal (active high)
DECLARE_WRITE_LINE_MEMBER(clk_write); // CLK signal (active high)
DECLARE_WRITE_LINE_MEMBER(di_write); // DI
protected:
// subclass overrides
@ -223,13 +222,13 @@ protected:
public:
// read handlers
DECLARE_READ_LINE_MEMBER(do_read); // DO
DECLARE_READ_LINE_MEMBER(ready_read); // READY/BUSY only
DECLARE_READ_LINE_MEMBER(do_read); // DO
DECLARE_READ_LINE_MEMBER(ready_read); // READY/BUSY only
// write handlers
DECLARE_WRITE_LINE_MEMBER(cs_write); // CS signal (active high)
DECLARE_WRITE_LINE_MEMBER(clk_write); // CLK signal (active high)
DECLARE_WRITE_LINE_MEMBER(di_write); // DI
DECLARE_WRITE_LINE_MEMBER(cs_write); // CS signal (active high)
DECLARE_WRITE_LINE_MEMBER(clk_write); // CLK signal (active high)
DECLARE_WRITE_LINE_MEMBER(di_write); // DI
protected:
// subclass overrides
@ -249,8 +248,7 @@ class eeprom_serial_##_lowercase##_##_bits##bit_device : public eeprom_serial_##
public: \
eeprom_serial_##_lowercase##_##_bits##bit_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); \
}; \
extern const device_type EEPROM_SERIAL_##_uppercase##_##_bits##BIT; \
extern const device_type EEPROM_SERIAL_##_uppercase##_##_bits##BIT;
// standard 93CX6 class of 16-bit EEPROMs
DECLARE_SERIAL_EEPROM_DEVICE(93cxx, 93c06, 93C06, 16)
DECLARE_SERIAL_EEPROM_DEVICE(93cxx, 93c46, 93C46, 16)

1
src/emu/machine/generic.c
View File

@ -558,4 +558,3 @@ void generic_pulse_irq_line(device_t *device, int irqline, int cycles) { device-
// legacy
INTERRUPT_GEN( irq2_line_hold ) { device->machine().driver_data()->irq2_line_hold(*device); }

4
src/emu/machine/mb87078.h
View File

@ -44,7 +44,7 @@ public:
Range from 100 to 0. (100 = 0dB; 50 = -6dB; 0 = -infinity)
This function is designed for use with MAME mixer_xxx() functions. */
int gain_percent_r(int channel);
void gain_recalc();
protected:
@ -52,7 +52,7 @@ protected:
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
private:
// internal state
int m_gain[4]; /* gain index 0-63,64,65 */

6
src/emu/machine/s2636.c
View File

@ -143,13 +143,13 @@ void s2636_device::device_start()
save_pointer(NAME(m_work_ram), m_work_ram_size);
save_item(NAME(*m_bitmap));
save_item(NAME(*m_collision_bitmap));
m_channel = machine().sound().stream_alloc(*this, 0, 1, machine().sample_rate(), this);
save_item(NAME(m_size));
save_item(NAME(m_pos));
save_item(NAME(m_level));
for (int i = 0; i < 1; i++)
save_item(NAME(m_reg[i]), i);
}

8
src/emu/machine/s2636.h
View File

@ -47,14 +47,14 @@ public:
bitmap_ind16 &update( const rectangle &cliprect );
DECLARE_WRITE8_MEMBER( work_ram_w );
DECLARE_READ8_MEMBER( work_ram_r );
void soundport_w (int mode, int data);
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
// sound stream update overrides
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
@ -63,13 +63,13 @@ private:
UINT8 *m_work_ram;
bitmap_ind16 *m_bitmap;
bitmap_ind16 *m_collision_bitmap;
sound_stream *m_channel;
UINT8 m_reg[1];
int m_size;
int m_pos;
unsigned m_level;
int check_collision( int spriteno1, int spriteno2, const rectangle &cliprect );
};

6
src/emu/machine/smc91c9x.h
View File

@ -35,13 +35,13 @@ public:
DECLARE_READ16_MEMBER( read );
DECLARE_WRITE16_MEMBER( write );
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
private:
// internal state
smc91c9x_irq_func m_irq_handler;
@ -64,7 +64,7 @@ private:
/* counters */
UINT32 m_sent;
UINT32 m_recd;
void update_ethernet_irq();
void update_stats();
void finish_enqueue(int param);

2
src/emu/machine/wd_fdc.c
View File

@ -1466,7 +1466,7 @@ void wd_fdc_t::live_run(attotime limit)
if(cur_live.bit_counter & 15)
break;
int slot = (cur_live.bit_counter >> 4)-1;
// fprintf(stderr, "%s: slot[%d] = %02x crc = %04x\n", tts(cur_live.tm).cstr(), slot, cur_live.data_reg, cur_live.crc);
// fprintf(stderr, "%s: slot[%d] = %02x crc = %04x\n", tts(cur_live.tm).cstr(), slot, cur_live.data_reg, cur_live.crc);
cur_live.idbuf[slot] = cur_live.data_reg;
if(slot == 5) {
live_delay(IDLE);

8
src/emu/mame.c
View File

@ -147,9 +147,9 @@ int mame_execute(emu_options &options, osd_interface &osd)
// loop across multiple hard resets
bool exit_pending = false;
int error = MAMERR_NONE;
web_engine web(options);
while (error == MAMERR_NONE && !exit_pending)
{
// if no driver, use the internal empty driver
@ -187,9 +187,9 @@ int mame_execute(emu_options &options, osd_interface &osd)
// looooong term: remove this
global_machine = &machine;
web.set_machine(machine);
web.push_message("update_machine");
web.push_message("update_machine");
// run the machine
error = machine.run(firstrun);
firstrun = false;

20
src/emu/memarray.h
View File

@ -37,16 +37,16 @@
****************************************************************************
A memory array in this case is an array of 8, 16, or 32-bit data
arranged logically.
A memory array is stored in "natural" order, i.e., read/writes to it
are done via AM_RAM, or standard COMBINE_DATA, even if the width of
the CPU is different from the array width.
The read_entry/write_entry functions serve to read/write entries of
the configured size regardless of the underlay width of the CPU's
memory system.
A memory array in this case is an array of 8, 16, or 32-bit data
arranged logically.
A memory array is stored in "natural" order, i.e., read/writes to it
are done via AM_RAM, or standard COMBINE_DATA, even if the width of
the CPU is different from the array width.
The read_entry/write_entry functions serve to read/write entries of
the configured size regardless of the underlay width of the CPU's
memory system.
***************************************************************************/

2
src/emu/profiler.h
View File

@ -119,7 +119,7 @@ public:
// getters
bool enabled() const
{
{
#ifndef MAME_DEBUG_FAST
return m_filoptr != NULL;
#else

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