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bus/ISA: Added HP82321A BASIC Language coprocessor (#10926)
* emu: add defer_access() method, which is useful for keeping the cpu in a loop restarting the current instruction to emulate waitstates. * add HP82321A Basic Language Coprocessor This adds support for the HP82321A Basic language coprocessor, which emulates a HP9816 system with a 68K cpu. See http://www.hpmuseum.net/display_item.php?hw=681 for more details and software to run on this card.
This commit is contained in:
Sven Schnelle
GitHub
parent
395d41d0e9
commit
972703281d
@ -1783,6 +1783,7 @@ if (BUSES["ISA"]~=null) then
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MAME_DIR .. "src/devices/bus/isa/lrk330.h",
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MAME_DIR .. "src/devices/bus/isa/opus100pm.cpp",
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MAME_DIR .. "src/devices/bus/isa/opus100pm.h",
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MAME_DIR .. "src/devices/bus/isa/hpblp.cpp",
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}
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end
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552
src/devices/bus/isa/hpblp.cpp
Normal file
552
src/devices/bus/isa/hpblp.cpp
Normal file
@ -0,0 +1,552 @@
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// license:BSD-3-Clause
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// copyright-holders:Sven Schnelle
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/***************************************************************************
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HP Basic Language Coprocessor (82321A)
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***************************************************************************/
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#include "emu.h"
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#include "bus/isa/isa.h"
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#include "bus/ieee488/ieee488.h"
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#include "bus/hp_dio/hp_dio.h"
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#include "cpu/m68000/m68000.h"
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#include "machine/tms9914.h"
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#include "hpblp.h"
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#include "logmacro.h"
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#define BLP_TAG "blpcpu"
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#define TMS_TAG "tms9914"
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DEFINE_DEVICE_TYPE(HPBLP, isa8_hpblp_device, "hpblp", "HP Basic Language Coprocessor")
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static INPUT_PORTS_START(hpblp)
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PORT_START("BLPPORT")
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PORT_DIPNAME(3, 0, "IO Address") PORT_DIPLOCATION("SW2:0,1")
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PORT_DIPSETTING(0, "250h-257h")
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PORT_DIPSETTING(1, "280h-287h")
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PORT_DIPSETTING(2, "330h-337h")
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PORT_DIPSETTING(3, "390h-397h")
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PORT_START("BLPIRQ")
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PORT_DIPNAME(7, 3, "Interrupt") PORT_DIPLOCATION("SW3:0,1,2")
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PORT_DIPSETTING(0x0, "IRQ 3")
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PORT_DIPSETTING(0x1, "IRQ 4")
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PORT_DIPSETTING(0x2, "IRQ 5")
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PORT_DIPSETTING(0x3, "IRQ 7")
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PORT_DIPSETTING(0x4, "IRQ 9")
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INPUT_PORTS_END
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ioport_constructor isa8_hpblp_device::device_input_ports() const
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{
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return INPUT_PORTS_NAME(hpblp);
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}
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isa8_hpblp_device::isa8_hpblp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, HPBLP, tag, owner, clock),
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device_isa8_card_interface(mconfig, *this),
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m_maincpu(*this, BLP_TAG),
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m_tms9914(*this, TMS_TAG),
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m_ieee488(*this, IEEE488_TAG),
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m_timer_10ms(nullptr),
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m_reset(false)
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{
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}
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void isa8_hpblp_device::device_add_mconfig(machine_config &config)
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{
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M68000(config, m_maincpu, 16_MHz_XTAL / 2);
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m_maincpu->set_addrmap(AS_PROGRAM, &isa8_hpblp_device::m68map);
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TMS9914(config, m_tms9914, XTAL(5'000'000));
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m_tms9914->eoi_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_eoi_w));
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m_tms9914->dav_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_dav_w));
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m_tms9914->nrfd_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_nrfd_w));
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m_tms9914->ndac_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_ndac_w));
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m_tms9914->ifc_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_ifc_w));
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m_tms9914->srq_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_srq_w));
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m_tms9914->atn_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_atn_w));
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m_tms9914->ren_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_ren_w));
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m_tms9914->dio_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_dio_w));
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m_tms9914->dio_read_cb().set(IEEE488_TAG, FUNC(ieee488_device::dio_r));
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m_tms9914->dio_read_cb().set(IEEE488_TAG, FUNC(ieee488_device::dio_r));
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m_tms9914->dio_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_dio_w));
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m_tms9914->int_write_cb().set(FUNC(isa8_hpblp_device::gpib_irq));
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IEEE488(config, m_ieee488, 0);
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m_ieee488->eoi_callback().set(m_tms9914, FUNC(tms9914_device::eoi_w));
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m_ieee488->dav_callback().set(m_tms9914, FUNC(tms9914_device::dav_w));
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m_ieee488->nrfd_callback().set(m_tms9914, FUNC(tms9914_device::nrfd_w));
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m_ieee488->ndac_callback().set(m_tms9914, FUNC(tms9914_device::ndac_w));
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m_ieee488->ifc_callback().set(m_tms9914, FUNC(tms9914_device::ifc_w));
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m_ieee488->srq_callback().set(m_tms9914, FUNC(tms9914_device::srq_w));
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m_ieee488->atn_callback().set(m_tms9914, FUNC(tms9914_device::atn_w));
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m_ieee488->ren_callback().set(m_tms9914, FUNC(tms9914_device::ren_w));
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ieee488_slot_device &slot0(IEEE488_SLOT(config, "ieee0", 0));
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hp_ieee488_devices(slot0);
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slot0.set_default_option("hp9122c");
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bus::hp_dio::dio16_device &dio16(DIO16(config, "diobus", 0));
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dio16.set_program_space(m_maincpu, AS_PROGRAM);
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m_maincpu->reset_cb().set(dio16, FUNC(bus::hp_dio::dio16_device::reset_in));
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dio16.irq1_out_cb().set_inputline(m_maincpu, M68K_IRQ_1);
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dio16.irq2_out_cb().set_inputline(m_maincpu, M68K_IRQ_2);
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dio16.irq3_out_cb().set_inputline(m_maincpu, M68K_IRQ_3);
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dio16.irq4_out_cb().set_inputline(m_maincpu, M68K_IRQ_4);
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dio16.irq5_out_cb().set_inputline(m_maincpu, M68K_IRQ_5);
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dio16.irq6_out_cb().set_inputline(m_maincpu, M68K_IRQ_6);
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dio16.irq7_out_cb().set_inputline(m_maincpu, M68K_IRQ_7);
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DIO32_SLOT(config, "sl0", 0, "diobus", dio16_cards, nullptr, false);
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DIO32_SLOT(config, "sl1", 0, "diobus", dio16_cards, nullptr, false);
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}
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offs_t isa8_hpblp_device::get_bus_address(offs_t offset, uint16_t mem_mask)
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{
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if (mem_mask == 0xff)
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offset++;
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return offset;
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}
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bool isa8_hpblp_device::forward_to_host(offs_t offset)
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{
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if (offset >= 0x200000 && offset <= 0x2fffff)
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return true;
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if (offset >= 0x420000 && offset <= 0x42ffff)
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return true;
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if (offset >= 0x510000 && offset <= 0x51ffff)
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return true;
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if (offset >= 0x520000 && offset <= 0x52ffff)
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return true;
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if (offset >= 0x538000 && offset <= 0x53ffff)
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return true;
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if (offset >= 0x5f2000 && offset <= 0x5f3fff)
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return true;
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if (offset >= 0x690000 && offset <= 0x69ffff)
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return true;
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if (offset >= 0x6f0000 && offset <= 0x6fffff)
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return true;
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if (offset >= 0x730000 && offset <= 0x73ffff)
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return true;
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if (offset >= 0x7a0000 && offset <= 0x7affff)
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return true;
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return false;
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}
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uint8_t isa8_hpblp_device::status_val(offs_t offset)
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{
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if (offset >= 0x200000 && offset <= 0x2fffff)
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return 0x30;
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if (offset >= 0x512000 && offset <= 0x517fff)
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return 0x70;
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if (offset >= 0x51ff00 && offset <= 0x51ffff)
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return 0x50;
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if (offset >= 0x538000 && offset <= 0x53ffff)
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return 0xb0;
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return 0xd0;
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}
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uint16_t isa8_hpblp_device::bus_r(offs_t offset, uint16_t mem_mask)
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{
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offset <<= 1;
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if (machine().side_effects_disabled())
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return m_bus_data;
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if (!forward_to_host(offset)) {
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LOG("%s: %06x -> BERR\n", __func__, offset);
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m_maincpu->trigger_bus_error();
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return 0xffff;
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}
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if (m_ack_buscycle) {
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m_ack_buscycle = false;
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m_bus_read = false;
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m_bus_address = 0;
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LOG("%s: %06x %04x (%04x)\n", __func__, offset, m_bus_data, mem_mask);
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return m_bus_data;
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} else {
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m_bus_address = get_bus_address(offset, mem_mask);
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m_bus_mem_mask = mem_mask;
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m_bus_read = true;
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}
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m_maincpu->defer_access();
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return 0xffff;
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}
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void isa8_hpblp_device::bus_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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offset <<= 1;
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if (!forward_to_host(offset)) {
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LOG("%s: %06x -> BERR\n", __func__, offset);
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m_maincpu->trigger_bus_error();
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return;
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}
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if (m_ack_buscycle) {
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m_ack_buscycle = false;
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m_bus_write = false;
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m_bus_address = 0;
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return;
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}
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if (!m_bus_write) {
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m_bus_address = get_bus_address(offset, mem_mask);
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m_bus_mem_mask = mem_mask;
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m_bus_write = true;
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m_bus_data = data;
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}
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m_maincpu->defer_access();
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}
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void isa8_hpblp_device::gpib_w(offs_t offset, uint16_t data)
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{
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if (offset & 0x08) {
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m_tms9914->write(offset & 0x07, data);
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return;
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}
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switch (offset) {
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case 0:
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m_tms9914->reset();
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break;
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case 1:
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if (data >> 8 == 0)
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m_gpib_reg1 = 0x84;
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else if (data >> 8 == 1)
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m_gpib_reg1 = 0xbf;
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else
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m_gpib_reg1 = 0xbe;
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break;
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default:
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break;
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}
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}
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uint16_t isa8_hpblp_device::gpib_r(offs_t offset)
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{
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uint8_t data = 0xff;
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if (offset & 0x8)
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return m_tms9914->read(offset & 0x07);
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switch(offset) {
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case 0: /* ID */
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data = 0x31;
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break;
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case 1:
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/* Int control */
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data = m_gpib_reg1;
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break;
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case 2:
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/* Address */
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data = 0xbe;
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break;
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default:
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break;
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}
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return data;
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}
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void isa8_hpblp_device::update_gpib_irq()
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{
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if ((m_gpib_reg1 & 0x40) && (m_gpib_reg1 & 0x80))
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m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
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else
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m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
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}
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WRITE_LINE_MEMBER(isa8_hpblp_device::gpib_irq)
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{
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if (state) {
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m_gpib_reg1 |= 0x40;
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} else {
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m_gpib_reg1 &= ~0x40;
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}
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update_gpib_irq();
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}
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void isa8_hpblp_device::m68map(address_map &map)
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{
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map(0x000000, 0xffffff).rw(FUNC(isa8_hpblp_device::bus_r), FUNC(isa8_hpblp_device::bus_w));
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map(0x000000, 0x00ffff).rom().nopw();
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map(0x470000, 0x47001f).mirror(0x00ffe0).rw(FUNC(isa8_hpblp_device::gpib_r), FUNC(isa8_hpblp_device::gpib_w));
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map(0xc00000, 0xffffff).ram();
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}
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WRITE_LINE_MEMBER(isa8_hpblp_device::hpblp_interrupt)
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{
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switch(m_irq) {
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case 0:
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m_isa->irq3_w(state);
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break;
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case 1:
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m_isa->irq4_w(state);
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break;
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case 2:
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m_isa->irq5_w(state);
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break;
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case 3:
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m_isa->irq7_w(state);
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break;
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case 4:
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m_isa->irq2_w(state);
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break;
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default:
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break;
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}
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}
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uint8_t isa8_hpblp_device::get_bus_address_partial(int shift)
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{
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offs_t addr;
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// The value read from the bus address registers (isa reg 2,3,4) is
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// either the address during a waiting 68k bus cycle, or, if the
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// processor is running the current bus address which might be a data
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// read/write or program fetch. The DOS software checks whether these
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// register changes during normal operation. Therefore just invert
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// the address on every read if the CPU is not waiting for the host.
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if (!m_bus_read && !m_bus_write)
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m_bus_address ^= 0xffffff;
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addr = m_bus_address;
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return (addr >> shift) & 0xff;
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}
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uint8_t isa8_hpblp_device::addrl_r(offs_t offset)
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{
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return get_bus_address_partial(0);
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}
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uint8_t isa8_hpblp_device::addrm_r(offs_t offset)
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{
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return get_bus_address_partial(8);
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}
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uint8_t isa8_hpblp_device::addrh_r(offs_t offset)
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{
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return get_bus_address_partial(16);
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}
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uint8_t isa8_hpblp_device::datal_r(offs_t offset)
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{
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return m_bus_data & 0xff;
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}
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uint8_t isa8_hpblp_device::datah_r(offs_t offset)
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{
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return m_bus_data >> 8;
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}
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void isa8_hpblp_device::datal_w(offs_t offset, uint8_t data)
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{
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m_bus_data &= ~0xff;
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m_bus_data |= data;
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}
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void isa8_hpblp_device::datah_w(offs_t offset, uint8_t data)
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{
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m_bus_data &= ~0xff00;
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m_bus_data |= (data << 8);
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}
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uint8_t isa8_hpblp_device::status_r(offs_t offset)
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{
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uint8_t ret;
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// bits:
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// 7-5: type of buscycle (exact encoding unknown)
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// 4 - INT status
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// 2 - CPU RW#
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if (m_bus_read || m_bus_write)
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ret = status_val(m_bus_address);
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else
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ret = 0xe4;
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if (m_bus_read)
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ret |= 0x04;
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if (!m_irq_state)
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ret |= 0x10;
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return ret;
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}
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void isa8_hpblp_device::irq_w(offs_t offset, uint8_t data)
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{
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hpblp_interrupt(1);
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}
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uint8_t isa8_hpblp_device::reg5_r(offs_t offset)
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{
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// state bits:
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// 3-0: OS running
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// 0: BOOTROM
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// 1: HPBASIC
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// 2: PASCAL
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// 4: Is a 82324A card
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return m_reg5;
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}
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uint8_t isa8_hpblp_device::reg6_r(offs_t offset)
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{
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return m_reg6;
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}
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void isa8_hpblp_device::reg2_w(offs_t offset, uint8_t data)
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{
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// bit 0 - CPU RESET# line
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m_reset = data & 1;
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if (m_reset)
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device_reset();
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}
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// reg 3: force BERR# on current bus cycle
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void isa8_hpblp_device::reg3_w(offs_t offset, uint8_t data)
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{
|
||||
m_ack_buscycle = false;
|
||||
m_bus_read = false;
|
||||
m_bus_write = false;
|
||||
m_maincpu->trigger_bus_error();
|
||||
machine().scheduler().synchronize();
|
||||
}
|
||||
|
||||
// reg 4: clear pending 10ms timer interrupt to host
|
||||
void isa8_hpblp_device::reg4_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
hpblp_interrupt(0);
|
||||
}
|
||||
|
||||
// reg 5: OS status
|
||||
void isa8_hpblp_device::reg5_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_reg5 = data;
|
||||
}
|
||||
|
||||
// reg 6: seems to be used to trigger interrupts on the 68k.
|
||||
// Only seen with keyboard irqs so far.
|
||||
void isa8_hpblp_device::reg6_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
// bit 2-0: IPL?
|
||||
if (data == 6) {
|
||||
m_maincpu->set_input_line(M68K_IRQ_1, ASSERT_LINE);
|
||||
} else {
|
||||
m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
|
||||
}
|
||||
m_reg6 = data;
|
||||
}
|
||||
|
||||
// reg 7: acknowledge current 68k bus cycle
|
||||
void isa8_hpblp_device::reg7_w(address_space &space, offs_t offset, uint8_t data)
|
||||
{
|
||||
if (m_reset) {
|
||||
// DOS software write to this reg during reset, so we need to ignore
|
||||
// this write in order to not acknowledge the first bus cycle early
|
||||
return;
|
||||
}
|
||||
|
||||
m_bus_read = false;
|
||||
m_bus_write = false;
|
||||
m_ack_buscycle = true;
|
||||
// It looks like the DOS software assumes that the m68k is always faster starting
|
||||
// the next buscycle than the PC reading the data registers. So it seems they
|
||||
// "optimized" the code to skip checking the bus status registers before accessing
|
||||
// the data registers during a 32 bit instruction. (which will be split into 2x 16
|
||||
// bit bus transactions by 68k. Eat all cycles to make the scheduler switch to 68k
|
||||
// before the x86 CPU can read the registers again.
|
||||
machine().scheduler().synchronize();
|
||||
}
|
||||
|
||||
void isa8_hpblp_device::isamap(address_map &map)
|
||||
{
|
||||
map(0, 0).rw(FUNC(isa8_hpblp_device::datal_r), FUNC(isa8_hpblp_device::datal_w));
|
||||
map(1, 1).rw(FUNC(isa8_hpblp_device::datah_r), FUNC(isa8_hpblp_device::datah_w));
|
||||
map(2, 2).rw(FUNC(isa8_hpblp_device::addrl_r), FUNC(isa8_hpblp_device::reg2_w));
|
||||
map(3, 3).rw(FUNC(isa8_hpblp_device::addrm_r), FUNC(isa8_hpblp_device::reg3_w));
|
||||
map(4, 4).rw(FUNC(isa8_hpblp_device::addrh_r), FUNC(isa8_hpblp_device::reg4_w));
|
||||
map(5, 5).rw(FUNC(isa8_hpblp_device::reg5_r), FUNC(isa8_hpblp_device::reg5_w));
|
||||
map(6, 6).rw(FUNC(isa8_hpblp_device::reg6_r), FUNC(isa8_hpblp_device::reg6_w));
|
||||
map(7, 7).rw(FUNC(isa8_hpblp_device::status_r), FUNC(isa8_hpblp_device::reg7_w));
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(isa8_hpblp_device::timer10ms)
|
||||
{
|
||||
if (m_reg6 & 2)
|
||||
hpblp_interrupt(1);
|
||||
m_timer_10ms->adjust(attotime::from_msec(10));
|
||||
}
|
||||
|
||||
void isa8_hpblp_device::device_start()
|
||||
{
|
||||
set_isa_device();
|
||||
m_installed = false;
|
||||
m_timer_10ms = timer_alloc(FUNC(isa8_hpblp_device::timer10ms), this);
|
||||
m_timer_10ms->adjust(attotime::from_msec(10));
|
||||
|
||||
save_item(NAME(m_bus_address));
|
||||
save_item(NAME(m_bus_mem_mask));
|
||||
save_item(NAME(m_bus_data));
|
||||
save_item(NAME(m_gpib_reg1));
|
||||
save_item(NAME(m_reg5));
|
||||
save_item(NAME(m_reg6));
|
||||
save_item(NAME(m_ack_buscycle));
|
||||
save_item(NAME(m_bus_read));
|
||||
save_item(NAME(m_bus_write));
|
||||
save_item(NAME(m_irq_state));
|
||||
save_item(NAME(m_reset));
|
||||
}
|
||||
|
||||
void isa8_hpblp_device::device_reset()
|
||||
{
|
||||
uint16_t port;
|
||||
|
||||
if (!m_installed) {
|
||||
// MAME doesn't allow reading ioport at device_start
|
||||
m_irq = ioport("BLPIRQ")->read();
|
||||
switch(ioport("BLPPORT")->read()) {
|
||||
case 1:
|
||||
port = 0x280;
|
||||
break;
|
||||
case 2:
|
||||
port = 0x330;
|
||||
break;
|
||||
case 3:
|
||||
port = 0x390;
|
||||
break;
|
||||
default:
|
||||
port = 0x250;
|
||||
break;
|
||||
}
|
||||
m_isa->install_device(port, port + 7, *this, &isa8_hpblp_device::isamap);
|
||||
m_installed = true;
|
||||
}
|
||||
|
||||
m_ack_buscycle = false;
|
||||
m_bus_read = false;
|
||||
m_bus_write = false;
|
||||
m_bus_address = 0;
|
||||
m_reg5 = 0;
|
||||
m_reg6 = 0;
|
||||
m_maincpu->reset();
|
||||
m_gpib_reg1 = 0xbe;
|
||||
m_tms9914->reset();
|
||||
}
|
||||
|
||||
ROM_START(hpblp)
|
||||
ROM_REGION(0x20000, BLP_TAG, 0)
|
||||
ROM_LOAD16_BYTE( "1818-4576.bin", 0x000000, 0x008000, CRC(8beb6bdb) SHA1(9b620c577aea54841608d0d46f7e8077eef607c6))
|
||||
ROM_LOAD16_BYTE( "1818-4577.bin", 0x000001, 0x008000, CRC(e8a5c071) SHA1(9e13c0ef2aed6565c33795780b7102f2647cf2a0))
|
||||
ROM_END
|
||||
|
||||
const tiny_rom_entry *isa8_hpblp_device::device_rom_region() const
|
||||
{
|
||||
return ROM_NAME(hpblp);
|
||||
}
|
||||
95
src/devices/bus/isa/hpblp.h
Normal file
95
src/devices/bus/isa/hpblp.h
Normal file
@ -0,0 +1,95 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Sven Schnelle
|
||||
#ifndef MAME_BUS_ISA_HPBLP_H
|
||||
#define MAME_BUS_ISA_HPBLP_H
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "isa.h"
|
||||
#include "bus/hp_dio/hp_dio.h"
|
||||
#include "bus/ieee488/ieee488.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
#include "machine/tms9914.h"
|
||||
|
||||
class isa8_hpblp_device :
|
||||
public device_t,
|
||||
public device_isa8_card_interface
|
||||
{
|
||||
public:
|
||||
isa8_hpblp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
private:
|
||||
// ISA part
|
||||
void isamap(address_map &map);
|
||||
|
||||
uint8_t datal_r(offs_t offset);
|
||||
uint8_t datah_r(offs_t offset);
|
||||
uint8_t status_r(offs_t offset);
|
||||
uint8_t addrh_r(offs_t offset);
|
||||
uint8_t addrm_r(offs_t offset);
|
||||
uint8_t addrl_r(offs_t offset);
|
||||
uint8_t reg5_r(offs_t offset);
|
||||
uint8_t reg6_r(offs_t offset);
|
||||
|
||||
void datal_w(offs_t offset, uint8_t data);
|
||||
void datah_w(offs_t offset, uint8_t data);
|
||||
void irq_w(offs_t offset, uint8_t data);
|
||||
void reg2_w(offs_t offset, uint8_t data);
|
||||
void reg3_w(offs_t offset, uint8_t data);
|
||||
void reg4_w(offs_t offset, uint8_t data);
|
||||
void reg5_w(offs_t offset, uint8_t data);
|
||||
void reg6_w(offs_t offset, uint8_t data);
|
||||
void reg7_w(address_space &space, offs_t offset, uint8_t data);
|
||||
|
||||
static uint8_t status_val(offs_t offset);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(hpblp_interrupt);
|
||||
TIMER_CALLBACK_MEMBER(timer10ms);
|
||||
|
||||
// M68000 part
|
||||
DECLARE_WRITE_LINE_MEMBER(gpib_irq);
|
||||
void m68map(address_map &map);
|
||||
|
||||
uint16_t bus_r(offs_t offset, uint16_t mem_mask);
|
||||
void bus_w(offs_t offset, uint16_t data, uint16_t mem_mask);
|
||||
uint16_t gpib_r(offs_t offset);
|
||||
void gpib_w(offs_t offset, uint16_t data);
|
||||
|
||||
static offs_t get_bus_address(offs_t offset, uint16_t mem_mask);
|
||||
uint8_t get_bus_address_partial(int shift);
|
||||
|
||||
static bool forward_to_host(offs_t offset);
|
||||
void update_gpib_irq();
|
||||
|
||||
required_device<m68000_device> m_maincpu;
|
||||
required_device<tms9914_device> m_tms9914;
|
||||
required_device<ieee488_device> m_ieee488;
|
||||
emu_timer *m_timer_10ms;
|
||||
|
||||
uint32_t m_bus_address;
|
||||
uint16_t m_bus_mem_mask;
|
||||
uint16_t m_bus_data;
|
||||
uint8_t m_gpib_reg1;
|
||||
uint8_t m_reg5;
|
||||
uint8_t m_reg6;
|
||||
uint8_t m_irq;
|
||||
|
||||
bool m_installed;
|
||||
bool m_ack_buscycle;
|
||||
bool m_bus_read;
|
||||
bool m_bus_write;
|
||||
bool m_irq_state;
|
||||
bool m_reset;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(HPBLP, isa8_hpblp_device)
|
||||
|
||||
#endif // MAME_BUS_ISA_HPBLP_H
|
||||
@ -81,6 +81,7 @@
|
||||
#include "pds.h"
|
||||
|
||||
// other
|
||||
#include "hpblp.h"
|
||||
#include "chessmdr.h"
|
||||
#include "chessmsr.h"
|
||||
#include "finalchs.h"
|
||||
@ -235,4 +236,5 @@ void pc_isa16_cards(device_slot_interface &device)
|
||||
device.option_add("dc820b", TEKRAM_DC820B); // actually an EISA card
|
||||
device.option_add("omti8621", ISA16_OMTI8621);
|
||||
device.option_add("lrk331", LRK331);
|
||||
device.option_add("hpblp", HPBLP);
|
||||
}
|
||||
|
||||
@ -59,6 +59,11 @@ bool cpu_device::cpu_is_interruptible() const
|
||||
return false;
|
||||
}
|
||||
|
||||
void cpu_device::defer_access(void)
|
||||
{
|
||||
m_access_to_be_redone = true;
|
||||
*m_icountptr = 0;
|
||||
}
|
||||
|
||||
bool cpu_device::access_before_time(u64 access_time, u64 current_time)
|
||||
{
|
||||
|
||||
@ -48,6 +48,7 @@ public:
|
||||
|
||||
// The access has already happened, nothing to abort
|
||||
void access_after_delay(u32 cycles);
|
||||
void defer_access(void);
|
||||
|
||||
protected:
|
||||
// construction/destruction
|
||||
|
||||
Loading…
Reference in New Issue
Block a user