Merge pull request #4831 from cam900/watchdog_args

devices/machine/watchdog.cpp : Simplify handlers
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R. Belmont 2019-03-31 10:34:37 -04:00 committed by GitHub
commit 97a61c2e39
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22 changed files with 40 additions and 40 deletions

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@ -180,21 +180,21 @@ void watchdog_timer_device::watchdog_vblank(screen_device &screen, bool vblank_s
// 8-bit reset read/write handlers
//-------------------------------------------------
WRITE8_MEMBER( watchdog_timer_device::reset_w ) { watchdog_reset(); }
READ8_MEMBER( watchdog_timer_device::reset_r ) { watchdog_reset(); return space.unmap(); }
void watchdog_timer_device::reset_w(u8 data) { watchdog_reset(); }
u8 watchdog_timer_device::reset_r(address_space &space) { watchdog_reset(); return space.unmap(); }
//-------------------------------------------------
// 16-bit reset read/write handlers
//-------------------------------------------------
WRITE16_MEMBER( watchdog_timer_device::reset16_w ) { watchdog_reset(); }
READ16_MEMBER( watchdog_timer_device::reset16_r ) { watchdog_reset(); return space.unmap(); }
void watchdog_timer_device::reset16_w(u16 data) { watchdog_reset(); }
u16 watchdog_timer_device::reset16_r(address_space &space) { watchdog_reset(); return space.unmap(); }
//-------------------------------------------------
// 32-bit reset read/write handlers
//-------------------------------------------------
WRITE32_MEMBER( watchdog_timer_device::reset32_w ) { watchdog_reset(); }
READ32_MEMBER( watchdog_timer_device::reset32_r ) { watchdog_reset(); return space.unmap(); }
void watchdog_timer_device::reset32_w(u32 data) { watchdog_reset(); }
u32 watchdog_timer_device::reset32_r(address_space &space) { watchdog_reset(); return space.unmap(); }

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@ -30,12 +30,12 @@ public:
int32_t get_vblank_counter() const { return m_counter; }
// read/write handlers
DECLARE_WRITE8_MEMBER( reset_w );
DECLARE_READ8_MEMBER( reset_r );
DECLARE_WRITE16_MEMBER( reset16_w );
DECLARE_READ16_MEMBER( reset16_r );
DECLARE_WRITE32_MEMBER( reset32_w );
DECLARE_READ32_MEMBER( reset32_r );
void reset_w(u8 data = 0);
u8 reset_r(address_space &space);
void reset16_w(u16 data = 0);
u16 reset16_r(address_space &space);
void reset32_w(u32 data = 0);
u32 reset32_r(address_space &space);
protected:
// device-level overrides

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@ -238,7 +238,7 @@ READ8_MEMBER(airbustr_state::devram_r)
that would reset the main cpu. We avoid this and patch
the rom instead (main cpu has to be reset once at startup) */
case 0xfe0:
return m_watchdog->reset_r(space, 0);
return m_watchdog->reset_r(space);
/* Reading a word at eff2 probably yelds the product
of the words written to eff0 and eff2 */

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@ -184,7 +184,7 @@ WRITE8_MEMBER(capbowl_state::track_reset_w)
m_last_trackball_val[0] = ioport("TRACKY")->read();
m_last_trackball_val[1] = ioport("TRACKX")->read();
m_watchdog->reset_w(space, offset, data);
m_watchdog->watchdog_reset();
}

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@ -240,7 +240,7 @@ WRITE8_MEMBER(destroyr_state::misc_w)
WRITE8_MEMBER(destroyr_state::cursor_load_w)
{
m_cursor = data;
m_watchdog->reset_w(space, offset, data);
m_watchdog->watchdog_reset();
}

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@ -624,7 +624,7 @@ READ8_MEMBER(dkong_state::dkong_in2_r)
{
// 2 board DK and all DKjr has a watchdog
if (m_watchdog)
m_watchdog->reset_w(space, 0, 0);
m_watchdog->watchdog_reset();
uint8_t r = ioport("IN2")->read();
machine().bookkeeping().coin_counter_w(offset, r >> 7);

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@ -75,7 +75,7 @@ WRITE8_MEMBER(flkatck_state::flkatck_ls138_w)
m_audiocpu->set_input_line(0, HOLD_LINE);
break;
case 0x07: /* watchdog reset */
m_watchdog->reset_w(space, 0, data);
m_watchdog->watchdog_reset();
break;
}
}

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@ -85,7 +85,7 @@ Stephh's notes (based on the games Z80 code and some tests) :
READ8_MEMBER(funkybee_state::funkybee_input_port_0_r)
{
m_watchdog->reset_r(space, 0);
m_watchdog->watchdog_reset();
return ioport("IN0")->read();
}

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@ -7580,7 +7580,7 @@ void galaxian_state::init_mandinga()
address_space &space = m_maincpu->space(AS_PROGRAM);
watchdog_timer_device *wdog = subdevice<watchdog_timer_device>("watchdog");
space.unmap_read(0x7000, 0x7000, 0x7ff);
space.install_read_handler(0x6800, 0x6800, 0, 0x7ff, 0, read8_delegate(FUNC(watchdog_timer_device::reset_r), wdog));
space.install_read_handler(0x6800, 0x6800, 0, 0x7ff, 0, read8mo_delegate(FUNC(watchdog_timer_device::reset_r), wdog));
}
void galaxian_state::init_sfx()
@ -7605,7 +7605,7 @@ void galaxian_state::init_atlantis()
/* watchdog is at $7800? (or is it just disabled?) */
watchdog_timer_device *wdog = subdevice<watchdog_timer_device>("watchdog");
space.unmap_read(0x7000, 0x77ff);
space.install_read_handler(0x7800, 0x7800, 0, 0x7ff, 0, read8_delegate(FUNC(watchdog_timer_device::reset_r), wdog));
space.install_read_handler(0x7800, 0x7800, 0, 0x7ff, 0, read8mo_delegate(FUNC(watchdog_timer_device::reset_r), wdog));
}

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@ -165,7 +165,7 @@ WRITE16_MEMBER(mcatadv_state::mcat_coin_w)
READ16_MEMBER(mcatadv_state::mcat_wd_r)
{
m_watchdog->reset_r(space, 0);
m_watchdog->watchdog_reset();
return 0xc00;
}

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@ -179,7 +179,7 @@ WRITE32_MEMBER(midvunit_state::midvunit_control_w)
/* bit 3 is the watchdog */
if ((olddata ^ m_control_data) & 0x0008)
m_watchdog->reset_w(space, 0, 0);
m_watchdog->watchdog_reset();
/* bit 1 is the DCS sound reset */
m_dcs->reset_w((~m_control_data >> 1) & 1);
@ -200,7 +200,7 @@ WRITE32_MEMBER(midvunit_state::crusnwld_control_w)
/* bit 9 is the watchdog */
if ((olddata ^ m_control_data) & 0x0200)
m_watchdog->reset_w(space, 0, 0);
m_watchdog->watchdog_reset();
/* bit 8 is the LED */
@ -544,7 +544,7 @@ WRITE32_MEMBER(midvunit_state::midvplus_misc_w)
/* bit 0x10 resets watchdog */
if ((olddata ^ m_midvplus_misc[offset]) & 0x0010)
{
m_watchdog->reset_w(space, 0, 0);
m_watchdog->watchdog_reset();
logit = false;
}
break;

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@ -916,7 +916,7 @@ WRITE8_MEMBER(mw8080bw_state::maze_io_w)
{
if (offset & 0x01) maze_coin_counter_w(space, 0, data);
if (offset & 0x02) m_watchdog->reset_w(space, 0, data);
if (offset & 0x02) m_watchdog->watchdog_reset();
}
@ -1082,7 +1082,7 @@ WRITE8_MEMBER(mw8080bw_state::checkmat_io_w)
{
if (offset & 0x01) checkmat_audio_w(space, 0, data);
if (offset & 0x02) m_watchdog->reset_w(space, 0, data);
if (offset & 0x02) m_watchdog->watchdog_reset();
}
@ -2170,7 +2170,7 @@ WRITE8_MEMBER(mw8080bw_state::spcenctr_io_w)
{ /* A7 A6 A5 A4 A3 A2 A1 A0 */
if ((offset & 0x07) == 0x02)
m_watchdog->reset_w(space, 0, data); /* - - - - - 0 1 0 */
m_watchdog->watchdog_reset(); /* - - - - - 0 1 0 */
else if ((offset & 0x5f) == 0x01)
spcenctr_audio_1_w(space, 0, data); /* - 0 - 0 0 0 0 1 */

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@ -258,7 +258,7 @@ WRITE8_MEMBER(namcos86_state::watchdog1_w)
if (m_wdog == 3)
{
m_wdog = 0;
m_watchdog->reset_w(space,0,0);
m_watchdog->watchdog_reset();
}
}
@ -268,7 +268,7 @@ WRITE8_MEMBER(namcos86_state::watchdog2_w)
if (m_wdog == 3)
{
m_wdog = 0;
m_watchdog->reset_w(space,0,0);
m_watchdog->watchdog_reset();
}
}

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@ -68,7 +68,7 @@ WRITE8_MEMBER(poolshrk_state::watchdog_w)
{
if ((offset & 3) == 3)
{
m_watchdog->reset_w(space, 0, 0);
m_watchdog->watchdog_reset();
}
}
@ -86,7 +86,7 @@ READ8_MEMBER(poolshrk_state::input_r)
if ((offset & 3) == 3)
{
m_watchdog->reset_r(space, 0);
m_watchdog->watchdog_reset();
}
return val;

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@ -655,7 +655,7 @@ READ16_MEMBER( segaorun_state::outrun_custom_io_r )
}
case 0x60/2:
return m_watchdog->reset_r(space, 0);
return m_watchdog->reset_r(space);
default:
break;

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@ -526,7 +526,7 @@ READ8_MEMBER( segas16a_state::mcu_io_r )
case 0:
// access watchdog? (unsure about this one)
if ( offset < 0x3fff)
return m_watchdog->reset_r(space, 0);
return m_watchdog->reset_r(space);
// access main work RAM
else if (offset >= 0x4000 && offset < 0x8000)

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@ -218,7 +218,7 @@ WRITE8_MEMBER(supdrapo_state::wdog8000_w)
if (m_wdog == data)
{
m_watchdog->reset_w(space, 0, 0); /* Reset */
m_watchdog->watchdog_reset(); /* Reset */
}
m_wdog = data;

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@ -275,7 +275,7 @@ WRITE8_MEMBER(warpwarp_state::warpwarp_out0_w)
m_warpwarp_sound->sound_w(data);
break;
case 3:
m_watchdog->reset_w(space,0,data);
m_watchdog->watchdog_reset();
break;
}
}

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@ -175,7 +175,7 @@ READ16_MEMBER(xtheball_state::analogx_r)
READ16_MEMBER(xtheball_state::analogy_watchdog_r)
{
/* doubles as a watchdog address */
m_watchdog->reset_w(space,0,0);
m_watchdog->watchdog_reset();
return (m_analog_y->read() << 8) | 0x00ff;
}

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@ -140,7 +140,7 @@ WRITE8_MEMBER(ajax_state::ls138_f10_w)
{
case 0x00: /* NSFIRQ + AFR */
if (offset)
m_watchdog->reset_w(space, 0, data);
m_watchdog->watchdog_reset();
else{
if (m_firq_enable) /* Cause interrupt on slave CPU */
m_subcpu->set_input_line(M6809_FIRQ_LINE, HOLD_LINE);

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@ -253,7 +253,7 @@ WRITE8_MEMBER(williams_state::williams_watchdog_reset_w)
{
/* yes, the data bits are checked for this specific value */
if (data == 0x39)
m_watchdog->reset_w(space,0,0);
m_watchdog->watchdog_reset();
}
@ -261,7 +261,7 @@ WRITE8_MEMBER(williams2_state::williams2_watchdog_reset_w)
{
/* yes, the data bits are checked for this specific value */
if ((data & 0x3f) == 0x14)
m_watchdog->reset_w(space,0,0);
m_watchdog->watchdog_reset();
}

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@ -144,7 +144,7 @@ WRITE_LINE_MEMBER(skydiver_state::lamp_r_w)
WRITE8_MEMBER(skydiver_state::latch3_watchdog_w)
{
m_watchdog->reset_w(space, 0, 0);
m_watchdog->watchdog_reset();
m_latch3->write_a0(space, offset, 0);
}