From 9824c667e40959c9ee8b721623b08931dd253e2e Mon Sep 17 00:00:00 2001 From: Aaron Giles Date: Wed, 10 Dec 2008 16:40:57 +0000 Subject: [PATCH] Pointer-ified the sh4 core. --- src/emu/cpu/sh4/sh4.c | 3130 ++++++++++++++++++------------------- src/emu/cpu/sh4/sh4.h | 2 +- src/emu/cpu/sh4/sh4comn.c | 942 +++++------ src/emu/cpu/sh4/sh4comn.h | 60 +- 4 files changed, 2064 insertions(+), 2070 deletions(-) diff --git a/src/emu/cpu/sh4/sh4.c b/src/emu/cpu/sh4/sh4.c index 156c9ac19b1..5ea24e8ab3c 100644 --- a/src/emu/cpu/sh4/sh4.c +++ b/src/emu/cpu/sh4/sh4.c @@ -29,34 +29,34 @@ #include "deprecat.h" /* Called for unimplemented opcodes */ -static void TODO(void) +static void TODO(SH4 *sh4) { } #if 0 int sign_of(int n) { - return(sh4.fr[n]>>31); + return(sh4->fr[n]>>31); } void zero(int n,int sign) { if (sign == 0) - sh4.fr[n] = 0x00000000; + sh4->fr[n] = 0x00000000; else - sh4.fr[n] = 0x80000000; -if ((sh4.fpscr & PR) == 1) - sh4.fr[n+1] = 0x00000000; + sh4->fr[n] = 0x80000000; +if ((sh4->fpscr & PR) == 1) + sh4->fr[n+1] = 0x00000000; } int data_type_of(int n) { UINT32 abs; - abs = sh4.fr[n] & 0x7fffffff; - if ((sh4.fpscr & PR) == 0) { /* Single-precision */ + abs = sh4->fr[n] & 0x7fffffff; + if ((sh4->fpscr & PR) == 0) { /* Single-precision */ if (abs < 0x00800000) { - if (((sh4.fpscr & DN) == 1) || (abs == 0x00000000)) { + if (((sh4->fpscr & DN) == 1) || (abs == 0x00000000)) { if (sign_of(n) == 0) { zero(n, 0); return(SH4_FPU_PZERO); @@ -82,7 +82,7 @@ UINT32 abs; return(SH4_FPU_sNaN); } else { /* Double-precision */ if (abs < 0x00100000) { - if (((sh4.fpscr & DN) == 1) || ((abs == 0x00000000) && (sh4.fr[n+1] == 0x00000000))) { + if (((sh4->fpscr & DN) == 1) || ((abs == 0x00000000) && (sh4->fr[n+1] == 0x00000000))) { if(sign_of(n) == 0) { zero(n, 0); return(SH4_FPU_PZERO); @@ -96,7 +96,7 @@ UINT32 abs; if (abs < 0x7ff00000) return(SH4_FPU_NORM); else - if ((abs == 0x7ff00000) && (sh4.fr[n+1] == 0x00000000)) { + if ((abs == 0x7ff00000) && (sh4->fr[n+1] == 0x00000000)) { if (sign_of(n) == 0) return(SH4_FPU_PINF); else @@ -111,150 +111,150 @@ UINT32 abs; } #endif -INLINE UINT8 RB(offs_t A) +INLINE UINT8 RB(SH4 *sh4, offs_t A) { if (A >= 0xfe000000) - return sh4_internal_r(sh4.internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xff << ((A & 3)*8)) >> ((A & 3)*8); + return sh4_internal_r(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xff << ((A & 3)*8)) >> ((A & 3)*8); if (A >= 0xe0000000) - return memory_read_byte_64le(sh4.program, A); + return memory_read_byte_64le(sh4->program, A); - return memory_read_byte_64le(sh4.program, A & AM); + return memory_read_byte_64le(sh4->program, A & AM); } -INLINE UINT16 RW(offs_t A) +INLINE UINT16 RW(SH4 *sh4, offs_t A) { if (A >= 0xfe000000) - return sh4_internal_r(sh4.internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xffff << ((A & 2)*8)) >> ((A & 2)*8); + return sh4_internal_r(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xffff << ((A & 2)*8)) >> ((A & 2)*8); if (A >= 0xe0000000) - return memory_read_word_64le(sh4.program, A); + return memory_read_word_64le(sh4->program, A); - return memory_read_word_64le(sh4.program, A & AM); + return memory_read_word_64le(sh4->program, A & AM); } -INLINE UINT32 RL(offs_t A) +INLINE UINT32 RL(SH4 *sh4, offs_t A) { if (A >= 0xfe000000) - return sh4_internal_r(sh4.internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xffffffff); + return sh4_internal_r(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), 0xffffffff); if (A >= 0xe0000000) - return memory_read_dword_64le(sh4.program, A); + return memory_read_dword_64le(sh4->program, A); - return memory_read_dword_64le(sh4.program, A & AM); + return memory_read_dword_64le(sh4->program, A & AM); } -INLINE void WB(offs_t A, UINT8 V) +INLINE void WB(SH4 *sh4, offs_t A, UINT8 V) { if (A >= 0xfe000000) { - sh4_internal_w(sh4.internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V << ((A & 3)*8), 0xff << ((A & 3)*8)); + sh4_internal_w(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V << ((A & 3)*8), 0xff << ((A & 3)*8)); return; } if (A >= 0xe0000000) { - memory_write_byte_64le(sh4.program, A,V); + memory_write_byte_64le(sh4->program, A,V); return; } - memory_write_byte_64le(sh4.program, A & AM,V); + memory_write_byte_64le(sh4->program, A & AM,V); } -INLINE void WW(offs_t A, UINT16 V) +INLINE void WW(SH4 *sh4, offs_t A, UINT16 V) { if (A >= 0xfe000000) { - sh4_internal_w(sh4.internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V << ((A & 2)*8), 0xffff << ((A & 2)*8)); + sh4_internal_w(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V << ((A & 2)*8), 0xffff << ((A & 2)*8)); return; } if (A >= 0xe0000000) { - memory_write_word_64le(sh4.program, A,V); + memory_write_word_64le(sh4->program, A,V); return; } - memory_write_word_64le(sh4.program, A & AM,V); + memory_write_word_64le(sh4->program, A & AM,V); } -INLINE void WL(offs_t A, UINT32 V) +INLINE void WL(SH4 *sh4, offs_t A, UINT32 V) { if (A >= 0xfe000000) { - sh4_internal_w(sh4.internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V, 0xffffffff); + sh4_internal_w(sh4->internal, ((A & 0x0fc) >> 2) | ((A & 0x1fe0000) >> 11), V, 0xffffffff); return; } if (A >= 0xe0000000) { - memory_write_dword_64le(sh4.program, A,V); + memory_write_dword_64le(sh4->program, A,V); return; } /* if (A >= 0x40000000) return;*/ - memory_write_dword_64le(sh4.program, A & AM,V); + memory_write_dword_64le(sh4->program, A & AM,V); } /* code cycles t-bit * 0011 nnnn mmmm 1100 1 - * ADD Rm,Rn */ -INLINE void ADD(UINT32 m, UINT32 n) +INLINE void ADD(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] += sh4.r[m]; + sh4->r[n] += sh4->r[m]; } /* code cycles t-bit * 0111 nnnn iiii iiii 1 - * ADD #imm,Rn */ -INLINE void ADDI(UINT32 i, UINT32 n) +INLINE void ADDI(SH4 *sh4, UINT32 i, UINT32 n) { - sh4.r[n] += (INT32)(INT16)(INT8)i; + sh4->r[n] += (INT32)(INT16)(INT8)i; } /* code cycles t-bit * 0011 nnnn mmmm 1110 1 carry * ADDC Rm,Rn */ -INLINE void ADDC(UINT32 m, UINT32 n) +INLINE void ADDC(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 tmp0, tmp1; - tmp1 = sh4.r[n] + sh4.r[m]; - tmp0 = sh4.r[n]; - sh4.r[n] = tmp1 + (sh4.sr & T); + tmp1 = sh4->r[n] + sh4->r[m]; + tmp0 = sh4->r[n]; + sh4->r[n] = tmp1 + (sh4->sr & T); if (tmp0 > tmp1) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; - if (tmp1 > sh4.r[n]) - sh4.sr |= T; + sh4->sr &= ~T; + if (tmp1 > sh4->r[n]) + sh4->sr |= T; } /* code cycles t-bit * 0011 nnnn mmmm 1111 1 overflow * ADDV Rm,Rn */ -INLINE void ADDV(UINT32 m, UINT32 n) +INLINE void ADDV(SH4 *sh4, UINT32 m, UINT32 n) { INT32 dest, src, ans; - if ((INT32) sh4.r[n] >= 0) + if ((INT32) sh4->r[n] >= 0) dest = 0; else dest = 1; - if ((INT32) sh4.r[m] >= 0) + if ((INT32) sh4->r[m] >= 0) src = 0; else src = 1; src += dest; - sh4.r[n] += sh4.r[m]; - if ((INT32) sh4.r[n] >= 0) + sh4->r[n] += sh4->r[m]; + if ((INT32) sh4->r[n] >= 0) ans = 0; else ans = 1; @@ -262,21 +262,21 @@ INLINE void ADDV(UINT32 m, UINT32 n) if (src == 0 || src == 2) { if (ans == 1) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0010 nnnn mmmm 1001 1 - * AND Rm,Rn */ -INLINE void AND(UINT32 m, UINT32 n) +INLINE void AND(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] &= sh4.r[m]; + sh4->r[n] &= sh4->r[m]; } @@ -284,36 +284,36 @@ INLINE void AND(UINT32 m, UINT32 n) * 1100 1001 iiii iiii 1 - * AND #imm,R0 */ -INLINE void ANDI(UINT32 i) +INLINE void ANDI(SH4 *sh4, UINT32 i) { - sh4.r[0] &= i; + sh4->r[0] &= i; } /* code cycles t-bit * 1100 1101 iiii iiii 1 - * AND.B #imm,@(R0,GBR) */ -INLINE void ANDM(UINT32 i) +INLINE void ANDM(SH4 *sh4, UINT32 i) { UINT32 temp; - sh4.ea = sh4.gbr + sh4.r[0]; - temp = i & RB( sh4.ea ); - WB( sh4.ea, temp ); - sh4.sh4_icount -= 2; + sh4->ea = sh4->gbr + sh4->r[0]; + temp = i & RB(sh4, sh4->ea ); + WB(sh4, sh4->ea, temp ); + sh4->sh4_icount -= 2; } /* code cycles t-bit * 1000 1011 dddd dddd 3/1 - * BF disp8 */ -INLINE void BF(UINT32 d) +INLINE void BF(SH4 *sh4, UINT32 d) { - if ((sh4.sr & T) == 0) + if ((sh4->sr & T) == 0) { INT32 disp = ((INT32)d << 24) >> 24; - sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4.sh4_icount -= 2; + sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; + sh4->sh4_icount -= 2; } } @@ -321,14 +321,14 @@ INLINE void BF(UINT32 d) * 1000 1111 dddd dddd 3/1 - * BFS disp8 */ -INLINE void BFS(UINT32 d) +INLINE void BFS(SH4 *sh4, UINT32 d) { - if ((sh4.sr & T) == 0) + if ((sh4->sr & T) == 0) { INT32 disp = ((INT32)d << 24) >> 24; - sh4.delay = sh4.pc; - sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4.sh4_icount--; + sh4->delay = sh4->pc; + sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; + sh4->sh4_icount--; } } @@ -336,74 +336,74 @@ INLINE void BFS(UINT32 d) * 1010 dddd dddd dddd 2 - * BRA disp12 */ -INLINE void BRA(UINT32 d) +INLINE void BRA(SH4 *sh4, UINT32 d) { INT32 disp = ((INT32)d << 20) >> 20; #if BUSY_LOOP_HACKS if (disp == -2) { - UINT32 next_opcode = RW(sh4.ppc & AM); + UINT32 next_opcode = RW(sh4,sh4->ppc & AM); /* BRA $ * NOP */ if (next_opcode == 0x0009) - sh4.sh4_icount %= 3; /* cycles for BRA $ and NOP taken (3) */ + sh4->sh4_icount %= 3; /* cycles for BRA $ and NOP taken (3) */ } #endif - sh4.delay = sh4.pc; - sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4.sh4_icount--; + sh4->delay = sh4->pc; + sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; + sh4->sh4_icount--; } /* code cycles t-bit * 0000 mmmm 0010 0011 2 - * BRAF Rm */ -INLINE void BRAF(UINT32 m) +INLINE void BRAF(SH4 *sh4, UINT32 m) { - sh4.delay = sh4.pc; - sh4.pc += sh4.r[m] + 2; - sh4.sh4_icount--; + sh4->delay = sh4->pc; + sh4->pc += sh4->r[m] + 2; + sh4->sh4_icount--; } /* code cycles t-bit * 1011 dddd dddd dddd 2 - * BSR disp12 */ -INLINE void BSR(UINT32 d) +INLINE void BSR(SH4 *sh4, UINT32 d) { INT32 disp = ((INT32)d << 20) >> 20; - sh4.pr = sh4.pc + 2; - sh4.delay = sh4.pc; - sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4.sh4_icount--; + sh4->pr = sh4->pc + 2; + sh4->delay = sh4->pc; + sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; + sh4->sh4_icount--; } /* code cycles t-bit * 0000 mmmm 0000 0011 2 - * BSRF Rm */ -INLINE void BSRF(UINT32 m) +INLINE void BSRF(SH4 *sh4, UINT32 m) { - sh4.pr = sh4.pc + 2; - sh4.delay = sh4.pc; - sh4.pc += sh4.r[m] + 2; - sh4.sh4_icount--; + sh4->pr = sh4->pc + 2; + sh4->delay = sh4->pc; + sh4->pc += sh4->r[m] + 2; + sh4->sh4_icount--; } /* code cycles t-bit * 1000 1001 dddd dddd 3/1 - * BT disp8 */ -INLINE void BT(UINT32 d) +INLINE void BT(SH4 *sh4, UINT32 d) { - if ((sh4.sr & T) != 0) + if ((sh4->sr & T) != 0) { INT32 disp = ((INT32)d << 24) >> 24; - sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4.sh4_icount -= 2; + sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; + sh4->sh4_icount -= 2; } } @@ -411,14 +411,14 @@ INLINE void BT(UINT32 d) * 1000 1101 dddd dddd 2/1 - * BTS disp8 */ -INLINE void BTS(UINT32 d) +INLINE void BTS(SH4 *sh4, UINT32 d) { - if ((sh4.sr & T) != 0) + if ((sh4->sr & T) != 0) { INT32 disp = ((INT32)d << 24) >> 24; - sh4.delay = sh4.pc; - sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2; - sh4.sh4_icount--; + sh4->delay = sh4->pc; + sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; + sh4->sh4_icount--; } } @@ -426,79 +426,79 @@ INLINE void BTS(UINT32 d) * 0000 0000 0010 1000 1 - * CLRMAC */ -INLINE void CLRMAC(void) +INLINE void CLRMAC(SH4 *sh4) { - sh4.mach = 0; - sh4.macl = 0; + sh4->mach = 0; + sh4->macl = 0; } /* code cycles t-bit * 0000 0000 0000 1000 1 - * CLRT */ -INLINE void CLRT(void) +INLINE void CLRT(SH4 *sh4) { - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0000 1 comparison result * CMP_EQ Rm,Rn */ -INLINE void CMPEQ(UINT32 m, UINT32 n) +INLINE void CMPEQ(SH4 *sh4, UINT32 m, UINT32 n) { - if (sh4.r[n] == sh4.r[m]) - sh4.sr |= T; + if (sh4->r[n] == sh4->r[m]) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0011 1 comparison result * CMP_GE Rm,Rn */ -INLINE void CMPGE(UINT32 m, UINT32 n) +INLINE void CMPGE(SH4 *sh4, UINT32 m, UINT32 n) { - if ((INT32) sh4.r[n] >= (INT32) sh4.r[m]) - sh4.sr |= T; + if ((INT32) sh4->r[n] >= (INT32) sh4->r[m]) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0111 1 comparison result * CMP_GT Rm,Rn */ -INLINE void CMPGT(UINT32 m, UINT32 n) +INLINE void CMPGT(SH4 *sh4, UINT32 m, UINT32 n) { - if ((INT32) sh4.r[n] > (INT32) sh4.r[m]) - sh4.sr |= T; + if ((INT32) sh4->r[n] > (INT32) sh4->r[m]) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0110 1 comparison result * CMP_HI Rm,Rn */ -INLINE void CMPHI(UINT32 m, UINT32 n) +INLINE void CMPHI(SH4 *sh4, UINT32 m, UINT32 n) { - if ((UINT32) sh4.r[n] > (UINT32) sh4.r[m]) - sh4.sr |= T; + if ((UINT32) sh4->r[n] > (UINT32) sh4->r[m]) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0010 1 comparison result * CMP_HS Rm,Rn */ -INLINE void CMPHS(UINT32 m, UINT32 n) +INLINE void CMPHS(SH4 *sh4, UINT32 m, UINT32 n) { - if ((UINT32) sh4.r[n] >= (UINT32) sh4.r[m]) - sh4.sr |= T; + if ((UINT32) sh4->r[n] >= (UINT32) sh4->r[m]) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } @@ -506,43 +506,43 @@ INLINE void CMPHS(UINT32 m, UINT32 n) * 0100 nnnn 0001 0101 1 comparison result * CMP_PL Rn */ -INLINE void CMPPL(UINT32 n) +INLINE void CMPPL(SH4 *sh4, UINT32 n) { - if ((INT32) sh4.r[n] > 0) - sh4.sr |= T; + if ((INT32) sh4->r[n] > 0) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0100 nnnn 0001 0001 1 comparison result * CMP_PZ Rn */ -INLINE void CMPPZ(UINT32 n) +INLINE void CMPPZ(SH4 *sh4, UINT32 n) { - if ((INT32) sh4.r[n] >= 0) - sh4.sr |= T; + if ((INT32) sh4->r[n] >= 0) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0010 nnnn mmmm 1100 1 comparison result * CMP_STR Rm,Rn */ -INLINE void CMPSTR(UINT32 m, UINT32 n) +INLINE void CMPSTR(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 temp; INT32 HH, HL, LH, LL; - temp = sh4.r[n] ^ sh4.r[m]; + temp = sh4->r[n] ^ sh4->r[m]; HH = (temp >> 24) & 0xff; HL = (temp >> 16) & 0xff; LH = (temp >> 8) & 0xff; LL = temp & 0xff; if (HH && HL && LH && LL) - sh4.sr &= ~T; + sh4->sr &= ~T; else - sh4.sr |= T; + sh4->sr |= T; } @@ -550,154 +550,154 @@ INLINE void CMPSTR(UINT32 m, UINT32 n) * 1000 1000 iiii iiii 1 comparison result * CMP/EQ #imm,R0 */ -INLINE void CMPIM(UINT32 i) +INLINE void CMPIM(SH4 *sh4, UINT32 i) { UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i; - if (sh4.r[0] == imm) - sh4.sr |= T; + if (sh4->r[0] == imm) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0010 nnnn mmmm 0111 1 calculation result * DIV0S Rm,Rn */ -INLINE void DIV0S(UINT32 m, UINT32 n) +INLINE void DIV0S(SH4 *sh4, UINT32 m, UINT32 n) { - if ((sh4.r[n] & 0x80000000) == 0) - sh4.sr &= ~Q; + if ((sh4->r[n] & 0x80000000) == 0) + sh4->sr &= ~Q; else - sh4.sr |= Q; - if ((sh4.r[m] & 0x80000000) == 0) - sh4.sr &= ~M; + sh4->sr |= Q; + if ((sh4->r[m] & 0x80000000) == 0) + sh4->sr &= ~M; else - sh4.sr |= M; - if ((sh4.r[m] ^ sh4.r[n]) & 0x80000000) - sh4.sr |= T; + sh4->sr |= M; + if ((sh4->r[m] ^ sh4->r[n]) & 0x80000000) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* code cycles t-bit * 0000 0000 0001 1001 1 0 * DIV0U */ -INLINE void DIV0U(void) +INLINE void DIV0U(SH4 *sh4) { - sh4.sr &= ~(M | Q | T); + sh4->sr &= ~(M | Q | T); } /* code cycles t-bit * 0011 nnnn mmmm 0100 1 calculation result * DIV1 Rm,Rn */ -INLINE void DIV1(UINT32 m, UINT32 n) +INLINE void DIV1(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 tmp0; UINT32 old_q; - old_q = sh4.sr & Q; - if (0x80000000 & sh4.r[n]) - sh4.sr |= Q; + old_q = sh4->sr & Q; + if (0x80000000 & sh4->r[n]) + sh4->sr |= Q; else - sh4.sr &= ~Q; + sh4->sr &= ~Q; - sh4.r[n] = (sh4.r[n] << 1) | (sh4.sr & T); + sh4->r[n] = (sh4->r[n] << 1) | (sh4->sr & T); if (!old_q) { - if (!(sh4.sr & M)) + if (!(sh4->sr & M)) { - tmp0 = sh4.r[n]; - sh4.r[n] -= sh4.r[m]; - if(!(sh4.sr & Q)) - if(sh4.r[n] > tmp0) - sh4.sr |= Q; + tmp0 = sh4->r[n]; + sh4->r[n] -= sh4->r[m]; + if(!(sh4->sr & Q)) + if(sh4->r[n] > tmp0) + sh4->sr |= Q; else - sh4.sr &= ~Q; + sh4->sr &= ~Q; else - if(sh4.r[n] > tmp0) - sh4.sr &= ~Q; + if(sh4->r[n] > tmp0) + sh4->sr &= ~Q; else - sh4.sr |= Q; + sh4->sr |= Q; } else { - tmp0 = sh4.r[n]; - sh4.r[n] += sh4.r[m]; - if(!(sh4.sr & Q)) + tmp0 = sh4->r[n]; + sh4->r[n] += sh4->r[m]; + if(!(sh4->sr & Q)) { - if(sh4.r[n] < tmp0) - sh4.sr &= ~Q; + if(sh4->r[n] < tmp0) + sh4->sr &= ~Q; else - sh4.sr |= Q; + sh4->sr |= Q; } else { - if(sh4.r[n] < tmp0) - sh4.sr |= Q; + if(sh4->r[n] < tmp0) + sh4->sr |= Q; else - sh4.sr &= ~Q; + sh4->sr &= ~Q; } } } else { - if (!(sh4.sr & M)) + if (!(sh4->sr & M)) { - tmp0 = sh4.r[n]; - sh4.r[n] += sh4.r[m]; - if(!(sh4.sr & Q)) - if(sh4.r[n] < tmp0) - sh4.sr |= Q; + tmp0 = sh4->r[n]; + sh4->r[n] += sh4->r[m]; + if(!(sh4->sr & Q)) + if(sh4->r[n] < tmp0) + sh4->sr |= Q; else - sh4.sr &= ~Q; + sh4->sr &= ~Q; else - if(sh4.r[n] < tmp0) - sh4.sr &= ~Q; + if(sh4->r[n] < tmp0) + sh4->sr &= ~Q; else - sh4.sr |= Q; + sh4->sr |= Q; } else { - tmp0 = sh4.r[n]; - sh4.r[n] -= sh4.r[m]; - if(!(sh4.sr & Q)) - if(sh4.r[n] > tmp0) - sh4.sr &= ~Q; + tmp0 = sh4->r[n]; + sh4->r[n] -= sh4->r[m]; + if(!(sh4->sr & Q)) + if(sh4->r[n] > tmp0) + sh4->sr &= ~Q; else - sh4.sr |= Q; + sh4->sr |= Q; else - if(sh4.r[n] > tmp0) - sh4.sr |= Q; + if(sh4->r[n] > tmp0) + sh4->sr |= Q; else - sh4.sr &= ~Q; + sh4->sr &= ~Q; } } - tmp0 = (sh4.sr & (Q | M)); + tmp0 = (sh4->sr & (Q | M)); if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */ - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* DMULS.L Rm,Rn */ -INLINE void DMULS(UINT32 m, UINT32 n) +INLINE void DMULS(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; UINT32 temp0, temp1, temp2, temp3; INT32 tempm, tempn, fnLmL; - tempn = (INT32) sh4.r[n]; - tempm = (INT32) sh4.r[m]; + tempn = (INT32) sh4->r[n]; + tempm = (INT32) sh4->r[m]; if (tempn < 0) tempn = 0 - tempn; if (tempm < 0) tempm = 0 - tempm; - if ((INT32) (sh4.r[n] ^ sh4.r[m]) < 0) + if ((INT32) (sh4->r[n] ^ sh4->r[m]) < 0) fnLmL = -1; else fnLmL = 0; @@ -728,21 +728,21 @@ INLINE void DMULS(UINT32 m, UINT32 n) else Res0 = (~Res0) + 1; } - sh4.mach = Res2; - sh4.macl = Res0; - sh4.sh4_icount--; + sh4->mach = Res2; + sh4->macl = Res0; + sh4->sh4_icount--; } /* DMULU.L Rm,Rn */ -INLINE void DMULU(UINT32 m, UINT32 n) +INLINE void DMULU(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; UINT32 temp0, temp1, temp2, temp3; - RnL = sh4.r[n] & 0x0000ffff; - RnH = (sh4.r[n] >> 16) & 0x0000ffff; - RmL = sh4.r[m] & 0x0000ffff; - RmH = (sh4.r[m] >> 16) & 0x0000ffff; + RnL = sh4->r[n] & 0x0000ffff; + RnH = (sh4->r[n] >> 16) & 0x0000ffff; + RmL = sh4->r[m] & 0x0000ffff; + RmH = (sh4->r[m] >> 16) & 0x0000ffff; temp0 = RmL * RnL; temp1 = RmH * RnL; temp2 = RmL * RnH; @@ -756,31 +756,31 @@ INLINE void DMULU(UINT32 m, UINT32 n) if (Res0 < temp0) Res2++; Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3; - sh4.mach = Res2; - sh4.macl = Res0; - sh4.sh4_icount--; + sh4->mach = Res2; + sh4->macl = Res0; + sh4->sh4_icount--; } /* DT Rn */ -INLINE void DT(UINT32 n) +INLINE void DT(SH4 *sh4, UINT32 n) { - sh4.r[n]--; - if (sh4.r[n] == 0) - sh4.sr |= T; + sh4->r[n]--; + if (sh4->r[n] == 0) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; #if BUSY_LOOP_HACKS { - UINT32 next_opcode = RW(sh4.ppc & AM); + UINT32 next_opcode = RW(sh4,sh4->ppc & AM); /* DT Rn * BF $-2 */ if (next_opcode == 0x8bfd) { - while (sh4.r[n] > 1 && sh4.sh4_icount > 4) + while (sh4->r[n] > 1 && sh4->sh4_icount > 4) { - sh4.r[n]--; - sh4.sh4_icount -= 4; /* cycles for DT (1) and BF taken (3) */ + sh4->r[n]--; + sh4->sh4_icount -= 4; /* cycles for DT (1) and BF taken (3) */ } } } @@ -788,160 +788,160 @@ INLINE void DT(UINT32 n) } /* EXTS.B Rm,Rn */ -INLINE void EXTSB(UINT32 m, UINT32 n) +INLINE void EXTSB(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = ((INT32)sh4.r[m] << 24) >> 24; + sh4->r[n] = ((INT32)sh4->r[m] << 24) >> 24; } /* EXTS.W Rm,Rn */ -INLINE void EXTSW(UINT32 m, UINT32 n) +INLINE void EXTSW(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = ((INT32)sh4.r[m] << 16) >> 16; + sh4->r[n] = ((INT32)sh4->r[m] << 16) >> 16; } /* EXTU.B Rm,Rn */ -INLINE void EXTUB(UINT32 m, UINT32 n) +INLINE void EXTUB(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = sh4.r[m] & 0x000000ff; + sh4->r[n] = sh4->r[m] & 0x000000ff; } /* EXTU.W Rm,Rn */ -INLINE void EXTUW(UINT32 m, UINT32 n) +INLINE void EXTUW(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = sh4.r[m] & 0x0000ffff; + sh4->r[n] = sh4->r[m] & 0x0000ffff; } /* JMP @Rm */ -INLINE void JMP(UINT32 m) +INLINE void JMP(SH4 *sh4, UINT32 m) { - sh4.delay = sh4.pc; - sh4.pc = sh4.ea = sh4.r[m]; + sh4->delay = sh4->pc; + sh4->pc = sh4->ea = sh4->r[m]; } /* JSR @Rm */ -INLINE void JSR(UINT32 m) +INLINE void JSR(SH4 *sh4, UINT32 m) { - sh4.delay = sh4.pc; - sh4.pr = sh4.pc + 2; - sh4.pc = sh4.ea = sh4.r[m]; - sh4.sh4_icount--; + sh4->delay = sh4->pc; + sh4->pr = sh4->pc + 2; + sh4->pc = sh4->ea = sh4->r[m]; + sh4->sh4_icount--; } /* LDC Rm,SR */ -INLINE void LDCSR(UINT32 m) +INLINE void LDCSR(SH4 *sh4, UINT32 m) { UINT32 reg; - reg = sh4.r[m]; + reg = sh4->r[m]; if ((Machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank((sh4.sr & sRB) >> 29); - if ((sh4.r[m] & sRB) != (sh4.sr & sRB)) - sh4_change_register_bank(sh4.r[m] & sRB ? 1 : 0); - sh4.sr = reg & FLAGS; - sh4_exception_recompute(); + sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); + if ((sh4->r[m] & sRB) != (sh4->sr & sRB)) + sh4_change_register_bank(sh4, sh4->r[m] & sRB ? 1 : 0); + sh4->sr = reg & FLAGS; + sh4_exception_recompute(sh4); } /* LDC Rm,GBR */ -INLINE void LDCGBR(UINT32 m) +INLINE void LDCGBR(SH4 *sh4, UINT32 m) { - sh4.gbr = sh4.r[m]; + sh4->gbr = sh4->r[m]; } /* LDC Rm,VBR */ -INLINE void LDCVBR(UINT32 m) +INLINE void LDCVBR(SH4 *sh4, UINT32 m) { - sh4.vbr = sh4.r[m]; + sh4->vbr = sh4->r[m]; } /* LDC.L @Rm+,SR */ -INLINE void LDCMSR(UINT32 m) +INLINE void LDCMSR(SH4 *sh4, UINT32 m) { UINT32 old; - old = sh4.sr; - sh4.ea = sh4.r[m]; - sh4.sr = RL( sh4.ea ) & FLAGS; + old = sh4->sr; + sh4->ea = sh4->r[m]; + sh4->sr = RL(sh4, sh4->ea ) & FLAGS; if ((Machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank((old & sRB) >> 29); - if ((old & sRB) != (sh4.sr & sRB)) - sh4_change_register_bank(sh4.sr & sRB ? 1 : 0); - sh4.r[m] += 4; - sh4.sh4_icount -= 2; - sh4_exception_recompute(); + sh4_syncronize_register_bank(sh4, (old & sRB) >> 29); + if ((old & sRB) != (sh4->sr & sRB)) + sh4_change_register_bank(sh4, sh4->sr & sRB ? 1 : 0); + sh4->r[m] += 4; + sh4->sh4_icount -= 2; + sh4_exception_recompute(sh4); } /* LDC.L @Rm+,GBR */ -INLINE void LDCMGBR(UINT32 m) +INLINE void LDCMGBR(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.gbr = RL( sh4.ea ); - sh4.r[m] += 4; - sh4.sh4_icount -= 2; + sh4->ea = sh4->r[m]; + sh4->gbr = RL(sh4, sh4->ea ); + sh4->r[m] += 4; + sh4->sh4_icount -= 2; } /* LDC.L @Rm+,VBR */ -INLINE void LDCMVBR(UINT32 m) +INLINE void LDCMVBR(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.vbr = RL( sh4.ea ); - sh4.r[m] += 4; - sh4.sh4_icount -= 2; + sh4->ea = sh4->r[m]; + sh4->vbr = RL(sh4, sh4->ea ); + sh4->r[m] += 4; + sh4->sh4_icount -= 2; } /* LDS Rm,MACH */ -INLINE void LDSMACH(UINT32 m) +INLINE void LDSMACH(SH4 *sh4, UINT32 m) { - sh4.mach = sh4.r[m]; + sh4->mach = sh4->r[m]; } /* LDS Rm,MACL */ -INLINE void LDSMACL(UINT32 m) +INLINE void LDSMACL(SH4 *sh4, UINT32 m) { - sh4.macl = sh4.r[m]; + sh4->macl = sh4->r[m]; } /* LDS Rm,PR */ -INLINE void LDSPR(UINT32 m) +INLINE void LDSPR(SH4 *sh4, UINT32 m) { - sh4.pr = sh4.r[m]; + sh4->pr = sh4->r[m]; } /* LDS.L @Rm+,MACH */ -INLINE void LDSMMACH(UINT32 m) +INLINE void LDSMMACH(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.mach = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->mach = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } /* LDS.L @Rm+,MACL */ -INLINE void LDSMMACL(UINT32 m) +INLINE void LDSMMACL(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.macl = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->macl = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } /* LDS.L @Rm+,PR */ -INLINE void LDSMPR(UINT32 m) +INLINE void LDSMPR(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.pr = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->pr = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } /* MAC.L @Rm+,@Rn+ */ -INLINE void MAC_L(UINT32 m, UINT32 n) +INLINE void MAC_L(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; UINT32 temp0, temp1, temp2, temp3; INT32 tempm, tempn, fnLmL; - tempn = (INT32) RL( sh4.r[n] ); - sh4.r[n] += 4; - tempm = (INT32) RL( sh4.r[m] ); - sh4.r[m] += 4; + tempn = (INT32) RL(sh4, sh4->r[n] ); + sh4->r[n] += 4; + tempm = (INT32) RL(sh4, sh4->r[m] ); + sh4->r[m] += 4; if ((INT32) (tempn ^ tempm) < 0) fnLmL = -1; else @@ -977,12 +977,12 @@ INLINE void MAC_L(UINT32 m, UINT32 n) else Res0 = (~Res0) + 1; } - if (sh4.sr & S) + if (sh4->sr & S) { - Res0 = sh4.macl + Res0; - if (sh4.macl > Res0) + Res0 = sh4->macl + Res0; + if (sh4->macl > Res0) Res2++; - Res2 += (sh4.mach & 0x0000ffff); + Res2 += (sh4->mach & 0x0000ffff); if (((INT32) Res2 < 0) && (Res2 < 0xffff8000)) { Res2 = 0x00008000; @@ -993,34 +993,34 @@ INLINE void MAC_L(UINT32 m, UINT32 n) Res2 = 0x00007fff; Res0 = 0xffffffff; } - sh4.mach = Res2; - sh4.macl = Res0; + sh4->mach = Res2; + sh4->macl = Res0; } else { - Res0 = sh4.macl + Res0; - if (sh4.macl > Res0) + Res0 = sh4->macl + Res0; + if (sh4->macl > Res0) Res2++; - Res2 += sh4.mach; - sh4.mach = Res2; - sh4.macl = Res0; + Res2 += sh4->mach; + sh4->mach = Res2; + sh4->macl = Res0; } - sh4.sh4_icount -= 2; + sh4->sh4_icount -= 2; } /* MAC.W @Rm+,@Rn+ */ -INLINE void MAC_W(UINT32 m, UINT32 n) +INLINE void MAC_W(SH4 *sh4, UINT32 m, UINT32 n) { INT32 tempm, tempn, dest, src, ans; UINT32 templ; - tempn = (INT32) RW( sh4.r[n] ); - sh4.r[n] += 2; - tempm = (INT32) RW( sh4.r[m] ); - sh4.r[m] += 2; - templ = sh4.macl; + tempn = (INT32) RW(sh4, sh4->r[n] ); + sh4->r[n] += 2; + tempm = (INT32) RW(sh4, sh4->r[m] ); + sh4->r[m] += 2; + templ = sh4->macl; tempm = ((INT32) (short) tempn * (INT32) (short) tempm); - if ((INT32) sh4.macl >= 0) + if ((INT32) sh4->macl >= 0) dest = 0; else dest = 1; @@ -1035,639 +1035,639 @@ INLINE void MAC_W(UINT32 m, UINT32 n) tempn = 0xffffffff; } src += dest; - sh4.macl += tempm; - if ((INT32) sh4.macl >= 0) + sh4->macl += tempm; + if ((INT32) sh4->macl >= 0) ans = 0; else ans = 1; ans += dest; - if (sh4.sr & S) + if (sh4->sr & S) { if (ans == 1) { if (src == 0) - sh4.macl = 0x7fffffff; + sh4->macl = 0x7fffffff; if (src == 2) - sh4.macl = 0x80000000; + sh4->macl = 0x80000000; } } else { - sh4.mach += tempn; - if (templ > sh4.macl) - sh4.mach += 1; + sh4->mach += tempn; + if (templ > sh4->macl) + sh4->mach += 1; } - sh4.sh4_icount -= 2; + sh4->sh4_icount -= 2; } /* MOV Rm,Rn */ -INLINE void MOV(UINT32 m, UINT32 n) +INLINE void MOV(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = sh4.r[m]; + sh4->r[n] = sh4->r[m]; } /* MOV.B Rm,@Rn */ -INLINE void MOVBS(UINT32 m, UINT32 n) +INLINE void MOVBS(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[n]; - WB( sh4.ea, sh4.r[m] & 0x000000ff); + sh4->ea = sh4->r[n]; + WB(sh4, sh4->ea, sh4->r[m] & 0x000000ff); } /* MOV.W Rm,@Rn */ -INLINE void MOVWS(UINT32 m, UINT32 n) +INLINE void MOVWS(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[n]; - WW( sh4.ea, sh4.r[m] & 0x0000ffff); + sh4->ea = sh4->r[n]; + WW(sh4, sh4->ea, sh4->r[m] & 0x0000ffff); } /* MOV.L Rm,@Rn */ -INLINE void MOVLS(UINT32 m, UINT32 n) +INLINE void MOVLS(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.r[m] ); + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->r[m] ); } /* MOV.B @Rm,Rn */ -INLINE void MOVBL(UINT32 m, UINT32 n) +INLINE void MOVBL(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[m]; - sh4.r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh4.ea ); + sh4->ea = sh4->r[m]; + sh4->r[n] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); } /* MOV.W @Rm,Rn */ -INLINE void MOVWL(UINT32 m, UINT32 n) +INLINE void MOVWL(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[m]; - sh4.r[n] = (UINT32)(INT32)(INT16) RW( sh4.ea ); + sh4->ea = sh4->r[m]; + sh4->r[n] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); } /* MOV.L @Rm,Rn */ -INLINE void MOVLL(UINT32 m, UINT32 n) +INLINE void MOVLL(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[m]; - sh4.r[n] = RL( sh4.ea ); + sh4->ea = sh4->r[m]; + sh4->r[n] = RL(sh4, sh4->ea ); } /* MOV.B Rm,@-Rn */ -INLINE void MOVBM(UINT32 m, UINT32 n) +INLINE void MOVBM(SH4 *sh4, UINT32 m, UINT32 n) { - /* SMG : bug fix, was reading sh4.r[n] */ - UINT32 data = sh4.r[m] & 0x000000ff; + /* SMG : bug fix, was reading sh4->r[n] */ + UINT32 data = sh4->r[m] & 0x000000ff; - sh4.r[n] -= 1; - WB( sh4.r[n], data ); + sh4->r[n] -= 1; + WB(sh4, sh4->r[n], data ); } /* MOV.W Rm,@-Rn */ -INLINE void MOVWM(UINT32 m, UINT32 n) +INLINE void MOVWM(SH4 *sh4, UINT32 m, UINT32 n) { - UINT32 data = sh4.r[m] & 0x0000ffff; + UINT32 data = sh4->r[m] & 0x0000ffff; - sh4.r[n] -= 2; - WW( sh4.r[n], data ); + sh4->r[n] -= 2; + WW(sh4, sh4->r[n], data ); } /* MOV.L Rm,@-Rn */ -INLINE void MOVLM(UINT32 m, UINT32 n) +INLINE void MOVLM(SH4 *sh4, UINT32 m, UINT32 n) { - UINT32 data = sh4.r[m]; + UINT32 data = sh4->r[m]; - sh4.r[n] -= 4; - WL( sh4.r[n], data ); + sh4->r[n] -= 4; + WL(sh4, sh4->r[n], data ); } /* MOV.B @Rm+,Rn */ -INLINE void MOVBP(UINT32 m, UINT32 n) +INLINE void MOVBP(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh4.r[m] ); + sh4->r[n] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->r[m] ); if (n != m) - sh4.r[m] += 1; + sh4->r[m] += 1; } /* MOV.W @Rm+,Rn */ -INLINE void MOVWP(UINT32 m, UINT32 n) +INLINE void MOVWP(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = (UINT32)(INT32)(INT16) RW( sh4.r[m] ); + sh4->r[n] = (UINT32)(INT32)(INT16) RW(sh4, sh4->r[m] ); if (n != m) - sh4.r[m] += 2; + sh4->r[m] += 2; } /* MOV.L @Rm+,Rn */ -INLINE void MOVLP(UINT32 m, UINT32 n) +INLINE void MOVLP(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = RL( sh4.r[m] ); + sh4->r[n] = RL(sh4, sh4->r[m] ); if (n != m) - sh4.r[m] += 4; + sh4->r[m] += 4; } /* MOV.B Rm,@(R0,Rn) */ -INLINE void MOVBS0(UINT32 m, UINT32 n) +INLINE void MOVBS0(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[n] + sh4.r[0]; - WB( sh4.ea, sh4.r[m] & 0x000000ff ); + sh4->ea = sh4->r[n] + sh4->r[0]; + WB(sh4, sh4->ea, sh4->r[m] & 0x000000ff ); } /* MOV.W Rm,@(R0,Rn) */ -INLINE void MOVWS0(UINT32 m, UINT32 n) +INLINE void MOVWS0(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[n] + sh4.r[0]; - WW( sh4.ea, sh4.r[m] & 0x0000ffff ); + sh4->ea = sh4->r[n] + sh4->r[0]; + WW(sh4, sh4->ea, sh4->r[m] & 0x0000ffff ); } /* MOV.L Rm,@(R0,Rn) */ -INLINE void MOVLS0(UINT32 m, UINT32 n) +INLINE void MOVLS0(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[n] + sh4.r[0]; - WL( sh4.ea, sh4.r[m] ); + sh4->ea = sh4->r[n] + sh4->r[0]; + WL(sh4, sh4->ea, sh4->r[m] ); } /* MOV.B @(R0,Rm),Rn */ -INLINE void MOVBL0(UINT32 m, UINT32 n) +INLINE void MOVBL0(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[m] + sh4.r[0]; - sh4.r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh4.ea ); + sh4->ea = sh4->r[m] + sh4->r[0]; + sh4->r[n] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); } /* MOV.W @(R0,Rm),Rn */ -INLINE void MOVWL0(UINT32 m, UINT32 n) +INLINE void MOVWL0(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[m] + sh4.r[0]; - sh4.r[n] = (UINT32)(INT32)(INT16) RW( sh4.ea ); + sh4->ea = sh4->r[m] + sh4->r[0]; + sh4->r[n] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); } /* MOV.L @(R0,Rm),Rn */ -INLINE void MOVLL0(UINT32 m, UINT32 n) +INLINE void MOVLL0(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[m] + sh4.r[0]; - sh4.r[n] = RL( sh4.ea ); + sh4->ea = sh4->r[m] + sh4->r[0]; + sh4->r[n] = RL(sh4, sh4->ea ); } /* MOV #imm,Rn */ -INLINE void MOVI(UINT32 i, UINT32 n) +INLINE void MOVI(SH4 *sh4, UINT32 i, UINT32 n) { - sh4.r[n] = (UINT32)(INT32)(INT16)(INT8) i; + sh4->r[n] = (UINT32)(INT32)(INT16)(INT8) i; } /* MOV.W @(disp8,PC),Rn */ -INLINE void MOVWI(UINT32 d, UINT32 n) +INLINE void MOVWI(SH4 *sh4, UINT32 d, UINT32 n) { UINT32 disp = d & 0xff; - sh4.ea = sh4.pc + disp * 2 + 2; - sh4.r[n] = (UINT32)(INT32)(INT16) RW( sh4.ea ); + sh4->ea = sh4->pc + disp * 2 + 2; + sh4->r[n] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); } /* MOV.L @(disp8,PC),Rn */ -INLINE void MOVLI(UINT32 d, UINT32 n) +INLINE void MOVLI(SH4 *sh4, UINT32 d, UINT32 n) { UINT32 disp = d & 0xff; - sh4.ea = ((sh4.pc + 2) & ~3) + disp * 4; - sh4.r[n] = RL( sh4.ea ); + sh4->ea = ((sh4->pc + 2) & ~3) + disp * 4; + sh4->r[n] = RL(sh4, sh4->ea ); } /* MOV.B @(disp8,GBR),R0 */ -INLINE void MOVBLG(UINT32 d) +INLINE void MOVBLG(SH4 *sh4, UINT32 d) { UINT32 disp = d & 0xff; - sh4.ea = sh4.gbr + disp; - sh4.r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh4.ea ); + sh4->ea = sh4->gbr + disp; + sh4->r[0] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); } /* MOV.W @(disp8,GBR),R0 */ -INLINE void MOVWLG(UINT32 d) +INLINE void MOVWLG(SH4 *sh4, UINT32 d) { UINT32 disp = d & 0xff; - sh4.ea = sh4.gbr + disp * 2; - sh4.r[0] = (INT32)(INT16) RW( sh4.ea ); + sh4->ea = sh4->gbr + disp * 2; + sh4->r[0] = (INT32)(INT16) RW(sh4, sh4->ea ); } /* MOV.L @(disp8,GBR),R0 */ -INLINE void MOVLLG(UINT32 d) +INLINE void MOVLLG(SH4 *sh4, UINT32 d) { UINT32 disp = d & 0xff; - sh4.ea = sh4.gbr + disp * 4; - sh4.r[0] = RL( sh4.ea ); + sh4->ea = sh4->gbr + disp * 4; + sh4->r[0] = RL(sh4, sh4->ea ); } /* MOV.B R0,@(disp8,GBR) */ -INLINE void MOVBSG(UINT32 d) +INLINE void MOVBSG(SH4 *sh4, UINT32 d) { UINT32 disp = d & 0xff; - sh4.ea = sh4.gbr + disp; - WB( sh4.ea, sh4.r[0] & 0x000000ff ); + sh4->ea = sh4->gbr + disp; + WB(sh4, sh4->ea, sh4->r[0] & 0x000000ff ); } /* MOV.W R0,@(disp8,GBR) */ -INLINE void MOVWSG(UINT32 d) +INLINE void MOVWSG(SH4 *sh4, UINT32 d) { UINT32 disp = d & 0xff; - sh4.ea = sh4.gbr + disp * 2; - WW( sh4.ea, sh4.r[0] & 0x0000ffff ); + sh4->ea = sh4->gbr + disp * 2; + WW(sh4, sh4->ea, sh4->r[0] & 0x0000ffff ); } /* MOV.L R0,@(disp8,GBR) */ -INLINE void MOVLSG(UINT32 d) +INLINE void MOVLSG(SH4 *sh4, UINT32 d) { UINT32 disp = d & 0xff; - sh4.ea = sh4.gbr + disp * 4; - WL( sh4.ea, sh4.r[0] ); + sh4->ea = sh4->gbr + disp * 4; + WL(sh4, sh4->ea, sh4->r[0] ); } /* MOV.B R0,@(disp4,Rn) */ -INLINE void MOVBS4(UINT32 d, UINT32 n) +INLINE void MOVBS4(SH4 *sh4, UINT32 d, UINT32 n) { UINT32 disp = d & 0x0f; - sh4.ea = sh4.r[n] + disp; - WB( sh4.ea, sh4.r[0] & 0x000000ff ); + sh4->ea = sh4->r[n] + disp; + WB(sh4, sh4->ea, sh4->r[0] & 0x000000ff ); } /* MOV.W R0,@(disp4,Rn) */ -INLINE void MOVWS4(UINT32 d, UINT32 n) +INLINE void MOVWS4(SH4 *sh4, UINT32 d, UINT32 n) { UINT32 disp = d & 0x0f; - sh4.ea = sh4.r[n] + disp * 2; - WW( sh4.ea, sh4.r[0] & 0x0000ffff ); + sh4->ea = sh4->r[n] + disp * 2; + WW(sh4, sh4->ea, sh4->r[0] & 0x0000ffff ); } /* MOV.L Rm,@(disp4,Rn) */ -INLINE void MOVLS4(UINT32 m, UINT32 d, UINT32 n) +INLINE void MOVLS4(SH4 *sh4, UINT32 m, UINT32 d, UINT32 n) { UINT32 disp = d & 0x0f; - sh4.ea = sh4.r[n] + disp * 4; - WL( sh4.ea, sh4.r[m] ); + sh4->ea = sh4->r[n] + disp * 4; + WL(sh4, sh4->ea, sh4->r[m] ); } /* MOV.B @(disp4,Rm),R0 */ -INLINE void MOVBL4(UINT32 m, UINT32 d) +INLINE void MOVBL4(SH4 *sh4, UINT32 m, UINT32 d) { UINT32 disp = d & 0x0f; - sh4.ea = sh4.r[m] + disp; - sh4.r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh4.ea ); + sh4->ea = sh4->r[m] + disp; + sh4->r[0] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); } /* MOV.W @(disp4,Rm),R0 */ -INLINE void MOVWL4(UINT32 m, UINT32 d) +INLINE void MOVWL4(SH4 *sh4, UINT32 m, UINT32 d) { UINT32 disp = d & 0x0f; - sh4.ea = sh4.r[m] + disp * 2; - sh4.r[0] = (UINT32)(INT32)(INT16) RW( sh4.ea ); + sh4->ea = sh4->r[m] + disp * 2; + sh4->r[0] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); } /* MOV.L @(disp4,Rm),Rn */ -INLINE void MOVLL4(UINT32 m, UINT32 d, UINT32 n) +INLINE void MOVLL4(SH4 *sh4, UINT32 m, UINT32 d, UINT32 n) { UINT32 disp = d & 0x0f; - sh4.ea = sh4.r[m] + disp * 4; - sh4.r[n] = RL( sh4.ea ); + sh4->ea = sh4->r[m] + disp * 4; + sh4->r[n] = RL(sh4, sh4->ea ); } /* MOVA @(disp8,PC),R0 */ -INLINE void MOVA(UINT32 d) +INLINE void MOVA(SH4 *sh4, UINT32 d) { UINT32 disp = d & 0xff; - sh4.ea = ((sh4.pc + 2) & ~3) + disp * 4; - sh4.r[0] = sh4.ea; + sh4->ea = ((sh4->pc + 2) & ~3) + disp * 4; + sh4->r[0] = sh4->ea; } /* MOVT Rn */ -INLINE void MOVT(UINT32 n) +INLINE void MOVT(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.sr & T; + sh4->r[n] = sh4->sr & T; } /* MUL.L Rm,Rn */ -INLINE void MULL(UINT32 m, UINT32 n) +INLINE void MULL(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.macl = sh4.r[n] * sh4.r[m]; - sh4.sh4_icount--; + sh4->macl = sh4->r[n] * sh4->r[m]; + sh4->sh4_icount--; } /* MULS Rm,Rn */ -INLINE void MULS(UINT32 m, UINT32 n) +INLINE void MULS(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.macl = (INT16) sh4.r[n] * (INT16) sh4.r[m]; + sh4->macl = (INT16) sh4->r[n] * (INT16) sh4->r[m]; } /* MULU Rm,Rn */ -INLINE void MULU(UINT32 m, UINT32 n) +INLINE void MULU(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.macl = (UINT16) sh4.r[n] * (UINT16) sh4.r[m]; + sh4->macl = (UINT16) sh4->r[n] * (UINT16) sh4->r[m]; } /* NEG Rm,Rn */ -INLINE void NEG(UINT32 m, UINT32 n) +INLINE void NEG(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = 0 - sh4.r[m]; + sh4->r[n] = 0 - sh4->r[m]; } /* NEGC Rm,Rn */ -INLINE void NEGC(UINT32 m, UINT32 n) +INLINE void NEGC(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 temp; - temp = sh4.r[m]; - sh4.r[n] = -temp - (sh4.sr & T); - if (temp || (sh4.sr & T)) - sh4.sr |= T; + temp = sh4->r[m]; + sh4->r[n] = -temp - (sh4->sr & T); + if (temp || (sh4->sr & T)) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* NOP */ -INLINE void NOP(void) +INLINE void NOP(SH4 *sh4) { } /* NOT Rm,Rn */ -INLINE void NOT(UINT32 m, UINT32 n) +INLINE void NOT(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = ~sh4.r[m]; + sh4->r[n] = ~sh4->r[m]; } /* OR Rm,Rn */ -INLINE void OR(UINT32 m, UINT32 n) +INLINE void OR(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] |= sh4.r[m]; + sh4->r[n] |= sh4->r[m]; } /* OR #imm,R0 */ -INLINE void ORI(UINT32 i) +INLINE void ORI(SH4 *sh4, UINT32 i) { - sh4.r[0] |= i; - sh4.sh4_icount -= 2; + sh4->r[0] |= i; + sh4->sh4_icount -= 2; } /* OR.B #imm,@(R0,GBR) */ -INLINE void ORM(UINT32 i) +INLINE void ORM(SH4 *sh4, UINT32 i) { UINT32 temp; - sh4.ea = sh4.gbr + sh4.r[0]; - temp = RB( sh4.ea ); + sh4->ea = sh4->gbr + sh4->r[0]; + temp = RB(sh4, sh4->ea ); temp |= i; - WB( sh4.ea, temp ); + WB(sh4, sh4->ea, temp ); } /* ROTCL Rn */ -INLINE void ROTCL(UINT32 n) +INLINE void ROTCL(SH4 *sh4, UINT32 n) { UINT32 temp; - temp = (sh4.r[n] >> 31) & T; - sh4.r[n] = (sh4.r[n] << 1) | (sh4.sr & T); - sh4.sr = (sh4.sr & ~T) | temp; + temp = (sh4->r[n] >> 31) & T; + sh4->r[n] = (sh4->r[n] << 1) | (sh4->sr & T); + sh4->sr = (sh4->sr & ~T) | temp; } /* ROTCR Rn */ -INLINE void ROTCR(UINT32 n) +INLINE void ROTCR(SH4 *sh4, UINT32 n) { UINT32 temp; - temp = (sh4.sr & T) << 31; - if (sh4.r[n] & T) - sh4.sr |= T; + temp = (sh4->sr & T) << 31; + if (sh4->r[n] & T) + sh4->sr |= T; else - sh4.sr &= ~T; - sh4.r[n] = (sh4.r[n] >> 1) | temp; + sh4->sr &= ~T; + sh4->r[n] = (sh4->r[n] >> 1) | temp; } /* ROTL Rn */ -INLINE void ROTL(UINT32 n) +INLINE void ROTL(SH4 *sh4, UINT32 n) { - sh4.sr = (sh4.sr & ~T) | ((sh4.r[n] >> 31) & T); - sh4.r[n] = (sh4.r[n] << 1) | (sh4.r[n] >> 31); + sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); + sh4->r[n] = (sh4->r[n] << 1) | (sh4->r[n] >> 31); } /* ROTR Rn */ -INLINE void ROTR(UINT32 n) +INLINE void ROTR(SH4 *sh4, UINT32 n) { - sh4.sr = (sh4.sr & ~T) | (sh4.r[n] & T); - sh4.r[n] = (sh4.r[n] >> 1) | (sh4.r[n] << 31); + sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); + sh4->r[n] = (sh4->r[n] >> 1) | (sh4->r[n] << 31); } /* RTE */ -INLINE void RTE(void) +INLINE void RTE(SH4 *sh4) { - sh4.delay = sh4.pc; - sh4.pc = sh4.ea = sh4.spc; + sh4->delay = sh4->pc; + sh4->pc = sh4->ea = sh4->spc; if ((Machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank((sh4.sr & sRB) >> 29); - if ((sh4.ssr & sRB) != (sh4.sr & sRB)) - sh4_change_register_bank(sh4.ssr & sRB ? 1 : 0); - sh4.sr = sh4.ssr; - sh4.sh4_icount--; - sh4_exception_recompute(); + sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); + if ((sh4->ssr & sRB) != (sh4->sr & sRB)) + sh4_change_register_bank(sh4, sh4->ssr & sRB ? 1 : 0); + sh4->sr = sh4->ssr; + sh4->sh4_icount--; + sh4_exception_recompute(sh4); } /* RTS */ -INLINE void RTS(void) +INLINE void RTS(SH4 *sh4) { - sh4.delay = sh4.pc; - sh4.pc = sh4.ea = sh4.pr; - sh4.sh4_icount--; + sh4->delay = sh4->pc; + sh4->pc = sh4->ea = sh4->pr; + sh4->sh4_icount--; } /* SETT */ -INLINE void SETT(void) +INLINE void SETT(SH4 *sh4) { - sh4.sr |= T; + sh4->sr |= T; } /* SHAL Rn (same as SHLL) */ -INLINE void SHAL(UINT32 n) +INLINE void SHAL(SH4 *sh4, UINT32 n) { - sh4.sr = (sh4.sr & ~T) | ((sh4.r[n] >> 31) & T); - sh4.r[n] <<= 1; + sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); + sh4->r[n] <<= 1; } /* SHAR Rn */ -INLINE void SHAR(UINT32 n) +INLINE void SHAR(SH4 *sh4, UINT32 n) { - sh4.sr = (sh4.sr & ~T) | (sh4.r[n] & T); - sh4.r[n] = (UINT32)((INT32)sh4.r[n] >> 1); + sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); + sh4->r[n] = (UINT32)((INT32)sh4->r[n] >> 1); } /* SHLL Rn (same as SHAL) */ -INLINE void SHLL(UINT32 n) +INLINE void SHLL(SH4 *sh4, UINT32 n) { - sh4.sr = (sh4.sr & ~T) | ((sh4.r[n] >> 31) & T); - sh4.r[n] <<= 1; + sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); + sh4->r[n] <<= 1; } /* SHLL2 Rn */ -INLINE void SHLL2(UINT32 n) +INLINE void SHLL2(SH4 *sh4, UINT32 n) { - sh4.r[n] <<= 2; + sh4->r[n] <<= 2; } /* SHLL8 Rn */ -INLINE void SHLL8(UINT32 n) +INLINE void SHLL8(SH4 *sh4, UINT32 n) { - sh4.r[n] <<= 8; + sh4->r[n] <<= 8; } /* SHLL16 Rn */ -INLINE void SHLL16(UINT32 n) +INLINE void SHLL16(SH4 *sh4, UINT32 n) { - sh4.r[n] <<= 16; + sh4->r[n] <<= 16; } /* SHLR Rn */ -INLINE void SHLR(UINT32 n) +INLINE void SHLR(SH4 *sh4, UINT32 n) { - sh4.sr = (sh4.sr & ~T) | (sh4.r[n] & T); - sh4.r[n] >>= 1; + sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); + sh4->r[n] >>= 1; } /* SHLR2 Rn */ -INLINE void SHLR2(UINT32 n) +INLINE void SHLR2(SH4 *sh4, UINT32 n) { - sh4.r[n] >>= 2; + sh4->r[n] >>= 2; } /* SHLR8 Rn */ -INLINE void SHLR8(UINT32 n) +INLINE void SHLR8(SH4 *sh4, UINT32 n) { - sh4.r[n] >>= 8; + sh4->r[n] >>= 8; } /* SHLR16 Rn */ -INLINE void SHLR16(UINT32 n) +INLINE void SHLR16(SH4 *sh4, UINT32 n) { - sh4.r[n] >>= 16; + sh4->r[n] >>= 16; } /* SLEEP */ -INLINE void SLEEP(void) +INLINE void SLEEP(SH4 *sh4) { - sh4.pc -= 2; - sh4.sh4_icount -= 2; + sh4->pc -= 2; + sh4->sh4_icount -= 2; /* Wait_for_exception; */ } /* STC SR,Rn */ -INLINE void STCSR(UINT32 n) +INLINE void STCSR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.sr; + sh4->r[n] = sh4->sr; } /* STC GBR,Rn */ -INLINE void STCGBR(UINT32 n) +INLINE void STCGBR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.gbr; + sh4->r[n] = sh4->gbr; } /* STC VBR,Rn */ -INLINE void STCVBR(UINT32 n) +INLINE void STCVBR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.vbr; + sh4->r[n] = sh4->vbr; } /* STC.L SR,@-Rn */ -INLINE void STCMSR(UINT32 n) +INLINE void STCMSR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.sr ); - sh4.sh4_icount--; + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->sr ); + sh4->sh4_icount--; } /* STC.L GBR,@-Rn */ -INLINE void STCMGBR(UINT32 n) +INLINE void STCMGBR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.gbr ); - sh4.sh4_icount--; + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->gbr ); + sh4->sh4_icount--; } /* STC.L VBR,@-Rn */ -INLINE void STCMVBR(UINT32 n) +INLINE void STCMVBR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.vbr ); - sh4.sh4_icount--; + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->vbr ); + sh4->sh4_icount--; } /* STS MACH,Rn */ -INLINE void STSMACH(UINT32 n) +INLINE void STSMACH(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.mach; + sh4->r[n] = sh4->mach; } /* STS MACL,Rn */ -INLINE void STSMACL(UINT32 n) +INLINE void STSMACL(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.macl; + sh4->r[n] = sh4->macl; } /* STS PR,Rn */ -INLINE void STSPR(UINT32 n) +INLINE void STSPR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.pr; + sh4->r[n] = sh4->pr; } /* STS.L MACH,@-Rn */ -INLINE void STSMMACH(UINT32 n) +INLINE void STSMMACH(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.mach ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->mach ); } /* STS.L MACL,@-Rn */ -INLINE void STSMMACL(UINT32 n) +INLINE void STSMMACL(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.macl ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->macl ); } /* STS.L PR,@-Rn */ -INLINE void STSMPR(UINT32 n) +INLINE void STSMPR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.pr ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->pr ); } /* SUB Rm,Rn */ -INLINE void SUB(UINT32 m, UINT32 n) +INLINE void SUB(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] -= sh4.r[m]; + sh4->r[n] -= sh4->r[m]; } /* SUBC Rm,Rn */ -INLINE void SUBC(UINT32 m, UINT32 n) +INLINE void SUBC(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 tmp0, tmp1; - tmp1 = sh4.r[n] - sh4.r[m]; - tmp0 = sh4.r[n]; - sh4.r[n] = tmp1 - (sh4.sr & T); + tmp1 = sh4->r[n] - sh4->r[m]; + tmp0 = sh4->r[n]; + sh4->r[n] = tmp1 - (sh4->sr & T); if (tmp0 < tmp1) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; - if (tmp1 < sh4.r[n]) - sh4.sr |= T; + sh4->sr &= ~T; + if (tmp1 < sh4->r[n]) + sh4->sr |= T; } /* SUBV Rm,Rn */ -INLINE void SUBV(UINT32 m, UINT32 n) +INLINE void SUBV(SH4 *sh4, UINT32 m, UINT32 n) { INT32 dest, src, ans; - if ((INT32) sh4.r[n] >= 0) + if ((INT32) sh4->r[n] >= 0) dest = 0; else dest = 1; - if ((INT32) sh4.r[m] >= 0) + if ((INT32) sh4->r[m] >= 0) src = 0; else src = 1; src += dest; - sh4.r[n] -= sh4.r[m]; - if ((INT32) sh4.r[n] >= 0) + sh4->r[n] -= sh4->r[m]; + if ((INT32) sh4->r[n] >= 0) ans = 0; else ans = 1; @@ -1675,412 +1675,412 @@ INLINE void SUBV(UINT32 m, UINT32 n) if (src == 1) { if (ans == 1) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* SWAP.B Rm,Rn */ -INLINE void SWAPB(UINT32 m, UINT32 n) +INLINE void SWAPB(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 temp0, temp1; - temp0 = sh4.r[m] & 0xffff0000; - temp1 = (sh4.r[m] & 0x000000ff) << 8; - sh4.r[n] = (sh4.r[m] >> 8) & 0x000000ff; - sh4.r[n] = sh4.r[n] | temp1 | temp0; + temp0 = sh4->r[m] & 0xffff0000; + temp1 = (sh4->r[m] & 0x000000ff) << 8; + sh4->r[n] = (sh4->r[m] >> 8) & 0x000000ff; + sh4->r[n] = sh4->r[n] | temp1 | temp0; } /* SWAP.W Rm,Rn */ -INLINE void SWAPW(UINT32 m, UINT32 n) +INLINE void SWAPW(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 temp; - temp = (sh4.r[m] >> 16) & 0x0000ffff; - sh4.r[n] = (sh4.r[m] << 16) | temp; + temp = (sh4->r[m] >> 16) & 0x0000ffff; + sh4->r[n] = (sh4->r[m] << 16) | temp; } /* TAS.B @Rn */ -INLINE void TAS(UINT32 n) +INLINE void TAS(SH4 *sh4, UINT32 n) { UINT32 temp; - sh4.ea = sh4.r[n]; + sh4->ea = sh4->r[n]; /* Bus Lock enable */ - temp = RB( sh4.ea ); + temp = RB(sh4, sh4->ea ); if (temp == 0) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; temp |= 0x80; /* Bus Lock disable */ - WB( sh4.ea, temp ); - sh4.sh4_icount -= 3; + WB(sh4, sh4->ea, temp ); + sh4->sh4_icount -= 3; } /* TRAPA #imm */ -INLINE void TRAPA(UINT32 i) +INLINE void TRAPA(SH4 *sh4, UINT32 i) { UINT32 imm = i & 0xff; - sh4.m[TRA] = imm; - sh4.ssr = sh4.sr; - sh4.spc = sh4.pc; - sh4.sgr = sh4.r[15]; + sh4->m[TRA] = imm; + sh4->ssr = sh4->sr; + sh4->spc = sh4->pc; + sh4->sgr = sh4->r[15]; - sh4.sr |= MD; + sh4->sr |= MD; if ((Machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank((sh4.sr & sRB) >> 29); - if (!(sh4.sr & sRB)) - sh4_change_register_bank(1); - sh4.sr |= sRB; - sh4.sr |= BL; - sh4_exception_recompute(); + sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); + if (!(sh4->sr & sRB)) + sh4_change_register_bank(sh4, 1); + sh4->sr |= sRB; + sh4->sr |= BL; + sh4_exception_recompute(sh4); - sh4.m[EXPEVT] = 0x00000160; - sh4.pc = sh4.vbr + 0x00000100; + sh4->m[EXPEVT] = 0x00000160; + sh4->pc = sh4->vbr + 0x00000100; - sh4.sh4_icount -= 7; + sh4->sh4_icount -= 7; } /* TST Rm,Rn */ -INLINE void TST(UINT32 m, UINT32 n) +INLINE void TST(SH4 *sh4, UINT32 m, UINT32 n) { - if ((sh4.r[n] & sh4.r[m]) == 0) - sh4.sr |= T; + if ((sh4->r[n] & sh4->r[m]) == 0) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* TST #imm,R0 */ -INLINE void TSTI(UINT32 i) +INLINE void TSTI(SH4 *sh4, UINT32 i) { UINT32 imm = i & 0xff; - if ((imm & sh4.r[0]) == 0) - sh4.sr |= T; + if ((imm & sh4->r[0]) == 0) + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } /* TST.B #imm,@(R0,GBR) */ -INLINE void TSTM(UINT32 i) +INLINE void TSTM(SH4 *sh4, UINT32 i) { UINT32 imm = i & 0xff; - sh4.ea = sh4.gbr + sh4.r[0]; - if ((imm & RB( sh4.ea )) == 0) - sh4.sr |= T; + sh4->ea = sh4->gbr + sh4->r[0]; + if ((imm & RB(sh4, sh4->ea )) == 0) + sh4->sr |= T; else - sh4.sr &= ~T; - sh4.sh4_icount -= 2; + sh4->sr &= ~T; + sh4->sh4_icount -= 2; } /* XOR Rm,Rn */ -INLINE void XOR(UINT32 m, UINT32 n) +INLINE void XOR(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] ^= sh4.r[m]; + sh4->r[n] ^= sh4->r[m]; } /* XOR #imm,R0 */ -INLINE void XORI(UINT32 i) +INLINE void XORI(SH4 *sh4, UINT32 i) { UINT32 imm = i & 0xff; - sh4.r[0] ^= imm; + sh4->r[0] ^= imm; } /* XOR.B #imm,@(R0,GBR) */ -INLINE void XORM(UINT32 i) +INLINE void XORM(SH4 *sh4, UINT32 i) { UINT32 imm = i & 0xff; UINT32 temp; - sh4.ea = sh4.gbr + sh4.r[0]; - temp = RB( sh4.ea ); + sh4->ea = sh4->gbr + sh4->r[0]; + temp = RB(sh4, sh4->ea ); temp ^= imm; - WB( sh4.ea, temp ); - sh4.sh4_icount -= 2; + WB(sh4, sh4->ea, temp ); + sh4->sh4_icount -= 2; } /* XTRCT Rm,Rn */ -INLINE void XTRCT(UINT32 m, UINT32 n) +INLINE void XTRCT(SH4 *sh4, UINT32 m, UINT32 n) { UINT32 temp; - temp = (sh4.r[m] << 16) & 0xffff0000; - sh4.r[n] = (sh4.r[n] >> 16) & 0x0000ffff; - sh4.r[n] |= temp; + temp = (sh4->r[m] << 16) & 0xffff0000; + sh4->r[n] = (sh4->r[n] >> 16) & 0x0000ffff; + sh4->r[n] |= temp; } /* STC SSR,Rn */ -INLINE void STCSSR(UINT32 n) +INLINE void STCSSR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.ssr; + sh4->r[n] = sh4->ssr; } /* STC SPC,Rn */ -INLINE void STCSPC(UINT32 n) +INLINE void STCSPC(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.spc; + sh4->r[n] = sh4->spc; } /* STC SGR,Rn */ -INLINE void STCSGR(UINT32 n) +INLINE void STCSGR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.sgr; + sh4->r[n] = sh4->sgr; } /* STS FPUL,Rn */ -INLINE void STSFPUL(UINT32 n) +INLINE void STSFPUL(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.fpul; + sh4->r[n] = sh4->fpul; } /* STS FPSCR,Rn */ -INLINE void STSFPSCR(UINT32 n) +INLINE void STSFPSCR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.fpscr & 0x003FFFFF; + sh4->r[n] = sh4->fpscr & 0x003FFFFF; } /* STC DBR,Rn */ -INLINE void STCDBR(UINT32 n) +INLINE void STCDBR(SH4 *sh4, UINT32 n) { - sh4.r[n] = sh4.dbr; + sh4->r[n] = sh4->dbr; } /* STCRBANK Rm_BANK,Rn */ -INLINE void STCRBANK(UINT32 m, UINT32 n) +INLINE void STCRBANK(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] = sh4.rbnk[sh4.sr&sRB ? 0 : 1][m & 7]; + sh4->r[n] = sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7]; } /* STCMRBANK Rm_BANK,@-Rn */ -INLINE void STCMRBANK(UINT32 m, UINT32 n) +INLINE void STCMRBANK(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.rbnk[sh4.sr&sRB ? 0 : 1][m & 7]); - sh4.sh4_icount--; + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7]); + sh4->sh4_icount--; } /* MOVCA.L R0,@Rn */ -INLINE void MOVCAL(UINT32 n) +INLINE void MOVCAL(SH4 *sh4, UINT32 n) { - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.r[0] ); + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->r[0] ); } -INLINE void CLRS(void) +INLINE void CLRS(SH4 *sh4) { - sh4.sr &= ~S; + sh4->sr &= ~S; } -INLINE void SETS(void) +INLINE void SETS(SH4 *sh4) { - sh4.sr |= S; + sh4->sr |= S; } /* STS.L SGR,@-Rn */ -INLINE void STCMSGR(UINT32 n) +INLINE void STCMSGR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.sgr ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->sgr ); } /* STS.L FPUL,@-Rn */ -INLINE void STSMFPUL(UINT32 n) +INLINE void STSMFPUL(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.fpul ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->fpul ); } /* STS.L FPSCR,@-Rn */ -INLINE void STSMFPSCR(UINT32 n) +INLINE void STSMFPSCR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.fpscr & 0x003FFFFF); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->fpscr & 0x003FFFFF); } /* STC.L DBR,@-Rn */ -INLINE void STCMDBR(UINT32 n) +INLINE void STCMDBR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.dbr ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->dbr ); } /* STC.L SSR,@-Rn */ -INLINE void STCMSSR(UINT32 n) +INLINE void STCMSSR(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.ssr ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->ssr ); } /* STC.L SPC,@-Rn */ -INLINE void STCMSPC(UINT32 n) +INLINE void STCMSPC(SH4 *sh4, UINT32 n) { - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea, sh4.spc ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea, sh4->spc ); } /* LDS.L @Rm+,FPUL */ -INLINE void LDSMFPUL(UINT32 m) +INLINE void LDSMFPUL(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.fpul = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->fpul = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } /* LDS.L @Rm+,FPSCR */ -INLINE void LDSMFPSCR(UINT32 m) +INLINE void LDSMFPSCR(SH4 *sh4, UINT32 m) { UINT32 s; - s = sh4.fpscr; - sh4.ea = sh4.r[m]; - sh4.fpscr = RL( sh4.ea ); - sh4.fpscr &= 0x003FFFFF; - sh4.r[m] += 4; - if ((s & FR) != (sh4.fpscr & FR)) - sh4_swap_fp_registers(); + s = sh4->fpscr; + sh4->ea = sh4->r[m]; + sh4->fpscr = RL(sh4, sh4->ea ); + sh4->fpscr &= 0x003FFFFF; + sh4->r[m] += 4; + if ((s & FR) != (sh4->fpscr & FR)) + sh4_swap_fp_registers(sh4); #ifdef LSB_FIRST - if ((s & PR) != (sh4.fpscr & PR)) - sh4_swap_fp_couples(); + if ((s & PR) != (sh4->fpscr & PR)) + sh4_swap_fp_couples(sh4); #endif - sh4.fpu_sz = (sh4.fpscr & SZ) ? 1 : 0; - sh4.fpu_pr = (sh4.fpscr & PR) ? 1 : 0; + sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; + sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0; } /* LDC.L @Rm+,DBR */ -INLINE void LDCMDBR(UINT32 m) +INLINE void LDCMDBR(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.dbr = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->dbr = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } /* LDC.L @Rn+,Rm_BANK */ -INLINE void LDCMRBANK(UINT32 m, UINT32 n) +INLINE void LDCMRBANK(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.ea = sh4.r[n]; - sh4.rbnk[sh4.sr&sRB ? 0 : 1][m & 7] = RL( sh4.ea ); - sh4.r[n] += 4; + sh4->ea = sh4->r[n]; + sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = RL(sh4, sh4->ea ); + sh4->r[n] += 4; } /* LDC.L @Rm+,SSR */ -INLINE void LDCMSSR(UINT32 m) +INLINE void LDCMSSR(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.ssr = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->ssr = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } /* LDC.L @Rm+,SPC */ -INLINE void LDCMSPC(UINT32 m) +INLINE void LDCMSPC(SH4 *sh4, UINT32 m) { - sh4.ea = sh4.r[m]; - sh4.spc = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->spc = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } /* LDS Rm,FPUL */ -INLINE void LDSFPUL(UINT32 m) +INLINE void LDSFPUL(SH4 *sh4, UINT32 m) { - sh4.fpul = sh4.r[m]; + sh4->fpul = sh4->r[m]; } /* LDS Rm,FPSCR */ -INLINE void LDSFPSCR(UINT32 m) +INLINE void LDSFPSCR(SH4 *sh4, UINT32 m) { UINT32 s; - s = sh4.fpscr; - sh4.fpscr = sh4.r[m] & 0x003FFFFF; - if ((s & FR) != (sh4.fpscr & FR)) - sh4_swap_fp_registers(); + s = sh4->fpscr; + sh4->fpscr = sh4->r[m] & 0x003FFFFF; + if ((s & FR) != (sh4->fpscr & FR)) + sh4_swap_fp_registers(sh4); #ifdef LSB_FIRST - if ((s & PR) != (sh4.fpscr & PR)) - sh4_swap_fp_couples(); + if ((s & PR) != (sh4->fpscr & PR)) + sh4_swap_fp_couples(sh4); #endif - sh4.fpu_sz = (sh4.fpscr & SZ) ? 1 : 0; - sh4.fpu_pr = (sh4.fpscr & PR) ? 1 : 0; + sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; + sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0; } /* LDC Rm,DBR */ -INLINE void LDCDBR(UINT32 m) +INLINE void LDCDBR(SH4 *sh4, UINT32 m) { - sh4.dbr = sh4.r[m]; + sh4->dbr = sh4->r[m]; } /* SHAD Rm,Rn */ -INLINE void SHAD(UINT32 m,UINT32 n) +INLINE void SHAD(SH4 *sh4, UINT32 m,UINT32 n) { - if ((sh4.r[m] & 0x80000000) == 0) - sh4.r[n] = sh4.r[n] << (sh4.r[m] & 0x1F); - else if ((sh4.r[m] & 0x1F) == 0) { - if ((sh4.r[n] & 0x80000000) == 0) - sh4.r[n] = 0; + if ((sh4->r[m] & 0x80000000) == 0) + sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F); + else if ((sh4->r[m] & 0x1F) == 0) { + if ((sh4->r[n] & 0x80000000) == 0) + sh4->r[n] = 0; else - sh4.r[n] = 0xFFFFFFFF; + sh4->r[n] = 0xFFFFFFFF; } else - sh4.r[n]=(INT32)sh4.r[n] >> ((~sh4.r[m] & 0x1F)+1); + sh4->r[n]=(INT32)sh4->r[n] >> ((~sh4->r[m] & 0x1F)+1); } /* SHLD Rm,Rn */ -INLINE void SHLD(UINT32 m,UINT32 n) +INLINE void SHLD(SH4 *sh4, UINT32 m,UINT32 n) { - if ((sh4.r[m] & 0x80000000) == 0) - sh4.r[n] = sh4.r[n] << (sh4.r[m] & 0x1F); - else if ((sh4.r[m] & 0x1F) == 0) - sh4.r[n] = 0; + if ((sh4->r[m] & 0x80000000) == 0) + sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F); + else if ((sh4->r[m] & 0x1F) == 0) + sh4->r[n] = 0; else - sh4.r[n] = sh4.r[n] >> ((~sh4.r[m] & 0x1F)+1); + sh4->r[n] = sh4->r[n] >> ((~sh4->r[m] & 0x1F)+1); } /* LDCRBANK Rn,Rm_BANK */ -INLINE void LDCRBANK(UINT32 m, UINT32 n) +INLINE void LDCRBANK(SH4 *sh4, UINT32 m, UINT32 n) { - sh4.rbnk[sh4.sr&sRB ? 0 : 1][m & 7] = sh4.r[n]; + sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = sh4->r[n]; } /* LDC Rm,SSR */ -INLINE void LDCSSR(UINT32 m) +INLINE void LDCSSR(SH4 *sh4, UINT32 m) { - sh4.ssr = sh4.r[m]; + sh4->ssr = sh4->r[m]; } /* LDC Rm,SPC */ -INLINE void LDCSPC(UINT32 m) +INLINE void LDCSPC(SH4 *sh4, UINT32 m) { - sh4.spc = sh4.r[m]; + sh4->spc = sh4->r[m]; } /* PREF @Rn */ -INLINE void PREFM(UINT32 n) +INLINE void PREFM(SH4 *sh4, UINT32 n) { int a; UINT32 addr,dest,sq; - addr = sh4.r[n]; // address + addr = sh4->r[n]; // address if ((addr >= 0xE0000000) && (addr <= 0xE3FFFFFF)) { sq = (addr & 0x20) >> 5; dest = addr & 0x03FFFFE0; if (sq == 0) - dest |= (sh4.m[QACR0] & 0x1C) << 24; + dest |= (sh4->m[QACR0] & 0x1C) << 24; else - dest |= (sh4.m[QACR1] & 0x1C) << 24; + dest |= (sh4->m[QACR1] & 0x1C) << 24; addr = addr & 0xFFFFFFE0; for (a = 0;a < 4;a++) { - memory_write_qword_64le(sh4.program, dest, memory_read_qword_64le(sh4.program, addr)); + memory_write_qword_64le(sh4->program, dest, memory_read_qword_64le(sh4->program, addr)); addr += 8; dest += 8; } @@ -2090,7 +2090,7 @@ UINT32 addr,dest,sq; /***************************************************************************** * OPCODE DISPATCHERS *****************************************************************************/ -INLINE void op0000(UINT16 opcode) +INLINE void op0000(SH4 *sh4, UINT16 opcode) { switch (opcode & 0xF) { @@ -2099,170 +2099,170 @@ INLINE void op0000(UINT16 opcode) break; case 0x2: if (opcode & 0x80) { - STCRBANK(Rm, Rn); return; + STCRBANK(sh4, Rm, Rn); return; } switch (opcode & 0x70) { case 0x00: - STCSR(Rn); break; + STCSR(sh4, Rn); break; case 0x10: - STCGBR(Rn); break; + STCGBR(sh4, Rn); break; case 0x20: - STCVBR(Rn); break; + STCVBR(sh4, Rn); break; case 0x30: - STCSSR(Rn); break; + STCSSR(sh4, Rn); break; case 0x40: - STCSPC(Rn); break; + STCSPC(sh4, Rn); break; } break; case 0x3: switch (opcode & 0xF0) { case 0x00: - BSRF(Rn); break; + BSRF(sh4, Rn); break; case 0x20: - BRAF(Rn); break; + BRAF(sh4, Rn); break; case 0x80: - PREFM(Rn); break; + PREFM(sh4, Rn); break; case 0x90: - TODO(); break; + TODO(sh4); break; case 0xA0: - TODO(); break; + TODO(sh4); break; case 0xB0: - TODO(); break; + TODO(sh4); break; case 0xC0: - MOVCAL(Rn); break; + MOVCAL(sh4, Rn); break; } break; case 0x4: - MOVBS0(Rm, Rn); break; + MOVBS0(sh4, Rm, Rn); break; case 0x5: - MOVWS0(Rm, Rn); break; + MOVWS0(sh4, Rm, Rn); break; case 0x6: - MOVLS0(Rm, Rn); break; + MOVLS0(sh4, Rm, Rn); break; case 0x7: - MULL(Rm, Rn); break; + MULL(sh4, Rm, Rn); break; case 0x8: switch (opcode & 0x70) { case 0x00: - CLRT(); break; + CLRT(sh4); break; case 0x10: - SETT(); break; + SETT(sh4); break; case 0x20: - CLRMAC(); break; + CLRMAC(sh4); break; case 0x30: - TODO(); break; + TODO(sh4); break; case 0x40: - CLRS(); break; + CLRS(sh4); break; case 0x50: - SETS(); break; + SETS(sh4); break; } break; case 0x9: switch (opcode & 0x30) { case 0x00: - NOP(); break; + NOP(sh4); break; case 0x10: - DIV0U(); break; + DIV0U(sh4); break; case 0x20: - MOVT(Rn); break; + MOVT(sh4, Rn); break; } break; case 0xA: switch (opcode & 0x70) { case 0x00: - STSMACH(Rn); break; + STSMACH(sh4, Rn); break; case 0x10: - STSMACL(Rn); break; + STSMACL(sh4, Rn); break; case 0x20: - STSPR(Rn); break; + STSPR(sh4, Rn); break; case 0x30: - STCSGR(Rn); break; + STCSGR(sh4, Rn); break; case 0x50: - STSFPUL(Rn); break; + STSFPUL(sh4, Rn); break; case 0x60: - STSFPSCR(Rn); break; + STSFPSCR(sh4, Rn); break; case 0x70: - STCDBR(Rn); break; + STCDBR(sh4, Rn); break; } break; case 0xB: switch (opcode & 0x30) { case 0x00: - RTS(); break; + RTS(sh4); break; case 0x10: - SLEEP(); break; + SLEEP(sh4); break; case 0x20: - RTE(); break; + RTE(sh4); break; } break; case 0xC: - MOVBL0(Rm, Rn); break; + MOVBL0(sh4, Rm, Rn); break; case 0xD: - MOVWL0(Rm, Rn); break; + MOVWL0(sh4, Rm, Rn); break; case 0xE: - MOVLL0(Rm, Rn); break; + MOVLL0(sh4, Rm, Rn); break; case 0xF: - MAC_L(Rm, Rn); break; + MAC_L(sh4, Rm, Rn); break; } } -INLINE void op0001(UINT16 opcode) +INLINE void op0001(SH4 *sh4, UINT16 opcode) { - MOVLS4(Rm, opcode & 0x0f, Rn); + MOVLS4(sh4, Rm, opcode & 0x0f, Rn); } -INLINE void op0010(UINT16 opcode) +INLINE void op0010(SH4 *sh4, UINT16 opcode) { switch (opcode & 15) { - case 0: MOVBS(Rm, Rn); break; - case 1: MOVWS(Rm, Rn); break; - case 2: MOVLS(Rm, Rn); break; - case 3: NOP(); break; - case 4: MOVBM(Rm, Rn); break; - case 5: MOVWM(Rm, Rn); break; - case 6: MOVLM(Rm, Rn); break; - case 7: DIV0S(Rm, Rn); break; - case 8: TST(Rm, Rn); break; - case 9: AND(Rm, Rn); break; - case 10: XOR(Rm, Rn); break; - case 11: OR(Rm, Rn); break; - case 12: CMPSTR(Rm, Rn); break; - case 13: XTRCT(Rm, Rn); break; - case 14: MULU(Rm, Rn); break; - case 15: MULS(Rm, Rn); break; + case 0: MOVBS(sh4, Rm, Rn); break; + case 1: MOVWS(sh4, Rm, Rn); break; + case 2: MOVLS(sh4, Rm, Rn); break; + case 3: NOP(sh4); break; + case 4: MOVBM(sh4, Rm, Rn); break; + case 5: MOVWM(sh4, Rm, Rn); break; + case 6: MOVLM(sh4, Rm, Rn); break; + case 7: DIV0S(sh4, Rm, Rn); break; + case 8: TST(sh4, Rm, Rn); break; + case 9: AND(sh4, Rm, Rn); break; + case 10: XOR(sh4, Rm, Rn); break; + case 11: OR(sh4, Rm, Rn); break; + case 12: CMPSTR(sh4, Rm, Rn); break; + case 13: XTRCT(sh4, Rm, Rn); break; + case 14: MULU(sh4, Rm, Rn); break; + case 15: MULS(sh4, Rm, Rn); break; } } -INLINE void op0011(UINT16 opcode) +INLINE void op0011(SH4 *sh4, UINT16 opcode) { switch (opcode & 15) { - case 0: CMPEQ(Rm, Rn); break; - case 1: NOP(); break; - case 2: CMPHS(Rm, Rn); break; - case 3: CMPGE(Rm, Rn); break; - case 4: DIV1(Rm, Rn); break; - case 5: DMULU(Rm, Rn); break; - case 6: CMPHI(Rm, Rn); break; - case 7: CMPGT(Rm, Rn); break; - case 8: SUB(Rm, Rn); break; - case 9: NOP(); break; - case 10: SUBC(Rm, Rn); break; - case 11: SUBV(Rm, Rn); break; - case 12: ADD(Rm, Rn); break; - case 13: DMULS(Rm, Rn); break; - case 14: ADDC(Rm, Rn); break; - case 15: ADDV(Rm, Rn); break; + case 0: CMPEQ(sh4, Rm, Rn); break; + case 1: NOP(sh4); break; + case 2: CMPHS(sh4, Rm, Rn); break; + case 3: CMPGE(sh4, Rm, Rn); break; + case 4: DIV1(sh4, Rm, Rn); break; + case 5: DMULU(sh4, Rm, Rn); break; + case 6: CMPHI(sh4, Rm, Rn); break; + case 7: CMPGT(sh4, Rm, Rn); break; + case 8: SUB(sh4, Rm, Rn); break; + case 9: NOP(sh4); break; + case 10: SUBC(sh4, Rm, Rn); break; + case 11: SUBV(sh4, Rm, Rn); break; + case 12: ADD(sh4, Rm, Rn); break; + case 13: DMULS(sh4, Rm, Rn); break; + case 14: ADDC(sh4, Rm, Rn); break; + case 15: ADDV(sh4, Rm, Rn); break; } } -INLINE void op0100(UINT16 opcode) +INLINE void op0100(SH4 *sh4, UINT16 opcode) { switch (opcode & 0xF) { @@ -2270,335 +2270,335 @@ INLINE void op0100(UINT16 opcode) switch (opcode & 0x30) { case 0x00: - SHLL(Rn); break; + SHLL(sh4, Rn); break; case 0x10: - DT(Rn); break; + DT(sh4, Rn); break; case 0x20: - SHAL(Rn); break; + SHAL(sh4, Rn); break; } break; case 0x1: switch (opcode & 0x30) { case 0x00: - SHLR(Rn); break; + SHLR(sh4, Rn); break; case 0x10: - CMPPZ(Rn); break; + CMPPZ(sh4, Rn); break; case 0x20: - SHAR(Rn); break; + SHAR(sh4, Rn); break; } break; case 0x2: switch (opcode & 0xF0) { case 0x00: - STSMMACH(Rn); break; + STSMMACH(sh4, Rn); break; case 0x10: - STSMMACL(Rn); break; + STSMMACL(sh4, Rn); break; case 0x20: - STSMPR(Rn); break; + STSMPR(sh4, Rn); break; case 0x30: - STCMSGR(Rn); break; + STCMSGR(sh4, Rn); break; case 0x50: - STSMFPUL(Rn); break; + STSMFPUL(sh4, Rn); break; case 0x60: - STSMFPSCR(Rn); break; + STSMFPSCR(sh4, Rn); break; case 0xF0: - STCMDBR(Rn); break; + STCMDBR(sh4, Rn); break; } break; case 0x3: if (opcode & 0x80) { - STCMRBANK(Rm, Rn); return; + STCMRBANK(sh4, Rm, Rn); return; } switch (opcode & 0x70) { case 0x00: - STCMSR(Rn); break; + STCMSR(sh4, Rn); break; case 0x10: - STCMGBR(Rn); break; + STCMGBR(sh4, Rn); break; case 0x20: - STCMVBR(Rn); break; + STCMVBR(sh4, Rn); break; case 0x30: - STCMSSR(Rn); break; + STCMSSR(sh4, Rn); break; case 0x40: - STCMSPC(Rn); break; + STCMSPC(sh4, Rn); break; } break; case 0x4: switch (opcode & 0x30) { case 0x00: - ROTL(Rn); break; + ROTL(sh4, Rn); break; case 0x20: - ROTCL(Rn); break; + ROTCL(sh4, Rn); break; } break; case 0x5: switch (opcode & 0x30) { case 0x00: - ROTR(Rn); break; + ROTR(sh4, Rn); break; case 0x10: - CMPPL(Rn); break; + CMPPL(sh4, Rn); break; case 0x20: - ROTCR(Rn); break; + ROTCR(sh4, Rn); break; } break; case 0x6: switch (opcode & 0xF0) { case 0x00: - LDSMMACH(Rn); break; + LDSMMACH(sh4, Rn); break; case 0x10: - LDSMMACL(Rn); break; + LDSMMACL(sh4, Rn); break; case 0x20: - LDSMPR(Rn); break; + LDSMPR(sh4, Rn); break; case 0x50: - LDSMFPUL(Rn); break; + LDSMFPUL(sh4, Rn); break; case 0x60: - LDSMFPSCR(Rn); break; + LDSMFPSCR(sh4, Rn); break; case 0xF0: - LDCMDBR(Rn); break; + LDCMDBR(sh4, Rn); break; } break; case 0x7: if (opcode & 0x80) { - LDCMRBANK(Rm,Rn); return; + LDCMRBANK(sh4, Rm,Rn); return; } switch (opcode & 0x70) { case 0x00: - LDCMSR(Rn); break; + LDCMSR(sh4, Rn); break; case 0x10: - LDCMGBR(Rn); break; + LDCMGBR(sh4, Rn); break; case 0x20: - LDCMVBR(Rn); break; + LDCMVBR(sh4, Rn); break; case 0x30: - LDCMSSR(Rn); break; + LDCMSSR(sh4, Rn); break; case 0x40: - LDCMSPC(Rn); break; + LDCMSPC(sh4, Rn); break; } break; case 0x8: switch (opcode & 0x30) { case 0x00: - SHLL2(Rn); break; + SHLL2(sh4, Rn); break; case 0x10: - SHLL8(Rn); break; + SHLL8(sh4, Rn); break; case 0x20: - SHLL16(Rn); break; + SHLL16(sh4, Rn); break; } break; case 0x9: switch (opcode & 0x30) { case 0x00: - SHLR2(Rn); break; + SHLR2(sh4, Rn); break; case 0x10: - SHLR8(Rn); break; + SHLR8(sh4, Rn); break; case 0x20: - SHLR16(Rn); break; + SHLR16(sh4, Rn); break; } break; case 0xA: switch (opcode & 0xF0) { case 0x00: - LDSMACH(Rn); break; + LDSMACH(sh4, Rn); break; case 0x10: - LDSMACL(Rn); break; + LDSMACL(sh4, Rn); break; case 0x20: - LDSPR(Rn); break; + LDSPR(sh4, Rn); break; case 0x50: - LDSFPUL(Rn); break; + LDSFPUL(sh4, Rn); break; case 0x60: - LDSFPSCR(Rn); break; + LDSFPSCR(sh4, Rn); break; case 0xF0: - LDCDBR(Rn); break; + LDCDBR(sh4, Rn); break; } break; case 0xB: switch (opcode & 0x30) { case 0x00: - JSR(Rn); break; + JSR(sh4, Rn); break; case 0x10: - TAS(Rn); break; + TAS(sh4, Rn); break; case 0x20: - JMP(Rn); break; + JMP(sh4, Rn); break; } break; case 0xC: - SHAD(Rm,Rn); break; + SHAD(sh4, Rm,Rn); break; case 0xD: - SHLD(Rm,Rn); break; + SHLD(sh4, Rm,Rn); break; case 0xE: if (opcode & 0x80) { - LDCRBANK(Rm,Rn); return; + LDCRBANK(sh4, Rm,Rn); return; } switch (opcode & 0x70) { case 0x00: - LDCSR(Rn); break; + LDCSR(sh4, Rn); break; case 0x10: - LDCGBR(Rn); break; + LDCGBR(sh4, Rn); break; case 0x20: - LDCVBR(Rn); break; + LDCVBR(sh4, Rn); break; case 0x30: - LDCSSR(Rn); break; + LDCSSR(sh4, Rn); break; case 0x40: - LDCSPC(Rn); break; + LDCSPC(sh4, Rn); break; } break; case 0xF: - MAC_W(Rm, Rn); break; + MAC_W(sh4, Rm, Rn); break; } } -INLINE void op0101(UINT16 opcode) +INLINE void op0101(SH4 *sh4, UINT16 opcode) { - MOVLL4(Rm, opcode & 0x0f, Rn); + MOVLL4(sh4, Rm, opcode & 0x0f, Rn); } -INLINE void op0110(UINT16 opcode) +INLINE void op0110(SH4 *sh4, UINT16 opcode) { switch (opcode & 15) { - case 0: MOVBL(Rm, Rn); break; - case 1: MOVWL(Rm, Rn); break; - case 2: MOVLL(Rm, Rn); break; - case 3: MOV(Rm, Rn); break; - case 4: MOVBP(Rm, Rn); break; - case 5: MOVWP(Rm, Rn); break; - case 6: MOVLP(Rm, Rn); break; - case 7: NOT(Rm, Rn); break; - case 8: SWAPB(Rm, Rn); break; - case 9: SWAPW(Rm, Rn); break; - case 10: NEGC(Rm, Rn); break; - case 11: NEG(Rm, Rn); break; - case 12: EXTUB(Rm, Rn); break; - case 13: EXTUW(Rm, Rn); break; - case 14: EXTSB(Rm, Rn); break; - case 15: EXTSW(Rm, Rn); break; + case 0: MOVBL(sh4, Rm, Rn); break; + case 1: MOVWL(sh4, Rm, Rn); break; + case 2: MOVLL(sh4, Rm, Rn); break; + case 3: MOV(sh4, Rm, Rn); break; + case 4: MOVBP(sh4, Rm, Rn); break; + case 5: MOVWP(sh4, Rm, Rn); break; + case 6: MOVLP(sh4, Rm, Rn); break; + case 7: NOT(sh4, Rm, Rn); break; + case 8: SWAPB(sh4, Rm, Rn); break; + case 9: SWAPW(sh4, Rm, Rn); break; + case 10: NEGC(sh4, Rm, Rn); break; + case 11: NEG(sh4, Rm, Rn); break; + case 12: EXTUB(sh4, Rm, Rn); break; + case 13: EXTUW(sh4, Rm, Rn); break; + case 14: EXTSB(sh4, Rm, Rn); break; + case 15: EXTSW(sh4, Rm, Rn); break; } } -INLINE void op0111(UINT16 opcode) +INLINE void op0111(SH4 *sh4, UINT16 opcode) { - ADDI(opcode & 0xff, Rn); + ADDI(sh4, opcode & 0xff, Rn); } -INLINE void op1000(UINT16 opcode) +INLINE void op1000(SH4 *sh4, UINT16 opcode) { switch ( opcode & (15<<8) ) { - case 0 << 8: MOVBS4(opcode & 0x0f, Rm); break; - case 1 << 8: MOVWS4(opcode & 0x0f, Rm); break; - case 2<< 8: NOP(); break; - case 3<< 8: NOP(); break; - case 4<< 8: MOVBL4(Rm, opcode & 0x0f); break; - case 5<< 8: MOVWL4(Rm, opcode & 0x0f); break; - case 6<< 8: NOP(); break; - case 7<< 8: NOP(); break; - case 8<< 8: CMPIM(opcode & 0xff); break; - case 9<< 8: BT(opcode & 0xff); break; - case 10<< 8: NOP(); break; - case 11<< 8: BF(opcode & 0xff); break; - case 12<< 8: NOP(); break; - case 13<< 8: BTS(opcode & 0xff); break; - case 14<< 8: NOP(); break; - case 15<< 8: BFS(opcode & 0xff); break; + case 0 << 8: MOVBS4(sh4, opcode & 0x0f, Rm); break; + case 1 << 8: MOVWS4(sh4, opcode & 0x0f, Rm); break; + case 2<< 8: NOP(sh4); break; + case 3<< 8: NOP(sh4); break; + case 4<< 8: MOVBL4(sh4, Rm, opcode & 0x0f); break; + case 5<< 8: MOVWL4(sh4, Rm, opcode & 0x0f); break; + case 6<< 8: NOP(sh4); break; + case 7<< 8: NOP(sh4); break; + case 8<< 8: CMPIM(sh4, opcode & 0xff); break; + case 9<< 8: BT(sh4, opcode & 0xff); break; + case 10<< 8: NOP(sh4); break; + case 11<< 8: BF(sh4, opcode & 0xff); break; + case 12<< 8: NOP(sh4); break; + case 13<< 8: BTS(sh4, opcode & 0xff); break; + case 14<< 8: NOP(sh4); break; + case 15<< 8: BFS(sh4, opcode & 0xff); break; } } -INLINE void op1001(UINT16 opcode) +INLINE void op1001(SH4 *sh4, UINT16 opcode) { - MOVWI(opcode & 0xff, Rn); + MOVWI(sh4, opcode & 0xff, Rn); } -INLINE void op1010(UINT16 opcode) +INLINE void op1010(SH4 *sh4, UINT16 opcode) { - BRA(opcode & 0xfff); + BRA(sh4, opcode & 0xfff); } -INLINE void op1011(UINT16 opcode) +INLINE void op1011(SH4 *sh4, UINT16 opcode) { - BSR(opcode & 0xfff); + BSR(sh4, opcode & 0xfff); } -INLINE void op1100(UINT16 opcode) +INLINE void op1100(SH4 *sh4, UINT16 opcode) { switch (opcode & (15<<8)) { - case 0<<8: MOVBSG(opcode & 0xff); break; - case 1<<8: MOVWSG(opcode & 0xff); break; - case 2<<8: MOVLSG(opcode & 0xff); break; - case 3<<8: TRAPA(opcode & 0xff); break; - case 4<<8: MOVBLG(opcode & 0xff); break; - case 5<<8: MOVWLG(opcode & 0xff); break; - case 6<<8: MOVLLG(opcode & 0xff); break; - case 7<<8: MOVA(opcode & 0xff); break; - case 8<<8: TSTI(opcode & 0xff); break; - case 9<<8: ANDI(opcode & 0xff); break; - case 10<<8: XORI(opcode & 0xff); break; - case 11<<8: ORI(opcode & 0xff); break; - case 12<<8: TSTM(opcode & 0xff); break; - case 13<<8: ANDM(opcode & 0xff); break; - case 14<<8: XORM(opcode & 0xff); break; - case 15<<8: ORM(opcode & 0xff); break; + case 0<<8: MOVBSG(sh4, opcode & 0xff); break; + case 1<<8: MOVWSG(sh4, opcode & 0xff); break; + case 2<<8: MOVLSG(sh4, opcode & 0xff); break; + case 3<<8: TRAPA(sh4, opcode & 0xff); break; + case 4<<8: MOVBLG(sh4, opcode & 0xff); break; + case 5<<8: MOVWLG(sh4, opcode & 0xff); break; + case 6<<8: MOVLLG(sh4, opcode & 0xff); break; + case 7<<8: MOVA(sh4, opcode & 0xff); break; + case 8<<8: TSTI(sh4, opcode & 0xff); break; + case 9<<8: ANDI(sh4, opcode & 0xff); break; + case 10<<8: XORI(sh4, opcode & 0xff); break; + case 11<<8: ORI(sh4, opcode & 0xff); break; + case 12<<8: TSTM(sh4, opcode & 0xff); break; + case 13<<8: ANDM(sh4, opcode & 0xff); break; + case 14<<8: XORM(sh4, opcode & 0xff); break; + case 15<<8: ORM(sh4, opcode & 0xff); break; } } -INLINE void op1101(UINT16 opcode) +INLINE void op1101(SH4 *sh4, UINT16 opcode) { - MOVLI(opcode & 0xff, Rn); + MOVLI(sh4, opcode & 0xff, Rn); } -INLINE void op1110(UINT16 opcode) +INLINE void op1110(SH4 *sh4, UINT16 opcode) { - MOVI(opcode & 0xff, Rn); + MOVI(sh4, opcode & 0xff, Rn); } /* FMOV.S @Rm+,FRn PR=0 SZ=0 1111nnnnmmmm1001 */ /* FMOV @Rm+,DRn PR=0 SZ=1 1111nnn0mmmm1001 */ /* FMOV @Rm+,XDn PR=0 SZ=1 1111nnn1mmmm1001 */ /* FMOV @Rm+,XDn PR=1 1111nnn1mmmm1001 */ -INLINE void FMOVMRIFR(UINT32 m,UINT32 n) +INLINE void FMOVMRIFR(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; - sh4.ea = sh4.r[m]; - sh4.r[m] += 8; + sh4->ea = sh4->r[m]; + sh4->r[m] += 8; #ifdef LSB_FIRST - sh4.xf[n+1] = RL( sh4.ea ); - sh4.xf[n] = RL( sh4.ea+4 ); + sh4->xf[n+1] = RL(sh4, sh4->ea ); + sh4->xf[n] = RL(sh4, sh4->ea+4 ); #else - sh4.xf[n] = RL( sh4.ea ); - sh4.xf[n+1] = RL( sh4.ea+4 ); + sh4->xf[n] = RL(sh4, sh4->ea ); + sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); #endif } else { /* PR = 0 */ - if (sh4.fpu_sz) { /* SZ = 1 */ + if (sh4->fpu_sz) { /* SZ = 1 */ if (n & 1) { n = n & 14; - sh4.ea = sh4.r[m]; - sh4.xf[n] = RL( sh4.ea ); - sh4.r[m] += 4; - sh4.xf[n+1] = RL( sh4.ea+4 ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->xf[n] = RL(sh4, sh4->ea ); + sh4->r[m] += 4; + sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); + sh4->r[m] += 4; } else { - sh4.ea = sh4.r[m]; - sh4.fr[n] = RL( sh4.ea ); - sh4.r[m] += 4; - sh4.fr[n+1] = RL( sh4.ea+4 ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->fr[n] = RL(sh4, sh4->ea ); + sh4->r[m] += 4; + sh4->fr[n+1] = RL(sh4, sh4->ea+4 ); + sh4->r[m] += 4; } } else { /* SZ = 0 */ - sh4.ea = sh4.r[m]; - sh4.fr[n] = RL( sh4.ea ); - sh4.r[m] += 4; + sh4->ea = sh4->r[m]; + sh4->fr[n] = RL(sh4, sh4->ea ); + sh4->r[m] += 4; } } } @@ -2607,33 +2607,33 @@ INLINE void FMOVMRIFR(UINT32 m,UINT32 n) /* FMOV DRm,@Rn PR=0 SZ=1 1111nnnnmmm01010 */ /* FMOV XDm,@Rn PR=0 SZ=1 1111nnnnmmm11010 */ /* FMOV XDm,@Rn PR=1 1111nnnnmmm11010 */ -INLINE void FMOVFRMR(UINT32 m,UINT32 n) +INLINE void FMOVFRMR(SH4 *sh4,UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ m= m & 14; - sh4.ea = sh4.r[n]; + sh4->ea = sh4->r[n]; #ifdef LSB_FIRST - WL( sh4.ea,sh4.xf[m+1] ); - WL( sh4.ea+4,sh4.xf[m] ); + WL(sh4, sh4->ea,sh4->xf[m+1] ); + WL(sh4, sh4->ea+4,sh4->xf[m] ); #else - WL( sh4.ea,sh4.xf[m] ); - WL( sh4.ea+4,sh4.xf[m+1] ); + WL(sh4, sh4->ea,sh4->xf[m] ); + WL(sh4, sh4->ea+4,sh4->xf[m+1] ); #endif } else { /* PR = 0 */ - if (sh4.fpu_sz) { /* SZ = 1 */ + if (sh4->fpu_sz) { /* SZ = 1 */ if (m & 1) { m= m & 14; - sh4.ea = sh4.r[n]; - WL( sh4.ea,sh4.xf[m] ); - WL( sh4.ea+4,sh4.xf[m+1] ); + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea,sh4->xf[m] ); + WL(sh4, sh4->ea+4,sh4->xf[m+1] ); } else { - sh4.ea = sh4.r[n]; - WL( sh4.ea,sh4.fr[m] ); - WL( sh4.ea+4,sh4.fr[m+1] ); + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea,sh4->fr[m] ); + WL(sh4, sh4->ea+4,sh4->fr[m+1] ); } } else { /* SZ = 0 */ - sh4.ea = sh4.r[n]; - WL( sh4.ea,sh4.fr[m] ); + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea,sh4->fr[m] ); } } } @@ -2642,37 +2642,37 @@ INLINE void FMOVFRMR(UINT32 m,UINT32 n) /* FMOV DRm,@-Rn PR=0 SZ=1 1111nnnnmmm01011 */ /* FMOV XDm,@-Rn PR=0 SZ=1 1111nnnnmmm11011 */ /* FMOV XDm,@-Rn PR=1 1111nnnnmmm11011 */ -INLINE void FMOVFRMDR(UINT32 m,UINT32 n) +INLINE void FMOVFRMDR(SH4 *sh4,UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ m= m & 14; - sh4.r[n] -= 8; - sh4.ea = sh4.r[n]; + sh4->r[n] -= 8; + sh4->ea = sh4->r[n]; #ifdef LSB_FIRST - WL( sh4.ea,sh4.xf[m+1] ); - WL( sh4.ea+4,sh4.xf[m] ); + WL(sh4, sh4->ea,sh4->xf[m+1] ); + WL(sh4, sh4->ea+4,sh4->xf[m] ); #else - WL( sh4.ea,sh4.xf[m] ); - WL( sh4.ea+4,sh4.xf[m+1] ); + WL(sh4, sh4->ea,sh4->xf[m] ); + WL(sh4, sh4->ea+4,sh4->xf[m+1] ); #endif } else { /* PR = 0 */ - if (sh4.fpu_sz) { /* SZ = 1 */ + if (sh4->fpu_sz) { /* SZ = 1 */ if (m & 1) { m= m & 14; - sh4.r[n] -= 8; - sh4.ea = sh4.r[n]; - WL( sh4.ea,sh4.xf[m] ); - WL( sh4.ea+4,sh4.xf[m+1] ); + sh4->r[n] -= 8; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea,sh4->xf[m] ); + WL(sh4, sh4->ea+4,sh4->xf[m+1] ); } else { - sh4.r[n] -= 8; - sh4.ea = sh4.r[n]; - WL( sh4.ea,sh4.fr[m] ); - WL( sh4.ea+4,sh4.fr[m+1] ); + sh4->r[n] -= 8; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea,sh4->fr[m] ); + WL(sh4, sh4->ea+4,sh4->fr[m+1] ); } } else { /* SZ = 0 */ - sh4.r[n] -= 4; - sh4.ea = sh4.r[n]; - WL( sh4.ea,sh4.fr[m] ); + sh4->r[n] -= 4; + sh4->ea = sh4->r[n]; + WL(sh4, sh4->ea,sh4->fr[m] ); } } } @@ -2681,33 +2681,33 @@ INLINE void FMOVFRMDR(UINT32 m,UINT32 n) /* FMOV DRm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm00111 */ /* FMOV XDm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm10111 */ /* FMOV XDm,@(R0,Rn) PR=1 1111nnnnmmm10111 */ -INLINE void FMOVFRS0(UINT32 m,UINT32 n) +INLINE void FMOVFRS0(SH4 *sh4,UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ m= m & 14; - sh4.ea = sh4.r[0] + sh4.r[n]; + sh4->ea = sh4->r[0] + sh4->r[n]; #ifdef LSB_FIRST - WL( sh4.ea,sh4.xf[m+1] ); - WL( sh4.ea+4,sh4.xf[m] ); + WL(sh4, sh4->ea,sh4->xf[m+1] ); + WL(sh4, sh4->ea+4,sh4->xf[m] ); #else - WL( sh4.ea,sh4.xf[m] ); - WL( sh4.ea+4,sh4.xf[m+1] ); + WL(sh4, sh4->ea,sh4->xf[m] ); + WL(sh4, sh4->ea+4,sh4->xf[m+1] ); #endif } else { /* PR = 0 */ - if (sh4.fpu_sz) { /* SZ = 1 */ + if (sh4->fpu_sz) { /* SZ = 1 */ if (m & 1) { m= m & 14; - sh4.ea = sh4.r[0] + sh4.r[n]; - WL( sh4.ea,sh4.xf[m] ); - WL( sh4.ea+4,sh4.xf[m+1] ); + sh4->ea = sh4->r[0] + sh4->r[n]; + WL(sh4, sh4->ea,sh4->xf[m] ); + WL(sh4, sh4->ea+4,sh4->xf[m+1] ); } else { - sh4.ea = sh4.r[0] + sh4.r[n]; - WL( sh4.ea,sh4.fr[m] ); - WL( sh4.ea+4,sh4.fr[m+1] ); + sh4->ea = sh4->r[0] + sh4->r[n]; + WL(sh4, sh4->ea,sh4->fr[m] ); + WL(sh4, sh4->ea+4,sh4->fr[m+1] ); } } else { /* SZ = 0 */ - sh4.ea = sh4.r[0] + sh4.r[n]; - WL( sh4.ea,sh4.fr[m] ); + sh4->ea = sh4->r[0] + sh4->r[n]; + WL(sh4, sh4->ea,sh4->fr[m] ); } } } @@ -2716,33 +2716,33 @@ INLINE void FMOVFRS0(UINT32 m,UINT32 n) /* FMOV @(R0,Rm),DRn PR=0 SZ=1 1111nnn0mmmm0110 */ /* FMOV @(R0,Rm),XDn PR=0 SZ=1 1111nnn1mmmm0110 */ /* FMOV @(R0,Rm),XDn PR=1 1111nnn1mmmm0110 */ -INLINE void FMOVS0FR(UINT32 m,UINT32 n) +INLINE void FMOVS0FR(SH4 *sh4,UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n= n & 14; - sh4.ea = sh4.r[0] + sh4.r[m]; + sh4->ea = sh4->r[0] + sh4->r[m]; #ifdef LSB_FIRST - sh4.xf[n+1] = RL( sh4.ea ); - sh4.xf[n] = RL( sh4.ea+4 ); + sh4->xf[n+1] = RL(sh4, sh4->ea ); + sh4->xf[n] = RL(sh4, sh4->ea+4 ); #else - sh4.xf[n] = RL( sh4.ea ); - sh4.xf[n+1] = RL( sh4.ea+4 ); + sh4->xf[n] = RL(sh4, sh4->ea ); + sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); #endif } else { /* PR = 0 */ - if (sh4.fpu_sz) { /* SZ = 1 */ + if (sh4->fpu_sz) { /* SZ = 1 */ if (n & 1) { n= n & 14; - sh4.ea = sh4.r[0] + sh4.r[m]; - sh4.xf[n] = RL( sh4.ea ); - sh4.xf[n+1] = RL( sh4.ea+4 ); + sh4->ea = sh4->r[0] + sh4->r[m]; + sh4->xf[n] = RL(sh4, sh4->ea ); + sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); } else { - sh4.ea = sh4.r[0] + sh4.r[m]; - sh4.fr[n] = RL( sh4.ea ); - sh4.fr[n+1] = RL( sh4.ea+4 ); + sh4->ea = sh4->r[0] + sh4->r[m]; + sh4->fr[n] = RL(sh4, sh4->ea ); + sh4->fr[n+1] = RL(sh4, sh4->ea+4 ); } } else { /* SZ = 0 */ - sh4.ea = sh4.r[0] + sh4.r[m]; - sh4.fr[n] = RL( sh4.ea ); + sh4->ea = sh4->r[0] + sh4->r[m]; + sh4->fr[n] = RL(sh4, sh4->ea ); } } } @@ -2752,46 +2752,46 @@ INLINE void FMOVS0FR(UINT32 m,UINT32 n) /* FMOV @Rm,XDn PR=0 SZ=1 1111nnn1mmmm1000 */ /* FMOV @Rm,XDn PR=1 1111nnn1mmmm1000 */ /* FMOV @Rm,DRn PR=1 1111nnn0mmmm1000 */ -INLINE void FMOVMRFR(UINT32 m,UINT32 n) +INLINE void FMOVMRFR(SH4 *sh4,UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ if (n & 1) { n= n & 14; - sh4.ea = sh4.r[m]; + sh4->ea = sh4->r[m]; #ifdef LSB_FIRST - sh4.xf[n+1] = RL( sh4.ea ); - sh4.xf[n] = RL( sh4.ea+4 ); + sh4->xf[n+1] = RL(sh4, sh4->ea ); + sh4->xf[n] = RL(sh4, sh4->ea+4 ); #else - sh4.xf[n] = RL( sh4.ea ); - sh4.xf[n+1] = RL( sh4.ea+4 ); + sh4->xf[n] = RL(sh4, sh4->ea ); + sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); #endif } else { n= n & 14; - sh4.ea = sh4.r[m]; + sh4->ea = sh4->r[m]; #ifdef LSB_FIRST - sh4.fr[n+1] = RL( sh4.ea ); - sh4.fr[n] = RL( sh4.ea+4 ); + sh4->fr[n+1] = RL(sh4, sh4->ea ); + sh4->fr[n] = RL(sh4, sh4->ea+4 ); #else - sh4.fr[n] = RL( sh4.ea ); - sh4.fr[n+1] = RL( sh4.ea+4 ); + sh4->fr[n] = RL(sh4, sh4->ea ); + sh4->fr[n+1] = RL(sh4, sh4->ea+4 ); #endif } } else { /* PR = 0 */ - if (sh4.fpu_sz) { /* SZ = 1 */ + if (sh4->fpu_sz) { /* SZ = 1 */ if (n & 1) { n= n & 14; - sh4.ea = sh4.r[m]; - sh4.xf[n] = RL( sh4.ea ); - sh4.xf[n+1] = RL( sh4.ea+4 ); + sh4->ea = sh4->r[m]; + sh4->xf[n] = RL(sh4, sh4->ea ); + sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); } else { n= n & 14; - sh4.ea = sh4.r[m]; - sh4.fr[n] = RL( sh4.ea ); - sh4.fr[n+1] = RL( sh4.ea+4 ); + sh4->ea = sh4->r[m]; + sh4->fr[n] = RL(sh4, sh4->ea ); + sh4->fr[n+1] = RL(sh4, sh4->ea+4 ); } } else { /* SZ = 0 */ - sh4.ea = sh4.r[m]; - sh4.fr[n] = RL( sh4.ea ); + sh4->ea = sh4->r[m]; + sh4->fr[n] = RL(sh4, sh4->ea ); } } } @@ -2801,99 +2801,99 @@ INLINE void FMOVMRFR(UINT32 m,UINT32 n) /* FMOV XDm,DRn PR=1 XDm -> DRn 1111nnn0mmm11100 */ /* FMOV DRm,XDn PR=1 DRm -> XDn 1111nnn1mmm01100 */ /* FMOV XDm,XDn PR=1 XDm -> XDn 1111nnn1mmm11100 */ -INLINE void FMOVFR(UINT32 m,UINT32 n) +INLINE void FMOVFR(SH4 *sh4,UINT32 m,UINT32 n) { - if ((sh4.fpu_sz == 0) && (sh4.fpu_pr == 0)) /* SZ = 0 */ - sh4.fr[n] = sh4.fr[m]; + if ((sh4->fpu_sz == 0) && (sh4->fpu_pr == 0)) /* SZ = 0 */ + sh4->fr[n] = sh4->fr[m]; else { /* SZ = 1 or PR = 1 */ if (m & 1) { if (n & 1) { - sh4.xf[n & 14] = sh4.xf[m & 14]; - sh4.xf[n | 1] = sh4.xf[m | 1]; + sh4->xf[n & 14] = sh4->xf[m & 14]; + sh4->xf[n | 1] = sh4->xf[m | 1]; } else { - sh4.fr[n] = sh4.xf[m & 14]; - sh4.fr[n | 1] = sh4.xf[m | 1]; + sh4->fr[n] = sh4->xf[m & 14]; + sh4->fr[n | 1] = sh4->xf[m | 1]; } } else { if (n & 1) { - sh4.xf[n & 14] = sh4.fr[m]; - sh4.xf[n | 1] = sh4.fr[m | 1]; // (a&14)+1 -> a|1 + sh4->xf[n & 14] = sh4->fr[m]; + sh4->xf[n | 1] = sh4->fr[m | 1]; // (a&14)+1 -> a|1 } else { - sh4.fr[n] = sh4.fr[m]; - sh4.fr[n | 1] = sh4.fr[m | 1]; + sh4->fr[n] = sh4->fr[m]; + sh4->fr[n | 1] = sh4->fr[m | 1]; } } } } /* FLDI1 FRn 1111nnnn10011101 */ -INLINE void FLDI1(UINT32 n) +INLINE void FLDI1(SH4 *sh4, UINT32 n) { - sh4.fr[n] = 0x3F800000; + sh4->fr[n] = 0x3F800000; } /* FLDI0 FRn 1111nnnn10001101 */ -INLINE void FLDI0(UINT32 n) +INLINE void FLDI0(SH4 *sh4, UINT32 n) { - sh4.fr[n] = 0; + sh4->fr[n] = 0; } /* FLDS FRm,FPUL 1111mmmm00011101 */ -INLINE void FLDS(UINT32 m) +INLINE void FLDS(SH4 *sh4, UINT32 m) { - sh4.fpul = sh4.fr[m]; + sh4->fpul = sh4->fr[m]; } /* FSTS FPUL,FRn 1111nnnn00001101 */ -INLINE void FSTS(UINT32 n) +INLINE void FSTS(SH4 *sh4, UINT32 n) { - sh4.fr[n] = sh4.fpul; + sh4->fr[n] = sh4->fpul; } /* FRCHG 1111101111111101 */ -INLINE void FRCHG(void) +INLINE void FRCHG(SH4 *sh4) { - sh4.fpscr ^= FR; - sh4_swap_fp_registers(); + sh4->fpscr ^= FR; + sh4_swap_fp_registers(sh4); } /* FSCHG 1111001111111101 */ -INLINE void FSCHG(void) +INLINE void FSCHG(SH4 *sh4) { - sh4.fpscr ^= SZ; - sh4.fpu_sz = (sh4.fpscr & SZ) ? 1 : 0; + sh4->fpscr ^= SZ; + sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; } /* FTRC FRm,FPUL PR=0 1111mmmm00111101 */ /* FTRC DRm,FPUL PR=1 1111mmm000111101 */ -INLINE void FTRC(UINT32 n) +INLINE void FTRC(SH4 *sh4, UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; - *((INT32 *)&sh4.fpul) = (INT32)FP_RFD(n); + *((INT32 *)&sh4->fpul) = (INT32)FP_RFD(n); } else { /* PR = 0 */ - /* read sh4.fr[n] as float -> truncate -> fpul(32) */ - *((INT32 *)&sh4.fpul) = (INT32)FP_RFS(n); + /* read sh4->fr[n] as float -> truncate -> fpul(32) */ + *((INT32 *)&sh4->fpul) = (INT32)FP_RFS(n); } } /* FLOAT FPUL,FRn PR=0 1111nnnn00101101 */ /* FLOAT FPUL,DRn PR=1 1111nnn000101101 */ -INLINE void FLOAT(UINT32 n) +INLINE void FLOAT(SH4 *sh4, UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; - FP_RFD(n) = (double)*((INT32 *)&sh4.fpul); + FP_RFD(n) = (double)*((INT32 *)&sh4->fpul); } else { /* PR = 0 */ - FP_RFS(n) = (float)*((INT32 *)&sh4.fpul); + FP_RFS(n) = (float)*((INT32 *)&sh4->fpul); } } /* FNEG FRn PR=0 1111nnnn01001101 */ /* FNEG DRn PR=1 1111nnn001001101 */ -INLINE void FNEG(UINT32 n) +INLINE void FNEG(SH4 *sh4, UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ FP_RFD(n) = -FP_RFD(n); } else { /* PR = 0 */ FP_RFS(n) = -FP_RFS(n); @@ -2902,89 +2902,89 @@ INLINE void FNEG(UINT32 n) /* FABS FRn PR=0 1111nnnn01011101 */ /* FABS DRn PR=1 1111nnn001011101 */ -INLINE void FABS(UINT32 n) +INLINE void FABS(SH4 *sh4, UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ #ifdef LSB_FIRST n = n | 1; // n & 14 + 1 - sh4.fr[n] = sh4.fr[n] & 0x7fffffff; + sh4->fr[n] = sh4->fr[n] & 0x7fffffff; #else n = n & 14; - sh4.fr[n] = sh4.fr[n] & 0x7fffffff; + sh4->fr[n] = sh4->fr[n] & 0x7fffffff; #endif } else { /* PR = 0 */ - sh4.fr[n] = sh4.fr[n] & 0x7fffffff; + sh4->fr[n] = sh4->fr[n] & 0x7fffffff; } } /* FCMP/EQ FRm,FRn PR=0 1111nnnnmmmm0100 */ /* FCMP/EQ DRm,DRn PR=1 1111nnn0mmm00100 */ -INLINE void FCMP_EQ(UINT32 m,UINT32 n) +INLINE void FCMP_EQ(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; if (FP_RFD(n) == FP_RFD(m)) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } else { /* PR = 0 */ if (FP_RFS(n) == FP_RFS(m)) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } } /* FCMP/GT FRm,FRn PR=0 1111nnnnmmmm0101 */ /* FCMP/GT DRm,DRn PR=1 1111nnn0mmm00101 */ -INLINE void FCMP_GT(UINT32 m,UINT32 n) +INLINE void FCMP_GT(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; if (FP_RFD(n) > FP_RFD(m)) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } else { /* PR = 0 */ if (FP_RFS(n) > FP_RFS(m)) - sh4.sr |= T; + sh4->sr |= T; else - sh4.sr &= ~T; + sh4->sr &= ~T; } } /* FCNVDS DRm,FPUL PR=1 1111mmm010111101 */ -INLINE void FCNVDS(UINT32 n) +INLINE void FCNVDS(SH4 *sh4, UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; #ifdef LSB_FIRST - if (sh4.fpscr & RM) - sh4.fr[n] &= 0xe0000000; /* round toward zero*/ + if (sh4->fpscr & RM) + sh4->fr[n] &= 0xe0000000; /* round toward zero*/ #else - if (sh4.fpscr & RM) - sh4.fr[n | 1] &= 0xe0000000; /* round toward zero*/ + if (sh4->fpscr & RM) + sh4->fr[n | 1] &= 0xe0000000; /* round toward zero*/ #endif - *((float *)&sh4.fpul) = (float)FP_RFD(n); + *((float *)&sh4->fpul) = (float)FP_RFD(n); } } /* FCNVSD FPUL, DRn PR=1 1111nnn010101101 */ -INLINE void FCNVSD(UINT32 n) +INLINE void FCNVSD(SH4 *sh4, UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; - FP_RFD(n) = (double)*((float *)&sh4.fpul); + FP_RFD(n) = (double)*((float *)&sh4->fpul); } } /* FADD FRm,FRn PR=0 1111nnnnmmmm0000 */ /* FADD DRm,DRn PR=1 1111nnn0mmm00000 */ -INLINE void FADD(UINT32 m,UINT32 n) +INLINE void FADD(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; FP_RFD(n) = FP_RFD(n) + FP_RFD(m); @@ -2995,9 +2995,9 @@ INLINE void FADD(UINT32 m,UINT32 n) /* FSUB FRm,FRn PR=0 1111nnnnmmmm0001 */ /* FSUB DRm,DRn PR=1 1111nnn0mmm00001 */ -INLINE void FSUB(UINT32 m,UINT32 n) +INLINE void FSUB(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; FP_RFD(n) = FP_RFD(n) - FP_RFD(m); @@ -3009,9 +3009,9 @@ INLINE void FSUB(UINT32 m,UINT32 n) /* FMUL FRm,FRn PR=0 1111nnnnmmmm0010 */ /* FMUL DRm,DRn PR=1 1111nnn0mmm00010 */ -INLINE void FMUL(UINT32 m,UINT32 n) +INLINE void FMUL(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; FP_RFD(n) = FP_RFD(n) * FP_RFD(m); @@ -3022,9 +3022,9 @@ INLINE void FMUL(UINT32 m,UINT32 n) /* FDIV FRm,FRn PR=0 1111nnnnmmmm0011 */ /* FDIV DRm,DRn PR=1 1111nnn0mmm00011 */ -INLINE void FDIV(UINT32 m,UINT32 n) +INLINE void FDIV(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; if (FP_RFD(m) == 0) @@ -3038,18 +3038,18 @@ INLINE void FDIV(UINT32 m,UINT32 n) } /* FMAC FR0,FRm,FRn PR=0 1111nnnnmmmm1110 */ -INLINE void FMAC(UINT32 m,UINT32 n) +INLINE void FMAC(SH4 *sh4, UINT32 m,UINT32 n) { - if (sh4.fpu_pr == 0) { /* PR = 0 */ + if (sh4->fpu_pr == 0) { /* PR = 0 */ FP_RFS(n) = (FP_RFS(0) * FP_RFS(m)) + FP_RFS(n); } } /* FSQRT FRn PR=0 1111nnnn01101101 */ /* FSQRT DRn PR=1 1111nnnn01101101 */ -INLINE void FSQRT(UINT32 n) +INLINE void FSQRT(SH4 *sh4, UINT32 n) { - if (sh4.fpu_pr) { /* PR = 1 */ + if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; if (FP_RFD(n) < 0) return; @@ -3062,7 +3062,7 @@ INLINE void FSQRT(UINT32 n) } /* FSRRA FRn PR=0 1111nnnn01111101 */ -INLINE void FSRRA(UINT32 n) +INLINE void FSRRA(SH4 *sh4, UINT32 n) { if (FP_RFS(n) < 0) return; @@ -3070,17 +3070,17 @@ INLINE void FSRRA(UINT32 n) } /* FSSCA FPUL,FRn PR=0 1111nnn011111101 */ -INLINE void FSSCA(UINT32 n) +INLINE void FSSCA(SH4 *sh4, UINT32 n) { float angle; - angle = (((float)(sh4.fpul & 0xFFFF)) / 65536.0) * 2.0 * M_PI; + angle = (((float)(sh4->fpul & 0xFFFF)) / 65536.0) * 2.0 * M_PI; FP_RFS(n) = sinf(angle); FP_RFS(n+1) = cosf(angle); } /* FIPR FVm,FVn PR=0 1111nnmm11101101 */ -INLINE void FIPR(UINT32 n) +INLINE void FIPR(SH4 *sh4, UINT32 n) { UINT32 m; float ml[4]; @@ -3094,7 +3094,7 @@ int a; } /* FTRV XMTRX,FVn PR=0 1111nn0111111101 */ -INLINE void FTRV(UINT32 n) +INLINE void FTRV(SH4 *sh4, UINT32 n) { int i,j; float sum[4]; @@ -3109,90 +3109,90 @@ float sum[4]; FP_RFS(n + i) = sum[i]; } -INLINE void op1111(UINT16 opcode) +INLINE void op1111(SH4 *sh4, UINT16 opcode) { switch (opcode & 0xf) { case 0: - FADD(Rm,Rn); + FADD(sh4, Rm,Rn); break; case 1: - FSUB(Rm,Rn); + FSUB(sh4, Rm,Rn); break; case 2: - FMUL(Rm,Rn); + FMUL(sh4, Rm,Rn); break; case 3: - FDIV(Rm,Rn); + FDIV(sh4, Rm,Rn); break; case 4: - FCMP_EQ(Rm,Rn); + FCMP_EQ(sh4, Rm,Rn); break; case 5: - FCMP_GT(Rm,Rn); + FCMP_GT(sh4, Rm,Rn); break; case 6: - FMOVS0FR(Rm,Rn); + FMOVS0FR(sh4, Rm,Rn); break; case 7: - FMOVFRS0(Rm,Rn); + FMOVFRS0(sh4, Rm,Rn); break; case 8: - FMOVMRFR(Rm,Rn); + FMOVMRFR(sh4, Rm,Rn); break; case 9: - FMOVMRIFR(Rm,Rn); + FMOVMRIFR(sh4, Rm,Rn); break; case 10: - FMOVFRMR(Rm,Rn); + FMOVFRMR(sh4, Rm,Rn); break; case 11: - FMOVFRMDR(Rm,Rn); + FMOVFRMDR(sh4, Rm,Rn); break; case 12: - FMOVFR(Rm,Rn); + FMOVFR(sh4, Rm,Rn); break; case 13: switch (opcode & 0xF0) { case 0x00: - FSTS(Rn); + FSTS(sh4, Rn); break; case 0x10: - FLDS(Rn); + FLDS(sh4, Rn); break; case 0x20: - FLOAT(Rn); + FLOAT(sh4, Rn); break; case 0x30: - FTRC(Rn); + FTRC(sh4, Rn); break; case 0x40: - FNEG(Rn); + FNEG(sh4, Rn); break; case 0x50: - FABS(Rn); + FABS(sh4, Rn); break; case 0x60: - FSQRT(Rn); + FSQRT(sh4, Rn); break; case 0x70: - FSRRA(Rn); + FSRRA(sh4, Rn); break; case 0x80: - FLDI0(Rn); + FLDI0(sh4, Rn); break; case 0x90: - FLDI1(Rn); + FLDI1(sh4, Rn); break; case 0xA0: - FCNVSD(Rn); + FCNVSD(sh4, Rn); break; case 0xB0: - FCNVDS(Rn); + FCNVDS(sh4, Rn); break; case 0xE0: - FIPR(Rn); + FIPR(sh4, Rn); break; case 0xF0: if (opcode & 0x100) { @@ -3200,20 +3200,20 @@ INLINE void op1111(UINT16 opcode) switch (opcode & 0xC00) { case 0x000: - FSCHG(); + FSCHG(sh4); break; case 0x800: - FRCHG(); + FRCHG(sh4); break; default: debugger_break(Machine); break; } } else { - FTRV(Rn); + FTRV(sh4, Rn); } } else { - FSSCA(Rn); + FSSCA(sh4, Rn); } break; default: @@ -3222,7 +3222,7 @@ INLINE void op1111(UINT16 opcode) } break; case 14: - FMAC(Rm,Rn); + FMAC(sh4, Rm,Rn); break; default: debugger_break(Machine); @@ -3236,6 +3236,7 @@ INLINE void op1111(UINT16 opcode) static CPU_RESET( sh4 ) { + SH4 *sh4 = device->token; void *tsaved[4]; emu_timer *tsave[5]; UINT32 *m; @@ -3246,141 +3247,126 @@ static CPU_RESET( sh4 ) void (*f)(UINT32 data); cpu_irq_callback save_irqcallback; - cpunum = sh4.cpu_number; - m = sh4.m; - tsaved[0] = sh4.dma_timer[0]; - tsaved[1] = sh4.dma_timer[1]; - tsaved[2] = sh4.dma_timer[2]; - tsaved[3] = sh4.dma_timer[3]; - tsave[0] = sh4.refresh_timer; - tsave[1] = sh4.rtc_timer; - tsave[2] = sh4.timer[0]; - tsave[3] = sh4.timer[1]; - tsave[4] = sh4.timer[2]; + m = sh4->m; + tsaved[0] = sh4->dma_timer[0]; + tsaved[1] = sh4->dma_timer[1]; + tsaved[2] = sh4->dma_timer[2]; + tsaved[3] = sh4->dma_timer[3]; + tsave[0] = sh4->refresh_timer; + tsave[1] = sh4->rtc_timer; + tsave[2] = sh4->timer[0]; + tsave[3] = sh4->timer[1]; + tsave[4] = sh4->timer[2]; - f = sh4.ftcsr_read_callback; - save_irqcallback = sh4.irq_callback; - save_is_slave = sh4.is_slave; - savecpu_clock = sh4.cpu_clock; - savebus_clock = sh4.bus_clock; - savepm_clock = sh4.pm_clock; - memset(&sh4, 0, sizeof(SH4)); - sh4.is_slave = save_is_slave; - sh4.cpu_clock = savecpu_clock; - sh4.bus_clock = savebus_clock; - sh4.pm_clock = savepm_clock; - sh4.ftcsr_read_callback = f; - sh4.irq_callback = save_irqcallback; - sh4.device = device; - sh4.internal = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); - sh4.program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); - sh4.io = cpu_get_address_space(device, ADDRESS_SPACE_IO); + f = sh4->ftcsr_read_callback; + save_irqcallback = sh4->irq_callback; + save_is_slave = sh4->is_slave; + savecpu_clock = sh4->cpu_clock; + savebus_clock = sh4->bus_clock; + savepm_clock = sh4->pm_clock; + memset(sh4, 0, sizeof(*sh4)); + sh4->is_slave = save_is_slave; + sh4->cpu_clock = savecpu_clock; + sh4->bus_clock = savebus_clock; + sh4->pm_clock = savepm_clock; + sh4->ftcsr_read_callback = f; + sh4->irq_callback = save_irqcallback; + sh4->device = device; + sh4->internal = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); + sh4->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); + sh4->io = cpu_get_address_space(device, ADDRESS_SPACE_IO); - sh4.dma_timer[0] = tsaved[0]; - sh4.dma_timer[1] = tsaved[1]; - sh4.dma_timer[2] = tsaved[2]; - sh4.dma_timer[3] = tsaved[3]; - sh4.refresh_timer = tsave[0]; - sh4.rtc_timer = tsave[1]; - sh4.timer[0] = tsave[2]; - sh4.timer[1] = tsave[3]; - sh4.timer[2] = tsave[4]; - sh4.cpu_number = cpunum; - sh4.m = m; - memset(sh4.m, 0, 16384*4); - sh4_default_exception_priorities(); - memset(sh4.exception_requesting, 0, sizeof(sh4.exception_requesting)); + sh4->dma_timer[0] = tsaved[0]; + sh4->dma_timer[1] = tsaved[1]; + sh4->dma_timer[2] = tsaved[2]; + sh4->dma_timer[3] = tsaved[3]; + sh4->refresh_timer = tsave[0]; + sh4->rtc_timer = tsave[1]; + sh4->timer[0] = tsave[2]; + sh4->timer[1] = tsave[3]; + sh4->timer[2] = tsave[4]; + sh4->m = m; + memset(sh4->m, 0, 16384*4); + sh4_default_exception_priorities(sh4); + memset(sh4->exception_requesting, 0, sizeof(sh4->exception_requesting)); - timer_adjust_oneshot(sh4.rtc_timer, ATTOTIME_IN_HZ(128), cpunum); - sh4.m[RCR2] = 0x09; - sh4.m[TCOR0] = 0xffffffff; - sh4.m[TCNT0] = 0xffffffff; - sh4.m[TCOR1] = 0xffffffff; - sh4.m[TCNT1] = 0xffffffff; - sh4.m[TCOR2] = 0xffffffff; - sh4.m[TCNT2] = 0xffffffff; + timer_adjust_oneshot(sh4->rtc_timer, ATTOTIME_IN_HZ(128), cpunum); + sh4->m[RCR2] = 0x09; + sh4->m[TCOR0] = 0xffffffff; + sh4->m[TCNT0] = 0xffffffff; + sh4->m[TCOR1] = 0xffffffff; + sh4->m[TCNT1] = 0xffffffff; + sh4->m[TCOR2] = 0xffffffff; + sh4->m[TCNT2] = 0xffffffff; - sh4.pc = 0xa0000000; - sh4.r[15] = RL(4); - sh4.sr = 0x700000f0; - sh4.fpscr = 0x00040001; - sh4.fpu_sz = (sh4.fpscr & SZ) ? 1 : 0; - sh4.fpu_pr = (sh4.fpscr & PR) ? 1 : 0; - sh4.fpul = 0; - sh4.dbr = 0; + sh4->pc = 0xa0000000; + sh4->r[15] = RL(sh4,4); + sh4->sr = 0x700000f0; + sh4->fpscr = 0x00040001; + sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; + sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0; + sh4->fpul = 0; + sh4->dbr = 0; - sh4.internal_irq_level = -1; - sh4.irln = 15; + sh4->internal_irq_level = -1; + sh4->irln = 15; } /* Execute cycles - returns number of cycles actually run */ static CPU_EXECUTE( sh4 ) { - sh4.sh4_icount = cycles; + SH4 *sh4 = device->token; + sh4->sh4_icount = cycles; - if (sh4.cpu_off) + if (sh4->cpu_off) return 0; do { UINT32 opcode; - if (sh4.delay) + if (sh4->delay) { - opcode = memory_decrypted_read_word(sh4.program, WORD2_XOR_LE((UINT32)(sh4.delay & AM))); - sh4.pc -= 2; + opcode = memory_decrypted_read_word(sh4->program, WORD2_XOR_LE((UINT32)(sh4->delay & AM))); + sh4->pc -= 2; } else - opcode = memory_decrypted_read_word(sh4.program, WORD2_XOR_LE((UINT32)(sh4.pc & AM))); + opcode = memory_decrypted_read_word(sh4->program, WORD2_XOR_LE((UINT32)(sh4->pc & AM))); - debugger_instruction_hook(device, sh4.pc & AM); + debugger_instruction_hook(device, sh4->pc & AM); - sh4.delay = 0; - sh4.pc += 2; - sh4.ppc = sh4.pc; + sh4->delay = 0; + sh4->pc += 2; + sh4->ppc = sh4->pc; switch (opcode & ( 15 << 12)) { - case 0<<12: op0000(opcode); break; - case 1<<12: op0001(opcode); break; - case 2<<12: op0010(opcode); break; - case 3<<12: op0011(opcode); break; - case 4<<12: op0100(opcode); break; - case 5<<12: op0101(opcode); break; - case 6<<12: op0110(opcode); break; - case 7<<12: op0111(opcode); break; - case 8<<12: op1000(opcode); break; - case 9<<12: op1001(opcode); break; - case 10<<12: op1010(opcode); break; - case 11<<12: op1011(opcode); break; - case 12<<12: op1100(opcode); break; - case 13<<12: op1101(opcode); break; - case 14<<12: op1110(opcode); break; - default: op1111(opcode); break; + case 0<<12: op0000(sh4, opcode); break; + case 1<<12: op0001(sh4, opcode); break; + case 2<<12: op0010(sh4, opcode); break; + case 3<<12: op0011(sh4, opcode); break; + case 4<<12: op0100(sh4, opcode); break; + case 5<<12: op0101(sh4, opcode); break; + case 6<<12: op0110(sh4, opcode); break; + case 7<<12: op0111(sh4, opcode); break; + case 8<<12: op1000(sh4, opcode); break; + case 9<<12: op1001(sh4, opcode); break; + case 10<<12: op1010(sh4, opcode); break; + case 11<<12: op1011(sh4, opcode); break; + case 12<<12: op1100(sh4, opcode); break; + case 13<<12: op1101(sh4, opcode); break; + case 14<<12: op1110(sh4, opcode); break; + default: op1111(sh4, opcode); break; } - if (sh4.test_irq && !sh4.delay) + if (sh4->test_irq && !sh4->delay) { - sh4_check_pending_irq("mame_sh4_execute"); + sh4_check_pending_irq(sh4, "mame_sh4_execute"); } - sh4.sh4_icount--; - } while( sh4.sh4_icount > 0 ); + sh4->sh4_icount--; + } while( sh4->sh4_icount > 0 ); - return cycles - sh4.sh4_icount; -} - -/* Get registers, return context size */ -static CPU_GET_CONTEXT( sh4 ) -{ - if( dst ) - memcpy(dst, &sh4, sizeof(SH4)); -} - -/* Set registers */ -static CPU_SET_CONTEXT( sh4 ) -{ - if( src ) - memcpy(&sh4, src, sizeof(SH4)); + return cycles - sh4->sh4_icount; } static CPU_DISASSEMBLE( sh4 ) @@ -3391,85 +3377,85 @@ static CPU_DISASSEMBLE( sh4 ) static CPU_INIT( sh4 ) { const struct sh4_config *conf = device->static_config; + SH4 *sh4 = device->token; sh4_common_init(device); - sh4_parse_configuration(conf); + sh4_parse_configuration(sh4, conf); - sh4.cpu_number = index; - sh4.irq_callback = irqcallback; - sh4.device = device; - sh4.internal = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); - sh4.program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); - sh4.io = cpu_get_address_space(device, ADDRESS_SPACE_IO); - sh4_default_exception_priorities(); - sh4.irln = 15; - sh4.test_irq = 0; + sh4->irq_callback = irqcallback; + sh4->device = device; + sh4->internal = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); + sh4->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM); + sh4->io = cpu_get_address_space(device, ADDRESS_SPACE_IO); + sh4_default_exception_priorities(sh4); + sh4->irln = 15; + sh4->test_irq = 0; - state_save_register_device_item(device, 0, sh4.pc); - state_save_register_device_item(device, 0, sh4.r[15]); - state_save_register_device_item(device, 0, sh4.sr); - state_save_register_device_item(device, 0, sh4.pr); - state_save_register_device_item(device, 0, sh4.gbr); - state_save_register_device_item(device, 0, sh4.vbr); - state_save_register_device_item(device, 0, sh4.mach); - state_save_register_device_item(device, 0, sh4.macl); - state_save_register_device_item(device, 0, sh4.spc); - state_save_register_device_item(device, 0, sh4.ssr); - state_save_register_device_item(device, 0, sh4.sgr); - state_save_register_device_item(device, 0, sh4.fpscr); - state_save_register_device_item(device, 0, sh4.r[ 0]); - state_save_register_device_item(device, 0, sh4.r[ 1]); - state_save_register_device_item(device, 0, sh4.r[ 2]); - state_save_register_device_item(device, 0, sh4.r[ 3]); - state_save_register_device_item(device, 0, sh4.r[ 4]); - state_save_register_device_item(device, 0, sh4.r[ 5]); - state_save_register_device_item(device, 0, sh4.r[ 6]); - state_save_register_device_item(device, 0, sh4.r[ 7]); - state_save_register_device_item(device, 0, sh4.r[ 8]); - state_save_register_device_item(device, 0, sh4.r[ 9]); - state_save_register_device_item(device, 0, sh4.r[10]); - state_save_register_device_item(device, 0, sh4.r[11]); - state_save_register_device_item(device, 0, sh4.r[12]); - state_save_register_device_item(device, 0, sh4.r[13]); - state_save_register_device_item(device, 0, sh4.r[14]); - state_save_register_device_item(device, 0, sh4.fr[ 0]); - state_save_register_device_item(device, 0, sh4.fr[ 1]); - state_save_register_device_item(device, 0, sh4.fr[ 2]); - state_save_register_device_item(device, 0, sh4.fr[ 3]); - state_save_register_device_item(device, 0, sh4.fr[ 4]); - state_save_register_device_item(device, 0, sh4.fr[ 5]); - state_save_register_device_item(device, 0, sh4.fr[ 6]); - state_save_register_device_item(device, 0, sh4.fr[ 7]); - state_save_register_device_item(device, 0, sh4.fr[ 8]); - state_save_register_device_item(device, 0, sh4.fr[ 9]); - state_save_register_device_item(device, 0, sh4.fr[10]); - state_save_register_device_item(device, 0, sh4.fr[11]); - state_save_register_device_item(device, 0, sh4.fr[12]); - state_save_register_device_item(device, 0, sh4.fr[13]); - state_save_register_device_item(device, 0, sh4.fr[14]); - state_save_register_device_item(device, 0, sh4.fr[15]); - state_save_register_device_item(device, 0, sh4.xf[ 0]); - state_save_register_device_item(device, 0, sh4.xf[ 1]); - state_save_register_device_item(device, 0, sh4.xf[ 2]); - state_save_register_device_item(device, 0, sh4.xf[ 3]); - state_save_register_device_item(device, 0, sh4.xf[ 4]); - state_save_register_device_item(device, 0, sh4.xf[ 5]); - state_save_register_device_item(device, 0, sh4.xf[ 6]); - state_save_register_device_item(device, 0, sh4.xf[ 7]); - state_save_register_device_item(device, 0, sh4.xf[ 8]); - state_save_register_device_item(device, 0, sh4.xf[ 9]); - state_save_register_device_item(device, 0, sh4.xf[10]); - state_save_register_device_item(device, 0, sh4.xf[11]); - state_save_register_device_item(device, 0, sh4.xf[12]); - state_save_register_device_item(device, 0, sh4.xf[13]); - state_save_register_device_item(device, 0, sh4.xf[14]); - state_save_register_device_item(device, 0, sh4.xf[15]); - state_save_register_device_item(device, 0, sh4.ea); - state_save_register_device_item(device, 0, sh4.fpul); - state_save_register_device_item(device, 0, sh4.dbr); - state_save_register_device_item_array(device, 0, sh4.exception_priority); - state_save_register_device_item_array(device, 0, sh4.exception_requesting); + state_save_register_device_item(device, 0, sh4->pc); + state_save_register_device_item(device, 0, sh4->r[15]); + state_save_register_device_item(device, 0, sh4->sr); + state_save_register_device_item(device, 0, sh4->pr); + state_save_register_device_item(device, 0, sh4->gbr); + state_save_register_device_item(device, 0, sh4->vbr); + state_save_register_device_item(device, 0, sh4->mach); + state_save_register_device_item(device, 0, sh4->macl); + state_save_register_device_item(device, 0, sh4->spc); + state_save_register_device_item(device, 0, sh4->ssr); + state_save_register_device_item(device, 0, sh4->sgr); + state_save_register_device_item(device, 0, sh4->fpscr); + state_save_register_device_item(device, 0, sh4->r[ 0]); + state_save_register_device_item(device, 0, sh4->r[ 1]); + state_save_register_device_item(device, 0, sh4->r[ 2]); + state_save_register_device_item(device, 0, sh4->r[ 3]); + state_save_register_device_item(device, 0, sh4->r[ 4]); + state_save_register_device_item(device, 0, sh4->r[ 5]); + state_save_register_device_item(device, 0, sh4->r[ 6]); + state_save_register_device_item(device, 0, sh4->r[ 7]); + state_save_register_device_item(device, 0, sh4->r[ 8]); + state_save_register_device_item(device, 0, sh4->r[ 9]); + state_save_register_device_item(device, 0, sh4->r[10]); + state_save_register_device_item(device, 0, sh4->r[11]); + state_save_register_device_item(device, 0, sh4->r[12]); + state_save_register_device_item(device, 0, sh4->r[13]); + state_save_register_device_item(device, 0, sh4->r[14]); + state_save_register_device_item(device, 0, sh4->fr[ 0]); + state_save_register_device_item(device, 0, sh4->fr[ 1]); + state_save_register_device_item(device, 0, sh4->fr[ 2]); + state_save_register_device_item(device, 0, sh4->fr[ 3]); + state_save_register_device_item(device, 0, sh4->fr[ 4]); + state_save_register_device_item(device, 0, sh4->fr[ 5]); + state_save_register_device_item(device, 0, sh4->fr[ 6]); + state_save_register_device_item(device, 0, sh4->fr[ 7]); + state_save_register_device_item(device, 0, sh4->fr[ 8]); + state_save_register_device_item(device, 0, sh4->fr[ 9]); + state_save_register_device_item(device, 0, sh4->fr[10]); + state_save_register_device_item(device, 0, sh4->fr[11]); + state_save_register_device_item(device, 0, sh4->fr[12]); + state_save_register_device_item(device, 0, sh4->fr[13]); + state_save_register_device_item(device, 0, sh4->fr[14]); + state_save_register_device_item(device, 0, sh4->fr[15]); + state_save_register_device_item(device, 0, sh4->xf[ 0]); + state_save_register_device_item(device, 0, sh4->xf[ 1]); + state_save_register_device_item(device, 0, sh4->xf[ 2]); + state_save_register_device_item(device, 0, sh4->xf[ 3]); + state_save_register_device_item(device, 0, sh4->xf[ 4]); + state_save_register_device_item(device, 0, sh4->xf[ 5]); + state_save_register_device_item(device, 0, sh4->xf[ 6]); + state_save_register_device_item(device, 0, sh4->xf[ 7]); + state_save_register_device_item(device, 0, sh4->xf[ 8]); + state_save_register_device_item(device, 0, sh4->xf[ 9]); + state_save_register_device_item(device, 0, sh4->xf[10]); + state_save_register_device_item(device, 0, sh4->xf[11]); + state_save_register_device_item(device, 0, sh4->xf[12]); + state_save_register_device_item(device, 0, sh4->xf[13]); + state_save_register_device_item(device, 0, sh4->xf[14]); + state_save_register_device_item(device, 0, sh4->xf[15]); + state_save_register_device_item(device, 0, sh4->ea); + state_save_register_device_item(device, 0, sh4->fpul); + state_save_register_device_item(device, 0, sh4->dbr); + state_save_register_device_item_array(device, 0, sh4->exception_priority); + state_save_register_device_item_array(device, 0, sh4->exception_requesting); } @@ -3479,142 +3465,144 @@ static CPU_INIT( sh4 ) static CPU_SET_INFO( sh4 ) { + SH4 *sh4 = device->token; + switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + SH4_IRL0: sh4_set_irq_line(SH4_IRL0, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL1: sh4_set_irq_line(SH4_IRL1, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL2: sh4_set_irq_line(SH4_IRL2, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL3: sh4_set_irq_line(SH4_IRL3, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRLn: sh4_set_irq_line(SH4_IRLn, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: sh4_set_irq_line(INPUT_LINE_NMI, info->i); break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL0: sh4_set_irq_line(sh4, SH4_IRL0, info->i); break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL1: sh4_set_irq_line(sh4, SH4_IRL1, info->i); break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL2: sh4_set_irq_line(sh4, SH4_IRL2, info->i); break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL3: sh4_set_irq_line(sh4, SH4_IRL3, info->i); break; + case CPUINFO_INT_INPUT_STATE + SH4_IRLn: sh4_set_irq_line(sh4, SH4_IRLn, info->i); break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: sh4_set_irq_line(sh4, INPUT_LINE_NMI, info->i); break; case CPUINFO_INT_REGISTER + SH4_PC: - case CPUINFO_INT_PC: sh4.pc = info->i; sh4.delay = 0; break; - case CPUINFO_INT_SP: sh4.r[15] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_PR: sh4.pr = info->i; break; + case CPUINFO_INT_PC: sh4->pc = info->i; sh4->delay = 0; break; + case CPUINFO_INT_SP: sh4->r[15] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_PR: sh4->pr = info->i; break; case CPUINFO_INT_REGISTER + SH4_SR: - sh4.sr = info->i; - sh4_exception_recompute(); - sh4_check_pending_irq("sh4_set_info"); + sh4->sr = info->i; + sh4_exception_recompute(sh4); + sh4_check_pending_irq(sh4, "sh4_set_info"); break; - case CPUINFO_INT_REGISTER + SH4_GBR: sh4.gbr = info->i; break; - case CPUINFO_INT_REGISTER + SH4_VBR: sh4.vbr = info->i; break; - case CPUINFO_INT_REGISTER + SH4_DBR: sh4.dbr = info->i; break; - case CPUINFO_INT_REGISTER + SH4_MACH: sh4.mach = info->i; break; - case CPUINFO_INT_REGISTER + SH4_MACL: sh4.macl = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R0: sh4.r[ 0] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R1: sh4.r[ 1] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R2: sh4.r[ 2] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R3: sh4.r[ 3] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R4: sh4.r[ 4] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R5: sh4.r[ 5] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R6: sh4.r[ 6] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R7: sh4.r[ 7] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R8: sh4.r[ 8] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R9: sh4.r[ 9] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R10: sh4.r[10] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R11: sh4.r[11] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R12: sh4.r[12] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R13: sh4.r[13] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R14: sh4.r[14] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R15: sh4.r[15] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_EA: sh4.ea = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R0_BK0: sh4.rbnk[0][0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R1_BK0: sh4.rbnk[0][1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R2_BK0: sh4.rbnk[0][2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R3_BK0: sh4.rbnk[0][3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R4_BK0: sh4.rbnk[0][4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R5_BK0: sh4.rbnk[0][5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R6_BK0: sh4.rbnk[0][6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R7_BK0: sh4.rbnk[0][7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R0_BK1: sh4.rbnk[1][0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R1_BK1: sh4.rbnk[1][1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R2_BK1: sh4.rbnk[1][2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R3_BK1: sh4.rbnk[1][3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R4_BK1: sh4.rbnk[1][4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R5_BK1: sh4.rbnk[1][5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R6_BK1: sh4.rbnk[1][6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R7_BK1: sh4.rbnk[1][7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_SPC: sh4.spc = info->i; break; - case CPUINFO_STR_REGISTER + SH4_SSR: sh4.ssr = info->i; break; - case CPUINFO_STR_REGISTER + SH4_SGR: sh4.sgr = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FPSCR: sh4.fpscr = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FPUL: sh4.fpul = info->i; break; + case CPUINFO_INT_REGISTER + SH4_GBR: sh4->gbr = info->i; break; + case CPUINFO_INT_REGISTER + SH4_VBR: sh4->vbr = info->i; break; + case CPUINFO_INT_REGISTER + SH4_DBR: sh4->dbr = info->i; break; + case CPUINFO_INT_REGISTER + SH4_MACH: sh4->mach = info->i; break; + case CPUINFO_INT_REGISTER + SH4_MACL: sh4->macl = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R0: sh4->r[ 0] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R1: sh4->r[ 1] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R2: sh4->r[ 2] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R3: sh4->r[ 3] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R4: sh4->r[ 4] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R5: sh4->r[ 5] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R6: sh4->r[ 6] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R7: sh4->r[ 7] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R8: sh4->r[ 8] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R9: sh4->r[ 9] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R10: sh4->r[10] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R11: sh4->r[11] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R12: sh4->r[12] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R13: sh4->r[13] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R14: sh4->r[14] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_R15: sh4->r[15] = info->i; break; + case CPUINFO_INT_REGISTER + SH4_EA: sh4->ea = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R0_BK0: sh4->rbnk[0][0] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R1_BK0: sh4->rbnk[0][1] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R2_BK0: sh4->rbnk[0][2] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R3_BK0: sh4->rbnk[0][3] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R4_BK0: sh4->rbnk[0][4] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R5_BK0: sh4->rbnk[0][5] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R6_BK0: sh4->rbnk[0][6] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R7_BK0: sh4->rbnk[0][7] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R0_BK1: sh4->rbnk[1][0] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R1_BK1: sh4->rbnk[1][1] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R2_BK1: sh4->rbnk[1][2] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R3_BK1: sh4->rbnk[1][3] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R4_BK1: sh4->rbnk[1][4] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R5_BK1: sh4->rbnk[1][5] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R6_BK1: sh4->rbnk[1][6] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_R7_BK1: sh4->rbnk[1][7] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_SPC: sh4->spc = info->i; break; + case CPUINFO_STR_REGISTER + SH4_SSR: sh4->ssr = info->i; break; + case CPUINFO_STR_REGISTER + SH4_SGR: sh4->sgr = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FPSCR: sh4->fpscr = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FPUL: sh4->fpul = info->i; break; #ifdef LSB_FIRST - case CPUINFO_STR_REGISTER + SH4_FR0: sh4.fr[ 0 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR1: sh4.fr[ 1 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR2: sh4.fr[ 2 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR3: sh4.fr[ 3 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR4: sh4.fr[ 4 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR5: sh4.fr[ 5 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR6: sh4.fr[ 6 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR7: sh4.fr[ 7 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR8: sh4.fr[ 8 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR9: sh4.fr[ 9 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR10: sh4.fr[10 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR11: sh4.fr[11 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR12: sh4.fr[12 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR13: sh4.fr[13 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR14: sh4.fr[14 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR15: sh4.fr[15 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF0: sh4.xf[ 0 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF1: sh4.xf[ 1 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF2: sh4.xf[ 2 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF3: sh4.xf[ 3 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF4: sh4.xf[ 4 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF5: sh4.xf[ 5 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF6: sh4.xf[ 6 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF7: sh4.xf[ 7 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF8: sh4.xf[ 8 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF9: sh4.xf[ 9 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF10: sh4.xf[10 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF11: sh4.xf[11 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF12: sh4.xf[12 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF13: sh4.xf[13 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF14: sh4.xf[14 ^ sh4.fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF15: sh4.xf[15 ^ sh4.fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR0: sh4->fr[ 0 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR1: sh4->fr[ 1 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR2: sh4->fr[ 2 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR3: sh4->fr[ 3 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR4: sh4->fr[ 4 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR5: sh4->fr[ 5 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR6: sh4->fr[ 6 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR7: sh4->fr[ 7 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR8: sh4->fr[ 8 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR9: sh4->fr[ 9 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR10: sh4->fr[10 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR11: sh4->fr[11 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR12: sh4->fr[12 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR13: sh4->fr[13 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR14: sh4->fr[14 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR15: sh4->fr[15 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF0: sh4->xf[ 0 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF1: sh4->xf[ 1 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF2: sh4->xf[ 2 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF3: sh4->xf[ 3 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF4: sh4->xf[ 4 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF5: sh4->xf[ 5 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF6: sh4->xf[ 6 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF7: sh4->xf[ 7 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF8: sh4->xf[ 8 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF9: sh4->xf[ 9 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF10: sh4->xf[10 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF11: sh4->xf[11 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF12: sh4->xf[12 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF13: sh4->xf[13 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF14: sh4->xf[14 ^ sh4->fpu_pr] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF15: sh4->xf[15 ^ sh4->fpu_pr] = info->i; break; #else - case CPUINFO_STR_REGISTER + SH4_FR0: sh4.fr[ 0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR1: sh4.fr[ 1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR2: sh4.fr[ 2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR3: sh4.fr[ 3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR4: sh4.fr[ 4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR5: sh4.fr[ 5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR6: sh4.fr[ 6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR7: sh4.fr[ 7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR8: sh4.fr[ 8] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR9: sh4.fr[ 9] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR10: sh4.fr[10] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR11: sh4.fr[11] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR12: sh4.fr[12] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR13: sh4.fr[13] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR14: sh4.fr[14] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR15: sh4.fr[15] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF0: sh4.xf[ 0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF1: sh4.xf[ 1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF2: sh4.xf[ 2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF3: sh4.xf[ 3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF4: sh4.xf[ 4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF5: sh4.xf[ 5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF6: sh4.xf[ 6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF7: sh4.xf[ 7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF8: sh4.xf[ 8] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF9: sh4.xf[ 9] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF10: sh4.xf[10] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF11: sh4.xf[11] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF12: sh4.xf[12] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF13: sh4.xf[13] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF14: sh4.xf[14] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF15: sh4.xf[15] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR0: sh4->fr[ 0] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR1: sh4->fr[ 1] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR2: sh4->fr[ 2] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR3: sh4->fr[ 3] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR4: sh4->fr[ 4] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR5: sh4->fr[ 5] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR6: sh4->fr[ 6] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR7: sh4->fr[ 7] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR8: sh4->fr[ 8] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR9: sh4->fr[ 9] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR10: sh4->fr[10] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR11: sh4->fr[11] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR12: sh4->fr[12] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR13: sh4->fr[13] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR14: sh4->fr[14] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_FR15: sh4->fr[15] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF0: sh4->xf[ 0] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF1: sh4->xf[ 1] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF2: sh4->xf[ 2] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF3: sh4->xf[ 3] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF4: sh4->xf[ 4] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF5: sh4->xf[ 5] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF6: sh4->xf[ 6] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF7: sh4->xf[ 7] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF8: sh4->xf[ 8] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF9: sh4->xf[ 9] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF10: sh4->xf[10] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF11: sh4->xf[11] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF12: sh4->xf[12] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF13: sh4->xf[13] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF14: sh4->xf[14] = info->i; break; + case CPUINFO_STR_REGISTER + SH4_XF15: sh4->xf[15] = info->i; break; #endif case CPUINFO_INT_SH4_IRLn_INPUT: sh4_set_irln_input(device, info->i); break; case CPUINFO_INT_SH4_FRT_INPUT: sh4_set_frt_input(device, info->i); break; /* --- the following bits of info are set as pointers to data or functions --- */ - case CPUINFO_PTR_SH4_FTCSR_READ_CALLBACK: sh4.ftcsr_read_callback = (void (*) (UINT32 ))info->f; break; - case CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA: sh4_dma_ddt((struct sh4_ddt_dma *)info->f); break; + case CPUINFO_PTR_SH4_FTCSR_READ_CALLBACK: sh4->ftcsr_read_callback = (void (*) (UINT32 ))info->f; break; + case CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA: sh4_dma_ddt(sh4, (struct sh4_ddt_dma *)info->f); break; } } @@ -3641,10 +3629,12 @@ ADDRESS_MAP_END CPU_GET_INFO( sh4 ) { + SH4 *sh4 = (device != NULL) ? device->token : NULL; + switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(sh4); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(SH4); break; case CPUINFO_INT_INPUT_LINES: info->i = 5; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; @@ -3667,52 +3657,52 @@ CPU_GET_INFO( sh4 ) case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(sh4_internal_map); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL0: info->i = sh4.irq_line_state[SH4_IRL0]; break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL1: info->i = sh4.irq_line_state[SH4_IRL1]; break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL2: info->i = sh4.irq_line_state[SH4_IRL2]; break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL3: info->i = sh4.irq_line_state[SH4_IRL3]; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = sh4.nmi_line_state; break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL0: info->i = sh4->irq_line_state[SH4_IRL0]; break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL1: info->i = sh4->irq_line_state[SH4_IRL1]; break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL2: info->i = sh4->irq_line_state[SH4_IRL2]; break; + case CPUINFO_INT_INPUT_STATE + SH4_IRL3: info->i = sh4->irq_line_state[SH4_IRL3]; break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = sh4->nmi_line_state; break; - case CPUINFO_INT_PREVIOUSPC: info->i = sh4.ppc; break; + case CPUINFO_INT_PREVIOUSPC: info->i = sh4->ppc; break; case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + SH4_PC: info->i = (sh4.delay) ? (sh4.delay & AM) : (sh4.pc & AM); break; - case CPUINFO_INT_SP: info->i = sh4.r[15]; break; - case CPUINFO_INT_REGISTER + SH4_PR: info->i = sh4.pr; break; - case CPUINFO_INT_REGISTER + SH4_SR: info->i = sh4.sr; break; - case CPUINFO_INT_REGISTER + SH4_GBR: info->i = sh4.gbr; break; - case CPUINFO_INT_REGISTER + SH4_VBR: info->i = sh4.vbr; break; - case CPUINFO_INT_REGISTER + SH4_DBR: info->i = sh4.dbr; break; - case CPUINFO_INT_REGISTER + SH4_MACH: info->i = sh4.mach; break; - case CPUINFO_INT_REGISTER + SH4_MACL: info->i = sh4.macl; break; - case CPUINFO_INT_REGISTER + SH4_R0: info->i = sh4.r[ 0]; break; - case CPUINFO_INT_REGISTER + SH4_R1: info->i = sh4.r[ 1]; break; - case CPUINFO_INT_REGISTER + SH4_R2: info->i = sh4.r[ 2]; break; - case CPUINFO_INT_REGISTER + SH4_R3: info->i = sh4.r[ 3]; break; - case CPUINFO_INT_REGISTER + SH4_R4: info->i = sh4.r[ 4]; break; - case CPUINFO_INT_REGISTER + SH4_R5: info->i = sh4.r[ 5]; break; - case CPUINFO_INT_REGISTER + SH4_R6: info->i = sh4.r[ 6]; break; - case CPUINFO_INT_REGISTER + SH4_R7: info->i = sh4.r[ 7]; break; - case CPUINFO_INT_REGISTER + SH4_R8: info->i = sh4.r[ 8]; break; - case CPUINFO_INT_REGISTER + SH4_R9: info->i = sh4.r[ 9]; break; - case CPUINFO_INT_REGISTER + SH4_R10: info->i = sh4.r[10]; break; - case CPUINFO_INT_REGISTER + SH4_R11: info->i = sh4.r[11]; break; - case CPUINFO_INT_REGISTER + SH4_R12: info->i = sh4.r[12]; break; - case CPUINFO_INT_REGISTER + SH4_R13: info->i = sh4.r[13]; break; - case CPUINFO_INT_REGISTER + SH4_R14: info->i = sh4.r[14]; break; - case CPUINFO_INT_REGISTER + SH4_R15: info->i = sh4.r[15]; break; - case CPUINFO_INT_REGISTER + SH4_EA: info->i = sh4.ea; break; + case CPUINFO_INT_REGISTER + SH4_PC: info->i = (sh4->delay) ? (sh4->delay & AM) : (sh4->pc & AM); break; + case CPUINFO_INT_SP: info->i = sh4->r[15]; break; + case CPUINFO_INT_REGISTER + SH4_PR: info->i = sh4->pr; break; + case CPUINFO_INT_REGISTER + SH4_SR: info->i = sh4->sr; break; + case CPUINFO_INT_REGISTER + SH4_GBR: info->i = sh4->gbr; break; + case CPUINFO_INT_REGISTER + SH4_VBR: info->i = sh4->vbr; break; + case CPUINFO_INT_REGISTER + SH4_DBR: info->i = sh4->dbr; break; + case CPUINFO_INT_REGISTER + SH4_MACH: info->i = sh4->mach; break; + case CPUINFO_INT_REGISTER + SH4_MACL: info->i = sh4->macl; break; + case CPUINFO_INT_REGISTER + SH4_R0: info->i = sh4->r[ 0]; break; + case CPUINFO_INT_REGISTER + SH4_R1: info->i = sh4->r[ 1]; break; + case CPUINFO_INT_REGISTER + SH4_R2: info->i = sh4->r[ 2]; break; + case CPUINFO_INT_REGISTER + SH4_R3: info->i = sh4->r[ 3]; break; + case CPUINFO_INT_REGISTER + SH4_R4: info->i = sh4->r[ 4]; break; + case CPUINFO_INT_REGISTER + SH4_R5: info->i = sh4->r[ 5]; break; + case CPUINFO_INT_REGISTER + SH4_R6: info->i = sh4->r[ 6]; break; + case CPUINFO_INT_REGISTER + SH4_R7: info->i = sh4->r[ 7]; break; + case CPUINFO_INT_REGISTER + SH4_R8: info->i = sh4->r[ 8]; break; + case CPUINFO_INT_REGISTER + SH4_R9: info->i = sh4->r[ 9]; break; + case CPUINFO_INT_REGISTER + SH4_R10: info->i = sh4->r[10]; break; + case CPUINFO_INT_REGISTER + SH4_R11: info->i = sh4->r[11]; break; + case CPUINFO_INT_REGISTER + SH4_R12: info->i = sh4->r[12]; break; + case CPUINFO_INT_REGISTER + SH4_R13: info->i = sh4->r[13]; break; + case CPUINFO_INT_REGISTER + SH4_R14: info->i = sh4->r[14]; break; + case CPUINFO_INT_REGISTER + SH4_R15: info->i = sh4->r[15]; break; + case CPUINFO_INT_REGISTER + SH4_EA: info->i = sh4->ea; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(sh4); break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(sh4); break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(sh4); break; + case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break; + case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(sh4); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(sh4); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(sh4); break; case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sh4); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sh4.sh4_icount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sh4->sh4_icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ case CPUINFO_STR_NAME: strcpy(info->s, "SH-4"); break; @@ -3723,63 +3713,63 @@ CPU_GET_INFO( sh4 ) case CPUINFO_STR_FLAGS: sprintf(info->s, "%s%s%s%s%c%c%d%c%c", - sh4.sr & MD ? "MD ":" ", - sh4.sr & sRB ? "RB ":" ", - sh4.sr & BL ? "BL ":" ", - sh4.sr & FD ? "FD ":" ", - sh4.sr & M ? 'M':'.', - sh4.sr & Q ? 'Q':'.', - (sh4.sr & I) >> 4, - sh4.sr & S ? 'S':'.', - sh4.sr & T ? 'T':'.'); + sh4->sr & MD ? "MD ":" ", + sh4->sr & sRB ? "RB ":" ", + sh4->sr & BL ? "BL ":" ", + sh4->sr & FD ? "FD ":" ", + sh4->sr & M ? 'M':'.', + sh4->sr & Q ? 'Q':'.', + (sh4->sr & I) >> 4, + sh4->sr & S ? 'S':'.', + sh4->sr & T ? 'T':'.'); break; - case CPUINFO_STR_REGISTER + SH4_PC: sprintf(info->s, "PC :%08X", sh4.pc); break; - case CPUINFO_STR_REGISTER + SH4_SR: sprintf(info->s, "SR :%08X", sh4.sr); break; - case CPUINFO_STR_REGISTER + SH4_PR: sprintf(info->s, "PR :%08X", sh4.pr); break; - case CPUINFO_STR_REGISTER + SH4_GBR: sprintf(info->s, "GBR :%08X", sh4.gbr); break; - case CPUINFO_STR_REGISTER + SH4_VBR: sprintf(info->s, "VBR :%08X", sh4.vbr); break; - case CPUINFO_STR_REGISTER + SH4_DBR: sprintf(info->s, "DBR :%08X", sh4.dbr); break; - case CPUINFO_STR_REGISTER + SH4_MACH: sprintf(info->s, "MACH:%08X", sh4.mach); break; - case CPUINFO_STR_REGISTER + SH4_MACL: sprintf(info->s, "MACL:%08X", sh4.macl); break; - case CPUINFO_STR_REGISTER + SH4_R0: sprintf(info->s, "R0 :%08X", sh4.r[ 0]); break; - case CPUINFO_STR_REGISTER + SH4_R1: sprintf(info->s, "R1 :%08X", sh4.r[ 1]); break; - case CPUINFO_STR_REGISTER + SH4_R2: sprintf(info->s, "R2 :%08X", sh4.r[ 2]); break; - case CPUINFO_STR_REGISTER + SH4_R3: sprintf(info->s, "R3 :%08X", sh4.r[ 3]); break; - case CPUINFO_STR_REGISTER + SH4_R4: sprintf(info->s, "R4 :%08X", sh4.r[ 4]); break; - case CPUINFO_STR_REGISTER + SH4_R5: sprintf(info->s, "R5 :%08X", sh4.r[ 5]); break; - case CPUINFO_STR_REGISTER + SH4_R6: sprintf(info->s, "R6 :%08X", sh4.r[ 6]); break; - case CPUINFO_STR_REGISTER + SH4_R7: sprintf(info->s, "R7 :%08X", sh4.r[ 7]); break; - case CPUINFO_STR_REGISTER + SH4_R8: sprintf(info->s, "R8 :%08X", sh4.r[ 8]); break; - case CPUINFO_STR_REGISTER + SH4_R9: sprintf(info->s, "R9 :%08X", sh4.r[ 9]); break; - case CPUINFO_STR_REGISTER + SH4_R10: sprintf(info->s, "R10 :%08X", sh4.r[10]); break; - case CPUINFO_STR_REGISTER + SH4_R11: sprintf(info->s, "R11 :%08X", sh4.r[11]); break; - case CPUINFO_STR_REGISTER + SH4_R12: sprintf(info->s, "R12 :%08X", sh4.r[12]); break; - case CPUINFO_STR_REGISTER + SH4_R13: sprintf(info->s, "R13 :%08X", sh4.r[13]); break; - case CPUINFO_STR_REGISTER + SH4_R14: sprintf(info->s, "R14 :%08X", sh4.r[14]); break; - case CPUINFO_STR_REGISTER + SH4_R15: sprintf(info->s, "R15 :%08X", sh4.r[15]); break; - case CPUINFO_STR_REGISTER + SH4_EA: sprintf(info->s, "EA :%08X", sh4.ea); break; - case CPUINFO_STR_REGISTER + SH4_R0_BK0: sprintf(info->s, "R0 BK 0 :%08X", sh4.rbnk[0][0]); break; - case CPUINFO_STR_REGISTER + SH4_R1_BK0: sprintf(info->s, "R1 BK 0 :%08X", sh4.rbnk[0][1]); break; - case CPUINFO_STR_REGISTER + SH4_R2_BK0: sprintf(info->s, "R2 BK 0 :%08X", sh4.rbnk[0][2]); break; - case CPUINFO_STR_REGISTER + SH4_R3_BK0: sprintf(info->s, "R3 BK 0 :%08X", sh4.rbnk[0][3]); break; - case CPUINFO_STR_REGISTER + SH4_R4_BK0: sprintf(info->s, "R4 BK 0 :%08X", sh4.rbnk[0][4]); break; - case CPUINFO_STR_REGISTER + SH4_R5_BK0: sprintf(info->s, "R5 BK 0 :%08X", sh4.rbnk[0][5]); break; - case CPUINFO_STR_REGISTER + SH4_R6_BK0: sprintf(info->s, "R6 BK 0 :%08X", sh4.rbnk[0][6]); break; - case CPUINFO_STR_REGISTER + SH4_R7_BK0: sprintf(info->s, "R7 BK 0 :%08X", sh4.rbnk[0][7]); break; - case CPUINFO_STR_REGISTER + SH4_R0_BK1: sprintf(info->s, "R0 BK 1 :%08X", sh4.rbnk[1][0]); break; - case CPUINFO_STR_REGISTER + SH4_R1_BK1: sprintf(info->s, "R1 BK 1 :%08X", sh4.rbnk[1][1]); break; - case CPUINFO_STR_REGISTER + SH4_R2_BK1: sprintf(info->s, "R2 BK 1 :%08X", sh4.rbnk[1][2]); break; - case CPUINFO_STR_REGISTER + SH4_R3_BK1: sprintf(info->s, "R3 BK 1 :%08X", sh4.rbnk[1][3]); break; - case CPUINFO_STR_REGISTER + SH4_R4_BK1: sprintf(info->s, "R4 BK 1 :%08X", sh4.rbnk[1][4]); break; - case CPUINFO_STR_REGISTER + SH4_R5_BK1: sprintf(info->s, "R5 BK 1 :%08X", sh4.rbnk[1][5]); break; - case CPUINFO_STR_REGISTER + SH4_R6_BK1: sprintf(info->s, "R6 BK 1 :%08X", sh4.rbnk[1][6]); break; - case CPUINFO_STR_REGISTER + SH4_R7_BK1: sprintf(info->s, "R7 BK 1 :%08X", sh4.rbnk[1][7]); break; - case CPUINFO_STR_REGISTER + SH4_SPC: sprintf(info->s, "SPC :%08X", sh4.spc); break; - case CPUINFO_STR_REGISTER + SH4_SSR: sprintf(info->s, "SSR :%08X", sh4.ssr); break; - case CPUINFO_STR_REGISTER + SH4_SGR: sprintf(info->s, "SGR :%08X", sh4.sgr); break; - case CPUINFO_STR_REGISTER + SH4_FPSCR: sprintf(info->s, "FPSCR :%08X", sh4.fpscr); break; - case CPUINFO_STR_REGISTER + SH4_FPUL: sprintf(info->s, "FPUL :%08X", sh4.fpul); break; + case CPUINFO_STR_REGISTER + SH4_PC: sprintf(info->s, "PC :%08X", sh4->pc); break; + case CPUINFO_STR_REGISTER + SH4_SR: sprintf(info->s, "SR :%08X", sh4->sr); break; + case CPUINFO_STR_REGISTER + SH4_PR: sprintf(info->s, "PR :%08X", sh4->pr); break; + case CPUINFO_STR_REGISTER + SH4_GBR: sprintf(info->s, "GBR :%08X", sh4->gbr); break; + case CPUINFO_STR_REGISTER + SH4_VBR: sprintf(info->s, "VBR :%08X", sh4->vbr); break; + case CPUINFO_STR_REGISTER + SH4_DBR: sprintf(info->s, "DBR :%08X", sh4->dbr); break; + case CPUINFO_STR_REGISTER + SH4_MACH: sprintf(info->s, "MACH:%08X", sh4->mach); break; + case CPUINFO_STR_REGISTER + SH4_MACL: sprintf(info->s, "MACL:%08X", sh4->macl); break; + case CPUINFO_STR_REGISTER + SH4_R0: sprintf(info->s, "R0 :%08X", sh4->r[ 0]); break; + case CPUINFO_STR_REGISTER + SH4_R1: sprintf(info->s, "R1 :%08X", sh4->r[ 1]); break; + case CPUINFO_STR_REGISTER + SH4_R2: sprintf(info->s, "R2 :%08X", sh4->r[ 2]); break; + case CPUINFO_STR_REGISTER + SH4_R3: sprintf(info->s, "R3 :%08X", sh4->r[ 3]); break; + case CPUINFO_STR_REGISTER + SH4_R4: sprintf(info->s, "R4 :%08X", sh4->r[ 4]); break; + case CPUINFO_STR_REGISTER + SH4_R5: sprintf(info->s, "R5 :%08X", sh4->r[ 5]); break; + case CPUINFO_STR_REGISTER + SH4_R6: sprintf(info->s, "R6 :%08X", sh4->r[ 6]); break; + case CPUINFO_STR_REGISTER + SH4_R7: sprintf(info->s, "R7 :%08X", sh4->r[ 7]); break; + case CPUINFO_STR_REGISTER + SH4_R8: sprintf(info->s, "R8 :%08X", sh4->r[ 8]); break; + case CPUINFO_STR_REGISTER + SH4_R9: sprintf(info->s, "R9 :%08X", sh4->r[ 9]); break; + case CPUINFO_STR_REGISTER + SH4_R10: sprintf(info->s, "R10 :%08X", sh4->r[10]); break; + case CPUINFO_STR_REGISTER + SH4_R11: sprintf(info->s, "R11 :%08X", sh4->r[11]); break; + case CPUINFO_STR_REGISTER + SH4_R12: sprintf(info->s, "R12 :%08X", sh4->r[12]); break; + case CPUINFO_STR_REGISTER + SH4_R13: sprintf(info->s, "R13 :%08X", sh4->r[13]); break; + case CPUINFO_STR_REGISTER + SH4_R14: sprintf(info->s, "R14 :%08X", sh4->r[14]); break; + case CPUINFO_STR_REGISTER + SH4_R15: sprintf(info->s, "R15 :%08X", sh4->r[15]); break; + case CPUINFO_STR_REGISTER + SH4_EA: sprintf(info->s, "EA :%08X", sh4->ea); break; + case CPUINFO_STR_REGISTER + SH4_R0_BK0: sprintf(info->s, "R0 BK 0 :%08X", sh4->rbnk[0][0]); break; + case CPUINFO_STR_REGISTER + SH4_R1_BK0: sprintf(info->s, "R1 BK 0 :%08X", sh4->rbnk[0][1]); break; + case CPUINFO_STR_REGISTER + SH4_R2_BK0: sprintf(info->s, "R2 BK 0 :%08X", sh4->rbnk[0][2]); break; + case CPUINFO_STR_REGISTER + SH4_R3_BK0: sprintf(info->s, "R3 BK 0 :%08X", sh4->rbnk[0][3]); break; + case CPUINFO_STR_REGISTER + SH4_R4_BK0: sprintf(info->s, "R4 BK 0 :%08X", sh4->rbnk[0][4]); break; + case CPUINFO_STR_REGISTER + SH4_R5_BK0: sprintf(info->s, "R5 BK 0 :%08X", sh4->rbnk[0][5]); break; + case CPUINFO_STR_REGISTER + SH4_R6_BK0: sprintf(info->s, "R6 BK 0 :%08X", sh4->rbnk[0][6]); break; + case CPUINFO_STR_REGISTER + SH4_R7_BK0: sprintf(info->s, "R7 BK 0 :%08X", sh4->rbnk[0][7]); break; + case CPUINFO_STR_REGISTER + SH4_R0_BK1: sprintf(info->s, "R0 BK 1 :%08X", sh4->rbnk[1][0]); break; + case CPUINFO_STR_REGISTER + SH4_R1_BK1: sprintf(info->s, "R1 BK 1 :%08X", sh4->rbnk[1][1]); break; + case CPUINFO_STR_REGISTER + SH4_R2_BK1: sprintf(info->s, "R2 BK 1 :%08X", sh4->rbnk[1][2]); break; + case CPUINFO_STR_REGISTER + SH4_R3_BK1: sprintf(info->s, "R3 BK 1 :%08X", sh4->rbnk[1][3]); break; + case CPUINFO_STR_REGISTER + SH4_R4_BK1: sprintf(info->s, "R4 BK 1 :%08X", sh4->rbnk[1][4]); break; + case CPUINFO_STR_REGISTER + SH4_R5_BK1: sprintf(info->s, "R5 BK 1 :%08X", sh4->rbnk[1][5]); break; + case CPUINFO_STR_REGISTER + SH4_R6_BK1: sprintf(info->s, "R6 BK 1 :%08X", sh4->rbnk[1][6]); break; + case CPUINFO_STR_REGISTER + SH4_R7_BK1: sprintf(info->s, "R7 BK 1 :%08X", sh4->rbnk[1][7]); break; + case CPUINFO_STR_REGISTER + SH4_SPC: sprintf(info->s, "SPC :%08X", sh4->spc); break; + case CPUINFO_STR_REGISTER + SH4_SSR: sprintf(info->s, "SSR :%08X", sh4->ssr); break; + case CPUINFO_STR_REGISTER + SH4_SGR: sprintf(info->s, "SGR :%08X", sh4->sgr); break; + case CPUINFO_STR_REGISTER + SH4_FPSCR: sprintf(info->s, "FPSCR :%08X", sh4->fpscr); break; + case CPUINFO_STR_REGISTER + SH4_FPUL: sprintf(info->s, "FPUL :%08X", sh4->fpul); break; #ifdef LSB_FIRST case CPUINFO_STR_REGISTER + SH4_FR0: sprintf(info->s, "FR0 :%08X %f", FP_RS2( 0),(double)FP_RFS2( 0)); break; case CPUINFO_STR_REGISTER + SH4_FR1: sprintf(info->s, "FR1 :%08X %f", FP_RS2( 1),(double)FP_RFS2( 1)); break; @@ -3847,7 +3837,7 @@ CPU_GET_INFO( sh4 ) case CPUINFO_STR_REGISTER + SH4_XF14: sprintf(info->s, "XF14 :%08X %f", FP_XS(14),(double)FP_XFS(14)); break; case CPUINFO_STR_REGISTER + SH4_XF15: sprintf(info->s, "XF15 :%08X %f", FP_XS(15),(double)FP_XFS(15)); break; //%01.2e #endif - case CPUINFO_PTR_SH4_FTCSR_READ_CALLBACK: info->f = (genf*)sh4.ftcsr_read_callback; break; + case CPUINFO_PTR_SH4_FTCSR_READ_CALLBACK: info->f = (genf*)sh4->ftcsr_read_callback; break; } } diff --git a/src/emu/cpu/sh4/sh4.h b/src/emu/cpu/sh4/sh4.h index 769ceb1d9d2..0bd0db5d861 100644 --- a/src/emu/cpu/sh4/sh4.h +++ b/src/emu/cpu/sh4/sh4.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * sh4.h + * sh4->h * Portable Hitachi SH-4 (SH7750 family) emulator interface * * By R. Belmont, based on sh2.c by Juergen Buchmueller, Mariusz Wojcieszek, diff --git a/src/emu/cpu/sh4/sh4comn.c b/src/emu/cpu/sh4/sh4comn.c index 140d7141372..c929aee7337 100644 --- a/src/emu/cpu/sh4/sh4comn.c +++ b/src/emu/cpu/sh4/sh4comn.c @@ -13,8 +13,6 @@ #include "sh4regs.h" #include "sh4comn.h" -SH4 sh4; - static const int tcnt_div[8] = { 4, 16, 64, 256, 1024, 1, 1, 1 }; static const int rtcnt_div[8] = { 0, 4, 16, 64, 256, 1024, 2048, 4096 }; static const int daysmonth[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; @@ -33,7 +31,7 @@ static const UINT16 tcnt[] = { TCNT0, TCNT1, TCNT2 }; static const UINT16 tcor[] = { TCOR0, TCOR1, TCOR2 }; static const UINT16 tcr[] = { TCR0, TCR1, TCR2 }; -void sh4_change_register_bank(int to) +void sh4_change_register_bank(SH4 *sh4, int to) { int s; @@ -41,192 +39,192 @@ int s; { for (s = 0;s < 8;s++) { - sh4.rbnk[0][s] = sh4.r[s]; - sh4.r[s] = sh4.rbnk[1][s]; + sh4->rbnk[0][s] = sh4->r[s]; + sh4->r[s] = sh4->rbnk[1][s]; } } else // 1 -> 0 { for (s = 0;s < 8;s++) { - sh4.rbnk[1][s] = sh4.r[s]; - sh4.r[s] = sh4.rbnk[0][s]; + sh4->rbnk[1][s] = sh4->r[s]; + sh4->r[s] = sh4->rbnk[0][s]; } } } -void sh4_swap_fp_registers(void) +void sh4_swap_fp_registers(SH4 *sh4) { int s; UINT32 z; for (s = 0;s <= 15;s++) { - z = sh4.fr[s]; - sh4.fr[s] = sh4.xf[s]; - sh4.xf[s] = z; + z = sh4->fr[s]; + sh4->fr[s] = sh4->xf[s]; + sh4->xf[s] = z; } } #ifdef LSB_FIRST -void sh4_swap_fp_couples(void) +void sh4_swap_fp_couples(SH4 *sh4) { int s; UINT32 z; for (s = 0;s <= 15;s = s+2) { - z = sh4.fr[s]; - sh4.fr[s] = sh4.fr[s + 1]; - sh4.fr[s + 1] = z; - z = sh4.xf[s]; - sh4.xf[s] = sh4.xf[s + 1]; - sh4.xf[s + 1] = z; + z = sh4->fr[s]; + sh4->fr[s] = sh4->fr[s + 1]; + sh4->fr[s + 1] = z; + z = sh4->xf[s]; + sh4->xf[s] = sh4->xf[s + 1]; + sh4->xf[s + 1] = z; } } #endif -void sh4_syncronize_register_bank(int to) +void sh4_syncronize_register_bank(SH4 *sh4, int to) { int s; for (s = 0;s < 8;s++) { - sh4.rbnk[to][s] = sh4.r[s]; + sh4->rbnk[to][s] = sh4->r[s]; } } -void sh4_default_exception_priorities(void) // setup default priorities for exceptions +void sh4_default_exception_priorities(SH4 *sh4) // setup default priorities for exceptions { int a; for (a=0;a <= SH4_INTC_NMI;a++) - sh4.exception_priority[a] = exception_priority_default[a]; + sh4->exception_priority[a] = exception_priority_default[a]; for (a=SH4_INTC_IRLn0;a <= SH4_INTC_IRLnE;a++) - sh4.exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a); - sh4.exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0); - sh4.exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1); - sh4.exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2); - sh4.exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3); + sh4->exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a); + sh4->exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0); + sh4->exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1); + sh4->exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2); + sh4->exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3); for (a=SH4_INTC_HUDI;a <= SH4_INTC_ROVI;a++) - sh4.exception_priority[a] = INTPRI(0, a); + sh4->exception_priority[a] = INTPRI(0, a); } -void sh4_exception_recompute(void) // checks if there is any interrupt with high enough priority +void sh4_exception_recompute(SH4 *sh4) // checks if there is any interrupt with high enough priority { int a,z; - sh4.test_irq = 0; - if ((!sh4.pending_irq) || ((sh4.sr & BL) && (sh4.exception_requesting[SH4_INTC_NMI] == 0))) + sh4->test_irq = 0; + if ((!sh4->pending_irq) || ((sh4->sr & BL) && (sh4->exception_requesting[SH4_INTC_NMI] == 0))) return; - z = (sh4.sr >> 4) & 15; + z = (sh4->sr >> 4) & 15; for (a=0;a <= SH4_INTC_ROVI;a++) { - if (sh4.exception_requesting[a]) - if ((((int)sh4.exception_priority[a] >> 8) & 255) > z) + if (sh4->exception_requesting[a]) + if ((((int)sh4->exception_priority[a] >> 8) & 255) > z) { - sh4.test_irq = 1; // will check for exception at end of instructions + sh4->test_irq = 1; // will check for exception at end of instructions break; } } } -void sh4_exception_request(int exception) // start requesting an exception +void sh4_exception_request(SH4 *sh4, int exception) // start requesting an exception { - if (!sh4.exception_requesting[exception]) + if (!sh4->exception_requesting[exception]) { - sh4.exception_requesting[exception] = 1; - sh4.pending_irq++; - sh4_exception_recompute(); + sh4->exception_requesting[exception] = 1; + sh4->pending_irq++; + sh4_exception_recompute(sh4); } } -void sh4_exception_unrequest(int exception) // stop requesting an exception +void sh4_exception_unrequest(SH4 *sh4, int exception) // stop requesting an exception { - if (sh4.exception_requesting[exception]) + if (sh4->exception_requesting[exception]) { - sh4.exception_requesting[exception] = 0; - sh4.pending_irq--; - sh4_exception_recompute(); + sh4->exception_requesting[exception] = 0; + sh4->pending_irq--; + sh4_exception_recompute(sh4); } } -void sh4_exception_checkunrequest(int exception) +void sh4_exception_checkunrequest(SH4 *sh4, int exception) { if (exception == SH4_INTC_NMI) - sh4_exception_unrequest(exception); + sh4_exception_unrequest(sh4, exception); if ((exception == SH4_INTC_DMTE0) || (exception == SH4_INTC_DMTE1) || (exception == SH4_INTC_DMTE2) || (exception == SH4_INTC_DMTE3)) - sh4_exception_unrequest(exception); + sh4_exception_unrequest(sh4, exception); } -void sh4_exception(const char *message, int exception) // handle exception +void sh4_exception(SH4 *sh4, const char *message, int exception) // handle exception { UINT32 vector; if (exception < SH4_INTC_NMI) return; // Not yet supported if (exception == SH4_INTC_NMI) { - if ((sh4.sr & BL) && (!(sh4.m[ICR] & 0x200))) + if ((sh4->sr & BL) && (!(sh4->m[ICR] & 0x200))) return; - sh4.m[ICR] &= ~0x200; - sh4.m[INTEVT] = 0x1c0; + sh4->m[ICR] &= ~0x200; + sh4->m[INTEVT] = 0x1c0; vector = 0x600; - sh4.irq_callback(sh4.device, INPUT_LINE_NMI); - LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4.device->tag, message)); + sh4->irq_callback(sh4->device, INPUT_LINE_NMI); + LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4->device->tag, message)); } else { -// if ((sh4.m[ICR] & 0x4000) && (sh4.nmi_line_state == ASSERT_LINE)) +// if ((sh4->m[ICR] & 0x4000) && (sh4->nmi_line_state == ASSERT_LINE)) // return; - if (sh4.sr & BL) + if (sh4->sr & BL) return; - if (((sh4.exception_priority[exception] >> 8) & 255) <= ((sh4.sr >> 4) & 15)) + if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15)) return; - sh4.m[INTEVT] = exception_codes[exception]; + sh4->m[INTEVT] = exception_codes[exception]; vector = 0x600; if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3)) - sh4.irq_callback(sh4.device, SH4_INTC_IRL0-exception+SH4_IRL0); + sh4->irq_callback(sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0); else - sh4.irq_callback(sh4.device, SH4_IRL3+1); - LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4.device->tag, exception, message)); + sh4->irq_callback(sh4->device, SH4_IRL3+1); + LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag, exception, message)); } - sh4_exception_checkunrequest(exception); + sh4_exception_checkunrequest(sh4, exception); - sh4.spc = sh4.pc; - sh4.ssr = sh4.sr; - sh4.sgr = sh4.r[15]; + sh4->spc = sh4->pc; + sh4->ssr = sh4->sr; + sh4->sgr = sh4->r[15]; - sh4.sr |= MD; + sh4->sr |= MD; if ((Machine->debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank((sh4.sr & sRB) >> 29); - if (!(sh4.sr & sRB)) - sh4_change_register_bank(1); - sh4.sr |= sRB; - sh4.sr |= BL; - sh4_exception_recompute(); + sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); + if (!(sh4->sr & sRB)) + sh4_change_register_bank(sh4, 1); + sh4->sr |= sRB; + sh4->sr |= BL; + sh4_exception_recompute(sh4); /* fetch PC */ - sh4.pc = sh4.vbr + vector; + sh4->pc = sh4->vbr + vector; } static UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor) { // elapsed:total = x : ticks - // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(sh4.m[RTCSR] >> 3) & 7] - // ticks/total=ticks / ((rtcnt_div[(sh4.m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(sh4.m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(sh4.m[RTCSR] >> 3) & 7] + // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] + // ticks/total=ticks / ((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] return base + (UINT32)((attotime_to_double(timer_timeelapsed(timer)) * (double)hertz) / (double)divisor); } -static void sh4_refresh_timer_recompute(void) +static void sh4_refresh_timer_recompute(SH4 *sh4) { UINT32 ticks; //if rtcnt < rtcor then rtcor-rtcnt //if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt - ticks = sh4.m[RTCOR]-sh4.m[RTCNT]; + ticks = sh4->m[RTCOR]-sh4->m[RTCNT]; if (ticks <= 0) ticks = 256 + ticks; - timer_adjust_oneshot(sh4.refresh_timer, attotime_mul(attotime_mul(ATTOTIME_IN_HZ(sh4.bus_clock), rtcnt_div[(sh4.m[RTCSR] >> 3) & 7]), ticks), sh4.cpu_number); - sh4.refresh_timer_base = sh4.m[RTCNT]; + timer_adjust_oneshot(sh4->refresh_timer, attotime_mul(attotime_mul(ATTOTIME_IN_HZ(sh4->bus_clock), rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]), ticks), 0); + sh4->refresh_timer_base = sh4->m[RTCNT]; } /*------------------------------------------------- @@ -247,47 +245,47 @@ static UINT32 compute_ticks_timer(emu_timer *timer, int hertz, int divisor) return (UINT32)ret; } -static void sh4_timer_recompute(int which) +static void sh4_timer_recompute(SH4 *sh4, int which) { double ticks; - ticks = sh4.m[tcnt[which]]; - timer_adjust_oneshot(sh4.timer[which], sh4_scale_up_mame_time(attotime_mul(ATTOTIME_IN_HZ(sh4.pm_clock), tcnt_div[sh4.m[tcr[which]] & 7]), ticks), sh4.cpu_number); + ticks = sh4->m[tcnt[which]]; + timer_adjust_oneshot(sh4->timer[which], sh4_scale_up_mame_time(attotime_mul(ATTOTIME_IN_HZ(sh4->pm_clock), tcnt_div[sh4->m[tcr[which]] & 7]), ticks), which); } static TIMER_CALLBACK( sh4_refresh_timer_callback ) { - int cpunum = param; + SH4 *sh4 = ptr; - cpu_push_context(machine->cpu[cpunum]); - sh4.m[RTCNT] = 0; - sh4_refresh_timer_recompute(); - sh4.m[RTCSR] |= 128; - if ((sh4.m[MCR] & 4) && !(sh4.m[MCR] & 2)) + cpu_push_context(sh4->device); + sh4->m[RTCNT] = 0; + sh4_refresh_timer_recompute(sh4); + sh4->m[RTCSR] |= 128; + if ((sh4->m[MCR] & 4) && !(sh4->m[MCR] & 2)) { - sh4.m[RFCR] = (sh4.m[RFCR] + 1) & 1023; - if (((sh4.m[RTCSR] & 1) && (sh4.m[RFCR] == 512)) || (sh4.m[RFCR] == 0)) + sh4->m[RFCR] = (sh4->m[RFCR] + 1) & 1023; + if (((sh4->m[RTCSR] & 1) && (sh4->m[RFCR] == 512)) || (sh4->m[RFCR] == 0)) { - sh4.m[RFCR] = 0; - sh4.m[RTCSR] |= 4; + sh4->m[RFCR] = 0; + sh4->m[RTCSR] |= 4; } } cpu_pop_context(); } -static void increment_rtc_time(int mode) +static void increment_rtc_time(SH4 *sh4, int mode) { int carry, year, leap, days; if (mode == 0) { carry = 0; - sh4.m[RSECCNT] = sh4.m[RSECCNT] + 1; - if ((sh4.m[RSECCNT] & 0xf) == 0xa) - sh4.m[RSECCNT] = sh4.m[RSECCNT] + 6; - if (sh4.m[RSECCNT] == 0x60) + sh4->m[RSECCNT] = sh4->m[RSECCNT] + 1; + if ((sh4->m[RSECCNT] & 0xf) == 0xa) + sh4->m[RSECCNT] = sh4->m[RSECCNT] + 6; + if (sh4->m[RSECCNT] == 0x60) { - sh4.m[RSECCNT] = 0; + sh4->m[RSECCNT] = 0; carry=1; } else @@ -296,34 +294,34 @@ static void increment_rtc_time(int mode) else carry = 1; - sh4.m[RMINCNT] = sh4.m[RMINCNT] + carry; - if ((sh4.m[RMINCNT] & 0xf) == 0xa) - sh4.m[RMINCNT] = sh4.m[RMINCNT] + 6; + sh4->m[RMINCNT] = sh4->m[RMINCNT] + carry; + if ((sh4->m[RMINCNT] & 0xf) == 0xa) + sh4->m[RMINCNT] = sh4->m[RMINCNT] + 6; carry=0; - if (sh4.m[RMINCNT] == 0x60) + if (sh4->m[RMINCNT] == 0x60) { - sh4.m[RMINCNT] = 0; + sh4->m[RMINCNT] = 0; carry = 1; } - sh4.m[RHRCNT] = sh4.m[RHRCNT] + carry; - if ((sh4.m[RHRCNT] & 0xf) == 0xa) - sh4.m[RHRCNT] = sh4.m[RHRCNT] + 6; + sh4->m[RHRCNT] = sh4->m[RHRCNT] + carry; + if ((sh4->m[RHRCNT] & 0xf) == 0xa) + sh4->m[RHRCNT] = sh4->m[RHRCNT] + 6; carry = 0; - if (sh4.m[RHRCNT] == 0x24) + if (sh4->m[RHRCNT] == 0x24) { - sh4.m[RHRCNT] = 0; + sh4->m[RHRCNT] = 0; carry = 1; } - sh4.m[RWKCNT] = sh4.m[RWKCNT] + carry; - if (sh4.m[RWKCNT] == 0x7) + sh4->m[RWKCNT] = sh4->m[RWKCNT] + carry; + if (sh4->m[RWKCNT] == 0x7) { - sh4.m[RWKCNT] = 0; + sh4->m[RWKCNT] = 0; } days = 0; - year = (sh4.m[RYRCNT] & 0xf) + ((sh4.m[RYRCNT] & 0xf0) >> 4)*10 + ((sh4.m[RYRCNT] & 0xf00) >> 8)*100 + ((sh4.m[RYRCNT] & 0xf000) >> 12)*1000; + year = (sh4->m[RYRCNT] & 0xf) + ((sh4->m[RYRCNT] & 0xf0) >> 4)*10 + ((sh4->m[RYRCNT] & 0xf00) >> 8)*100 + ((sh4->m[RYRCNT] & 0xf000) >> 12)*1000; leap = 0; if (!(year%100)) { @@ -332,54 +330,54 @@ static void increment_rtc_time(int mode) } else if (!(year%4)) leap = 1; - if (sh4.m[RMONCNT] != 2) + if (sh4->m[RMONCNT] != 2) leap = 0; - if (sh4.m[RMONCNT]) - days = daysmonth[(sh4.m[RMONCNT] & 0xf) + ((sh4.m[RMONCNT] & 0xf0) >> 4)*10 - 1]; + if (sh4->m[RMONCNT]) + days = daysmonth[(sh4->m[RMONCNT] & 0xf) + ((sh4->m[RMONCNT] & 0xf0) >> 4)*10 - 1]; - sh4.m[RDAYCNT] = sh4.m[RDAYCNT] + carry; - if ((sh4.m[RDAYCNT] & 0xf) == 0xa) - sh4.m[RDAYCNT] = sh4.m[RDAYCNT] + 6; + sh4->m[RDAYCNT] = sh4->m[RDAYCNT] + carry; + if ((sh4->m[RDAYCNT] & 0xf) == 0xa) + sh4->m[RDAYCNT] = sh4->m[RDAYCNT] + 6; carry = 0; - if (sh4.m[RDAYCNT] > (days+leap)) + if (sh4->m[RDAYCNT] > (days+leap)) { - sh4.m[RDAYCNT] = 1; + sh4->m[RDAYCNT] = 1; carry = 1; } - sh4.m[RMONCNT] = sh4.m[RMONCNT] + carry; - if ((sh4.m[RMONCNT] & 0xf) == 0xa) - sh4.m[RMONCNT] = sh4.m[RMONCNT] + 6; + sh4->m[RMONCNT] = sh4->m[RMONCNT] + carry; + if ((sh4->m[RMONCNT] & 0xf) == 0xa) + sh4->m[RMONCNT] = sh4->m[RMONCNT] + 6; carry=0; - if (sh4.m[RMONCNT] == 0x13) + if (sh4->m[RMONCNT] == 0x13) { - sh4.m[RMONCNT] = 1; + sh4->m[RMONCNT] = 1; carry = 1; } - sh4.m[RYRCNT] = sh4.m[RYRCNT] + carry; - if ((sh4.m[RYRCNT] & 0xf) >= 0xa) - sh4.m[RYRCNT] = sh4.m[RYRCNT] + 6; - if ((sh4.m[RYRCNT] & 0xf0) >= 0xa0) - sh4.m[RYRCNT] = sh4.m[RYRCNT] + 0x60; - if ((sh4.m[RYRCNT] & 0xf00) >= 0xa00) - sh4.m[RYRCNT] = sh4.m[RYRCNT] + 0x600; - if ((sh4.m[RYRCNT] & 0xf000) >= 0xa000) - sh4.m[RYRCNT] = 0; + sh4->m[RYRCNT] = sh4->m[RYRCNT] + carry; + if ((sh4->m[RYRCNT] & 0xf) >= 0xa) + sh4->m[RYRCNT] = sh4->m[RYRCNT] + 6; + if ((sh4->m[RYRCNT] & 0xf0) >= 0xa0) + sh4->m[RYRCNT] = sh4->m[RYRCNT] + 0x60; + if ((sh4->m[RYRCNT] & 0xf00) >= 0xa00) + sh4->m[RYRCNT] = sh4->m[RYRCNT] + 0x600; + if ((sh4->m[RYRCNT] & 0xf000) >= 0xa000) + sh4->m[RYRCNT] = 0; } static TIMER_CALLBACK( sh4_rtc_timer_callback ) { - int cpunum = param; + SH4 *sh4 = ptr; - cpu_push_context(machine->cpu[cpunum]); - timer_adjust_oneshot(sh4.rtc_timer, ATTOTIME_IN_HZ(128), cpunum); - sh4.m[R64CNT] = (sh4.m[R64CNT]+1) & 0x7f; - if (sh4.m[R64CNT] == 64) + cpu_push_context(sh4->device); + timer_adjust_oneshot(sh4->rtc_timer, ATTOTIME_IN_HZ(128), 0); + sh4->m[R64CNT] = (sh4->m[R64CNT]+1) & 0x7f; + if (sh4->m[R64CNT] == 64) { - sh4.m[RCR1] |= 0x80; - increment_rtc_time(0); - //sh4_exception_request(SH4_INTC_NMI); // TEST + sh4->m[RCR1] |= 0x80; + increment_rtc_time(sh4, 0); + //sh4_exception_request(sh4, SH4_INTC_NMI); // TEST } cpu_pop_context(); } @@ -387,58 +385,58 @@ static TIMER_CALLBACK( sh4_rtc_timer_callback ) static TIMER_CALLBACK( sh4_timer_callback ) { static const UINT16 tuni[] = { SH4_INTC_TUNI0, SH4_INTC_TUNI1, SH4_INTC_TUNI2 }; - int which = (int)(FPTR)ptr; - int cpunum = param; + SH4 *sh4 = ptr; + int which = param; int idx = tcr[which]; - cpu_push_context(machine->cpu[cpunum]); - sh4.m[tcnt[which]] = sh4.m[tcor[which]]; - sh4_timer_recompute(which); - sh4.m[idx] = sh4.m[idx] | 0x100; - if (sh4.m[idx] & 0x20) - sh4_exception_request(tuni[which]); + cpu_push_context(sh4->device); + sh4->m[tcnt[which]] = sh4->m[tcor[which]]; + sh4_timer_recompute(sh4, which); + sh4->m[idx] = sh4->m[idx] | 0x100; + if (sh4->m[idx] & 0x20) + sh4_exception_request(sh4, tuni[which]); cpu_pop_context(); } static TIMER_CALLBACK( sh4_dmac_callback ) { - int cpunum = param >> 8; - int channel = param & 255; + SH4 *sh4 = ptr; + int channel = param; - cpu_push_context(machine->cpu[cpunum]); - LOG(("SH4.%d: DMA %d complete\n", cpunum, channel)); - sh4.dma_timer_active[channel] = 0; + cpu_push_context(sh4->device); + LOG(("SH4 '%s': DMA %d complete\n", sh4->device->tag, channel)); + sh4->dma_timer_active[channel] = 0; switch (channel) { case 0: - sh4.m[DMATCR0] = 0; - sh4.m[CHCR0] |= 2; - if (sh4.m[CHCR0] & 4) - sh4_exception_request(SH4_INTC_DMTE0); + sh4->m[DMATCR0] = 0; + sh4->m[CHCR0] |= 2; + if (sh4->m[CHCR0] & 4) + sh4_exception_request(sh4, SH4_INTC_DMTE0); break; case 1: - sh4.m[DMATCR1] = 0; - sh4.m[CHCR1] |= 2; - if (sh4.m[CHCR1] & 4) - sh4_exception_request(SH4_INTC_DMTE1); + sh4->m[DMATCR1] = 0; + sh4->m[CHCR1] |= 2; + if (sh4->m[CHCR1] & 4) + sh4_exception_request(sh4, SH4_INTC_DMTE1); break; case 2: - sh4.m[DMATCR2] = 0; - sh4.m[CHCR2] |= 2; - if (sh4.m[CHCR2] & 4) - sh4_exception_request(SH4_INTC_DMTE2); + sh4->m[DMATCR2] = 0; + sh4->m[CHCR2] |= 2; + if (sh4->m[CHCR2] & 4) + sh4_exception_request(sh4, SH4_INTC_DMTE2); break; case 3: - sh4.m[DMATCR3] = 0; - sh4.m[CHCR3] |= 2; - if (sh4.m[CHCR3] & 4) - sh4_exception_request(SH4_INTC_DMTE3); + sh4->m[DMATCR3] = 0; + sh4->m[CHCR3] |= 2; + if (sh4->m[CHCR3] & 4) + sh4_exception_request(sh4, SH4_INTC_DMTE3); break; } cpu_pop_context(); } -static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) +static int sh4_dma_transfer(SH4 *sh4, int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) { int incs, incd, size; UINT32 src, dst, count; @@ -461,13 +459,13 @@ static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar if (timermode == 1) { - sh4.dma_timer_active[channel] = 1; - timer_adjust_oneshot(sh4.dma_timer[channel], cpu_clocks_to_attotime(sh4.device, 2*count+1), (sh4.cpu_number << 8) | channel); + sh4->dma_timer_active[channel] = 1; + timer_adjust_oneshot(sh4->dma_timer[channel], cpu_clocks_to_attotime(sh4->device, 2*count+1), channel); } else if (timermode == 2) { - sh4.dma_timer_active[channel] = 1; - timer_adjust_oneshot(sh4.dma_timer[channel], attotime_zero, (sh4.cpu_number << 8) | channel); + sh4->dma_timer_active[channel] = 1; + timer_adjust_oneshot(sh4->dma_timer[channel], attotime_zero, channel); } src &= AM; @@ -482,7 +480,7 @@ static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar src --; if(incd == 2) dst --; - memory_write_byte_64le(sh4.program, dst, memory_read_byte_64le(sh4.program, src)); + memory_write_byte_64le(sh4->program, dst, memory_read_byte_64le(sh4->program, src)); if(incs == 1) src ++; if(incd == 1) @@ -498,7 +496,7 @@ static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar src -= 2; if(incd == 2) dst -= 2; - memory_write_word_64le(sh4.program, dst, memory_read_word_64le(sh4.program, src)); + memory_write_word_64le(sh4->program, dst, memory_read_word_64le(sh4->program, src)); if(incs == 1) src += 2; if(incd == 1) @@ -514,7 +512,7 @@ static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar src -= 8; if(incd == 2) dst -= 8; - memory_write_qword_64le(sh4.program, dst, memory_read_qword_64le(sh4.program, src)); + memory_write_qword_64le(sh4->program, dst, memory_read_qword_64le(sh4->program, src)); if(incs == 1) src += 8; if(incd == 1) @@ -531,7 +529,7 @@ static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar src -= 4; if(incd == 2) dst -= 4; - memory_write_dword_64le(sh4.program, dst, memory_read_dword_64le(sh4.program, src)); + memory_write_dword_64le(sh4->program, dst, memory_read_dword_64le(sh4->program, src)); if(incs == 1) src += 4; if(incd == 1) @@ -548,10 +546,10 @@ static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar src -= 32; if(incd == 2) dst -= 32; - memory_write_qword_64le(sh4.program, dst, memory_read_qword_64le(sh4.program, src)); - memory_write_qword_64le(sh4.program, dst+8, memory_read_qword_64le(sh4.program, src+8)); - memory_write_qword_64le(sh4.program, dst+16, memory_read_qword_64le(sh4.program, src+16)); - memory_write_qword_64le(sh4.program, dst+24, memory_read_qword_64le(sh4.program, src+24)); + memory_write_qword_64le(sh4->program, dst, memory_read_qword_64le(sh4->program, src)); + memory_write_qword_64le(sh4->program, dst+8, memory_read_qword_64le(sh4->program, src+8)); + memory_write_qword_64le(sh4->program, dst+16, memory_read_qword_64le(sh4->program, src+16)); + memory_write_qword_64le(sh4->program, dst+24, memory_read_qword_64le(sh4->program, src+24)); if(incs == 1) src += 32; if(incd == 1) @@ -565,78 +563,79 @@ static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar return 1; } -static void sh4_dmac_check(int channel) +static void sh4_dmac_check(SH4 *sh4, int channel) { UINT32 dmatcr,chcr,sar,dar; switch (channel) { case 0: - sar = sh4.m[SAR0]; - dar = sh4.m[DAR0]; - chcr = sh4.m[CHCR0]; - dmatcr = sh4.m[DMATCR0]; + sar = sh4->m[SAR0]; + dar = sh4->m[DAR0]; + chcr = sh4->m[CHCR0]; + dmatcr = sh4->m[DMATCR0]; break; case 1: - sar = sh4.m[SAR1]; - dar = sh4.m[DAR1]; - chcr = sh4.m[CHCR1]; - dmatcr = sh4.m[DMATCR1]; + sar = sh4->m[SAR1]; + dar = sh4->m[DAR1]; + chcr = sh4->m[CHCR1]; + dmatcr = sh4->m[DMATCR1]; break; case 2: - sar = sh4.m[SAR2]; - dar = sh4.m[DAR2]; - chcr = sh4.m[CHCR2]; - dmatcr = sh4.m[DMATCR2]; + sar = sh4->m[SAR2]; + dar = sh4->m[DAR2]; + chcr = sh4->m[CHCR2]; + dmatcr = sh4->m[DMATCR2]; break; case 3: - sar = sh4.m[SAR3]; - dar = sh4.m[DAR3]; - chcr = sh4.m[CHCR3]; - dmatcr = sh4.m[DMATCR3]; + sar = sh4->m[SAR3]; + dar = sh4->m[DAR3]; + chcr = sh4->m[CHCR3]; + dmatcr = sh4->m[DMATCR3]; break; default: return; } - if (chcr & sh4.m[DMAOR] & 1) + if (chcr & sh4->m[DMAOR] & 1) { if ((((chcr >> 8) & 15) < 4) || (((chcr >> 8) & 15) > 6)) return; - if (!sh4.dma_timer_active[channel] && !(chcr & 2) && !(sh4.m[DMAOR] & 6)) - sh4_dma_transfer(channel, 1, chcr, &sar, &dar, &dmatcr); + if (!sh4->dma_timer_active[channel] && !(chcr & 2) && !(sh4->m[DMAOR] & 6)) + sh4_dma_transfer(sh4, channel, 1, chcr, &sar, &dar, &dmatcr); } else { - if (sh4.dma_timer_active[channel]) + if (sh4->dma_timer_active[channel]) { logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel); - timer_adjust_oneshot(sh4.dma_timer[channel], attotime_never, 0); - sh4.dma_timer_active[channel] = 0; + timer_adjust_oneshot(sh4->dma_timer[channel], attotime_never, channel); + sh4->dma_timer_active[channel] = 0; } } } -static void sh4_dmac_nmi(void) // manage dma when nmi +static void sh4_dmac_nmi(SH4 *sh4) // manage dma when nmi { int s; - sh4.m[DMAOR] |= 2; // nmif = 1 + sh4->m[DMAOR] |= 2; // nmif = 1 for (s = 0;s < 4;s++) { - if (sh4.dma_timer_active[s]) + if (sh4->dma_timer_active[s]) { logerror("SH4: DMA %d cancelled due to NMI but all data transferred", s); - timer_adjust_oneshot(sh4.dma_timer[s], attotime_never, 0); - sh4.dma_timer_active[s] = 0; + timer_adjust_oneshot(sh4->dma_timer[s], attotime_never, s); + sh4->dma_timer_active[s] = 0; } } } WRITE32_HANDLER( sh4_internal_w ) { + SH4 *sh4 = space->cpu->token; int a; - UINT32 old = sh4.m[offset]; - COMBINE_DATA(sh4.m+offset); + UINT32 old = sh4->m[offset]; + COMBINE_DATA(sh4->m+offset); // logerror("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask); @@ -644,192 +643,192 @@ WRITE32_HANDLER( sh4_internal_w ) { // Memory refresh case RTCSR: - sh4.m[RTCSR] &= 255; + sh4->m[RTCSR] &= 255; if ((old >> 3) & 7) - sh4.m[RTCNT] = compute_ticks_refresh_timer(sh4.refresh_timer, sh4.bus_clock, sh4.refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff; - if ((sh4.m[RTCSR] >> 3) & 7) + sh4->m[RTCNT] = compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff; + if ((sh4->m[RTCSR] >> 3) & 7) { // activated - sh4_refresh_timer_recompute(); + sh4_refresh_timer_recompute(sh4); } else { - timer_adjust_oneshot(sh4.refresh_timer, attotime_never, 0); + timer_adjust_oneshot(sh4->refresh_timer, attotime_never, 0); } break; case RTCNT: - sh4.m[RTCNT] &= 255; - if ((sh4.m[RTCSR] >> 3) & 7) + sh4->m[RTCNT] &= 255; + if ((sh4->m[RTCSR] >> 3) & 7) { // active - sh4_refresh_timer_recompute(); + sh4_refresh_timer_recompute(sh4); } break; case RTCOR: - sh4.m[RTCOR] &= 255; - if ((sh4.m[RTCSR] >> 3) & 7) + sh4->m[RTCOR] &= 255; + if ((sh4->m[RTCSR] >> 3) & 7) { // active - sh4.m[RTCNT] = compute_ticks_refresh_timer(sh4.refresh_timer, sh4.bus_clock, sh4.refresh_timer_base, rtcnt_div[(sh4.m[RTCSR] >> 3) & 7]) & 0xff; - sh4_refresh_timer_recompute(); + sh4->m[RTCNT] = compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff; + sh4_refresh_timer_recompute(sh4); } break; case RFCR: - sh4.m[RFCR] &= 1023; + sh4->m[RFCR] &= 1023; break; // RTC case RCR1: - if ((sh4.m[RCR1] & 8) && (~old & 8)) // 0 -> 1 - sh4.m[RCR1] ^= 1; + if ((sh4->m[RCR1] & 8) && (~old & 8)) // 0 -> 1 + sh4->m[RCR1] ^= 1; break; case RCR2: - if (sh4.m[RCR2] & 2) + if (sh4->m[RCR2] & 2) { - sh4.m[R64CNT] = 0; - sh4.m[RCR2] ^= 2; + sh4->m[R64CNT] = 0; + sh4->m[RCR2] ^= 2; } - if (sh4.m[RCR2] & 4) + if (sh4->m[RCR2] & 4) { - sh4.m[R64CNT] = 0; - if (sh4.m[RSECCNT] >= 30) - increment_rtc_time(1); - sh4.m[RSECCNT] = 0; + sh4->m[R64CNT] = 0; + if (sh4->m[RSECCNT] >= 30) + increment_rtc_time(sh4, 1); + sh4->m[RSECCNT] = 0; } - if ((sh4.m[RCR2] & 8) && (~old & 8)) + if ((sh4->m[RCR2] & 8) && (~old & 8)) { // 0 -> 1 - timer_adjust_oneshot(sh4.rtc_timer, ATTOTIME_IN_HZ(128), sh4.cpu_number); + timer_adjust_oneshot(sh4->rtc_timer, ATTOTIME_IN_HZ(128), 0); } - else if (~(sh4.m[RCR2]) & 8) + else if (~(sh4->m[RCR2]) & 8) { // 0 - timer_adjust_oneshot(sh4.rtc_timer, attotime_never, 0); + timer_adjust_oneshot(sh4->rtc_timer, attotime_never, 0); } break; // TMU case TSTR: if (old & 1) - sh4.m[TCNT0] = compute_ticks_timer(sh4.timer[0], sh4.pm_clock, tcnt_div[sh4.m[TCR0] & 7]); - if ((sh4.m[TSTR] & 1) == 0) { - timer_adjust_oneshot(sh4.timer[0], attotime_never, 0); + sh4->m[TCNT0] = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->m[TCR0] & 7]); + if ((sh4->m[TSTR] & 1) == 0) { + timer_adjust_oneshot(sh4->timer[0], attotime_never, 0); } else - sh4_timer_recompute(0); + sh4_timer_recompute(sh4, 0); if (old & 2) - sh4.m[TCNT1] = compute_ticks_timer(sh4.timer[1], sh4.pm_clock, tcnt_div[sh4.m[TCR1] & 7]); - if ((sh4.m[TSTR] & 2) == 0) { - timer_adjust_oneshot(sh4.timer[1], attotime_never, 0); + sh4->m[TCNT1] = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->m[TCR1] & 7]); + if ((sh4->m[TSTR] & 2) == 0) { + timer_adjust_oneshot(sh4->timer[1], attotime_never, 0); } else - sh4_timer_recompute(1); + sh4_timer_recompute(sh4, 1); if (old & 4) - sh4.m[TCNT2] = compute_ticks_timer(sh4.timer[2], sh4.pm_clock, tcnt_div[sh4.m[TCR2] & 7]); - if ((sh4.m[TSTR] & 4) == 0) { - timer_adjust_oneshot(sh4.timer[2], attotime_never, 0); + sh4->m[TCNT2] = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->m[TCR2] & 7]); + if ((sh4->m[TSTR] & 4) == 0) { + timer_adjust_oneshot(sh4->timer[2], attotime_never, 0); } else - sh4_timer_recompute(2); + sh4_timer_recompute(sh4, 2); break; case TCR0: - if (sh4.m[TSTR] & 1) + if (sh4->m[TSTR] & 1) { - sh4.m[TCNT0] = compute_ticks_timer(sh4.timer[0], sh4.pm_clock, tcnt_div[old & 7]); - sh4_timer_recompute(0); + sh4->m[TCNT0] = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[old & 7]); + sh4_timer_recompute(sh4, 0); } - if (!(sh4.m[TCR0] & 0x20) || !(sh4.m[TCR0] & 0x100)) - sh4_exception_unrequest(SH4_INTC_TUNI0); + if (!(sh4->m[TCR0] & 0x20) || !(sh4->m[TCR0] & 0x100)) + sh4_exception_unrequest(sh4, SH4_INTC_TUNI0); break; case TCR1: - if (sh4.m[TSTR] & 2) + if (sh4->m[TSTR] & 2) { - sh4.m[TCNT1] = compute_ticks_timer(sh4.timer[1], sh4.pm_clock, tcnt_div[old & 7]); - sh4_timer_recompute(1); + sh4->m[TCNT1] = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[old & 7]); + sh4_timer_recompute(sh4, 1); } - if (!(sh4.m[TCR1] & 0x20) || !(sh4.m[TCR1] & 0x100)) - sh4_exception_unrequest(SH4_INTC_TUNI1); + if (!(sh4->m[TCR1] & 0x20) || !(sh4->m[TCR1] & 0x100)) + sh4_exception_unrequest(sh4, SH4_INTC_TUNI1); break; case TCR2: - if (sh4.m[TSTR] & 4) + if (sh4->m[TSTR] & 4) { - sh4.m[TCNT2] = compute_ticks_timer(sh4.timer[2], sh4.pm_clock, tcnt_div[old & 7]); - sh4_timer_recompute(2); + sh4->m[TCNT2] = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[old & 7]); + sh4_timer_recompute(sh4, 2); } - if (!(sh4.m[TCR2] & 0x20) || !(sh4.m[TCR2] & 0x100)) - sh4_exception_unrequest(SH4_INTC_TUNI2); + if (!(sh4->m[TCR2] & 0x20) || !(sh4->m[TCR2] & 0x100)) + sh4_exception_unrequest(sh4, SH4_INTC_TUNI2); break; case TCOR0: - if (sh4.m[TSTR] & 1) + if (sh4->m[TSTR] & 1) { - sh4.m[TCNT0] = compute_ticks_timer(sh4.timer[0], sh4.pm_clock, tcnt_div[sh4.m[TCR0] & 7]); - sh4_timer_recompute(0); + sh4->m[TCNT0] = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->m[TCR0] & 7]); + sh4_timer_recompute(sh4, 0); } break; case TCNT0: - if (sh4.m[TSTR] & 1) - sh4_timer_recompute(0); + if (sh4->m[TSTR] & 1) + sh4_timer_recompute(sh4, 0); break; case TCOR1: - if (sh4.m[TSTR] & 2) + if (sh4->m[TSTR] & 2) { - sh4.m[TCNT1] = compute_ticks_timer(sh4.timer[1], sh4.pm_clock, tcnt_div[sh4.m[TCR1] & 7]); - sh4_timer_recompute(1); + sh4->m[TCNT1] = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->m[TCR1] & 7]); + sh4_timer_recompute(sh4, 1); } break; case TCNT1: - if (sh4.m[TSTR] & 2) - sh4_timer_recompute(1); + if (sh4->m[TSTR] & 2) + sh4_timer_recompute(sh4, 1); break; case TCOR2: - if (sh4.m[TSTR] & 4) + if (sh4->m[TSTR] & 4) { - sh4.m[TCNT2] = compute_ticks_timer(sh4.timer[2], sh4.pm_clock, tcnt_div[sh4.m[TCR2] & 7]); - sh4_timer_recompute(2); + sh4->m[TCNT2] = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->m[TCR2] & 7]); + sh4_timer_recompute(sh4, 2); } break; case TCNT2: - if (sh4.m[TSTR] & 4) - sh4_timer_recompute(2); + if (sh4->m[TSTR] & 4) + sh4_timer_recompute(sh4, 2); break; // INTC case ICR: - sh4.m[ICR] = (sh4.m[ICR] & 0x7fff) | (old & 0x8000); + sh4->m[ICR] = (sh4->m[ICR] & 0x7fff) | (old & 0x8000); break; case IPRA: - sh4.exception_priority[SH4_INTC_ATI] = INTPRI(sh4.m[IPRA] & 0x000f, SH4_INTC_ATI); - sh4.exception_priority[SH4_INTC_PRI] = INTPRI(sh4.m[IPRA] & 0x000f, SH4_INTC_PRI); - sh4.exception_priority[SH4_INTC_CUI] = INTPRI(sh4.m[IPRA] & 0x000f, SH4_INTC_CUI); - sh4.exception_priority[SH4_INTC_TUNI2] = INTPRI((sh4.m[IPRA] & 0x00f0) >> 4, SH4_INTC_TUNI2); - sh4.exception_priority[SH4_INTC_TICPI2] = INTPRI((sh4.m[IPRA] & 0x00f0) >> 4, SH4_INTC_TICPI2); - sh4.exception_priority[SH4_INTC_TUNI1] = INTPRI((sh4.m[IPRA] & 0x0f00) >> 8, SH4_INTC_TUNI1); - sh4.exception_priority[SH4_INTC_TUNI0] = INTPRI((sh4.m[IPRA] & 0xf000) >> 12, SH4_INTC_TUNI0); - sh4_exception_recompute(); + sh4->exception_priority[SH4_INTC_ATI] = INTPRI(sh4->m[IPRA] & 0x000f, SH4_INTC_ATI); + sh4->exception_priority[SH4_INTC_PRI] = INTPRI(sh4->m[IPRA] & 0x000f, SH4_INTC_PRI); + sh4->exception_priority[SH4_INTC_CUI] = INTPRI(sh4->m[IPRA] & 0x000f, SH4_INTC_CUI); + sh4->exception_priority[SH4_INTC_TUNI2] = INTPRI((sh4->m[IPRA] & 0x00f0) >> 4, SH4_INTC_TUNI2); + sh4->exception_priority[SH4_INTC_TICPI2] = INTPRI((sh4->m[IPRA] & 0x00f0) >> 4, SH4_INTC_TICPI2); + sh4->exception_priority[SH4_INTC_TUNI1] = INTPRI((sh4->m[IPRA] & 0x0f00) >> 8, SH4_INTC_TUNI1); + sh4->exception_priority[SH4_INTC_TUNI0] = INTPRI((sh4->m[IPRA] & 0xf000) >> 12, SH4_INTC_TUNI0); + sh4_exception_recompute(sh4); break; case IPRB: - sh4.exception_priority[SH4_INTC_SCI1ERI] = INTPRI((sh4.m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI); - sh4.exception_priority[SH4_INTC_SCI1RXI] = INTPRI((sh4.m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI); - sh4.exception_priority[SH4_INTC_SCI1TXI] = INTPRI((sh4.m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI); - sh4.exception_priority[SH4_INTC_SCI1TEI] = INTPRI((sh4.m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI); - sh4.exception_priority[SH4_INTC_RCMI] = INTPRI((sh4.m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI); - sh4.exception_priority[SH4_INTC_ROVI] = INTPRI((sh4.m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI); - sh4.exception_priority[SH4_INTC_ITI] = INTPRI((sh4.m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI); - sh4_exception_recompute(); + sh4->exception_priority[SH4_INTC_SCI1ERI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI); + sh4->exception_priority[SH4_INTC_SCI1RXI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI); + sh4->exception_priority[SH4_INTC_SCI1TXI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI); + sh4->exception_priority[SH4_INTC_SCI1TEI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI); + sh4->exception_priority[SH4_INTC_RCMI] = INTPRI((sh4->m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI); + sh4->exception_priority[SH4_INTC_ROVI] = INTPRI((sh4->m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI); + sh4->exception_priority[SH4_INTC_ITI] = INTPRI((sh4->m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI); + sh4_exception_recompute(sh4); break; case IPRC: - sh4.exception_priority[SH4_INTC_HUDI] = INTPRI(sh4.m[IPRC] & 0x000f, SH4_INTC_HUDI); - sh4.exception_priority[SH4_INTC_SCIFERI] = INTPRI((sh4.m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI); - sh4.exception_priority[SH4_INTC_SCIFRXI] = INTPRI((sh4.m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI); - sh4.exception_priority[SH4_INTC_SCIFBRI] = INTPRI((sh4.m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI); - sh4.exception_priority[SH4_INTC_SCIFTXI] = INTPRI((sh4.m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI); - sh4.exception_priority[SH4_INTC_DMTE0] = INTPRI((sh4.m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0); - sh4.exception_priority[SH4_INTC_DMTE1] = INTPRI((sh4.m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1); - sh4.exception_priority[SH4_INTC_DMTE2] = INTPRI((sh4.m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2); - sh4.exception_priority[SH4_INTC_DMTE3] = INTPRI((sh4.m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3); - sh4.exception_priority[SH4_INTC_DMAE] = INTPRI((sh4.m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE); - sh4.exception_priority[SH4_INTC_GPOI] = INTPRI((sh4.m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI); - sh4_exception_recompute(); + sh4->exception_priority[SH4_INTC_HUDI] = INTPRI(sh4->m[IPRC] & 0x000f, SH4_INTC_HUDI); + sh4->exception_priority[SH4_INTC_SCIFERI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI); + sh4->exception_priority[SH4_INTC_SCIFRXI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI); + sh4->exception_priority[SH4_INTC_SCIFBRI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI); + sh4->exception_priority[SH4_INTC_SCIFTXI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI); + sh4->exception_priority[SH4_INTC_DMTE0] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0); + sh4->exception_priority[SH4_INTC_DMTE1] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1); + sh4->exception_priority[SH4_INTC_DMTE2] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2); + sh4->exception_priority[SH4_INTC_DMTE3] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3); + sh4->exception_priority[SH4_INTC_DMAE] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE); + sh4->exception_priority[SH4_INTC_GPOI] = INTPRI((sh4->m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI); + sh4_exception_recompute(sh4); break; // DMA @@ -847,26 +846,26 @@ WRITE32_HANDLER( sh4_internal_w ) case DMATCR3: break; case CHCR0: - sh4_dmac_check(0); + sh4_dmac_check(sh4, 0); break; case CHCR1: - sh4_dmac_check(1); + sh4_dmac_check(sh4, 1); break; case CHCR2: - sh4_dmac_check(2); + sh4_dmac_check(sh4, 2); break; case CHCR3: - sh4_dmac_check(3); + sh4_dmac_check(sh4, 3); break; case DMAOR: - if ((sh4.m[DMAOR] & 4) && (~old & 4)) - sh4.m[DMAOR] &= ~4; - if ((sh4.m[DMAOR] & 2) && (~old & 2)) - sh4.m[DMAOR] &= ~2; - sh4_dmac_check(0); - sh4_dmac_check(1); - sh4_dmac_check(2); - sh4_dmac_check(3); + if ((sh4->m[DMAOR] & 4) && (~old & 4)) + sh4->m[DMAOR] &= ~4; + if ((sh4->m[DMAOR] & 2) && (~old & 2)) + sh4->m[DMAOR] &= ~2; + sh4_dmac_check(sh4, 0); + sh4_dmac_check(sh4, 1); + sh4_dmac_check(sh4, 2); + sh4_dmac_check(sh4, 3); break; // Store Queues @@ -876,36 +875,36 @@ WRITE32_HANDLER( sh4_internal_w ) // I/O ports case PCTRA: - sh4.ioport16_pullup = 0; - sh4.ioport16_direction = 0; + sh4->ioport16_pullup = 0; + sh4->ioport16_direction = 0; for (a=0;a < 16;a++) { - sh4.ioport16_direction |= (sh4.m[PCTRA] & (1 << (a*2))) >> a; - sh4.ioport16_pullup |= (sh4.m[PCTRA] & (1 << (a*2+1))) >> (a+1); + sh4->ioport16_direction |= (sh4->m[PCTRA] & (1 << (a*2))) >> a; + sh4->ioport16_pullup |= (sh4->m[PCTRA] & (1 << (a*2+1))) >> (a+1); } - sh4.ioport16_direction &= 0xffff; - sh4.ioport16_pullup = (sh4.ioport16_pullup | sh4.ioport16_direction) ^ 0xffff; - if (sh4.m[BCR2] & 1) - memory_write_dword_64le(sh4.io, SH4_IOPORT_16, (UINT64)(sh4.m[PDTRA] & sh4.ioport16_direction) | ((UINT64)sh4.m[PCTRA] << 16)); + sh4->ioport16_direction &= 0xffff; + sh4->ioport16_pullup = (sh4->ioport16_pullup | sh4->ioport16_direction) ^ 0xffff; + if (sh4->m[BCR2] & 1) + memory_write_dword_64le(sh4->io, SH4_IOPORT_16, (UINT64)(sh4->m[PDTRA] & sh4->ioport16_direction) | ((UINT64)sh4->m[PCTRA] << 16)); break; case PDTRA: - if (sh4.m[BCR2] & 1) - memory_write_dword_64le(sh4.io, SH4_IOPORT_16, (UINT64)(sh4.m[PDTRA] & sh4.ioport16_direction) | ((UINT64)sh4.m[PCTRA] << 16)); + if (sh4->m[BCR2] & 1) + memory_write_dword_64le(sh4->io, SH4_IOPORT_16, (UINT64)(sh4->m[PDTRA] & sh4->ioport16_direction) | ((UINT64)sh4->m[PCTRA] << 16)); break; case PCTRB: - sh4.ioport4_pullup = 0; - sh4.ioport4_direction = 0; + sh4->ioport4_pullup = 0; + sh4->ioport4_direction = 0; for (a=0;a < 4;a++) { - sh4.ioport4_direction |= (sh4.m[PCTRB] & (1 << (a*2))) >> a; - sh4.ioport4_pullup |= (sh4.m[PCTRB] & (1 << (a*2+1))) >> (a+1); + sh4->ioport4_direction |= (sh4->m[PCTRB] & (1 << (a*2))) >> a; + sh4->ioport4_pullup |= (sh4->m[PCTRB] & (1 << (a*2+1))) >> (a+1); } - sh4.ioport4_direction &= 0xf; - sh4.ioport4_pullup = (sh4.ioport4_pullup | sh4.ioport4_direction) ^ 0xf; - if (sh4.m[BCR2] & 1) - memory_write_dword_64le(sh4.io, SH4_IOPORT_4, (sh4.m[PDTRB] & sh4.ioport4_direction) | (sh4.m[PCTRB] << 16)); + sh4->ioport4_direction &= 0xf; + sh4->ioport4_pullup = (sh4->ioport4_pullup | sh4->ioport4_direction) ^ 0xf; + if (sh4->m[BCR2] & 1) + memory_write_dword_64le(sh4->io, SH4_IOPORT_4, (sh4->m[PDTRB] & sh4->ioport4_direction) | (sh4->m[PCTRB] << 16)); break; case PDTRB: - if (sh4.m[BCR2] & 1) - memory_write_dword_64le(sh4.io, SH4_IOPORT_4, (sh4.m[PDTRB] & sh4.ioport4_direction) | (sh4.m[PCTRB] << 16)); + if (sh4->m[BCR2] & 1) + memory_write_dword_64le(sh4->io, SH4_IOPORT_4, (sh4->m[PDTRB] & sh4->ioport4_direction) | (sh4->m[PCTRB] << 16)); break; case SCBRR2: @@ -919,54 +918,57 @@ WRITE32_HANDLER( sh4_internal_w ) READ32_HANDLER( sh4_internal_r ) { + SH4 *sh4 = space->cpu->token; // logerror("sh4_internal_r: Read %08x (%x) @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, mem_mask); switch( offset ) { case RTCNT: - if ((sh4.m[RTCSR] >> 3) & 7) + if ((sh4->m[RTCSR] >> 3) & 7) { // activated - //((double)rtcnt_div[(sh4.m[RTCSR] >> 3) & 7] / (double)100000000) - //return (refresh_timer_base + (timer_timeelapsed(sh4.refresh_timer) * (double)100000000) / (double)rtcnt_div[(sh4.m[RTCSR] >> 3) & 7]) & 0xff; - return compute_ticks_refresh_timer(sh4.refresh_timer, sh4.bus_clock, sh4.refresh_timer_base, rtcnt_div[(sh4.m[RTCSR] >> 3) & 7]) & 0xff; + //((double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / (double)100000000) + //return (refresh_timer_base + (timer_timeelapsed(sh4->refresh_timer) * (double)100000000) / (double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff; + return compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff; } else - return sh4.m[RTCNT]; + return sh4->m[RTCNT]; break; case TCNT0: - if (sh4.m[TSTR] & 1) - return compute_ticks_timer(sh4.timer[0], sh4.pm_clock, tcnt_div[sh4.m[TCR0] & 7]); + if (sh4->m[TSTR] & 1) + return compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->m[TCR0] & 7]); else - return sh4.m[TCNT0]; + return sh4->m[TCNT0]; break; case TCNT1: - if (sh4.m[TSTR] & 2) - return compute_ticks_timer(sh4.timer[1], sh4.pm_clock, tcnt_div[sh4.m[TCR1] & 7]); + if (sh4->m[TSTR] & 2) + return compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->m[TCR1] & 7]); else - return sh4.m[TCNT1]; + return sh4->m[TCNT1]; break; case TCNT2: - if (sh4.m[TSTR] & 4) - return compute_ticks_timer(sh4.timer[2], sh4.pm_clock, tcnt_div[sh4.m[TCR2] & 7]); + if (sh4->m[TSTR] & 4) + return compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->m[TCR2] & 7]); else - return sh4.m[TCNT2]; + return sh4->m[TCNT2]; break; // I/O ports case PDTRA: - if (sh4.m[BCR2] & 1) - return (memory_read_dword_64le(sh4.io, SH4_IOPORT_16) & ~sh4.ioport16_direction) | (sh4.m[PDTRA] & sh4.ioport16_direction); + if (sh4->m[BCR2] & 1) + return (memory_read_dword_64le(sh4->io, SH4_IOPORT_16) & ~sh4->ioport16_direction) | (sh4->m[PDTRA] & sh4->ioport16_direction); break; case PDTRB: - if (sh4.m[BCR2] & 1) - return (memory_read_dword_64le(sh4.io, SH4_IOPORT_4) & ~sh4.ioport4_direction) | (sh4.m[PDTRB] & sh4.ioport4_direction); + if (sh4->m[BCR2] & 1) + return (memory_read_dword_64le(sh4->io, SH4_IOPORT_4) & ~sh4->ioport4_direction) | (sh4->m[PDTRB] & sh4->ioport4_direction); break; } - return sh4.m[offset]; + return sh4->m[offset]; } void sh4_set_frt_input(const device_config *device, int state) { + SH4 *sh4 = device->token; + if(state == PULSE_LINE) { sh4_set_frt_input(device, ASSERT_LINE); @@ -976,14 +978,14 @@ void sh4_set_frt_input(const device_config *device, int state) cpu_push_context(device); - if(sh4.frt_input == state) { + if(sh4->frt_input == state) { cpu_pop_context(); return; } - sh4.frt_input = state; + sh4->frt_input = state; - if(sh4.m[5] & 0x8000) { + if(sh4->m[5] & 0x8000) { if(state == CLEAR_LINE) { cpu_pop_context(); return; @@ -997,9 +999,9 @@ void sh4_set_frt_input(const device_config *device, int state) #if 0 sh4_timer_resync(); - sh4.icr = sh4.frc; - sh4.m[4] |= ICF; - logerror("SH4.%d: ICF activated (%x)\n", sh4.cpu_number, sh4.pc & AM); + sh4->icr = sh4->frc; + sh4->m[4] |= ICF; + logerror("SH4 '%s': ICF activated (%x)\n", sh4->device->tag, sh4->pc & AM); sh4_recalc_irq(); #endif cpu_pop_context(); @@ -1007,228 +1009,232 @@ void sh4_set_frt_input(const device_config *device, int state) void sh4_set_irln_input(const device_config *device, int value) { - if (sh4.irln == value) + SH4 *sh4 = device->token; + + if (sh4->irln == value) return; - sh4.irln = value; - cpu_set_input_line(device, SH4_IRLn, PULSE_LINE); + sh4->irln = value; + cpu_set_input_line(device, SH4_IRLn, ASSERT_LINE); + cpu_set_input_line(device, SH4_IRLn, CLEAR_LINE); } -void sh4_set_irq_line(int irqline, int state) // set state of external interrupt line +void sh4_set_irq_line(SH4 *sh4, int irqline, int state) // set state of external interrupt line { -int s; + int s; if (irqline == INPUT_LINE_NMI) { - if (sh4.nmi_line_state == state) + if (sh4->nmi_line_state == state) return; - if (sh4.m[ICR] & 0x100) + if (sh4->m[ICR] & 0x100) { - if ((state == CLEAR_LINE) && (sh4.nmi_line_state == ASSERT_LINE)) // rising + if ((state == CLEAR_LINE) && (sh4->nmi_line_state == ASSERT_LINE)) // rising { - LOG(("SH-4 '%s' assert nmi\n", sh4.device->tag)); - sh4_exception_request(SH4_INTC_NMI); - sh4_dmac_nmi(); + LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag)); + sh4_exception_request(sh4, SH4_INTC_NMI); + sh4_dmac_nmi(sh4); } } else { - if ((state == ASSERT_LINE) && (sh4.nmi_line_state == CLEAR_LINE)) // falling + if ((state == ASSERT_LINE) && (sh4->nmi_line_state == CLEAR_LINE)) // falling { - LOG(("SH-4 '%s' assert nmi\n", sh4.device->tag)); - sh4_exception_request(SH4_INTC_NMI); - sh4_dmac_nmi(); + LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag)); + sh4_exception_request(sh4, SH4_INTC_NMI); + sh4_dmac_nmi(sh4); } } if (state == CLEAR_LINE) - sh4.m[ICR] ^= 0x8000; + sh4->m[ICR] ^= 0x8000; else - sh4.m[ICR] |= 0x8000; - sh4.nmi_line_state = state; + sh4->m[ICR] |= 0x8000; + sh4->nmi_line_state = state; } else { - if (sh4.m[ICR] & 0x80) // four independent external interrupt sources + if (sh4->m[ICR] & 0x80) // four independent external interrupt sources { if (irqline > SH4_IRL3) return; - if (sh4.irq_line_state[irqline] == state) + if (sh4->irq_line_state[irqline] == state) return; - sh4.irq_line_state[irqline] = state; + sh4->irq_line_state[irqline] = state; if( state == CLEAR_LINE ) { - LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4.device->tag, irqline)); - sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0); + LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4->device->tag, irqline)); + sh4_exception_unrequest(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0); } else { - LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4.device->tag, irqline)); - sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0); + LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag, irqline)); + sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0); } } else // level-encoded interrupt { if (irqline != SH4_IRLn) return; - if ((sh4.irln > 15) || (sh4.irln < 0)) + if ((sh4->irln > 15) || (sh4->irln < 0)) return; for (s = 0; s < 15; s++) - sh4_exception_unrequest(SH4_INTC_IRLn0+s); - if (sh4.irln < 15) - sh4_exception_request(SH4_INTC_IRLn0+sh4.irln); - LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4.device->tag, sh4.irln)); + sh4_exception_unrequest(sh4, SH4_INTC_IRLn0+s); + if (sh4->irln < 15) + sh4_exception_request(sh4, SH4_INTC_IRLn0+sh4->irln); + LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4->device->tag, sh4->irln)); } } - if (sh4.test_irq && (!sh4.delay)) - sh4_check_pending_irq("sh4_set_irq_line"); + if (sh4->test_irq && (!sh4->delay)) + sh4_check_pending_irq(sh4, "sh4_set_irq_line"); } -void sh4_parse_configuration(const struct sh4_config *conf) +void sh4_parse_configuration(SH4 *sh4, const struct sh4_config *conf) { if(conf) { switch((conf->md2 << 2) | (conf->md1 << 1) | (conf->md0)) { case 0: - sh4.cpu_clock = conf->clock; - sh4.bus_clock = conf->clock / 4; - sh4.pm_clock = conf->clock / 4; + sh4->cpu_clock = conf->clock; + sh4->bus_clock = conf->clock / 4; + sh4->pm_clock = conf->clock / 4; break; case 1: - sh4.cpu_clock = conf->clock; - sh4.bus_clock = conf->clock / 6; - sh4.pm_clock = conf->clock / 6; + sh4->cpu_clock = conf->clock; + sh4->bus_clock = conf->clock / 6; + sh4->pm_clock = conf->clock / 6; break; case 2: - sh4.cpu_clock = conf->clock; - sh4.bus_clock = conf->clock / 3; - sh4.pm_clock = conf->clock / 6; + sh4->cpu_clock = conf->clock; + sh4->bus_clock = conf->clock / 3; + sh4->pm_clock = conf->clock / 6; break; case 3: - sh4.cpu_clock = conf->clock; - sh4.bus_clock = conf->clock / 3; - sh4.pm_clock = conf->clock / 6; + sh4->cpu_clock = conf->clock; + sh4->bus_clock = conf->clock / 3; + sh4->pm_clock = conf->clock / 6; break; case 4: - sh4.cpu_clock = conf->clock; - sh4.bus_clock = conf->clock / 2; - sh4.pm_clock = conf->clock / 4; + sh4->cpu_clock = conf->clock; + sh4->bus_clock = conf->clock / 2; + sh4->pm_clock = conf->clock / 4; break; case 5: - sh4.cpu_clock = conf->clock; - sh4.bus_clock = conf->clock / 2; - sh4.pm_clock = conf->clock / 4; + sh4->cpu_clock = conf->clock; + sh4->bus_clock = conf->clock / 2; + sh4->pm_clock = conf->clock / 4; break; } - sh4.is_slave = (~(conf->md7)) & 1; + sh4->is_slave = (~(conf->md7)) & 1; } else { - sh4.cpu_clock = 200000000; - sh4.bus_clock = 100000000; - sh4.pm_clock = 50000000; - sh4.is_slave = 0; + sh4->cpu_clock = 200000000; + sh4->bus_clock = 100000000; + sh4->pm_clock = 50000000; + sh4->is_slave = 0; } } void sh4_common_init(const device_config *device) { + SH4 *sh4 = device->token; int i; for (i=0; i<3; i++) { - sh4.timer[i] = timer_alloc(device->machine, sh4_timer_callback, (void*)(FPTR)i); - timer_adjust_oneshot(sh4.timer[i], attotime_never, 0); + sh4->timer[i] = timer_alloc(device->machine, sh4_timer_callback, sh4); + timer_adjust_oneshot(sh4->timer[i], attotime_never, i); } for (i=0; i<4; i++) { - sh4.dma_timer[i] = timer_alloc(device->machine, sh4_dmac_callback, NULL); - timer_adjust_oneshot(sh4.dma_timer[i], attotime_never, 0); + sh4->dma_timer[i] = timer_alloc(device->machine, sh4_dmac_callback, sh4); + timer_adjust_oneshot(sh4->dma_timer[i], attotime_never, i); } - sh4.refresh_timer = timer_alloc(device->machine, sh4_refresh_timer_callback, NULL); - timer_adjust_oneshot(sh4.refresh_timer, attotime_never, 0); - sh4.refresh_timer_base = 0; + sh4->refresh_timer = timer_alloc(device->machine, sh4_refresh_timer_callback, sh4); + timer_adjust_oneshot(sh4->refresh_timer, attotime_never, 0); + sh4->refresh_timer_base = 0; - sh4.rtc_timer = timer_alloc(device->machine, sh4_rtc_timer_callback, NULL); - timer_adjust_oneshot(sh4.rtc_timer, attotime_never, 0); + sh4->rtc_timer = timer_alloc(device->machine, sh4_rtc_timer_callback, sh4); + timer_adjust_oneshot(sh4->rtc_timer, attotime_never, 0); - sh4.m = auto_malloc(16384*4); + sh4->m = auto_malloc(16384*4); } -void sh4_dma_ddt(struct sh4_ddt_dma *s) +void sh4_dma_ddt(SH4 *sh4, struct sh4_ddt_dma *s) { UINT32 chcr; UINT32 *p32bits; UINT64 *p32bytes; UINT32 pos,len,siz; - if (sh4.dma_timer_active[s->channel]) + if (sh4->dma_timer_active[s->channel]) return; if (s->mode >= 0) { switch (s->channel) { case 0: if (s->mode & 1) - s->source = sh4.m[SAR0]; + s->source = sh4->m[SAR0]; if (s->mode & 2) - sh4.m[SAR0] = s->source; + sh4->m[SAR0] = s->source; if (s->mode & 4) - s->destination = sh4.m[DAR0]; + s->destination = sh4->m[DAR0]; if (s->mode & 8) - sh4.m[DAR0] = s->destination; + sh4->m[DAR0] = s->destination; break; case 1: if (s->mode & 1) - s->source = sh4.m[SAR1]; + s->source = sh4->m[SAR1]; if (s->mode & 2) - sh4.m[SAR1] = s->source; + sh4->m[SAR1] = s->source; if (s->mode & 4) - s->destination = sh4.m[DAR1]; + s->destination = sh4->m[DAR1]; if (s->mode & 8) - sh4.m[DAR1] = s->destination; + sh4->m[DAR1] = s->destination; break; case 2: if (s->mode & 1) - s->source = sh4.m[SAR2]; + s->source = sh4->m[SAR2]; if (s->mode & 2) - sh4.m[SAR2] = s->source; + sh4->m[SAR2] = s->source; if (s->mode & 4) - s->destination = sh4.m[DAR2]; + s->destination = sh4->m[DAR2]; if (s->mode & 8) - sh4.m[DAR2] = s->destination; + sh4->m[DAR2] = s->destination; break; case 3: default: if (s->mode & 1) - s->source = sh4.m[SAR3]; + s->source = sh4->m[SAR3]; if (s->mode & 2) - sh4.m[SAR3] = s->source; + sh4->m[SAR3] = s->source; if (s->mode & 4) - s->destination = sh4.m[DAR3]; + s->destination = sh4->m[DAR3]; if (s->mode & 8) - sh4.m[DAR3] = s->destination; + sh4->m[DAR3] = s->destination; break; } switch (s->channel) { case 0: - chcr = sh4.m[CHCR0]; - len = sh4.m[DMATCR0]; + chcr = sh4->m[CHCR0]; + len = sh4->m[DMATCR0]; break; case 1: - chcr = sh4.m[CHCR1]; - len = sh4.m[DMATCR1]; + chcr = sh4->m[CHCR1]; + len = sh4->m[DMATCR1]; break; case 2: - chcr = sh4.m[CHCR2]; - len = sh4.m[DMATCR2]; + chcr = sh4->m[CHCR2]; + len = sh4->m[DMATCR2]; break; case 3: default: - chcr = sh4.m[CHCR3]; - len = sh4.m[DMATCR3]; + chcr = sh4->m[CHCR3]; + len = sh4->m[DMATCR3]; break; } if ((s->direction) == 0) { @@ -1240,14 +1246,14 @@ UINT32 pos,len,siz; if (siz && (s->size)) if ((len * siz) != (s->length * s->size)) return; - sh4_dma_transfer(s->channel, 0, chcr, &s->source, &s->destination, &len); + sh4_dma_transfer(sh4, s->channel, 0, chcr, &s->source, &s->destination, &len); } else { if (s->size == 4) { if ((s->direction) == 0) { len = s->length; p32bits = (UINT32 *)(s->buffer); for (pos = 0;pos < len;pos++) { - *p32bits = memory_read_dword_64le(sh4.program, s->source); + *p32bits = memory_read_dword_64le(sh4->program, s->source); p32bits++; s->source = s->source + 4; } @@ -1255,7 +1261,7 @@ UINT32 pos,len,siz; len = s->length; p32bits = (UINT32 *)(s->buffer); for (pos = 0;pos < len;pos++) { - memory_write_dword_64le(sh4.program, s->destination, *p32bits); + memory_write_dword_64le(sh4->program, s->destination, *p32bits); p32bits++; s->destination = s->destination + 4; } @@ -1267,9 +1273,9 @@ UINT32 pos,len,siz; p32bytes = (UINT64 *)(s->buffer); for (pos = 0;pos < len;pos++) { #ifdef LSB_FIRST - *p32bytes = memory_read_qword_64le(sh4.program, s->source); + *p32bytes = memory_read_qword_64le(sh4->program, s->source); #else - *p32bytes = memory_read_qword_64be(sh4.program, s->source); + *p32bytes = memory_read_qword_64be(sh4->program, s->source); #endif p32bytes++; s->destination = s->destination + 8; @@ -1279,9 +1285,9 @@ UINT32 pos,len,siz; p32bytes = (UINT64 *)(s->buffer); for (pos = 0;pos < len;pos++) { #ifdef LSB_FIRST - memory_write_qword_64le(sh4.program, s->destination, *p32bytes); + memory_write_qword_64le(sh4->program, s->destination, *p32bytes); #else - memory_write_qword_64be(sh4.program, s->destination, *p32bytes); + memory_write_qword_64be(sh4->program, s->destination, *p32bytes); #endif p32bytes++; s->destination = s->destination + 8; diff --git a/src/emu/cpu/sh4/sh4comn.h b/src/emu/cpu/sh4/sh4comn.h index 2b5c5ba09ae..ed3c541bf40 100644 --- a/src/emu/cpu/sh4/sh4comn.h +++ b/src/emu/cpu/sh4/sh4comn.h @@ -24,17 +24,17 @@ #define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI) #define INTPRI(p,n) EXPPRI(4,2,p,n) -#define FP_RS(r) sh4.fr[(r)] // binary representation of single precision floating point register r -#define FP_RFS(r) *( (float *)(sh4.fr+(r)) ) // single precision floating point register r -#define FP_RFD(r) *( (double *)(sh4.fr+(r)) ) // double precision floating point register r -#define FP_XS(r) sh4.xf[(r)] // binary representation of extended single precision floating point register r -#define FP_XFS(r) *( (float *)(sh4.xf+(r)) ) // single precision extended floating point register r -#define FP_XFD(r) *( (double *)(sh4.xf+(r)) ) // double precision extended floating point register r +#define FP_RS(r) sh4->fr[(r)] // binary representation of single precision floating point register r +#define FP_RFS(r) *( (float *)(sh4->fr+(r)) ) // single precision floating point register r +#define FP_RFD(r) *( (double *)(sh4->fr+(r)) ) // double precision floating point register r +#define FP_XS(r) sh4->xf[(r)] // binary representation of extended single precision floating point register r +#define FP_XFS(r) *( (float *)(sh4->xf+(r)) ) // single precision extended floating point register r +#define FP_XFD(r) *( (double *)(sh4->xf+(r)) ) // double precision extended floating point register r #ifdef LSB_FIRST -#define FP_RS2(r) sh4.fr[(r) ^ sh4.fpu_pr] -#define FP_RFS2(r) *( (float *)(sh4.fr+((r) ^ sh4.fpu_pr)) ) -#define FP_XS2(r) sh4.xf[(r) ^ sh4.fpu_pr] -#define FP_XFS2(r) *( (float *)(sh4.xf+((r) ^ sh4.fpu_pr)) ) +#define FP_RS2(r) sh4->fr[(r) ^ sh4->fpu_pr] +#define FP_RFS2(r) *( (float *)(sh4->fr+((r) ^ sh4->fpu_pr)) ) +#define FP_XS2(r) sh4->xf[(r) ^ sh4->fpu_pr] +#define FP_XFS2(r) *( (float *)(sh4->xf+((r) ^ sh4->fpu_pr)) ) #endif typedef struct @@ -81,7 +81,7 @@ typedef struct int dma_timer_active[4]; int sh4_icount; - int is_slave, cpu_number; + int is_slave; int cpu_clock, bus_clock, pm_clock; int fpu_sz, fpu_pr; int ioport16_pullup, ioport16_direction; @@ -90,8 +90,6 @@ typedef struct void (*ftcsr_read_callback)(UINT32 data); } SH4; -extern SH4 sh4; - enum { ICF = 0x00800000, @@ -126,26 +124,26 @@ enum #define Rn ((opcode>>8)&15) #define Rm ((opcode>>4)&15) -void sh4_exception_recompute(void); // checks if there is any interrupt with high enough priority -void sh4_exception_request(int exception); // start requesting an exception -void sh4_exception_unrequest(int exception); // stop requesting an exception -void sh4_exception_checkunrequest(int exception); -void sh4_exception(const char *message, int exception); // handle exception -void sh4_change_register_bank(int to); -void sh4_syncronize_register_bank(int to); -void sh4_swap_fp_registers(void); -void sh4_default_exception_priorities(void); // setup default priorities for exceptions -void sh4_parse_configuration(const struct sh4_config *conf); -void sh4_dma_ddt(struct sh4_ddt_dma *s); -void sh4_set_irq_line(int irqline, int state); // set state of external interrupt line +void sh4_exception_recompute(SH4 *sh4); // checks if there is any interrupt with high enough priority +void sh4_exception_request(SH4 *sh4, int exception); // start requesting an exception +void sh4_exception_unrequest(SH4 *sh4, int exception); // stop requesting an exception +void sh4_exception_checkunrequest(SH4 *sh4, int exception); +void sh4_exception(SH4 *sh4, const char *message, int exception); // handle exception +void sh4_change_register_bank(SH4 *sh4, int to); +void sh4_syncronize_register_bank(SH4 *sh4, int to); +void sh4_swap_fp_registers(SH4 *sh4); +void sh4_default_exception_priorities(SH4 *sh4); // setup default priorities for exceptions +void sh4_parse_configuration(SH4 *sh4, const struct sh4_config *conf); +void sh4_dma_ddt(SH4 *sh4, struct sh4_ddt_dma *s); +void sh4_set_irq_line(SH4 *sh4, int irqline, int state); // set state of external interrupt line void sh4_set_frt_input(const device_config *device, int state); void sh4_set_irln_input(const device_config *device, int value); #ifdef LSB_FIRST -void sh4_swap_fp_couples(void); +void sh4_swap_fp_couples(SH4 *sh4); #endif void sh4_common_init(const device_config *device); -INLINE void sh4_check_pending_irq(const char *message) // look for highest priority active exception and handle it +INLINE void sh4_check_pending_irq(SH4 *sh4, const char *message) // look for highest priority active exception and handle it { int a,irq,z; @@ -153,18 +151,18 @@ INLINE void sh4_check_pending_irq(const char *message) // look for highest prior z = -1; for (a=0;a <= SH4_INTC_ROVI;a++) { - if (sh4.exception_requesting[a]) + if (sh4->exception_requesting[a]) { - if ((int)sh4.exception_priority[a] > z) + if ((int)sh4->exception_priority[a] > z) { - z = sh4.exception_priority[a]; + z = sh4->exception_priority[a]; irq = a; } } } if (z >= 0) { - sh4_exception(message, irq); + sh4_exception(sh4, message, irq); } }