mirror of
https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
-hd63450: Removed MCFG, nw
-x68k: Some initial driver cleanup, split into separate classes, nw
This commit is contained in:
mooglyguy
parent
8acd61c257
commit
9854bd7f66
@ -228,37 +228,37 @@ ROM_START (fcscsi1)
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ROM_END
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MACHINE_CONFIG_START(vme_fcscsi1_card_device::device_add_mconfig)
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void vme_fcscsi1_card_device::device_add_mconfig(machine_config &config)
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{
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/* basic machine hardware */
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MCFG_DEVICE_ADD("maincpu", M68010, CPU_CRYSTAL / 2) /* 7474 based frequency divide by 2 */
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MCFG_DEVICE_PROGRAM_MAP(fcscsi1_mem)
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MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(vme_fcscsi1_card_device, maincpu_irq_acknowledge_callback)
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M68010(config, m_maincpu, CPU_CRYSTAL / 2); /* 7474 based frequency divide by 2 */
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m_maincpu->set_addrmap(AS_PROGRAM, &vme_fcscsi1_card_device::fcscsi1_mem);
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m_maincpu->set_irq_acknowledge_callback(FUNC(vme_fcscsi1_card_device::maincpu_irq_acknowledge_callback));
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/* FDC */
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MCFG_DEVICE_ADD("fdc", WD1772, PIT_CRYSTAL / 2)
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MCFG_WD_FDC_INTRQ_CALLBACK(WRITE8(*this, vme_fcscsi1_card_device, fdc_irq))
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MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE("mc68450", hd63450_device, drq1_w))
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MCFG_FLOPPY_DRIVE_ADD("fdc:0", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
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MCFG_FLOPPY_DRIVE_ADD("fdc:1", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
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MCFG_FLOPPY_DRIVE_ADD("fdc:2", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
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MCFG_FLOPPY_DRIVE_ADD("fdc:3", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
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WD1772(config, m_fdc, PIT_CRYSTAL / 2);
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m_fdc->intrq_wr_callback().set(FUNC(vme_fcscsi1_card_device::fdc_irq));
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m_fdc->drq_wr_callback().set("mc68450", FUNC(hd63450_device::drq1_w));
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FLOPPY_CONNECTOR(config, "fdc:0", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats);
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FLOPPY_CONNECTOR(config, "fdc:1", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats);
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FLOPPY_CONNECTOR(config, "fdc:2", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats);
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FLOPPY_CONNECTOR(config, "fdc:3", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats);
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/* PIT Parallel Interface and Timer device */
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PIT68230(config, m_pit, PIT_CRYSTAL / 2); /* 7474 based frequency divide by 2 */
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m_pit->pb_out_callback().set(FUNC(vme_fcscsi1_card_device::led_w));
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/* DMAC it is really a M68450 but the HD63850 is upwards compatible */
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MCFG_DEVICE_ADD("mc68450", HD63450, CPU_CRYSTAL / 2) // MC68450 compatible
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MCFG_HD63450_CPU("maincpu")
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MCFG_HD63450_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2))
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MCFG_HD63450_BURST_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50))
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MCFG_HD63450_DMA_END_CB(WRITE8(*this, vme_fcscsi1_card_device, dma_end))
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MCFG_HD63450_DMA_ERROR_CB(WRITE8(*this, vme_fcscsi1_card_device, dma_error))
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//MCFG_HD63450_DMA_READ_0_CB(READ8(*this, vme_fcscsi1_card_device, scsi_read_byte)) // ch 0 = SCSI
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//MCFG_HD63450_DMA_WRITE_0_CB(WRITE8(*this, vme_fcscsi1_card_device, scsi_write_byte))
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MCFG_HD63450_DMA_READ_1_CB(READ8(*this, vme_fcscsi1_card_device, fdc_read_byte)) // ch 1 = fdc
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MCFG_HD63450_DMA_WRITE_1_CB(WRITE8(*this, vme_fcscsi1_card_device, fdc_write_byte))
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MACHINE_CONFIG_END
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HD63450(config, m_dmac, CPU_CRYSTAL / 2, "maincpu"); // MC68450 compatible
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m_dmac->set_clocks(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2));
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m_dmac->set_burst_clocks(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50));
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m_dmac->dma_end().set(FUNC(vme_fcscsi1_card_device::dma_end));
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m_dmac->dma_error().set(FUNC(vme_fcscsi1_card_device::dma_error));
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//m_dmac->dma_read<0>().set(FUNC(vme_fcscsi1_card_device::scsi_read_byte)); // ch 0 = SCSI
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//m_dmac->dma_write<0>().set(FUNC(vme_fcscsi1_card_device::scsi_write_byte));
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m_dmac->dma_read<1>().set(FUNC(vme_fcscsi1_card_device::fdc_read_byte)); // ch 1 = fdc
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m_dmac->dma_write<1>().set(FUNC(vme_fcscsi1_card_device::fdc_write_byte));
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}
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const tiny_rom_entry *vme_fcscsi1_card_device::device_rom_region() const
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{
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@ -8,56 +8,17 @@
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#pragma once
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#define MCFG_HD63450_DMA_END_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_end_callback(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_ERROR_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_error_callback(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_READ_0_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_read_callback<0>(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_READ_1_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_read_callback<1>(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_READ_2_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_read_callback<2>(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_READ_3_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_read_callback<3>(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_0_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_write_callback<0>(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_1_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_write_callback<1>(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_2_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_write_callback<2>(DEVCB_##_devcb);
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#define MCFG_HD63450_DMA_WRITE_3_CB(_devcb) \
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downcast<hd63450_device &>(*device).set_dma_write_callback<3>(DEVCB_##_devcb);
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#define MCFG_HD63450_CPU(_tag) \
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downcast<hd63450_device &>(*device).set_cpu_tag(_tag);
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#define MCFG_HD63450_CLOCKS(_clk1, _clk2, _clk3, _clk4) \
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downcast<hd63450_device &>(*device).set_our_clocks(_clk1, _clk2, _clk3, _clk4);
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#define MCFG_HD63450_BURST_CLOCKS(_clk1, _clk2, _clk3, _clk4) \
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downcast<hd63450_device &>(*device).set_burst_clocks(_clk1, _clk2, _clk3, _clk4);
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class hd63450_device : public device_t
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{
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public:
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hd63450_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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template <typename T>
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hd63450_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cputag)
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: hd63450_device(mconfig, tag, owner, clock)
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{
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set_cpu_tag(std::forward<T>(cputag));
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}
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template <class Object> devcb_base &set_dma_end_callback(Object &&cb) { return m_dma_end.set_callback(std::forward<Object>(cb)); }
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template <class Object> devcb_base &set_dma_error_callback(Object &&cb) { return m_dma_error.set_callback(std::forward<Object>(cb)); }
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template <int Ch, class Object> devcb_base &set_dma_read_callback(Object &&cb) { return m_dma_read[Ch].set_callback(std::forward<Object>(cb)); }
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template <int Ch, class Object> devcb_base &set_dma_write_callback(Object &&cb) { return m_dma_write[Ch].set_callback(std::forward<Object>(cb)); }
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hd63450_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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auto dma_end() { return m_dma_end.bind(); }
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auto dma_error() { return m_dma_error.bind(); }
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@ -65,7 +26,7 @@ public:
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template<int Ch> auto dma_write() { return m_dma_write[Ch].bind(); }
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template <typename T> void set_cpu_tag(T &&cpu_tag) { m_cpu.set_tag(std::forward<T>(cpu_tag)); }
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void set_our_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const attotime &clk4)
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void set_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const attotime &clk4)
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{
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m_our_clock[0] = clk1;
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m_our_clock[1] = clk2;
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@ -25,24 +25,6 @@
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#include "dirtc.h"
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//**************************************************************************
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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#define MCFG_RP5C15_OUT_ALARM_CB(_devcb) \
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downcast<rp5c15_device &>(*device).set_out_alarm_callback(DEVCB_##_devcb);
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#define MCFG_RP5C15_OUT_CLKOUT_CB(_devcb) \
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downcast<rp5c15_device &>(*device).set_out_clkout_callback(DEVCB_##_devcb);
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> rp5c15_device
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class rp5c15_device : public device_t,
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public device_rtc_interface
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{
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@ -52,6 +34,8 @@ public:
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template <class Object> devcb_base &set_out_alarm_callback(Object &&cb) { return m_out_alarm_cb.set_callback(std::forward<Object>(cb)); }
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template <class Object> devcb_base &set_out_clkout_callback(Object &&cb) { return m_out_clkout_cb.set_callback(std::forward<Object>(cb)); }
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auto alarm() { return m_out_alarm_cb.bind(); }
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auto clkout() { return m_out_clkout_cb.bind(); }
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DECLARE_READ8_MEMBER( read );
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DECLARE_WRITE8_MEMBER( write );
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@ -441,7 +441,9 @@ protected:
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class upd765a_device : public upd765_family_device {
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public:
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upd765a_device(const machine_config &mconfig, const char *tag, device_t *owner, bool ready, bool select) : upd765a_device(mconfig, tag, owner, 0U) {
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upd765a_device(const machine_config &mconfig, const char *tag, device_t *owner, bool ready, bool select)
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: upd765a_device(mconfig, tag, owner, 0U)
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{
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set_ready_line_connected(ready);
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set_select_lines_connected(select);
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}
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@ -507,6 +509,13 @@ public:
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class upd72065_device : public upd765_family_device {
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public:
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upd72065_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, bool ready, bool select)
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: upd72065_device(mconfig, tag, owner, clock)
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{
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set_ready_line_connected(ready);
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set_select_lines_connected(select);
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}
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upd72065_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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virtual void map(address_map &map) override;
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@ -681,7 +681,7 @@ void esq5505_state::eps(machine_config &config)
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HD63450(config, m_dmac, 10_MHz_XTAL); // MC68450 compatible
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m_dmac->set_cpu_tag(m_maincpu);
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m_dmac->set_our_clocks(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2));
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m_dmac->set_clocks(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2));
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m_dmac->set_burst_clocks(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50));
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m_dmac->dma_end().set(FUNC(esq5505_state::dma_end));
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m_dmac->dma_error().set(FUNC(esq5505_state::dma_error));
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@ -98,8 +98,7 @@ MACHINE_CONFIG_START(harriet_state::harriet)
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//mfp.out_tco_cb().set("mfp", FUNC(mc68901_device::rc_w));
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//mfp.out_tdo_cb().set("mfp", FUNC(mc68901_device::tc_w));
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MCFG_DEVICE_ADD("dmac", HD63450, 40_MHz_XTAL / 4) // MC68450R10 (or HD68450Y-10)
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MCFG_HD63450_CPU("maincpu")
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HD63450(config, "dmac", 40_MHz_XTAL / 4, "maincpu"); // MC68450R10 (or HD68450Y-10)
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MCFG_DEVICE_ADD("timekpr", M48T02, 0)
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NVRAM(config, "zpram", nvram_device::DEFAULT_ALL_0); // MK48Z02
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@ -1821,8 +1821,8 @@ MACHINE_CONFIG_START(mz2500_state::mz2500)
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Z80SIO(config, "z80sio", 6000000);
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MCFG_DEVICE_ADD(RP5C15_TAG, RP5C15, 32.768_kHz_XTAL)
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MCFG_RP5C15_OUT_ALARM_CB(WRITELINE(*this, mz2500_state, mz2500_rtc_alarm_irq))
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RP5C15(config, m_rtc, 32.768_kHz_XTAL);
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m_rtc->alarm().set(FUNC(mz2500_state::mz2500_rtc_alarm_irq));
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MCFG_DEVICE_ADD("pit", PIT8253, 0)
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MCFG_PIT8253_CLK0(31250)
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@ -1788,10 +1788,10 @@ void pet_state::base_pet_devices(machine_config &config, const char *default_dri
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quickload.set_handler(snapquick_load_delegate(&QUICKLOAD_LOAD_NAME(pet_state, cbm_pet), this), "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS);
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quickload.set_interface("cbm_quik");
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SOFTWARE_LIST(config, "cass_list").set_type("pet_cass", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "flop_list").set_type("pet_flop", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "hdd_list").set_type("pet_hdd", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "quik_list").set_type("pet_quik", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "cass_list").set_original("pet_cass");
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SOFTWARE_LIST(config, "flop_list").set_original("pet_flop");
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SOFTWARE_LIST(config, "hdd_list").set_original("pet_hdd");
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SOFTWARE_LIST(config, "quik_list").set_original("pet_quik");
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}
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void pet_state::pet(machine_config &config)
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@ -1840,7 +1840,7 @@ void pet_state::pet2001n(machine_config &config, bool with_b000)
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if (with_b000)
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GENERIC_CARTSLOT(config, "cart_b000", generic_linear_slot, "pet_b000_rom", "bin,rom");
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SOFTWARE_LIST(config, "rom_list").set_type("pet_rom", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "rom_list").set_original("pet_rom");
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}
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@ -2103,7 +2103,7 @@ void pet80_state::pet80(machine_config &config)
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GENERIC_CARTSLOT(config, "cart_a000", generic_linear_slot, "pet_a000_rom", "bin,rom");
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// software lists
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SOFTWARE_LIST(config, "rom_list").set_type("pet_rom", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "rom_list").set_original("pet_rom");
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}
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void pet80_state::pet8032(machine_config &config)
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@ -2116,7 +2116,7 @@ void superpet_state::superpet(machine_config &config)
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{
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pet8032(config);
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m_exp->set_default_option("superpet");
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SOFTWARE_LIST(config, "flop_list2").set_type("superpet_flop", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "flop_list2").set_original("superpet_flop");
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}
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void cbm8096_state::cbm8096(machine_config &config)
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@ -2127,7 +2127,7 @@ void cbm8096_state::cbm8096(machine_config &config)
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RAM(config, m_ram);
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m_ram->set_default_size("96K");
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SOFTWARE_LIST(config, "flop_list2").set_type("cbm8096_flop", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "flop_list2").set_original("cbm8096_flop");
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}
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void cbm8296_state::cbm8296(machine_config &config)
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@ -2152,7 +2152,7 @@ void cbm8296_state::cbm8296(machine_config &config)
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RAM(config, m_ram);
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m_ram->set_default_size("128K");
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SOFTWARE_LIST(config, "flop_list2").set_type("cbm8296_flop", SOFTWARE_LIST_ORIGINAL_SYSTEM);
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SOFTWARE_LIST(config, "flop_list2").set_original("cbm8296_flop");
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}
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void cbm8296_state::cbm8296d(machine_config &config)
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@ -120,7 +120,6 @@
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#include "machine/x68k_hdc.h"
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#include "machine/x68k_kbd.h"
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#include "machine/mb89352.h"
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#include "machine/nvram.h"
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#include "bus/x68k/x68k_neptunex.h"
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@ -153,10 +152,10 @@ void x68k_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
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switch (id)
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{
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case TIMER_X68K_LED:
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x68k_led_callback(ptr, param);
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led_callback(ptr, param);
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break;
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case TIMER_X68K_SCC_ACK:
|
||||
x68k_scc_ack(ptr, param);
|
||||
scc_ack(ptr, param);
|
||||
break;
|
||||
case TIMER_MD_6BUTTON_PORT1_TIMEOUT:
|
||||
md_6button_port1_timeout(ptr, param);
|
||||
@ -165,10 +164,10 @@ void x68k_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
|
||||
md_6button_port2_timeout(ptr, param);
|
||||
break;
|
||||
case TIMER_X68K_BUS_ERROR:
|
||||
x68k_bus_error(ptr, param);
|
||||
bus_error(ptr, param);
|
||||
break;
|
||||
case TIMER_X68K_NET_IRQ:
|
||||
x68k_net_irq(ptr, param);
|
||||
net_irq(ptr, param);
|
||||
break;
|
||||
case TIMER_X68K_FDC_TC:
|
||||
m_upd72065->tc_w(ASSERT_LINE);
|
||||
@ -184,7 +183,7 @@ void x68k_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
|
||||
}
|
||||
|
||||
// LED timer callback
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::x68k_led_callback)
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::led_callback)
|
||||
{
|
||||
m_led_state = !m_led_state ? 1 : 0;
|
||||
if(m_led_state)
|
||||
@ -203,7 +202,7 @@ TIMER_CALLBACK_MEMBER(x68k_state::x68k_led_callback)
|
||||
// mouse input
|
||||
// port B of the Z8530 SCC
|
||||
// typically read from the SCC data port on receive buffer full interrupt per byte
|
||||
int x68k_state::x68k_read_mouse()
|
||||
int x68k_state::read_mouse()
|
||||
{
|
||||
char val = 0;
|
||||
char ipt = 0;
|
||||
@ -247,7 +246,7 @@ int x68k_state::x68k_read_mouse()
|
||||
0xe98005 - Z8530 command port A
|
||||
0xe98007 - Z8530 data port A (RS232)
|
||||
*/
|
||||
READ16_MEMBER(x68k_state::x68k_scc_r )
|
||||
READ16_MEMBER(x68k_state::scc_r )
|
||||
{
|
||||
offset %= 4;
|
||||
switch(offset)
|
||||
@ -255,7 +254,7 @@ READ16_MEMBER(x68k_state::x68k_scc_r )
|
||||
case 0:
|
||||
return m_scc->reg_r(space, 0);
|
||||
case 1:
|
||||
return x68k_read_mouse();
|
||||
return read_mouse();
|
||||
case 2:
|
||||
return m_scc->reg_r(space, 1);
|
||||
case 3:
|
||||
@ -265,7 +264,7 @@ READ16_MEMBER(x68k_state::x68k_scc_r )
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_scc_w )
|
||||
WRITE16_MEMBER(x68k_state::scc_w )
|
||||
{
|
||||
offset %= 4;
|
||||
|
||||
@ -297,7 +296,7 @@ WRITE16_MEMBER(x68k_state::x68k_scc_w )
|
||||
m_scc_prev = m_scc->get_reg_b(5) & 0x02;
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::x68k_scc_ack)
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::scc_ack)
|
||||
{
|
||||
if(m_mouse.bufferempty != 0) // nothing to do if the mouse data buffer is empty
|
||||
return;
|
||||
@ -321,7 +320,7 @@ TIMER_CALLBACK_MEMBER(x68k_state::x68k_scc_ack)
|
||||
}
|
||||
}
|
||||
|
||||
void x68k_state::x68k_set_adpcm()
|
||||
void x68k_state::set_adpcm()
|
||||
{
|
||||
uint32_t rate = adpcm_div[m_adpcm.rate];
|
||||
uint32_t res_clock = adpcm_clock[m_adpcm.clock]/2;
|
||||
@ -570,7 +569,7 @@ WRITE8_MEMBER(x68k_state::ppi_port_c_w)
|
||||
if (m_adpcm.rate == 3)
|
||||
LOGMASKED(LOG_SYS, "PPI: Invalid ADPCM sample rate set.\n");
|
||||
|
||||
x68k_set_adpcm();
|
||||
set_adpcm();
|
||||
m_okim6258->set_divider(m_adpcm.rate);
|
||||
m_adpcm_out[0]->flt_volume_set_volume((m_adpcm.pan & 1) ? 0.0f : 1.0f);
|
||||
m_adpcm_out[1]->flt_volume_set_volume((m_adpcm.pan & 2) ? 0.0f : 1.0f);
|
||||
@ -600,7 +599,7 @@ WRITE8_MEMBER(x68k_state::ppi_port_c_w)
|
||||
|
||||
|
||||
// NEC uPD72065 at 0xe94000
|
||||
WRITE16_MEMBER(x68k_state::x68k_fdc_w)
|
||||
WRITE16_MEMBER(x68k_state::fdc_w)
|
||||
{
|
||||
unsigned int drive, x;
|
||||
switch(offset)
|
||||
@ -644,7 +643,7 @@ WRITE16_MEMBER(x68k_state::x68k_fdc_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_fdc_r)
|
||||
READ16_MEMBER(x68k_state::fdc_r)
|
||||
{
|
||||
unsigned int ret;
|
||||
int x;
|
||||
@ -689,7 +688,7 @@ WRITE_LINE_MEMBER( x68k_state::fdc_irq )
|
||||
m_maincpu->set_input_line(1, CLEAR_LINE);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(x68k_state::x68k_ct_w)
|
||||
WRITE8_MEMBER(x68k_state::ct_w)
|
||||
{
|
||||
// CT1 and CT2 bits from YM2151 port 0x1b
|
||||
// CT1 - ADPCM clock - 0 = 8MHz, 1 = 4MHz
|
||||
@ -703,7 +702,7 @@ WRITE8_MEMBER(x68k_state::x68k_ct_w)
|
||||
m_upd72065->set_ready_line_connected(1);
|
||||
|
||||
m_adpcm.clock = (data & 0x02) >> 1;
|
||||
x68k_set_adpcm();
|
||||
set_adpcm();
|
||||
m_okim6258->set_unscaled_clock(adpcm_clock[m_adpcm.clock]);
|
||||
}
|
||||
|
||||
@ -723,7 +722,7 @@ WRITE8_MEMBER(x68k_state::x68k_ct_w)
|
||||
- bits 7-2 = vector
|
||||
- bits 1,0 = device (00 = FDC, 01 = FDD, 10 = HDD, 11 = Printer)
|
||||
*/
|
||||
WRITE16_MEMBER(x68k_state::x68k_ioc_w)
|
||||
WRITE16_MEMBER(x68k_state::ioc_w)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -755,7 +754,7 @@ WRITE16_MEMBER(x68k_state::x68k_ioc_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_ioc_r)
|
||||
READ16_MEMBER(x68k_state::ioc_r)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -787,7 +786,7 @@ READ16_MEMBER(x68k_state::x68k_ioc_r)
|
||||
Any other value, then SRAM is read only.
|
||||
Port 8 (0xe8e00f) - Power off control - write 0x00, 0x0f, 0x0f sequentially to switch power off.
|
||||
*/
|
||||
WRITE16_MEMBER(x68k_state::x68k_sysport_w)
|
||||
WRITE16_MEMBER(x68k_state::sysport_w)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -810,7 +809,7 @@ WRITE16_MEMBER(x68k_state::x68k_sysport_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_sysport_r)
|
||||
READ16_MEMBER(x68k_state::sysport_r)
|
||||
{
|
||||
int ret = 0;
|
||||
switch(offset)
|
||||
@ -830,18 +829,18 @@ READ16_MEMBER(x68k_state::x68k_sysport_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_ppi_w)
|
||||
WRITE16_MEMBER(x68k_state::ppi_w)
|
||||
{
|
||||
m_ppi->write(space,offset & 0x03,data);
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_ppi_r)
|
||||
READ16_MEMBER(x68k_state::ppi_r)
|
||||
{
|
||||
return m_ppi->read(space,offset & 0x03);
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_sram_w)
|
||||
WRITE16_MEMBER(x68k_state::sram_w)
|
||||
{
|
||||
if(m_sysport.sram_writeprotect == 0x31)
|
||||
{
|
||||
@ -849,7 +848,7 @@ WRITE16_MEMBER(x68k_state::x68k_sram_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_sram_r)
|
||||
READ16_MEMBER(x68k_state::sram_r)
|
||||
{
|
||||
// HACKS!
|
||||
// if(offset == 0x5a/2) // 0x5a should be 0 if no SASI HDs are present.
|
||||
@ -859,7 +858,7 @@ READ16_MEMBER(x68k_state::x68k_sram_r)
|
||||
return m_nvram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_vid_w)
|
||||
WRITE16_MEMBER(x68k_state::vid_w)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -896,7 +895,7 @@ WRITE16_MEMBER(x68k_state::x68k_vid_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_vid_r)
|
||||
READ16_MEMBER(x68k_state::vid_r)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -913,25 +912,25 @@ READ16_MEMBER(x68k_state::x68k_vid_r)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_areaset_r)
|
||||
READ16_MEMBER(x68k_state::areaset_r)
|
||||
{
|
||||
// register is write-only
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_areaset_w)
|
||||
WRITE16_MEMBER(x68k_state::areaset_w)
|
||||
{
|
||||
// TODO
|
||||
LOGMASKED(LOG_SYS, "SYS: Supervisor area set: 0x%02x\n",data & 0xff);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_enh_areaset_w )
|
||||
WRITE16_MEMBER(x68k_state::enh_areaset_w )
|
||||
{
|
||||
// TODO
|
||||
LOGMASKED(LOG_SYS, "SYS: Enhanced Supervisor area set (from %iMB): 0x%02x\n",(offset + 1) * 2,data & 0xff);
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::x68k_bus_error)
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::bus_error)
|
||||
{
|
||||
m_bus_error = false;
|
||||
}
|
||||
@ -950,7 +949,7 @@ void x68k_state::set_bus_error(uint32_t address, bool write, uint16_t mem_mask)
|
||||
LOGMASKED(LOG_SYS, "%s: Bus error: Unused RAM access [%08x]\n", machine().describe_context(), address);
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_rom0_r)
|
||||
READ16_MEMBER(x68k_state::rom0_r)
|
||||
{
|
||||
/* this location contains the address of some expansion device ROM, if no ROM exists,
|
||||
then access causes a bus error */
|
||||
@ -959,7 +958,7 @@ READ16_MEMBER(x68k_state::x68k_rom0_r)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_rom0_w)
|
||||
WRITE16_MEMBER(x68k_state::rom0_w)
|
||||
{
|
||||
/* this location contains the address of some expansion device ROM, if no ROM exists,
|
||||
then access causes a bus error */
|
||||
@ -967,7 +966,7 @@ WRITE16_MEMBER(x68k_state::x68k_rom0_w)
|
||||
set_bus_error((offset << 1) + 0xbffffc, 1, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_emptyram_r)
|
||||
READ16_MEMBER(x68k_state::emptyram_r)
|
||||
{
|
||||
/* this location is unused RAM, access here causes a bus error
|
||||
Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
|
||||
@ -976,7 +975,7 @@ READ16_MEMBER(x68k_state::x68k_emptyram_r)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_emptyram_w)
|
||||
WRITE16_MEMBER(x68k_state::emptyram_w)
|
||||
{
|
||||
/* this location is unused RAM, access here causes a bus error
|
||||
Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
|
||||
@ -984,7 +983,7 @@ WRITE16_MEMBER(x68k_state::x68k_emptyram_w)
|
||||
set_bus_error((offset << 1), 1, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_exp_r)
|
||||
READ16_MEMBER(x68k_state::exp_r)
|
||||
{
|
||||
/* These are expansion devices, if not present, they cause a bus error */
|
||||
if((m_options->read() & 0x02) && !machine().side_effects_disabled())
|
||||
@ -992,7 +991,7 @@ READ16_MEMBER(x68k_state::x68k_exp_r)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_exp_w)
|
||||
WRITE16_MEMBER(x68k_state::exp_w)
|
||||
{
|
||||
/* These are expansion devices, if not present, they cause a bus error */
|
||||
if((m_options->read() & 0x02) && !machine().side_effects_disabled())
|
||||
@ -1030,7 +1029,7 @@ WRITE8_MEMBER(x68k_state::dma_error)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(x68k_state::x68k_fm_irq)
|
||||
WRITE_LINE_MEMBER(x68k_state::fm_irq)
|
||||
{
|
||||
if(state == CLEAR_LINE)
|
||||
{
|
||||
@ -1042,7 +1041,7 @@ WRITE_LINE_MEMBER(x68k_state::x68k_fm_irq)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(x68k_state::x68030_adpcm_w)
|
||||
WRITE8_MEMBER(x68k_state::adpcm_w)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -1068,7 +1067,7 @@ WRITE_LINE_MEMBER(x68k_state::mfp_irq_callback)
|
||||
m_mfp_prev = state;
|
||||
}
|
||||
|
||||
IRQ_CALLBACK_MEMBER(x68k_state::x68k_int_ack)
|
||||
IRQ_CALLBACK_MEMBER(x68k_state::int_ack)
|
||||
{
|
||||
if(irqline == 6) // MFP
|
||||
{
|
||||
@ -1094,7 +1093,7 @@ IRQ_CALLBACK_MEMBER(x68k_state::x68k_int_ack)
|
||||
return m_current_vector[irqline];
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(x68k_state::x68k_scsi_irq)
|
||||
WRITE_LINE_MEMBER(x68ksupr_state::scsi_irq)
|
||||
{
|
||||
// TODO : Internal SCSI IRQ vector 0x6c, External SCSI IRQ vector 0xf6, IRQs go through the IOSC (IRQ line 1)
|
||||
if(state != 0)
|
||||
@ -1105,128 +1104,76 @@ WRITE_LINE_MEMBER(x68k_state::x68k_scsi_irq)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(x68k_state::x68k_scsi_drq)
|
||||
WRITE_LINE_MEMBER(x68ksupr_state::scsi_drq)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
void x68k_state::x68k_base_map(address_map &map)
|
||||
{
|
||||
map(0x000000, 0xbffffb).rw(FUNC(x68k_state::emptyram_r), FUNC(x68k_state::emptyram_w));
|
||||
map(0xbffffc, 0xbfffff).rw(FUNC(x68k_state::rom0_r), FUNC(x68k_state::rom0_w));
|
||||
map(0xc00000, 0xdfffff).rw(m_crtc, FUNC(x68k_crtc_device::gvram_r), FUNC(x68k_crtc_device::gvram_w));
|
||||
map(0xe00000, 0xe7ffff).rw(m_crtc, FUNC(x68k_crtc_device::tvram_r), FUNC(x68k_crtc_device::tvram_w));
|
||||
map(0xe80000, 0xe81fff).rw(m_crtc, FUNC(x68k_crtc_device::crtc_r), FUNC(x68k_crtc_device::crtc_w));
|
||||
map(0xe82000, 0xe821ff).rw(m_gfxpalette, FUNC(palette_device::read16), FUNC(palette_device::write16)).share("gfxpalette");
|
||||
map(0xe82200, 0xe823ff).rw(m_pcgpalette, FUNC(palette_device::read16), FUNC(palette_device::write16)).share("pcgpalette");
|
||||
map(0xe82400, 0xe83fff).rw(FUNC(x68k_state::vid_r), FUNC(x68k_state::vid_w));
|
||||
map(0xe84000, 0xe85fff).rw(m_hd63450, FUNC(hd63450_device::read), FUNC(hd63450_device::write));
|
||||
map(0xe86000, 0xe87fff).rw(FUNC(x68k_state::areaset_r), FUNC(x68k_state::areaset_w));
|
||||
map(0xe88000, 0xe89fff).rw(m_mfpdev, FUNC(mc68901_device::read), FUNC(mc68901_device::write)).umask16(0x00ff);
|
||||
map(0xe8a000, 0xe8bfff).rw(m_rtc, FUNC(rp5c15_device::read), FUNC(rp5c15_device::write)).umask16(0x00ff);
|
||||
// AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE(x68k_printer_r, x68k_printer_w)
|
||||
map(0xe8e000, 0xe8ffff).rw(FUNC(x68k_state::sysport_r), FUNC(x68k_state::sysport_w));
|
||||
map(0xe90000, 0xe91fff).rw(m_ym2151, FUNC(ym2151_device::read), FUNC(ym2151_device::write)).umask16(0x00ff);
|
||||
map(0xe94000, 0xe94003).m(m_upd72065, FUNC(upd72065_device::map)).umask16(0x00ff);
|
||||
map(0xe94004, 0xe94007).rw(FUNC(x68k_state::fdc_r), FUNC(x68k_state::fdc_w));
|
||||
map(0xe98000, 0xe99fff).rw(FUNC(x68k_state::scc_r), FUNC(x68k_state::scc_w));
|
||||
map(0xe9a000, 0xe9bfff).rw(FUNC(x68k_state::ppi_r), FUNC(x68k_state::ppi_w));
|
||||
map(0xe9c000, 0xe9dfff).rw(FUNC(x68k_state::ioc_r), FUNC(x68k_state::ioc_w));
|
||||
map(0xe9e000, 0xe9e3ff).rw(FUNC(x68k_state::exp_r), FUNC(x68k_state::exp_w)); // FPU (Optional)
|
||||
map(0xeafa00, 0xeafa1f).rw(FUNC(x68k_state::exp_r), FUNC(x68k_state::exp_w));
|
||||
map(0xeb0000, 0xeb7fff).rw(FUNC(x68k_state::spritereg_r), FUNC(x68k_state::spritereg_w));
|
||||
map(0xeb8000, 0xebffff).rw(FUNC(x68k_state::spriteram_r), FUNC(x68k_state::spriteram_w));
|
||||
map(0xece000, 0xece3ff).rw(FUNC(x68k_state::exp_r), FUNC(x68k_state::exp_w)); // User I/O
|
||||
map(0xed0000, 0xed3fff).rw(FUNC(x68k_state::sram_r), FUNC(x68k_state::sram_w));
|
||||
map(0xed4000, 0xefffff).noprw();
|
||||
map(0xf00000, 0xfbffff).rom();
|
||||
map(0xfe0000, 0xffffff).rom();
|
||||
}
|
||||
|
||||
void x68k_state::x68k_map(address_map &map)
|
||||
{
|
||||
map(0x000000, 0xbffffb).rw(FUNC(x68k_state::x68k_emptyram_r), FUNC(x68k_state::x68k_emptyram_w));
|
||||
map(0xbffffc, 0xbfffff).rw(FUNC(x68k_state::x68k_rom0_r), FUNC(x68k_state::x68k_rom0_w));
|
||||
map(0xc00000, 0xdfffff).rw(m_crtc, FUNC(x68k_crtc_device::gvram_r), FUNC(x68k_crtc_device::gvram_w));
|
||||
map(0xe00000, 0xe7ffff).rw(m_crtc, FUNC(x68k_crtc_device::tvram_r), FUNC(x68k_crtc_device::tvram_w));
|
||||
map(0xe80000, 0xe81fff).rw(m_crtc, FUNC(x68k_crtc_device::crtc_r), FUNC(x68k_crtc_device::crtc_w));
|
||||
map(0xe82000, 0xe821ff).rw(m_gfxpalette, FUNC(palette_device::read16), FUNC(palette_device::write16)).share("gfxpalette");
|
||||
map(0xe82200, 0xe823ff).rw(m_pcgpalette, FUNC(palette_device::read16), FUNC(palette_device::write16)).share("pcgpalette");
|
||||
map(0xe82400, 0xe83fff).rw(FUNC(x68k_state::x68k_vid_r), FUNC(x68k_state::x68k_vid_w));
|
||||
map(0xe84000, 0xe85fff).rw(m_hd63450, FUNC(hd63450_device::read), FUNC(hd63450_device::write));
|
||||
map(0xe86000, 0xe87fff).rw(FUNC(x68k_state::x68k_areaset_r), FUNC(x68k_state::x68k_areaset_w));
|
||||
map(0xe88000, 0xe89fff).rw(m_mfpdev, FUNC(mc68901_device::read), FUNC(mc68901_device::write)).umask16(0x00ff);
|
||||
map(0xe8a000, 0xe8bfff).rw(m_rtc, FUNC(rp5c15_device::read), FUNC(rp5c15_device::write)).umask16(0x00ff);
|
||||
// AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE(x68k_printer_r, x68k_printer_w)
|
||||
map(0xe8e000, 0xe8ffff).rw(FUNC(x68k_state::x68k_sysport_r), FUNC(x68k_state::x68k_sysport_w));
|
||||
map(0xe90000, 0xe91fff).rw(m_ym2151, FUNC(ym2151_device::read), FUNC(ym2151_device::write)).umask16(0x00ff);
|
||||
x68k_base_map(map);
|
||||
map(0xe92001, 0xe92001).rw(m_okim6258, FUNC(okim6258_device::status_r), FUNC(okim6258_device::ctrl_w));
|
||||
map(0xe92003, 0xe92003).rw(m_okim6258, FUNC(okim6258_device::status_r), FUNC(okim6258_device::data_w));
|
||||
map(0xe94000, 0xe94003).m(m_upd72065, FUNC(upd72065_device::map)).umask16(0x00ff);
|
||||
map(0xe94004, 0xe94007).rw(FUNC(x68k_state::x68k_fdc_r), FUNC(x68k_state::x68k_fdc_w));
|
||||
map(0xe96000, 0xe9601f).rw("x68k_hdc", FUNC(x68k_hdc_image_device::hdc_r), FUNC(x68k_hdc_image_device::hdc_w));
|
||||
map(0xe98000, 0xe99fff).rw(FUNC(x68k_state::x68k_scc_r), FUNC(x68k_state::x68k_scc_w));
|
||||
map(0xe9a000, 0xe9bfff).rw(FUNC(x68k_state::x68k_ppi_r), FUNC(x68k_state::x68k_ppi_w));
|
||||
map(0xe9c000, 0xe9dfff).rw(FUNC(x68k_state::x68k_ioc_r), FUNC(x68k_state::x68k_ioc_w));
|
||||
map(0xe9e000, 0xe9e3ff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // FPU (Optional)
|
||||
map(0xea0000, 0xea1fff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // external SCSI ROM and controller
|
||||
map(0xeafa00, 0xeafa1f).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w));
|
||||
map(0xeafa80, 0xeafa89).rw(FUNC(x68k_state::x68k_areaset_r), FUNC(x68k_state::x68k_enh_areaset_w));
|
||||
map(0xeb0000, 0xeb7fff).rw(FUNC(x68k_state::x68k_spritereg_r), FUNC(x68k_state::x68k_spritereg_w));
|
||||
map(0xeb8000, 0xebffff).rw(FUNC(x68k_state::x68k_spriteram_r), FUNC(x68k_state::x68k_spriteram_w));
|
||||
map(0xece000, 0xece3ff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // User I/O
|
||||
map(0xed0000, 0xed3fff).rw(FUNC(x68k_state::x68k_sram_r), FUNC(x68k_state::x68k_sram_w));
|
||||
map(0xed4000, 0xefffff).noprw();
|
||||
map(0xf00000, 0xfbffff).rom();
|
||||
map(0xfc0000, 0xfdffff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // internal SCSI ROM
|
||||
map(0xfe0000, 0xffffff).rom();
|
||||
map(0xea0000, 0xea1fff).rw(FUNC(x68k_state::exp_r), FUNC(x68k_state::exp_w)); // external SCSI ROM and controller
|
||||
map(0xeafa80, 0xeafa89).rw(FUNC(x68k_state::areaset_r), FUNC(x68k_state::enh_areaset_w));
|
||||
map(0xfc0000, 0xfdffff).rw(FUNC(x68k_state::exp_r), FUNC(x68k_state::exp_w)); // internal SCSI ROM
|
||||
}
|
||||
|
||||
void x68k_state::x68kxvi_map(address_map &map)
|
||||
void x68ksupr_state::x68kxvi_map(address_map &map)
|
||||
{
|
||||
map(0x000000, 0xbffffb).rw(FUNC(x68k_state::x68k_emptyram_r), FUNC(x68k_state::x68k_emptyram_w));
|
||||
map(0xbffffc, 0xbfffff).rw(FUNC(x68k_state::x68k_rom0_r), FUNC(x68k_state::x68k_rom0_w));
|
||||
map(0xc00000, 0xdfffff).rw(m_crtc, FUNC(x68k_crtc_device::gvram_r), FUNC(x68k_crtc_device::gvram_w));
|
||||
map(0xe00000, 0xe7ffff).rw(m_crtc, FUNC(x68k_crtc_device::tvram_r), FUNC(x68k_crtc_device::tvram_w));
|
||||
map(0xe80000, 0xe81fff).rw(m_crtc, FUNC(x68k_crtc_device::crtc_r), FUNC(x68k_crtc_device::crtc_w));
|
||||
map(0xe82000, 0xe821ff).rw(m_gfxpalette, FUNC(palette_device::read16), FUNC(palette_device::write16)).share("gfxpalette");
|
||||
map(0xe82200, 0xe823ff).rw(m_pcgpalette, FUNC(palette_device::read16), FUNC(palette_device::write16)).share("pcgpalette");
|
||||
map(0xe82400, 0xe83fff).rw(FUNC(x68k_state::x68k_vid_r), FUNC(x68k_state::x68k_vid_w));
|
||||
map(0xe84000, 0xe85fff).rw(m_hd63450, FUNC(hd63450_device::read), FUNC(hd63450_device::write));
|
||||
map(0xe86000, 0xe87fff).rw(FUNC(x68k_state::x68k_areaset_r), FUNC(x68k_state::x68k_areaset_w));
|
||||
map(0xe88000, 0xe89fff).rw(m_mfpdev, FUNC(mc68901_device::read), FUNC(mc68901_device::write)).umask16(0x00ff);
|
||||
map(0xe8a000, 0xe8bfff).rw(m_rtc, FUNC(rp5c15_device::read), FUNC(rp5c15_device::write)).umask16(0x00ff);
|
||||
// AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE(x68k_printer_r, x68k_printer_w)
|
||||
map(0xe8e000, 0xe8ffff).rw(FUNC(x68k_state::x68k_sysport_r), FUNC(x68k_state::x68k_sysport_w));
|
||||
map(0xe90000, 0xe91fff).rw(m_ym2151, FUNC(ym2151_device::read), FUNC(ym2151_device::write)).umask16(0x00ff);
|
||||
x68k_base_map(map);
|
||||
map(0xe92001, 0xe92001).rw(m_okim6258, FUNC(okim6258_device::status_r), FUNC(okim6258_device::ctrl_w));
|
||||
map(0xe92003, 0xe92003).rw(m_okim6258, FUNC(okim6258_device::status_r), FUNC(okim6258_device::data_w));
|
||||
map(0xe94000, 0xe94003).m(m_upd72065, FUNC(upd72065_device::map)).umask16(0x00ff);
|
||||
map(0xe94004, 0xe94007).rw(FUNC(x68k_state::x68k_fdc_r), FUNC(x68k_state::x68k_fdc_w));
|
||||
// AM_RANGE(0xe96000, 0xe9601f) AM_DEVREADWRITE("x68k_hdc", x68k_hdc_image_device, hdc_r, hdc_w)
|
||||
map(0xe96020, 0xe9603f).rw("mb89352", FUNC(mb89352_device::mb89352_r), FUNC(mb89352_device::mb89352_w)).umask16(0x00ff);
|
||||
map(0xe98000, 0xe99fff).rw(FUNC(x68k_state::x68k_scc_r), FUNC(x68k_state::x68k_scc_w));
|
||||
map(0xe9a000, 0xe9bfff).rw(FUNC(x68k_state::x68k_ppi_r), FUNC(x68k_state::x68k_ppi_w));
|
||||
map(0xe9c000, 0xe9dfff).rw(FUNC(x68k_state::x68k_ioc_r), FUNC(x68k_state::x68k_ioc_w));
|
||||
map(0xe9e000, 0xe9e3ff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // FPU (Optional)
|
||||
map(0xea0000, 0xea1fff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // external SCSI ROM and controller
|
||||
map(0xeafa00, 0xeafa1f).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w));
|
||||
map(0xeafa80, 0xeafa89).rw(FUNC(x68k_state::x68k_areaset_r), FUNC(x68k_state::x68k_enh_areaset_w));
|
||||
map(0xeb0000, 0xeb7fff).rw(FUNC(x68k_state::x68k_spritereg_r), FUNC(x68k_state::x68k_spritereg_w));
|
||||
map(0xeb8000, 0xebffff).rw(FUNC(x68k_state::x68k_spriteram_r), FUNC(x68k_state::x68k_spriteram_w));
|
||||
map(0xece000, 0xece3ff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // User I/O
|
||||
map(0xed0000, 0xed3fff).rw(FUNC(x68k_state::x68k_sram_r), FUNC(x68k_state::x68k_sram_w));
|
||||
map(0xed4000, 0xefffff).noprw();
|
||||
map(0xf00000, 0xfbffff).rom();
|
||||
map(0xea0000, 0xea1fff).rw(FUNC(x68ksupr_state::exp_r), FUNC(x68ksupr_state::exp_w)); // external SCSI ROM and controller
|
||||
map(0xeafa80, 0xeafa89).rw(FUNC(x68ksupr_state::areaset_r), FUNC(x68ksupr_state::enh_areaset_w));
|
||||
map(0xfc0000, 0xfdffff).rom(); // internal SCSI ROM
|
||||
map(0xfe0000, 0xffffff).rom();
|
||||
}
|
||||
|
||||
void x68k_state::x68030_map(address_map &map)
|
||||
void x68030_state::x68030_map(address_map &map)
|
||||
{
|
||||
map.global_mask(0x00ffffff); // Still only has 24-bit address space
|
||||
map(0x000000, 0xbffffb).rw(FUNC(x68k_state::x68k_emptyram_r), FUNC(x68k_state::x68k_emptyram_w));
|
||||
map(0xbffffc, 0xbfffff).rw(FUNC(x68k_state::x68k_rom0_r), FUNC(x68k_state::x68k_rom0_w));
|
||||
map(0xc00000, 0xdfffff).rw(m_crtc, FUNC(x68k_crtc_device::gvram_r), FUNC(x68k_crtc_device::gvram_w));
|
||||
map(0xe00000, 0xe7ffff).rw(m_crtc, FUNC(x68k_crtc_device::tvram_r), FUNC(x68k_crtc_device::tvram_w));
|
||||
map(0xe80000, 0xe81fff).rw(m_crtc, FUNC(x68k_crtc_device::crtc_r), FUNC(x68k_crtc_device::crtc_w));
|
||||
map(0xe82000, 0xe821ff).rw(m_gfxpalette, FUNC(palette_device::read32), FUNC(palette_device::write32)).share("gfxpalette");
|
||||
map(0xe82200, 0xe823ff).rw(m_pcgpalette, FUNC(palette_device::read32), FUNC(palette_device::write32)).share("pcgpalette");
|
||||
map(0xe82400, 0xe83fff).rw(FUNC(x68k_state::x68k_vid_r), FUNC(x68k_state::x68k_vid_w));
|
||||
map(0xe84000, 0xe85fff).rw(m_hd63450, FUNC(hd63450_device::read), FUNC(hd63450_device::write));
|
||||
map(0xe86000, 0xe87fff).rw(FUNC(x68k_state::x68k_areaset_r), FUNC(x68k_state::x68k_areaset_w));
|
||||
map(0xe88000, 0xe89fff).rw(m_mfpdev, FUNC(mc68901_device::read), FUNC(mc68901_device::write)).umask32(0x00ff00ff);
|
||||
map(0xe8a000, 0xe8bfff).rw(m_rtc, FUNC(rp5c15_device::read), FUNC(rp5c15_device::write)).umask32(0x00ff00ff);
|
||||
x68k_base_map(map);
|
||||
// AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE(x68k_printer_r, x68k_printer_w)
|
||||
map(0xe8e000, 0xe8ffff).rw(FUNC(x68k_state::x68k_sysport_r), FUNC(x68k_state::x68k_sysport_w));
|
||||
map(0xe90000, 0xe91fff).rw(m_ym2151, FUNC(ym2151_device::read), FUNC(ym2151_device::write)).umask32(0x00ff00ff);
|
||||
map(0xe92000, 0xe92003).r(m_okim6258, FUNC(okim6258_device::status_r)).umask32(0x00ff00ff).w(FUNC(x68k_state::x68030_adpcm_w)).umask32(0x00ff00ff);
|
||||
map(0xe94000, 0xe94003).m(m_upd72065, FUNC(upd72065_device::map)).umask32(0x00ff00ff);
|
||||
map(0xe94004, 0xe94007).rw(FUNC(x68k_state::x68k_fdc_r), FUNC(x68k_state::x68k_fdc_w));
|
||||
// AM_RANGE(0xe96000, 0xe9601f) AM_DEVREADWRITE16("x68k_hdc", x68k_hdc_image_device, hdc_r, hdc_w, 0xffffffff)
|
||||
map(0xe92000, 0xe92003).r(m_okim6258, FUNC(okim6258_device::status_r)).umask32(0x00ff00ff).w(FUNC(x68030_state::adpcm_w)).umask32(0x00ff00ff);
|
||||
|
||||
map(0xe96020, 0xe9603f).rw("mb89352", FUNC(mb89352_device::mb89352_r), FUNC(mb89352_device::mb89352_w)).umask32(0x00ff00ff);
|
||||
map(0xe98000, 0xe99fff).rw(FUNC(x68k_state::x68k_scc_r), FUNC(x68k_state::x68k_scc_w));
|
||||
map(0xe9a000, 0xe9bfff).rw(FUNC(x68k_state::x68k_ppi_r), FUNC(x68k_state::x68k_ppi_w));
|
||||
map(0xe9c000, 0xe9dfff).rw(FUNC(x68k_state::x68k_ioc_r), FUNC(x68k_state::x68k_ioc_w));
|
||||
map(0xe9e000, 0xe9e3ff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // FPU (Optional)
|
||||
map(0xea0000, 0xea1fff).noprw();//AM_READWRITE16(x68k_exp_r, x68k_exp_w,0xffffffff) // external SCSI ROM and controller
|
||||
map(0xeafa00, 0xeafa1f).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w));
|
||||
map(0xeafa80, 0xeafa8b).rw(FUNC(x68k_state::x68k_areaset_r), FUNC(x68k_state::x68k_enh_areaset_w));
|
||||
map(0xeb0000, 0xeb7fff).rw(FUNC(x68k_state::x68k_spritereg_r), FUNC(x68k_state::x68k_spritereg_w));
|
||||
map(0xeb8000, 0xebffff).rw(FUNC(x68k_state::x68k_spriteram_r), FUNC(x68k_state::x68k_spriteram_w));
|
||||
map(0xece000, 0xece3ff).rw(FUNC(x68k_state::x68k_exp_r), FUNC(x68k_state::x68k_exp_w)); // User I/O
|
||||
map(0xed0000, 0xed3fff).rw(FUNC(x68k_state::x68k_sram_r), FUNC(x68k_state::x68k_sram_w));
|
||||
map(0xed4000, 0xefffff).noprw();
|
||||
map(0xf00000, 0xfbffff).rom();
|
||||
map(0xea0000, 0xea1fff).noprw();//AM_READWRITE16(exp_r, exp_w,0xffffffff) // external SCSI ROM and controller
|
||||
map(0xeafa80, 0xeafa8b).rw(FUNC(x68030_state::areaset_r), FUNC(x68030_state::enh_areaset_w));
|
||||
map(0xfc0000, 0xfdffff).rom(); // internal SCSI ROM
|
||||
map(0xfe0000, 0xffffff).rom();
|
||||
}
|
||||
|
||||
static INPUT_PORTS_START( x68000 )
|
||||
@ -1430,14 +1377,14 @@ void x68k_state::floppy_unload(floppy_image_device *dev)
|
||||
floppy_load_unload(false, dev);
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::x68k_net_irq)
|
||||
TIMER_CALLBACK_MEMBER(x68k_state::net_irq)
|
||||
{
|
||||
m_current_vector[2] = 0xf9;
|
||||
m_current_irq_line = 2;
|
||||
m_maincpu->set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(x68k_state::x68k_irq2_line)
|
||||
WRITE_LINE_MEMBER(x68k_state::irq2_line)
|
||||
{
|
||||
if(state==ASSERT_LINE)
|
||||
{
|
||||
@ -1449,7 +1396,7 @@ WRITE_LINE_MEMBER(x68k_state::x68k_irq2_line)
|
||||
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(x68k_state::x68k_irq4_line)
|
||||
WRITE_LINE_MEMBER(x68k_state::irq4_line)
|
||||
{
|
||||
m_current_vector[4] = m_expansion->vector();
|
||||
m_maincpu->set_input_line_and_vector(4,state,m_current_vector[4]);
|
||||
@ -1535,7 +1482,7 @@ void x68k_state::machine_start()
|
||||
m_fdc.motor = 0;
|
||||
}
|
||||
|
||||
void x68k_state::init_x68000()
|
||||
void x68k_state::driver_init()
|
||||
{
|
||||
unsigned char* rom = memregion("maincpu")->base();
|
||||
unsigned char* user2 = memregion("user2")->base();
|
||||
@ -1570,16 +1517,16 @@ void x68k_state::init_x68000()
|
||||
save_item(NAME(m_spritereg));
|
||||
}
|
||||
|
||||
void x68k_state::init_x68kxvi()
|
||||
void x68ksupr_state::driver_init()
|
||||
{
|
||||
init_x68000();
|
||||
x68k_state::driver_init();
|
||||
m_sysport.cputype = 0xfe; // 68000, 16MHz
|
||||
m_is_32bit = false;
|
||||
}
|
||||
|
||||
void x68k_state::init_x68030()
|
||||
void x68030_state::driver_init()
|
||||
{
|
||||
init_x68000();
|
||||
x68k_state::driver_init();
|
||||
m_sysport.cputype = 0xdc; // 68030, 25MHz
|
||||
m_is_32bit = true;
|
||||
}
|
||||
@ -1594,17 +1541,12 @@ static void x68k_floppies(device_slot_interface &device)
|
||||
device.option_add("525hd", FLOPPY_525_HD);
|
||||
}
|
||||
|
||||
static void keyboard(device_slot_interface &device)
|
||||
static void keyboard_devices(device_slot_interface &device)
|
||||
{
|
||||
device.option_add("x68k", X68K_KEYBOARD);
|
||||
}
|
||||
|
||||
MACHINE_CONFIG_START(x68k_state::x68000)
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", M68000, 40_MHz_XTAL / 4) /* 10 MHz */
|
||||
MCFG_DEVICE_PROGRAM_MAP(x68k_map)
|
||||
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(x68k_state,x68k_int_ack)
|
||||
|
||||
MACHINE_CONFIG_START(x68k_state::x68000_base)
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(60))
|
||||
|
||||
/* device hardware */
|
||||
@ -1616,150 +1558,153 @@ MACHINE_CONFIG_START(x68k_state::x68000)
|
||||
m_mfpdev->out_tbo_cb().set(m_mfpdev, FUNC(mc68901_device::clock_w));
|
||||
m_mfpdev->out_so_cb().set("keyboard", FUNC(rs232_port_device::write_txd));
|
||||
|
||||
MCFG_DEVICE_ADD("keyboard", RS232_PORT, keyboard, "x68k")
|
||||
MCFG_RS232_RXD_HANDLER(WRITELINE("mc68901", mc68901_device, write_rx))
|
||||
rs232_port_device &keyboard(RS232_PORT(config, "keyboard", keyboard_devices, "x68k"));
|
||||
keyboard.rxd_handler().set(m_mfpdev, FUNC(mc68901_device::write_rx));
|
||||
|
||||
MCFG_DEVICE_ADD("ppi8255", I8255A, 0)
|
||||
MCFG_I8255_IN_PORTA_CB(READ8(*this, x68k_state, ppi_port_a_r))
|
||||
MCFG_I8255_IN_PORTB_CB(READ8(*this, x68k_state, ppi_port_b_r))
|
||||
MCFG_I8255_IN_PORTC_CB(READ8(*this, x68k_state, ppi_port_c_r))
|
||||
MCFG_I8255_OUT_PORTC_CB(WRITE8(*this, x68k_state, ppi_port_c_w))
|
||||
I8255A(config, m_ppi, 0);
|
||||
m_ppi->in_pa_callback().set(FUNC(x68k_state::ppi_port_a_r));
|
||||
m_ppi->in_pb_callback().set(FUNC(x68k_state::ppi_port_b_r));
|
||||
m_ppi->in_pc_callback().set(FUNC(x68k_state::ppi_port_c_r));
|
||||
m_ppi->out_pc_callback().set(FUNC(x68k_state::ppi_port_c_w));
|
||||
|
||||
MCFG_DEVICE_ADD("hd63450", HD63450, 40_MHz_XTAL / 4)
|
||||
MCFG_HD63450_CPU("maincpu")
|
||||
MCFG_HD63450_CLOCKS(attotime::from_usec(2), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2))
|
||||
MCFG_HD63450_BURST_CLOCKS(attotime::from_usec(2), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50))
|
||||
MCFG_HD63450_DMA_END_CB(WRITE8(*this, x68k_state, dma_end))
|
||||
MCFG_HD63450_DMA_ERROR_CB(WRITE8(*this, x68k_state, dma_error))
|
||||
MCFG_HD63450_DMA_READ_0_CB(READ8("upd72065", upd72065_device, mdma_r))
|
||||
MCFG_HD63450_DMA_WRITE_0_CB(WRITE8("upd72065", upd72065_device, mdma_w))
|
||||
HD63450(config, m_hd63450, 40_MHz_XTAL / 4, "maincpu");
|
||||
m_hd63450->set_clocks(attotime::from_usec(2), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2));
|
||||
m_hd63450->set_burst_clocks(attotime::from_usec(2), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50));
|
||||
m_hd63450->dma_end().set(FUNC(x68k_state::dma_end));
|
||||
m_hd63450->dma_error().set(FUNC(x68k_state::dma_error));
|
||||
m_hd63450->dma_read<0>().set("upd72065", FUNC(upd72065_device::mdma_r));
|
||||
m_hd63450->dma_write<0>().set("upd72065", FUNC(upd72065_device::mdma_w));
|
||||
|
||||
SCC8530(config, m_scc, 40_MHz_XTAL / 8);
|
||||
|
||||
MCFG_DEVICE_ADD("rp5c15", RP5C15, 32.768_kHz_XTAL)
|
||||
MCFG_RP5C15_OUT_ALARM_CB(WRITELINE("mc68901", mc68901_device, i0_w))
|
||||
RP5C15(config, m_rtc, 32.768_kHz_XTAL);
|
||||
m_rtc->alarm().set(m_mfpdev, FUNC(mc68901_device::i0_w));
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_RAW_PARAMS(69.55199_MHz_XTAL / 2, 1096, 0, 768, 568, 0, 512) // initial setting
|
||||
MCFG_SCREEN_UPDATE_DRIVER(x68k_state, screen_update_x68000)
|
||||
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
||||
m_screen->set_raw(69.55199_MHz_XTAL / 2, 1096, 0, 768, 568, 0, 512); // initial setting
|
||||
m_screen->set_screen_update(FUNC(x68k_state::screen_update));
|
||||
|
||||
VINAS(config, m_crtc, 38.86363_MHz_XTAL);
|
||||
m_crtc->set_screen("screen");
|
||||
m_crtc->vdisp_cb().set("mc68901", FUNC(mc68901_device::i4_w));
|
||||
m_crtc->vdisp_cb().append("mc68901", FUNC(mc68901_device::tai_w));
|
||||
m_crtc->rint_cb().set("mc68901", FUNC(mc68901_device::i6_w));
|
||||
m_crtc->hsync_cb().set("mc68901", FUNC(mc68901_device::i7_w));
|
||||
m_crtc->tvram_read_cb().set(FUNC(x68k_state::tvram_read));
|
||||
m_crtc->tvram_write_cb().set(FUNC(x68k_state::tvram_write));
|
||||
m_crtc->gvram_read_cb().set(FUNC(x68k_state::gvram_read));
|
||||
m_crtc->gvram_write_cb().set(FUNC(x68k_state::gvram_write));
|
||||
GFXDECODE(config, m_gfxdecode, "pcgpalette", gfxdecode_device::empty);
|
||||
|
||||
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "pcgpalette", gfxdecode_device::empty)
|
||||
PALETTE(config, m_gfxpalette, 256).set_format(raw_to_rgb_converter(2, &x68k_state::GGGGGRRRRRBBBBBI_decoder));
|
||||
PALETTE(config, m_pcgpalette, 256).set_format(raw_to_rgb_converter(2, &x68k_state::GGGGGRRRRRBBBBBI_decoder));
|
||||
|
||||
MCFG_PALETTE_ADD("gfxpalette", 256)
|
||||
MCFG_PALETTE_FORMAT_CLASS(2, x68k_state, GGGGGRRRRRBBBBBI)
|
||||
MCFG_PALETTE_ADD("pcgpalette", 256)
|
||||
MCFG_PALETTE_FORMAT_CLASS(2, x68k_state, GGGGGRRRRRBBBBBI)
|
||||
|
||||
MCFG_VIDEO_START_OVERRIDE(x68k_state, x68000 )
|
||||
MCFG_VIDEO_START_OVERRIDE(x68k_state, x68000)
|
||||
|
||||
config.set_default_layout(layout_x68000);
|
||||
|
||||
/* sound hardware */
|
||||
SPEAKER(config, "lspeaker").front_left();
|
||||
SPEAKER(config, "rspeaker").front_right();
|
||||
MCFG_DEVICE_ADD("ym2151", YM2151, 16_MHz_XTAL / 4)
|
||||
MCFG_YM2151_IRQ_HANDLER(WRITELINE(*this, x68k_state,x68k_fm_irq))
|
||||
MCFG_YM2151_PORT_WRITE_HANDLER(WRITE8(*this, x68k_state,x68k_ct_w)) // CT1, CT2 from YM2151 port 0x1b
|
||||
MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
|
||||
MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
|
||||
YM2151(config, m_ym2151, 16_MHz_XTAL / 4);
|
||||
m_ym2151->irq_handler().set(FUNC(x68k_state::fm_irq));
|
||||
m_ym2151->port_write_handler().set(FUNC(x68k_state::ct_w)); // CT1, CT2 from YM2151 port 0x1b
|
||||
m_ym2151->add_route(0, "lspeaker", 0.50);
|
||||
m_ym2151->add_route(1, "rspeaker", 0.50);
|
||||
|
||||
MCFG_DEVICE_ADD("okim6258", OKIM6258, 16_MHz_XTAL / 4)
|
||||
MCFG_OKIM6258_DIVIDER(FOSC_DIV_BY_512)
|
||||
MCFG_OKIM6258_ADPCM_TYPE(TYPE_4BITS)
|
||||
MCFG_OKIM6258_OUT_BITS(OUTPUT_10BITS)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "adpcm_outl", 0.50)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "adpcm_outr", 0.50)
|
||||
OKIM6258(config, m_okim6258, 16_MHz_XTAL / 4);
|
||||
m_okim6258->set_start_div(okim6258_device::FOSC_DIV_BY_512);
|
||||
m_okim6258->set_type(okim6258_device::TYPE_4BITS);
|
||||
m_okim6258->set_outbits(okim6258_device::OUTPUT_10BITS);
|
||||
m_okim6258->add_route(ALL_OUTPUTS, "adpcm_outl", 0.50);
|
||||
m_okim6258->add_route(ALL_OUTPUTS, "adpcm_outr", 0.50);
|
||||
|
||||
FILTER_VOLUME(config, "adpcm_outl").add_route(ALL_OUTPUTS, "lspeaker", 1.0);
|
||||
FILTER_VOLUME(config, "adpcm_outr").add_route(ALL_OUTPUTS, "rspeaker", 1.0);
|
||||
FILTER_VOLUME(config, m_adpcm_out[0]).add_route(ALL_OUTPUTS, "lspeaker", 1.0);
|
||||
FILTER_VOLUME(config, m_adpcm_out[1]).add_route(ALL_OUTPUTS, "rspeaker", 1.0);
|
||||
|
||||
MCFG_UPD72065_ADD("upd72065", true, false)
|
||||
MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(*this, x68k_state, fdc_irq))
|
||||
MCFG_UPD765_DRQ_CALLBACK(WRITELINE("hd63450", hd63450_device, drq0_w))
|
||||
MCFG_FLOPPY_DRIVE_ADD("upd72065:0", x68k_floppies, "525hd", x68k_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("upd72065:1", x68k_floppies, "525hd", x68k_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("upd72065:2", x68k_floppies, "525hd", x68k_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("upd72065:3", x68k_floppies, "525hd", x68k_state::floppy_formats)
|
||||
UPD72065(config, m_upd72065, 0, true, false);
|
||||
m_upd72065->intrq_wr_callback().set(FUNC(x68k_state::fdc_irq));
|
||||
m_upd72065->drq_wr_callback().set(m_hd63450, FUNC(hd63450_device::drq0_w));
|
||||
FLOPPY_CONNECTOR(config, "upd72065:0", x68k_floppies, "525hd", x68k_state::floppy_formats);
|
||||
FLOPPY_CONNECTOR(config, "upd72065:1", x68k_floppies, "525hd", x68k_state::floppy_formats);
|
||||
FLOPPY_CONNECTOR(config, "upd72065:2", x68k_floppies, "525hd", x68k_state::floppy_formats);
|
||||
FLOPPY_CONNECTOR(config, "upd72065:3", x68k_floppies, "525hd", x68k_state::floppy_formats);
|
||||
|
||||
MCFG_SOFTWARE_LIST_ADD("flop_list","x68k_flop")
|
||||
SOFTWARE_LIST(config, "flop_list").set_original("x68k_flop");
|
||||
|
||||
MCFG_DEVICE_ADD("exp", X68K_EXPANSION_SLOT, 0)
|
||||
MCFG_DEVICE_SLOT_INTERFACE(x68000_exp_cards, nullptr, false)
|
||||
MCFG_X68K_EXPANSION_SLOT_OUT_IRQ2_CB(WRITELINE(*this, x68k_state, x68k_irq2_line))
|
||||
MCFG_X68K_EXPANSION_SLOT_OUT_IRQ4_CB(WRITELINE(*this, x68k_state, x68k_irq4_line))
|
||||
MCFG_X68K_EXPANSION_SLOT_OUT_IRQ2_CB(WRITELINE(*this, x68k_state, irq2_line))
|
||||
MCFG_X68K_EXPANSION_SLOT_OUT_IRQ4_CB(WRITELINE(*this, x68k_state, irq4_line))
|
||||
MCFG_X68K_EXPANSION_SLOT_OUT_NMI_CB(INPUTLINE("maincpu", M68K_IRQ_7))
|
||||
|
||||
/* internal ram */
|
||||
RAM(config, RAM_TAG).set_default_size("4M").set_extra_options("1M,2M,3M,5M,6M,7M,8M,9M,10M,11M,12M");
|
||||
RAM(config, m_ram).set_default_size("4M").set_extra_options("1M,2M,3M,5M,6M,7M,8M,9M,10M,11M,12M");
|
||||
|
||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||
|
||||
MCFG_X68KHDC_ADD( "x68k_hdc" )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
MACHINE_CONFIG_START(x68k_state::x68ksupr)
|
||||
x68000(config);
|
||||
MCFG_DEVICE_REMOVE("x68k_hdc")
|
||||
void x68k_state::x68000(machine_config &config)
|
||||
{
|
||||
add_cpu(config, M68000, &x68k_state::x68k_map, 40_MHz_XTAL / 4);
|
||||
x68000_base(config);
|
||||
|
||||
MCFG_DEVICE_MODIFY("maincpu")
|
||||
MCFG_DEVICE_PROGRAM_MAP(x68kxvi_map)
|
||||
|
||||
MCFG_DEVICE_ADD("scsi", SCSI_PORT, 0)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE1, "harddisk", SCSIHD, SCSI_ID_0)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE2, "harddisk", SCSIHD, SCSI_ID_1)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE3, "harddisk", SCSIHD, SCSI_ID_2)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE4, "harddisk", SCSIHD, SCSI_ID_3)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE5, "harddisk", SCSIHD, SCSI_ID_4)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE6, "harddisk", SCSIHD, SCSI_ID_5)
|
||||
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE7, "cdrom", SCSICD, SCSI_ID_6)
|
||||
|
||||
mb89352_device &scsictrl(MB89352A(config, "mb89352", 40_MHz_XTAL / 8));
|
||||
scsictrl.set_scsi_port("scsi");
|
||||
scsictrl.irq_cb().set(FUNC(x68k_state::x68k_scsi_irq));
|
||||
scsictrl.drq_cb().set(FUNC(x68k_state::x68k_scsi_drq));
|
||||
|
||||
VICON(config.replace(), m_crtc, 38.86363_MHz_XTAL);
|
||||
VINAS(config, m_crtc, 38.86363_MHz_XTAL);
|
||||
m_crtc->set_screen("screen");
|
||||
m_crtc->vdisp_cb().set("mc68901", FUNC(mc68901_device::i4_w));
|
||||
m_crtc->vdisp_cb().append("mc68901", FUNC(mc68901_device::tai_w));
|
||||
m_crtc->rint_cb().set("mc68901", FUNC(mc68901_device::i6_w));
|
||||
m_crtc->hsync_cb().set("mc68901", FUNC(mc68901_device::i7_w));
|
||||
m_crtc->vdisp_cb().set(m_mfpdev, FUNC(mc68901_device::i4_w));
|
||||
m_crtc->vdisp_cb().append(m_mfpdev, FUNC(mc68901_device::tai_w));
|
||||
m_crtc->rint_cb().set(m_mfpdev, FUNC(mc68901_device::i6_w));
|
||||
m_crtc->hsync_cb().set(m_mfpdev, FUNC(mc68901_device::i7_w));
|
||||
m_crtc->tvram_read_cb().set(FUNC(x68k_state::tvram_read));
|
||||
m_crtc->tvram_write_cb().set(FUNC(x68k_state::tvram_write));
|
||||
m_crtc->gvram_read_cb().set(FUNC(x68k_state::gvram_read));
|
||||
m_crtc->gvram_write_cb().set(FUNC(x68k_state::gvram_write));
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
MACHINE_CONFIG_START(x68k_state::x68kxvi)
|
||||
x68ksupr(config);
|
||||
MCFG_DEVICE_MODIFY("maincpu")
|
||||
MCFG_DEVICE_CLOCK(33.333_MHz_XTAL / 2) /* 16 MHz (nominally) */
|
||||
MACHINE_CONFIG_END
|
||||
X68KHDC(config, "x68k_hdc", 0);
|
||||
}
|
||||
|
||||
MACHINE_CONFIG_START(x68k_state::x68030)
|
||||
x68ksupr(config);
|
||||
MCFG_DEVICE_REPLACE("maincpu", M68030, 50_MHz_XTAL / 2) /* 25 MHz 68EC030 */
|
||||
MCFG_DEVICE_PROGRAM_MAP(x68030_map)
|
||||
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(x68k_state,x68k_int_ack)
|
||||
void x68ksupr_state::x68ksupr_base(machine_config &config)
|
||||
{
|
||||
x68000_base(config);
|
||||
|
||||
MCFG_DEVICE_MODIFY("hd63450")
|
||||
MCFG_DEVICE_CLOCK(50_MHz_XTAL / 4)
|
||||
scsi_port_device &scsi(SCSI_PORT(config, "scsi"));
|
||||
scsi.set_slot_device(1, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_0));
|
||||
scsi.set_slot_device(2, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_1));
|
||||
scsi.set_slot_device(3, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_2));
|
||||
scsi.set_slot_device(4, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_3));
|
||||
scsi.set_slot_device(5, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_4));
|
||||
scsi.set_slot_device(6, "harddisk", SCSIHD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_5));
|
||||
scsi.set_slot_device(7, "cdrom", SCSICD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_6));
|
||||
|
||||
MB89352A(config, m_scsictrl, 40_MHz_XTAL / 8);
|
||||
m_scsictrl->set_scsi_port("scsi");
|
||||
m_scsictrl->irq_cb().set(FUNC(x68ksupr_state::scsi_irq));
|
||||
m_scsictrl->drq_cb().set(FUNC(x68ksupr_state::scsi_drq));
|
||||
|
||||
VICON(config, m_crtc, 38.86363_MHz_XTAL);
|
||||
m_crtc->set_screen("screen");
|
||||
m_crtc->vdisp_cb().set(m_mfpdev, FUNC(mc68901_device::i4_w));
|
||||
m_crtc->vdisp_cb().append(m_mfpdev, FUNC(mc68901_device::tai_w));
|
||||
m_crtc->rint_cb().set(m_mfpdev, FUNC(mc68901_device::i6_w));
|
||||
m_crtc->hsync_cb().set(m_mfpdev, FUNC(mc68901_device::i7_w));
|
||||
m_crtc->tvram_read_cb().set(FUNC(x68ksupr_state::tvram_read));
|
||||
m_crtc->tvram_write_cb().set(FUNC(x68ksupr_state::tvram_write));
|
||||
m_crtc->gvram_read_cb().set(FUNC(x68ksupr_state::gvram_read));
|
||||
m_crtc->gvram_write_cb().set(FUNC(x68ksupr_state::gvram_write));
|
||||
}
|
||||
|
||||
void x68ksupr_state::x68ksupr(machine_config &config)
|
||||
{
|
||||
add_cpu(config, M68000, &x68ksupr_state::x68kxvi_map, 40_MHz_XTAL / 4);
|
||||
x68ksupr_base(config);
|
||||
}
|
||||
|
||||
void x68ksupr_state::x68kxvi(machine_config &config)
|
||||
{
|
||||
add_cpu(config, M68000, &x68ksupr_state::x68kxvi_map, 33.333_MHz_XTAL / 2); /* 16 MHz (nominally) */
|
||||
x68ksupr_base(config);
|
||||
}
|
||||
|
||||
void x68030_state::x68030(machine_config &config)
|
||||
{
|
||||
add_cpu(config, M68030, &x68030_state::x68030_map, 50_MHz_XTAL / 2); /* 25 MHz 68EC030 */
|
||||
x68ksupr_base(config);
|
||||
|
||||
m_hd63450->set_clock(50_MHz_XTAL / 4);
|
||||
m_scc->set_clock(20_MHz_XTAL / 4);
|
||||
MCFG_DEVICE_MODIFY("mb89352")
|
||||
MCFG_DEVICE_CLOCK(20_MHz_XTAL / 4)
|
||||
MACHINE_CONFIG_END
|
||||
m_scsictrl->set_clock(20_MHz_XTAL / 4);
|
||||
}
|
||||
|
||||
ROM_START( x68000 )
|
||||
ROM_REGION16_BE(0x1000000, "maincpu", 0) // 16MB address space
|
||||
@ -1852,8 +1797,8 @@ ROM_START( x68030 )
|
||||
ROM_END
|
||||
|
||||
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1987, x68000, 0, 0, x68000, x68000, x68k_state, init_x68000, "Sharp", "X68000", MACHINE_IMPERFECT_GRAPHICS )
|
||||
COMP( 1990, x68ksupr, x68000, 0, x68ksupr, x68000, x68k_state, init_x68000, "Sharp", "X68000 Super", MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING )
|
||||
COMP( 1991, x68kxvi, x68000, 0, x68kxvi, x68000, x68k_state, init_x68kxvi,"Sharp", "X68000 XVI", MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING )
|
||||
COMP( 1993, x68030, x68000, 0, x68030, x68000, x68k_state, init_x68030, "Sharp", "X68030", MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING )
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1987, x68000, 0, 0, x68000, x68000, x68k_state, empty_init, "Sharp", "X68000", MACHINE_IMPERFECT_GRAPHICS )
|
||||
COMP( 1990, x68ksupr, x68000, 0, x68ksupr, x68000, x68ksupr_state, empty_init, "Sharp", "X68000 Super", MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING )
|
||||
COMP( 1991, x68kxvi, x68000, 0, x68kxvi, x68000, x68ksupr_state, empty_init, "Sharp", "X68000 XVI", MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING )
|
||||
COMP( 1993, x68030, x68000, 0, x68030, x68000, x68030_state, empty_init, "Sharp", "X68030", MACHINE_IMPERFECT_GRAPHICS | MACHINE_NOT_WORKING )
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#include "machine/8530scc.h"
|
||||
#include "machine/hd63450.h"
|
||||
#include "machine/i8255.h"
|
||||
#include "machine/mb89352.h"
|
||||
#include "machine/mc68901.h"
|
||||
#include "machine/ram.h"
|
||||
#include "machine/rp5c15.h"
|
||||
@ -74,16 +75,12 @@ public:
|
||||
, m_spritereg(0x8000/sizeof(uint16_t), 0)
|
||||
{ }
|
||||
|
||||
void x68kxvi(machine_config &config);
|
||||
void x68ksupr(machine_config &config);
|
||||
void x68030(machine_config &config);
|
||||
void x68000_base(machine_config &config);
|
||||
void x68000(machine_config &config);
|
||||
|
||||
void init_x68kxvi();
|
||||
void init_x68030();
|
||||
void init_x68000();
|
||||
void driver_init() override;
|
||||
|
||||
private:
|
||||
protected:
|
||||
enum
|
||||
{
|
||||
TIMER_X68K_LED,
|
||||
@ -96,6 +93,14 @@ private:
|
||||
TIMER_X68K_ADPCM
|
||||
};
|
||||
|
||||
template <typename CpuType, typename AddrMap, typename Clock>
|
||||
void add_cpu(machine_config &config, CpuType &&type, AddrMap &&map, Clock &&clock)
|
||||
{
|
||||
type(config, m_maincpu, std::forward<Clock>(clock));
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, std::forward<AddrMap>(map));
|
||||
m_maincpu->set_irq_acknowledge_callback(FUNC(x68k_state::int_ack));
|
||||
}
|
||||
|
||||
required_device<m68000_base_device> m_maincpu;
|
||||
required_device<okim6258_device> m_okim6258;
|
||||
required_device<hd63450_device> m_hd63450;
|
||||
@ -240,89 +245,86 @@ private:
|
||||
int m_sprite_shift;
|
||||
bool m_is_32bit;
|
||||
|
||||
TILE_GET_INFO_MEMBER(x68k_get_bg0_tile);
|
||||
TILE_GET_INFO_MEMBER(x68k_get_bg1_tile);
|
||||
TILE_GET_INFO_MEMBER(x68k_get_bg0_tile_16);
|
||||
TILE_GET_INFO_MEMBER(x68k_get_bg1_tile_16);
|
||||
TILE_GET_INFO_MEMBER(get_bg0_tile);
|
||||
TILE_GET_INFO_MEMBER(get_bg1_tile);
|
||||
TILE_GET_INFO_MEMBER(get_bg0_tile_16);
|
||||
TILE_GET_INFO_MEMBER(get_bg1_tile_16);
|
||||
DECLARE_VIDEO_START(x68000);
|
||||
DECLARE_PALETTE_INIT(x68000);
|
||||
uint32_t screen_update_x68000(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
TIMER_CALLBACK_MEMBER(x68k_led_callback);
|
||||
TIMER_CALLBACK_MEMBER(x68k_scc_ack);
|
||||
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
TIMER_CALLBACK_MEMBER(led_callback);
|
||||
TIMER_CALLBACK_MEMBER(scc_ack);
|
||||
TIMER_CALLBACK_MEMBER(md_6button_port1_timeout);
|
||||
TIMER_CALLBACK_MEMBER(md_6button_port2_timeout);
|
||||
TIMER_CALLBACK_MEMBER(x68k_bus_error);
|
||||
TIMER_CALLBACK_MEMBER(x68k_net_irq);
|
||||
TIMER_CALLBACK_MEMBER(bus_error);
|
||||
TIMER_CALLBACK_MEMBER(net_irq);
|
||||
DECLARE_READ8_MEMBER(ppi_port_a_r);
|
||||
DECLARE_READ8_MEMBER(ppi_port_b_r);
|
||||
DECLARE_READ8_MEMBER(ppi_port_c_r);
|
||||
DECLARE_WRITE8_MEMBER(ppi_port_c_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_irq);
|
||||
DECLARE_WRITE8_MEMBER(x68k_ct_w);
|
||||
DECLARE_WRITE8_MEMBER(x68030_adpcm_w);
|
||||
DECLARE_WRITE8_MEMBER(ct_w);
|
||||
DECLARE_WRITE8_MEMBER(adpcm_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(mfp_irq_callback);
|
||||
DECLARE_WRITE_LINE_MEMBER(x68k_scsi_irq);
|
||||
DECLARE_WRITE_LINE_MEMBER(x68k_scsi_drq);
|
||||
|
||||
//dmac
|
||||
void dma_irq(int channel);
|
||||
DECLARE_WRITE8_MEMBER(dma_end);
|
||||
DECLARE_WRITE8_MEMBER(dma_error);
|
||||
|
||||
int x68k_read_mouse();
|
||||
void x68k_set_adpcm();
|
||||
int read_mouse();
|
||||
void set_adpcm();
|
||||
uint8_t md_3button_r(int port);
|
||||
void md_6button_init();
|
||||
uint8_t md_6button_r(int port);
|
||||
uint8_t xpd1lr_r(int port);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(x68k_fm_irq);
|
||||
DECLARE_WRITE_LINE_MEMBER(x68k_irq2_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(x68k_irq4_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(fm_irq);
|
||||
DECLARE_WRITE_LINE_MEMBER(irq2_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(irq4_line);
|
||||
|
||||
DECLARE_WRITE16_MEMBER(x68k_scc_w);
|
||||
DECLARE_WRITE16_MEMBER(x68k_fdc_w);
|
||||
DECLARE_READ16_MEMBER(x68k_fdc_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_ioc_w);
|
||||
DECLARE_READ16_MEMBER(x68k_ioc_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_sysport_w);
|
||||
DECLARE_READ16_MEMBER(x68k_sysport_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_ppi_w);
|
||||
DECLARE_READ16_MEMBER(x68k_ppi_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_sram_w);
|
||||
DECLARE_READ16_MEMBER(x68k_sram_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_vid_w);
|
||||
DECLARE_READ16_MEMBER(x68k_vid_r);
|
||||
DECLARE_READ16_MEMBER(x68k_areaset_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_areaset_w);
|
||||
DECLARE_WRITE16_MEMBER(x68k_enh_areaset_w);
|
||||
DECLARE_READ16_MEMBER(x68k_rom0_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_rom0_w);
|
||||
DECLARE_READ16_MEMBER(x68k_emptyram_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_emptyram_w);
|
||||
DECLARE_READ16_MEMBER(x68k_exp_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_exp_w);
|
||||
DECLARE_READ16_MEMBER(x68k_scc_r);
|
||||
DECLARE_WRITE16_MEMBER(scc_w);
|
||||
DECLARE_READ16_MEMBER(scc_r);
|
||||
DECLARE_WRITE16_MEMBER(fdc_w);
|
||||
DECLARE_READ16_MEMBER(fdc_r);
|
||||
DECLARE_WRITE16_MEMBER(ioc_w);
|
||||
DECLARE_READ16_MEMBER(ioc_r);
|
||||
DECLARE_WRITE16_MEMBER(sysport_w);
|
||||
DECLARE_READ16_MEMBER(sysport_r);
|
||||
DECLARE_WRITE16_MEMBER(ppi_w);
|
||||
DECLARE_READ16_MEMBER(ppi_r);
|
||||
DECLARE_WRITE16_MEMBER(sram_w);
|
||||
DECLARE_READ16_MEMBER(sram_r);
|
||||
DECLARE_WRITE16_MEMBER(vid_w);
|
||||
DECLARE_READ16_MEMBER(vid_r);
|
||||
DECLARE_READ16_MEMBER(areaset_r);
|
||||
DECLARE_WRITE16_MEMBER(areaset_w);
|
||||
DECLARE_WRITE16_MEMBER(enh_areaset_w);
|
||||
DECLARE_READ16_MEMBER(rom0_r);
|
||||
DECLARE_WRITE16_MEMBER(rom0_w);
|
||||
DECLARE_READ16_MEMBER(emptyram_r);
|
||||
DECLARE_WRITE16_MEMBER(emptyram_w);
|
||||
DECLARE_READ16_MEMBER(exp_r);
|
||||
DECLARE_WRITE16_MEMBER(exp_w);
|
||||
|
||||
DECLARE_READ16_MEMBER(x68k_spritereg_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_spritereg_w);
|
||||
DECLARE_READ16_MEMBER(x68k_spriteram_r);
|
||||
DECLARE_WRITE16_MEMBER(x68k_spriteram_w);
|
||||
DECLARE_READ16_MEMBER(spritereg_r);
|
||||
DECLARE_WRITE16_MEMBER(spritereg_w);
|
||||
DECLARE_READ16_MEMBER(spriteram_r);
|
||||
DECLARE_WRITE16_MEMBER(spriteram_w);
|
||||
DECLARE_READ16_MEMBER(tvram_read);
|
||||
DECLARE_WRITE16_MEMBER(tvram_write);
|
||||
DECLARE_READ16_MEMBER(gvram_read);
|
||||
DECLARE_WRITE16_MEMBER(gvram_write);
|
||||
IRQ_CALLBACK_MEMBER(x68k_int_ack);
|
||||
IRQ_CALLBACK_MEMBER(int_ack);
|
||||
|
||||
void x68030_map(address_map &map);
|
||||
void x68k_base_map(address_map &map);
|
||||
void x68k_map(address_map &map);
|
||||
void x68kxvi_map(address_map &map);
|
||||
|
||||
inline void x68k_plot_pixel(bitmap_rgb32 &bitmap, int x, int y, uint32_t color);
|
||||
void x68k_draw_text(bitmap_rgb32 &bitmap, int xscr, int yscr, rectangle rect);
|
||||
bool x68k_draw_gfx_scanline(bitmap_ind16 &bitmap, rectangle cliprect, uint8_t priority);
|
||||
void x68k_draw_gfx(bitmap_rgb32 &bitmap,rectangle cliprect);
|
||||
void x68k_draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect);
|
||||
inline void plot_pixel(bitmap_rgb32 &bitmap, int x, int y, uint32_t color);
|
||||
void draw_text(bitmap_rgb32 &bitmap, int xscr, int yscr, rectangle rect);
|
||||
bool draw_gfx_scanline(bitmap_ind16 &bitmap, rectangle cliprect, uint8_t priority);
|
||||
void draw_gfx(bitmap_rgb32 &bitmap,rectangle cliprect);
|
||||
void draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect);
|
||||
|
||||
public:
|
||||
DECLARE_PALETTE_DECODER(GGGGGRRRRRBBBBBI);
|
||||
@ -335,6 +337,44 @@ protected:
|
||||
bool m_bus_error;
|
||||
};
|
||||
|
||||
class x68ksupr_state : public x68k_state
|
||||
{
|
||||
public:
|
||||
x68ksupr_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: x68k_state(mconfig, type, tag)
|
||||
, m_scsictrl(*this, "mb89352")
|
||||
{
|
||||
}
|
||||
|
||||
void x68ksupr_base(machine_config &config);
|
||||
void x68kxvi(machine_config &config);
|
||||
void x68ksupr(machine_config &config);
|
||||
|
||||
void driver_init() override;
|
||||
|
||||
protected:
|
||||
DECLARE_WRITE_LINE_MEMBER(scsi_irq);
|
||||
DECLARE_WRITE_LINE_MEMBER(scsi_drq);
|
||||
|
||||
required_device<mb89352_device> m_scsictrl;
|
||||
|
||||
void x68kxvi_map(address_map &map);
|
||||
};
|
||||
|
||||
class x68030_state : public x68ksupr_state
|
||||
{
|
||||
public:
|
||||
x68030_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: x68ksupr_state(mconfig, type, tag)
|
||||
{
|
||||
}
|
||||
|
||||
void x68030(machine_config &config);
|
||||
|
||||
void driver_init() override;
|
||||
|
||||
protected:
|
||||
void x68030_map(address_map &map);
|
||||
};
|
||||
|
||||
#endif // MAME_INCLUDES_X68K_H
|
||||
|
||||
@ -49,7 +49,7 @@ PALETTE_DECODER_MEMBER(x68k_state, GGGGGRRRRRBBBBBI)
|
||||
return rgb_t(r, g, b);
|
||||
}
|
||||
|
||||
inline void x68k_state::x68k_plot_pixel(bitmap_rgb32 &bitmap, int x, int y, uint32_t color)
|
||||
inline void x68k_state::plot_pixel(bitmap_rgb32 &bitmap, int x, int y, uint32_t color)
|
||||
{
|
||||
bitmap.pix32(y, x) = (uint16_t)color;
|
||||
}
|
||||
@ -113,7 +113,7 @@ WRITE16_MEMBER(x68k_state::gvram_write)
|
||||
COMBINE_DATA(&m_gvram[offset]);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_spritereg_w )
|
||||
WRITE16_MEMBER(x68k_state::spritereg_w )
|
||||
{
|
||||
COMBINE_DATA(&m_spritereg[offset]);
|
||||
switch(offset)
|
||||
@ -161,14 +161,14 @@ WRITE16_MEMBER(x68k_state::x68k_spritereg_w )
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_spritereg_r )
|
||||
READ16_MEMBER(x68k_state::spritereg_r )
|
||||
{
|
||||
if(offset >= 0x400 && offset < 0x404)
|
||||
return m_spritereg[offset] & 0x3ff;
|
||||
return m_spritereg[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(x68k_state::x68k_spriteram_w )
|
||||
WRITE16_MEMBER(x68k_state::spriteram_w )
|
||||
{
|
||||
COMBINE_DATA(m_spriteram+offset);
|
||||
m_video.tile8_dirty[offset / 16] = 1;
|
||||
@ -192,12 +192,12 @@ WRITE16_MEMBER(x68k_state::x68k_spriteram_w )
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(x68k_state::x68k_spriteram_r )
|
||||
READ16_MEMBER(x68k_state::spriteram_r )
|
||||
{
|
||||
return m_spriteram[offset];
|
||||
}
|
||||
|
||||
void x68k_state::x68k_draw_text(bitmap_rgb32 &bitmap, int xscr, int yscr, rectangle rect)
|
||||
void x68k_state::draw_text(bitmap_rgb32 &bitmap, int xscr, int yscr, rectangle rect)
|
||||
{
|
||||
unsigned int line,pixel; // location on screen
|
||||
uint32_t loc; // location in TVRAM
|
||||
@ -231,7 +231,7 @@ void x68k_state::x68k_draw_text(bitmap_rgb32 &bitmap, int xscr, int yscr, rectan
|
||||
}
|
||||
}
|
||||
|
||||
bool x68k_state::x68k_draw_gfx_scanline( bitmap_ind16 &bitmap, rectangle cliprect, uint8_t priority)
|
||||
bool x68k_state::draw_gfx_scanline( bitmap_ind16 &bitmap, rectangle cliprect, uint8_t priority)
|
||||
{
|
||||
int pixel;
|
||||
int page;
|
||||
@ -388,7 +388,7 @@ bool x68k_state::x68k_draw_gfx_scanline( bitmap_ind16 &bitmap, rectangle cliprec
|
||||
return ret;
|
||||
}
|
||||
|
||||
void x68k_state::x68k_draw_gfx(bitmap_rgb32 &bitmap,rectangle cliprect)
|
||||
void x68k_state::draw_gfx(bitmap_rgb32 &bitmap,rectangle cliprect)
|
||||
{
|
||||
int priority, scanline, pixel;
|
||||
bool gfxblend=false;
|
||||
@ -405,7 +405,7 @@ void x68k_state::x68k_draw_gfx(bitmap_rgb32 &bitmap,rectangle cliprect)
|
||||
|
||||
for(priority=3;priority>=0;priority--)
|
||||
{
|
||||
gfxblend = x68k_draw_gfx_scanline(m_gfxbitmap,cliprect,priority);
|
||||
gfxblend = draw_gfx_scanline(m_gfxbitmap,cliprect,priority);
|
||||
}
|
||||
|
||||
for(scanline=cliprect.min_y;scanline<=cliprect.max_y;scanline++)
|
||||
@ -458,7 +458,7 @@ void x68k_state::x68k_draw_gfx(bitmap_rgb32 &bitmap,rectangle cliprect)
|
||||
}
|
||||
|
||||
// Sprite controller "Cynthia" at 0xeb0000
|
||||
void x68k_state::x68k_draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect)
|
||||
void x68k_state::draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect)
|
||||
{
|
||||
/*
|
||||
0xeb0000 - 0xeb07ff - Sprite registers (up to 128)
|
||||
@ -543,7 +543,7 @@ static const gfx_layout x68k_pcg_16 =
|
||||
128*8
|
||||
};
|
||||
|
||||
TILE_GET_INFO_MEMBER(x68k_state::x68k_get_bg0_tile)
|
||||
TILE_GET_INFO_MEMBER(x68k_state::get_bg0_tile)
|
||||
{
|
||||
int code = m_spriteram[0x3000+tile_index] & 0x00ff;
|
||||
int colour = (m_spriteram[0x3000+tile_index] & 0x0f00) >> 8;
|
||||
@ -551,7 +551,7 @@ TILE_GET_INFO_MEMBER(x68k_state::x68k_get_bg0_tile)
|
||||
SET_TILE_INFO_MEMBER(0,code,colour,flags);
|
||||
}
|
||||
|
||||
TILE_GET_INFO_MEMBER(x68k_state::x68k_get_bg1_tile)
|
||||
TILE_GET_INFO_MEMBER(x68k_state::get_bg1_tile)
|
||||
{
|
||||
int code = m_spriteram[0x2000+tile_index] & 0x00ff;
|
||||
int colour = (m_spriteram[0x2000+tile_index] & 0x0f00) >> 8;
|
||||
@ -559,7 +559,7 @@ TILE_GET_INFO_MEMBER(x68k_state::x68k_get_bg1_tile)
|
||||
SET_TILE_INFO_MEMBER(0,code,colour,flags);
|
||||
}
|
||||
|
||||
TILE_GET_INFO_MEMBER(x68k_state::x68k_get_bg0_tile_16)
|
||||
TILE_GET_INFO_MEMBER(x68k_state::get_bg0_tile_16)
|
||||
{
|
||||
int code = m_spriteram[0x3000+tile_index] & 0x00ff;
|
||||
int colour = (m_spriteram[0x3000+tile_index] & 0x0f00) >> 8;
|
||||
@ -567,7 +567,7 @@ TILE_GET_INFO_MEMBER(x68k_state::x68k_get_bg0_tile_16)
|
||||
SET_TILE_INFO_MEMBER(1,code,colour,flags);
|
||||
}
|
||||
|
||||
TILE_GET_INFO_MEMBER(x68k_state::x68k_get_bg1_tile_16)
|
||||
TILE_GET_INFO_MEMBER(x68k_state::get_bg1_tile_16)
|
||||
{
|
||||
int code = m_spriteram[0x2000+tile_index] & 0x00ff;
|
||||
int colour = (m_spriteram[0x2000+tile_index] & 0x0f00) >> 8;
|
||||
@ -592,10 +592,10 @@ VIDEO_START_MEMBER(x68k_state,x68000)
|
||||
m_gfxdecode->gfx(gfx_index)->set_colors(32);
|
||||
|
||||
/* Tilemaps */
|
||||
m_bg0_8 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::x68k_get_bg0_tile),this),TILEMAP_SCAN_ROWS,8,8,64,64);
|
||||
m_bg1_8 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::x68k_get_bg1_tile),this),TILEMAP_SCAN_ROWS,8,8,64,64);
|
||||
m_bg0_16 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::x68k_get_bg0_tile_16),this),TILEMAP_SCAN_ROWS,16,16,64,64);
|
||||
m_bg1_16 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::x68k_get_bg1_tile_16),this),TILEMAP_SCAN_ROWS,16,16,64,64);
|
||||
m_bg0_8 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::get_bg0_tile),this),TILEMAP_SCAN_ROWS,8,8,64,64);
|
||||
m_bg1_8 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::get_bg1_tile),this),TILEMAP_SCAN_ROWS,8,8,64,64);
|
||||
m_bg0_16 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::get_bg0_tile_16),this),TILEMAP_SCAN_ROWS,16,16,64,64);
|
||||
m_bg1_16 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(x68k_state::get_bg1_tile_16),this),TILEMAP_SCAN_ROWS,16,16,64,64);
|
||||
|
||||
m_bg0_8->set_transparent_pen(0);
|
||||
m_bg1_8->set_transparent_pen(0);
|
||||
@ -609,7 +609,7 @@ VIDEO_START_MEMBER(x68k_state,x68000)
|
||||
// m_scanline_timer->adjust(attotime::zero, 0, attotime::from_hz(55.45)/568);
|
||||
}
|
||||
|
||||
uint32_t x68k_state::screen_update_x68000(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
uint32_t x68k_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
rectangle rect(0,0,0,0);
|
||||
int priority;
|
||||
@ -670,13 +670,13 @@ uint32_t x68k_state::screen_update_x68000(screen_device &screen, bitmap_rgb32 &b
|
||||
{
|
||||
// Graphics screen(s)
|
||||
if(priority == m_video.gfx_pri)
|
||||
x68k_draw_gfx(bitmap,rect);
|
||||
draw_gfx(bitmap,rect);
|
||||
|
||||
// Sprite / BG Tiles
|
||||
if(priority == m_video.sprite_pri /*&& (m_spritereg[0x404] & 0x0200)*/ && (m_video.reg[2] & 0x0040))
|
||||
{
|
||||
m_pcgbitmap.fill(0, rect);
|
||||
x68k_draw_sprites(m_pcgbitmap,1,rect);
|
||||
draw_sprites(m_pcgbitmap,1,rect);
|
||||
if((m_spritereg[0x404] & 0x0008))
|
||||
{
|
||||
if((m_spritereg[0x404] & 0x0030) == 0x10) // BG1 TXSEL
|
||||
@ -692,7 +692,7 @@ uint32_t x68k_state::screen_update_x68000(screen_device &screen, bitmap_rgb32 &b
|
||||
x68k_bg1->draw(screen, m_pcgbitmap,rect,0,0);
|
||||
}
|
||||
}
|
||||
x68k_draw_sprites(m_pcgbitmap,2,rect);
|
||||
draw_sprites(m_pcgbitmap,2,rect);
|
||||
if((m_spritereg[0x404] & 0x0001))
|
||||
{
|
||||
if((m_spritereg[0x404] & 0x0006) == 0x02) // BG0 TXSEL
|
||||
@ -708,7 +708,7 @@ uint32_t x68k_state::screen_update_x68000(screen_device &screen, bitmap_rgb32 &b
|
||||
x68k_bg1->draw(screen, m_pcgbitmap,rect,0,0);
|
||||
}
|
||||
}
|
||||
x68k_draw_sprites(m_pcgbitmap,3,rect);
|
||||
draw_sprites(m_pcgbitmap,3,rect);
|
||||
|
||||
for(scanline=rect.min_y;scanline<=rect.max_y;scanline++)
|
||||
{
|
||||
@ -727,7 +727,7 @@ uint32_t x68k_state::screen_update_x68000(screen_device &screen, bitmap_rgb32 &b
|
||||
xscr = (m_crtc->xscr_text() & 0x3ff);
|
||||
yscr = (m_crtc->yscr_text() & 0x3ff);
|
||||
if(!m_crtc->text_layer_buffer()) // if text layer is set to buffer, then it's not visible
|
||||
x68k_draw_text(bitmap,xscr,yscr,rect);
|
||||
draw_text(bitmap,xscr,yscr,rect);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user