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m6801: Add DDRs as mask for port output callbacks; implement more HD6301X weirdness (nw)

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psion: Use callbacks for port 2; misc. additional cleanups (nw)
This commit is contained in:
AJR 2020-03-13 15:57:47 -04:00
parent 6ccb3256e8
commit 98884c10d8
4 changed files with 50 additions and 41 deletions
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39
src/devices/cpu/m6800/m6801.cpp
View File

@ -884,7 +884,7 @@ void m6801_cpu_device::write_port2()
data &= 0x1f;
m_out_port_func[1](data);
m_out_port_func[1](0, data, ddr);
}
void hd6301x_cpu_device::write_port2()
@ -899,7 +899,7 @@ void hd6301x_cpu_device::write_port2()
data = (data & 0xef) | (m_tx << 4);
}
m_out_port_func[1](data);
m_out_port_func[1](0, data, ddr);
}
/*
@ -925,7 +925,7 @@ void m6801_cpu_device::p1_ddr_w(uint8_t data)
if (m_port_ddr[0] != data)
{
m_port_ddr[0] = data;
m_out_port_func[0]((m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff));
m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
}
}
@ -942,7 +942,7 @@ void m6801_cpu_device::p1_data_w(uint8_t data)
LOGPORT("Port 1 Data Register: %02x\n", data);
m_port_data[0] = data;
m_out_port_func[0]((m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff));
m_out_port_func[0](0, (m_port_data[0] & m_port_ddr[0]) | (m_port_ddr[0] ^ 0xff), m_port_ddr[0]);
}
void m6801_cpu_device::p2_ddr_w(uint8_t data)
@ -956,6 +956,19 @@ void m6801_cpu_device::p2_ddr_w(uint8_t data)
}
}
// HD6301X0/HD63701X0/HD6303X only
void hd6301x_cpu_device::p2_ddr_2bit_w(uint8_t data)
{
LOGPORT("Port 2 Data Direction Register: %02x\n", data);
data = (BIT(data, 1) ? 0xfe : 0x00) | (data & 0x01);
if (m_port_ddr[1] != data)
{
m_port_ddr[1] = data;
write_port2();
}
}
uint8_t m6801_cpu_device::p2_data_r()
{
if(m_port_ddr[1] == 0xff)
@ -980,7 +993,7 @@ void m6801_cpu_device::p3_ddr_w(uint8_t data)
if (m_port_ddr[2] != data)
{
m_port_ddr[2] = data;
m_out_port_func[2]((m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff));
m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff), m_port_ddr[2]);
}
}
@ -1038,7 +1051,7 @@ void m6801_cpu_device::p3_data_w(uint8_t data)
}
m_port_data[2] = data;
m_out_port_func[2]((m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff));
m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff), m_port_ddr[2]);
if (m_p3csr & M6801_P3CSR_OSS)
{
@ -1070,7 +1083,7 @@ void m6801_cpu_device::p4_ddr_w(uint8_t data)
if (m_port_ddr[3] != data)
{
m_port_ddr[3] = data;
m_out_port_func[3]((m_port_data[3] & m_port_ddr[3]) | (m_port_ddr[3] ^ 0xff));
m_out_port_func[3](0, (m_port_data[3] & m_port_ddr[3]) | (m_port_ddr[3] ^ 0xff), m_port_ddr[3]);
}
}
@ -1087,7 +1100,7 @@ void m6801_cpu_device::p4_data_w(uint8_t data)
LOGPORT("Port 4 Data Register: %02x\n", data);
m_port_data[3] = data;
m_out_port_func[3]((m_port_data[3] & m_port_ddr[3]) | (m_port_ddr[3] ^ 0xff));
m_out_port_func[3](0, (m_port_data[3] & m_port_ddr[3]) | (m_port_ddr[3] ^ 0xff), m_port_ddr[3]);
}
void hd6301x_cpu_device::p5_ddr_w(uint8_t data)
@ -1097,7 +1110,7 @@ void hd6301x_cpu_device::p5_ddr_w(uint8_t data)
if (m_portx_ddr[0] != data)
{
m_portx_ddr[0] = data;
m_out_portx_func[0]((m_portx_data[0] & m_portx_ddr[0]) | (m_portx_ddr[0] ^ 0xff));
m_out_portx_func[0](0, (m_portx_data[0] & m_portx_ddr[0]) | (m_portx_ddr[0] ^ 0xff), m_portx_ddr[0]);
}
}
@ -1114,7 +1127,7 @@ void hd6301x_cpu_device::p5_data_w(uint8_t data)
LOGPORT("Port 5 Data Register: %02x\n", data);
m_portx_data[0] = data;
m_out_portx_func[0]((m_portx_data[0] & m_portx_ddr[0]) | (m_portx_ddr[0] ^ 0xff));
m_out_portx_func[0](0, (m_portx_data[0] & m_portx_ddr[0]) | (m_portx_ddr[0] ^ 0xff), m_portx_ddr[0]);
}
void hd6301x_cpu_device::p6_ddr_w(uint8_t data)
@ -1124,7 +1137,7 @@ void hd6301x_cpu_device::p6_ddr_w(uint8_t data)
if (m_portx_ddr[1] != data)
{
m_portx_ddr[1] = data;
m_out_portx_func[1]((m_portx_data[1] & m_portx_ddr[1]) | (m_portx_ddr[1] ^ 0xff));
m_out_portx_func[1](0, (m_portx_data[1] & m_portx_ddr[1]) | (m_portx_ddr[1] ^ 0xff), m_portx_ddr[1]);
}
}
@ -1141,7 +1154,7 @@ void hd6301x_cpu_device::p6_data_w(uint8_t data)
LOGPORT("Port 6 Data Register: %02x\n", data);
m_portx_data[1] = data;
m_out_portx_func[1]((m_portx_data[1] & m_portx_ddr[1]) | (m_portx_ddr[1] ^ 0xff));
m_out_portx_func[1](0, (m_portx_data[1] & m_portx_ddr[1]) | (m_portx_ddr[1] ^ 0xff), m_portx_ddr[1]);
}
uint8_t hd6301x_cpu_device::p7_data_r()
@ -1156,7 +1169,7 @@ void hd6301x_cpu_device::p7_data_w(uint8_t data)
data &= 0x1f;
m_portx_data[2] = data;
m_out_portx_func[2](m_portx_data[2]);
m_out_portx_func[2](0, m_portx_data[2], 0x1f);
}
uint8_t m6801_cpu_device::tcsr_r()

1
src/devices/cpu/m6800/m6801.h
View File

@ -254,6 +254,7 @@ public:
auto out_p7_cb() { return m_out_portx_func[2].bind(); }
// TODO: privatize eventually
void p2_ddr_2bit_w(uint8_t data);
void p5_ddr_w(uint8_t data);
uint8_t p5_data_r();
void p5_data_w(uint8_t data);

40
src/mame/drivers/psion.cpp
View File

@ -36,20 +36,19 @@ TIMER_DEVICE_CALLBACK_MEMBER(psion_state::nmi_timer)
uint8_t psion_state::kb_read()
{
static const char *const bitnames[] = {"K1", "K2", "K3", "K4", "K5", "K6", "K7"};
uint8_t line, data = 0x7c;
uint8_t data = 0x7c;
if (m_kb_counter)
{
for (line = 0; line < 7; line++)
for (int line = 0; line < 7; line++)
if (m_kb_counter == (0x7f & ~(1 << line)))
data = machine().root_device().ioport(bitnames[line])->read();
data = m_kb_lines[line]->read();
}
else
{
//Read all the input lines
for (line = 0; line < 7; line++)
data &= machine().root_device().ioport(bitnames[line])->read();
for (int line = 0; line < 7; line++)
data &= m_kb_lines[line]->read();
}
return data & 0x7c;
@ -64,22 +63,17 @@ void psion_state::update_banks()
membank("rombank")->set_entry(m_rom_bank);
}
void psion_state::port2_ddr_w(uint8_t data)
{
m_port2_ddr = data;
}
void psion_state::port2_w(uint8_t data)
void psion_state::port2_w(offs_t offset, uint8_t data, uint8_t ddr)
{
/* datapack i/o data bus */
m_pack1->data_w(data & m_port2_ddr);
m_pack2->data_w(data & m_port2_ddr);
m_pack1->data_w(data & ddr);
m_pack2->data_w(data & ddr);
}
uint8_t psion_state::port2_r()
{
/* datapack i/o data bus */
return (m_pack1->data_r() | m_pack2->data_r()) & (~m_port2_ddr);
return m_pack1->data_r() | m_pack2->data_r();
}
void psion_state::tcsr_w(uint8_t data)
@ -135,7 +129,7 @@ uint8_t psion_state::port6_r()
}
/* Read/Write common */
void psion_state::io_rw(address_space &space, uint16_t offset)
void psion_state::io_rw(uint16_t offset)
{
if (machine().side_effects_disabled())
return;
@ -202,7 +196,7 @@ WRITE8_MEMBER( psion_state::io_w )
m_lcdc->write(offset & 0x01, data);
break;
default:
io_rw(space, offset);
io_rw(offset);
}
}
@ -213,7 +207,8 @@ READ8_MEMBER( psion_state::io_r )
case 0x80:
return m_lcdc->read(offset & 0x01);
default:
io_rw(space, offset);
if (!machine().side_effects_disabled())
io_rw(offset);
}
return 0;
@ -252,8 +247,7 @@ void psion_state::psion_int_reg(address_map &map)
{
// FIXME: this should all be made internal to the CPU device
map(0x0000, 0x001f).m(m_maincpu, FUNC(hd6301x_cpu_device::m6801_io));
map(0x0001, 0x0001).w(FUNC(psion_state::port2_ddr_w));
map(0x0003, 0x0003).rw(FUNC(psion_state::port2_r), FUNC(psion_state::port2_w));
map(0x0001, 0x0001).w(m_maincpu, FUNC(hd6301x_cpu_device::p2_ddr_2bit_w));
map(0x0008, 0x0008).rw(FUNC(psion_state::tcsr_r), FUNC(psion_state::tcsr_w));
map(0x0014, 0x0014).r(FUNC(psion_state::rcp5c_r));
map(0x0015, 0x0015).r(m_maincpu, FUNC(hd6301x_cpu_device::p5_data_r)).nopw();
@ -511,8 +505,6 @@ void psion_state::machine_start()
save_item(NAME(m_pulse));
save_item(NAME(m_rom_bank));
save_item(NAME(m_ram_bank));
save_item(NAME(m_port2_ddr));
save_item(NAME(m_port2));
save_pointer(NAME(m_paged_ram), m_ram_bank_count * 0x4000);
}
@ -583,6 +575,8 @@ void psion_state::psion_2lines(machine_config &config)
{
/* basic machine hardware */
HD6303X(config, m_maincpu, 3.6864_MHz_XTAL); // internal operating frequency is 0.9216 MHz
m_maincpu->in_p2_cb().set(FUNC(psion_state::port2_r));
m_maincpu->out_p2_cb().set(FUNC(psion_state::port2_w));
m_maincpu->in_p5_cb().set(FUNC(psion_state::port5_r));
m_maincpu->in_p6_cb().set(FUNC(psion_state::port6_r));
m_maincpu->out_p6_cb().set(FUNC(psion_state::port6_w));
@ -636,6 +630,8 @@ void psion1_state::psion1(machine_config &config)
psion_2lines(config);
HD6301X0(config.replace(), m_maincpu, 3.6864_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &psion1_state::psion1_mem);
m_maincpu->in_p2_cb().set(FUNC(psion1_state::port2_r));
m_maincpu->out_p2_cb().set(FUNC(psion1_state::port2_w));
m_maincpu->in_p5_cb().set(FUNC(psion1_state::port5_r));
m_maincpu->in_p6_cb().set(FUNC(psion1_state::port6_r));
m_maincpu->out_p6_cb().set(FUNC(psion1_state::port6_w));

11
src/mame/includes/psion.h
View File

@ -37,6 +37,7 @@ public:
, m_sys_register(*this, "sys_register")
, m_stby_pwr(1)
, m_ram(*this, "ram")
, m_kb_lines(*this, "K%u", 1U)
{ }
void psion_2lines(machine_config &config);
@ -66,9 +67,6 @@ protected:
uint8_t m_stby_pwr;
uint8_t m_pulse;
uint8_t m_port2_ddr; // datapack i/o ddr
uint8_t m_port2; // datapack i/o data bus
// RAM/ROM banks
required_shared_ptr<uint8_t> m_ram;
std::unique_ptr<uint8_t[]> m_paged_ram;
@ -77,14 +75,15 @@ protected:
uint8_t m_ram_bank_count;
uint8_t m_rom_bank_count;
required_ioport_array<7> m_kb_lines;
virtual void machine_start() override;
virtual void machine_reset() override;
void nvram_init(nvram_device &nvram, void *data, size_t size);
uint8_t kb_read();
void update_banks();
void port2_ddr_w(uint8_t data);
void port2_w(uint8_t data);
void port2_w(offs_t offset, uint8_t data, uint8_t ddr);
uint8_t port2_r();
void tcsr_w(uint8_t data);
uint8_t tcsr_r();
@ -92,7 +91,7 @@ protected:
uint8_t port5_r();
void port6_w(uint8_t data);
uint8_t port6_r();
void io_rw(address_space &space, uint16_t offset);
void io_rw(uint16_t offset);
DECLARE_WRITE8_MEMBER( io_w );
DECLARE_READ8_MEMBER( io_r );
void psion_palette(palette_device &palette) const;