mirror of
https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
8042kbdc.c [Peter Ferrie]
- add support for keyboard enable command - add support for keyboard reset command idectrl.c [Peter Ferrie] - correct status flags for multi-sector reads - implement more correct controller reset values - fix phantom slave drive detection problem calchase.c [Peter Ferrie] - corrected memory map to 64kb blocks - corrected access to PAM register - removed execution hack queen.c [Peter Ferrie] - split BIOS region into 64kb blocks - implement missing PAM registers - remove unused PAM regions savquest.c [Peter Ferrie] - split BIOS region into 16kb blocks - implement missing PAM registers - correct slave_ack configuration member declaration
This commit is contained in:
Scott Stone
parent
f5e3f157b1
commit
99345a6c27
@ -364,12 +364,19 @@ READ8_HANDLER(kbdc8042_8_r)
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switch (offset) {
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case 0:
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data = kbdc8042.data;
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if (kbdc8042.type != KBDC8042_AT386 || (data != 0x55))
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if ((kbdc8042.status_read_mode != 3) || (data != 0xfa))
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{
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/* at386 self test doesn't like this */
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at_8042_clear_keyboard_received();
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if (kbdc8042.type != KBDC8042_AT386 || (data != 0x55))
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{
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/* at386 self test doesn't like this */
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at_8042_clear_keyboard_received();
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}
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at_8042_check_keyboard(space.machine());
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}
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else
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{
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kbdc8042.status_read_mode = 4;
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}
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at_8042_check_keyboard(space.machine());
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break;
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case 1:
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@ -428,6 +435,10 @@ READ8_HANDLER(kbdc8042_8_r)
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case 2:
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data |= kbdc8042.inport<<4;
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break;
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case 4:
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at_8042_receive(space.machine(), 0xaa);
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kbdc8042.status_read_mode = 0;
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break;
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}
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break;
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}
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@ -447,6 +458,18 @@ WRITE8_HANDLER(kbdc8042_8_w)
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kbdc8042.status_read_mode = 0;
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switch (kbdc8042.operation_write_state) {
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case 0:
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if ((data == 0xf4) || (data == 0xff)) /* keyboard enable or keyboard reset */
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{
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at_8042_receive(space.machine(), 0xfa); /* ACK, delivered a bit differently */
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if (data == 0xff)
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{
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kbdc8042.status_read_mode = 3; /* keyboard buffer to be written again after next read */
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}
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break;
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}
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/* normal case */
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kbdc8042.data = data;
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kbdc8042.sending=1;
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@ -518,8 +518,10 @@ void ide_controller_device::continue_read()
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/* reset the totals */
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buffer_offset = 0;
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/* clear the buffer ready and busy flag */
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status &= ~IDE_STATUS_BUFFER_READY;
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/* clear just the busy flag
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the buffer ready flag stays set until all sectors are read
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*/
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// status &= ~IDE_STATUS_BUFFER_READY;
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status &= ~IDE_STATUS_BUSY;
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if (master_password_enable || user_password_enable)
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@ -540,6 +542,7 @@ void ide_controller_device::continue_read()
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read_next_sector();
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else
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{
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status &= ~IDE_STATUS_BUFFER_READY; /* now clear it */
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bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
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dma_active = 0;
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}
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@ -696,7 +699,7 @@ void ide_controller_device::read_first_sector()
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void ide_controller_device::read_next_sector()
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{
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/* mark ourselves busy */
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status |= IDE_STATUS_BUSY;
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// status |= IDE_STATUS_BUSY;
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if (command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
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{
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@ -1180,6 +1183,10 @@ UINT32 ide_controller_device::ide_controller_read(int bank, offs_t offset, int s
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status &= ~IDE_STATUS_DRIVE_READY;
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}
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}
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else
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{
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return 0;
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}
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switch (BANK(bank, offset))
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{
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@ -1432,9 +1439,17 @@ void ide_controller_device::ide_controller_write(int bank, offs_t offset, int si
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//if (data == 0x04)
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if (data & 0x04)
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{
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status |= IDE_STATUS_BUSY;
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status &= ~IDE_STATUS_DRIVE_READY;
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reset_timer->adjust(attotime::from_msec(5));
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// status |= IDE_STATUS_BUSY;
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// status &= ~IDE_STATUS_DRIVE_READY;
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// reset_timer->adjust(attotime::from_msec(5));
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device_reset(); /* deliver instantly to support buggy BIOSes that don't poll properly */
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sector_count = 1;
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drive[0].cur_sector = 1;
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drive[0].cur_head = 0;
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drive[0].cur_cylinder = 0;
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drive[1].cur_sector = 1;
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drive[1].cur_head = 0;
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drive[1].cur_cylinder = 0;
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}
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break;
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}
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@ -104,6 +104,10 @@ something wrong in the disk geometry reported by calchase.chd (20,255,63) since
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255 heads as parameter. Perhaps a bad dump?
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TODO: A lot of work to do yet!!!
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- update by peter ferrie:
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- corrected memory map to 64kb blocks
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- corrected access to PAM register
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*/
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@ -131,6 +135,7 @@ public:
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{ }
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UINT32 *m_bios_ram;
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UINT32 *m_bios_ext_ram;
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int m_dma_channel;
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UINT8 m_dma_offset[2][4];
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UINT8 m_at_pages[0x10];
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@ -149,6 +154,7 @@ public:
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DECLARE_WRITE8_MEMBER(at_page8_w);
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DECLARE_READ8_MEMBER(pc_dma_read_byte);
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DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
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DECLARE_WRITE32_MEMBER(bios_ext_ram_w);
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DECLARE_WRITE32_MEMBER(bios_ram_w);
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DECLARE_READ16_MEMBER(calchase_iocard1_r);
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DECLARE_READ16_MEMBER(calchase_iocard2_r);
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@ -336,32 +342,26 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
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calchase_state *state = busdevice->machine().driver_data<calchase_state>();
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// mame_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
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switch(reg)
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{
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//case 0x59:
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case 0x63: // PAM0
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{
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//if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
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if ((data & 0x50) | (data & 0xA0))
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{
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state->membank("bank1")->set_base(state->m_bios_ram);
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}
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else // disable RAM access (reads go to BIOS ROM)
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{
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//Execution Hack to avoid crash when switch back from Shadow RAM to Bios ROM, since i386 emu haven't yet pipelined execution structure.
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//It happens when exit from BIOS SETUP.
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#if 0
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if ((state->m_mxtc_config_reg[0x63] & 0x50) | ( state->m_mxtc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM.
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{
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if ( busdevice->machine(->safe_pc().device("maincpu"))==0xff74e) busdevice->machine().device("maincpu")->state().set_pc(0xff74d);
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}
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#endif
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/*
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memory banking with North Bridge:
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0x63 (PAM) xx-- ---- BIOS extension 0xe0000 - 0xeffff
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--xx ---- BIOS area 0xf0000-0xfffff
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---- xx-- ISA add-on BIOS 0xc0000 - 0xcffff
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---- --xx ISA add-on BIOS 0xd0000 - 0xdffff
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state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x10000);
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state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base());
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}
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break;
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}
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10 -> 1 = Write Enable, 0 = Read Enable
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*/
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if (reg == 0x63)
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{
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if (data & 0x20) // enable RAM access to region 0xf0000 - 0xfffff
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state->membank("bios_bank")->set_base(state->m_bios_ram);
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else // disable RAM access (reads go to BIOS ROM)
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state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x10000);
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if (data & 0x80) // enable RAM access to region 0xe0000 - 0xeffff
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state->membank("bios_ext")->set_base(state->m_bios_ext_ram);
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else
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state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0);
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}
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state->m_mxtc_config_reg[reg] = data;
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@ -489,13 +489,20 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi
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WRITE32_MEMBER(calchase_state::bios_ram_w)
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{
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//if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
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if (m_mxtc_config_reg[0x63] & 0x50)
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if (m_mxtc_config_reg[0x63] & 0x10) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_bios_ram + offset);
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}
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}
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WRITE32_MEMBER(calchase_state::bios_ext_ram_w)
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{
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if (m_mxtc_config_reg[0x63] & 0x40) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_bios_ext_ram + offset);
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}
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}
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READ16_MEMBER(calchase_state::calchase_iocard1_r)
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{
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return ioport("IOCARD1")->read();
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@ -555,8 +562,8 @@ static ADDRESS_MAP_START( calchase_map, AS_PROGRAM, 32, calchase_state )
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//GRULL AM_RANGE(0x000e0000, 0x000effff) AM_RAM
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//GRULL-AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bank1")
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//GRULL AM_RANGE(0x000f0000, 0x000fffff) AM_WRITE(bios_ram_w)
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AM_RANGE(0x000e0000, 0x000fffff) AM_ROMBANK("bank1")
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AM_RANGE(0x000e0000, 0x000fffff) AM_WRITE(bios_ram_w)
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AM_RANGE(0x000e0000, 0x000effff) AM_ROMBANK("bios_ext") AM_WRITE(bios_ext_ram_w)
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AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_bank") AM_WRITE(bios_ram_w)
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AM_RANGE(0x00100000, 0x03ffffff) AM_RAM // 64MB
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AM_RANGE(0x02000000, 0x28ffffff) AM_NOP
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//AM_RANGE(0x04000000, 0x040001ff) AM_RAM
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@ -804,6 +811,9 @@ static IRQ_CALLBACK(irq_callback)
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void calchase_state::machine_start()
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{
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m_bios_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
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m_bios_ext_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
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machine().device("maincpu")->execute().set_irq_acknowledge_callback(irq_callback);
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m_pit8254 = machine().device( "pit8254" );
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@ -877,7 +887,8 @@ static const struct pit8253_config calchase_pit8254_config =
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void calchase_state::machine_reset()
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{
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//machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base() + 0x10000);
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machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base());
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machine().root_device().membank("bios_bank")->set_base(machine().root_device().memregion("bios")->base() + 0x10000);
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machine().root_device().membank("bios_ext")->set_base(machine().root_device().memregion("bios")->base() + 0);
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}
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static void set_gate_a20(running_machine &machine, int a20)
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@ -2,18 +2,6 @@
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/*
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TODO:
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- goes to la-la-land almost immediately:
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000F4023: sbb [42F9h],ah
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000F4027: loop 0F4003h
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000F4003: ror word ptr [si+48B2h],1
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000F4007: cmp ax,44B2h
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000F400A: retf
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000903D3: add [bx+si],al
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000903D5: add [bx+si],al
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(Reads stack from BIOS ROM?)
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Produttore STG
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N.revisione
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CPU main PCB is a standard EPIA
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@ -29,6 +17,10 @@ processor speed is 533MHz <- likely to be a Celeron or a Pentium III class CPU -
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it's a 2002 era PC at least based on the BIOS,
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almost certainly newer than the standard 'PENTIUM' CPU
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- update by Peter Ferrie:
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- split BIOS region into 64kb blocks and implement missing PAM registers
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- VIA Apollo VXPro chipset is not compatible with Intel i430.
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*/
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@ -60,12 +52,7 @@ public:
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{ }
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UINT32 *m_bios_ram;
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UINT32 *m_bios_ext1_ram;
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UINT32 *m_bios_ext2_ram;
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UINT32 *m_bios_ext3_ram;
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UINT32 *m_bios_ext4_ram;
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UINT32 *m_isa_ram1;
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UINT32 *m_isa_ram2;
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UINT32 *m_bios_ext_ram;
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int m_dma_channel;
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UINT8 m_dma_offset[2][4];
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UINT8 m_at_pages[0x10];
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@ -82,13 +69,7 @@ public:
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DECLARE_READ8_MEMBER( get_slave_ack );
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DECLARE_WRITE32_MEMBER( isa_ram1_w );
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DECLARE_WRITE32_MEMBER( isa_ram2_w );
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DECLARE_WRITE32_MEMBER( bios_ext1_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ext2_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ext3_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ext4_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ext_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ram_w );
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DECLARE_READ8_MEMBER(at_page8_r);
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@ -129,76 +110,24 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
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/*
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memory banking with North Bridge:
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0x59 (PAM0) xxxx ---- BIOS area 0xf0000-0xfffff
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---- xxxx Reserved
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0x5a (PAM1) xxxx ---- ISA add-on BIOS 0xc4000 - 0xc7fff
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---- xxxx ISA add-on BIOS 0xc0000 - 0xc3fff
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0x5b (PAM2) xxxx ---- ISA add-on BIOS 0xcc000 - 0xcffff
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---- xxxx ISA add-on BIOS 0xc8000 - 0xcbfff
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0x5c (PAM3) xxxx ---- ISA add-on BIOS 0xd4000 - 0xd7fff
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---- xxxx ISA add-on BIOS 0xd0000 - 0xd3fff
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0x5d (PAM4) xxxx ---- ISA add-on BIOS 0xdc000 - 0xdffff
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---- xxxx ISA add-on BIOS 0xd8000 - 0xdbfff
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0x5e (PAM5) xxxx ---- BIOS extension 0xe4000 - 0xe7fff
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---- xxxx BIOS extension 0xe0000 - 0xe3fff
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0x5f (PAM6) xxxx ---- BIOS extension 0xec000 - 0xeffff
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---- xxxx BIOS extension 0xe8000 - 0xebfff
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0x63 (PAM) xx-- ---- BIOS area 0xf0000-0xfffff
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--xx ---- BIOS extension 0xe0000 - 0xeffff
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---- xx-- ISA add-on BIOS 0xd0000 - 0xdffff
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---- --xx ISA add-on BIOS 0xc0000 - 0xcffff
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3210 -> 3 = reserved, 2 = Cache Enable, 1 = Write Enable, 0 = Read Enable
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10 -> 1 = Write Enable, 0 = Read Enable
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*/
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switch(reg)
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if (reg == 0x63)
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{
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case 0x59: // PAM0
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{
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if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
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state->membank("bios_bank")->set_base(state->m_bios_ram);
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else // disable RAM access (reads go to BIOS ROM)
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state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x10000);
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break;
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}
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case 0x5a: // PAM1
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{
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if (data & 0x1)
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state->membank("video_bank1")->set_base(state->m_isa_ram1);
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else
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state->membank("video_bank1")->set_base(state->memregion("video_bios")->base() + 0);
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if (data & 0x10)
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state->membank("video_bank2")->set_base(state->m_isa_ram2);
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else
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state->membank("video_bank2")->set_base(state->memregion("video_bios")->base() + 0x4000);
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break;
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}
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case 0x5e: // PAM5
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{
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if (data & 0x1)
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state->membank("bios_ext1")->set_base(state->m_bios_ext1_ram);
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else
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state->membank("bios_ext1")->set_base(state->memregion("bios")->base() + 0);
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if (data & 0x10)
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state->membank("bios_ext2")->set_base(state->m_bios_ext2_ram);
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else
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state->membank("bios_ext2")->set_base(state->memregion("bios")->base() + 0x4000);
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break;
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}
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case 0x5f: // PAM6
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{
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if (data & 0x1)
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state->membank("bios_ext3")->set_base(state->m_bios_ext3_ram);
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else
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state->membank("bios_ext3")->set_base(state->memregion("bios")->base() + 0x8000);
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if (data & 0x10)
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state->membank("bios_ext4")->set_base(state->m_bios_ext4_ram);
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else
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state->membank("bios_ext4")->set_base(state->memregion("bios")->base() + 0xc000);
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break;
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}
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if (data & 0x20) // enable RAM access to region 0xf0000 - 0xfffff
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state->membank("bios_bank")->set_base(state->m_bios_ram);
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else // disable RAM access (reads go to BIOS ROM)
|
||||
state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x30000);
|
||||
if (data & 0x80) // enable RAM access to region 0xe0000 - 0xeffff
|
||||
state->membank("bios_ext")->set_base(state->m_bios_ext_ram);
|
||||
else
|
||||
state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0x20000);
|
||||
}
|
||||
|
||||
state->m_mxtc_config_reg[reg] = data;
|
||||
@ -316,61 +245,18 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(queen_state::isa_ram1_w)
|
||||
WRITE32_MEMBER(queen_state::bios_ext_ram_w)
|
||||
{
|
||||
if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
|
||||
if (m_mxtc_config_reg[0x63] & 0x40) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_isa_ram1 + offset);
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(queen_state::isa_ram2_w)
|
||||
{
|
||||
if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_isa_ram2 + offset);
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(queen_state::bios_ext1_ram_w)
|
||||
{
|
||||
if (m_mxtc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_ext1_ram + offset);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(queen_state::bios_ext2_ram_w)
|
||||
{
|
||||
if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_ext2_ram + offset);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(queen_state::bios_ext3_ram_w)
|
||||
{
|
||||
if (m_mxtc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_ext3_ram + offset);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(queen_state::bios_ext4_ram_w)
|
||||
{
|
||||
if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_ext4_ram + offset);
|
||||
COMBINE_DATA(m_bios_ext_ram + offset);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(queen_state::bios_ram_w)
|
||||
{
|
||||
if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
|
||||
if (m_mxtc_config_reg[0x63] & 0x10) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_ram + offset);
|
||||
}
|
||||
@ -518,12 +404,7 @@ static I8237_INTERFACE( dma8237_2_config )
|
||||
static ADDRESS_MAP_START( queen_map, AS_PROGRAM, 32, queen_state )
|
||||
AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
|
||||
AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
|
||||
AM_RANGE(0x000c0000, 0x000c3fff) AM_ROMBANK("video_bank1") AM_WRITE(isa_ram1_w)
|
||||
AM_RANGE(0x000c4000, 0x000c7fff) AM_ROMBANK("video_bank2") AM_WRITE(isa_ram2_w)
|
||||
AM_RANGE(0x000e0000, 0x000e3fff) AM_ROMBANK("bios_ext1") AM_WRITE(bios_ext1_ram_w)
|
||||
AM_RANGE(0x000e4000, 0x000e7fff) AM_ROMBANK("bios_ext2") AM_WRITE(bios_ext2_ram_w)
|
||||
AM_RANGE(0x000e8000, 0x000ebfff) AM_ROMBANK("bios_ext3") AM_WRITE(bios_ext3_ram_w)
|
||||
AM_RANGE(0x000ec000, 0x000effff) AM_ROMBANK("bios_ext4") AM_WRITE(bios_ext4_ram_w)
|
||||
AM_RANGE(0x000e0000, 0x000effff) AM_ROMBANK("bios_ext") AM_WRITE(bios_ext_ram_w)
|
||||
AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_bank") AM_WRITE(bios_ram_w)
|
||||
AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
|
||||
AM_RANGE(0xfffc0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
|
||||
@ -635,12 +516,7 @@ static IRQ_CALLBACK(irq_callback)
|
||||
void queen_state::machine_start()
|
||||
{
|
||||
m_bios_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
|
||||
m_bios_ext1_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_bios_ext2_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_bios_ext3_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_bios_ext4_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_isa_ram1 = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_isa_ram2 = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_bios_ext_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
|
||||
|
||||
init_pc_common(machine(), PCCOMMON_KEYBOARD_AT, queen_set_keyb_int);
|
||||
|
||||
@ -653,12 +529,7 @@ void queen_state::machine_start()
|
||||
void queen_state::machine_reset()
|
||||
{
|
||||
machine().root_device().membank("bios_bank")->set_base(machine().root_device().memregion("bios")->base() + 0x30000);
|
||||
machine().root_device().membank("bios_ext1")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
|
||||
machine().root_device().membank("bios_ext2")->set_base(machine().root_device().memregion("bios")->base() + 0x24000);
|
||||
machine().root_device().membank("bios_ext3")->set_base(machine().root_device().memregion("bios")->base() + 0x28000);
|
||||
machine().root_device().membank("bios_ext4")->set_base(machine().root_device().memregion("bios")->base() + 0x2c000);
|
||||
machine().root_device().membank("video_bank1")->set_base(machine().root_device().memregion("video_bios")->base() + 0);
|
||||
machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000);
|
||||
machine().root_device().membank("bios_ext")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -5,10 +5,6 @@
|
||||
"Savage Quest" (c) 1999 Interactive Light, developed by Angel Studios.
|
||||
Skeleton by R. Belmont
|
||||
|
||||
TODO:
|
||||
- BIOS ROM checksum error;
|
||||
- floppy drive error, system halt;
|
||||
|
||||
H/W is a white-box PC consisting of:
|
||||
Pentium II 450 CPU
|
||||
DFI P2XBL motherboard (i440BX chipset)
|
||||
@ -22,6 +18,10 @@
|
||||
Copyright Nicola Salmoria and the MAME Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
- update by Peter Ferrie:
|
||||
- split BIOS region into 16kb blocks and implement missing PAM registers
|
||||
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
@ -52,12 +52,16 @@ public:
|
||||
m_pic8259_2(*this, "pic8259_2")
|
||||
{ }
|
||||
|
||||
UINT32 *m_bios_ram;
|
||||
UINT32 *m_bios_f0000_ram;
|
||||
UINT32 *m_bios_e0000_ram;
|
||||
UINT32 *m_bios_e4000_ram;
|
||||
UINT32 *m_bios_e8000_ram;
|
||||
UINT32 *m_bios_ec000_ram;
|
||||
int m_dma_channel;
|
||||
UINT8 m_dma_offset[2][4];
|
||||
UINT8 m_at_pages[0x10];
|
||||
UINT8 m_mxtc_config_reg[256];
|
||||
UINT8 m_piix4_config_reg[4][256];
|
||||
UINT8 m_piix4_config_reg[8][256];
|
||||
|
||||
// devices
|
||||
required_device<cpu_device> m_maincpu;
|
||||
@ -68,7 +72,11 @@ public:
|
||||
required_device<pic8259_device> m_pic8259_2;
|
||||
|
||||
DECLARE_READ8_MEMBER( get_slave_ack );
|
||||
DECLARE_WRITE32_MEMBER( bios_ram_w );
|
||||
DECLARE_WRITE32_MEMBER( bios_f0000_ram_w );
|
||||
DECLARE_WRITE32_MEMBER( bios_e0000_ram_w );
|
||||
DECLARE_WRITE32_MEMBER( bios_e4000_ram_w );
|
||||
DECLARE_WRITE32_MEMBER( bios_e8000_ram_w );
|
||||
DECLARE_WRITE32_MEMBER( bios_ec000_ram_w );
|
||||
|
||||
protected:
|
||||
|
||||
@ -118,11 +126,55 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
|
||||
{
|
||||
if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
|
||||
{
|
||||
state->membank("bank1")->set_base(state->m_bios_ram);
|
||||
state->membank("bios_f0000")->set_base(state->m_bios_f0000_ram);
|
||||
}
|
||||
else // disable RAM access (reads go to BIOS ROM)
|
||||
{
|
||||
state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x20000);
|
||||
state->membank("bios_f0000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x30000);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x5e: // PAM5
|
||||
{
|
||||
if (data & 0x10) // enable RAM access to region 0xe4000 - 0xe7fff
|
||||
{
|
||||
state->membank("bios_e4000")->set_base(state->m_bios_e4000_ram);
|
||||
}
|
||||
else // disable RAM access (reads go to BIOS ROM)
|
||||
{
|
||||
state->membank("bios_e4000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x24000);
|
||||
}
|
||||
|
||||
if (data & 1) // enable RAM access to region 0xe0000 - 0xe3fff
|
||||
{
|
||||
state->membank("bios_e0000")->set_base(state->m_bios_e0000_ram);
|
||||
}
|
||||
else // disable RAM access (reads go to BIOS ROM)
|
||||
{
|
||||
state->membank("bios_e0000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x20000);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x5f: // PAM6
|
||||
{
|
||||
if (data & 0x10) // enable RAM access to region 0xec000 - 0xeffff
|
||||
{
|
||||
state->membank("bios_ec000")->set_base(state->m_bios_ec000_ram);
|
||||
}
|
||||
else // disable RAM access (reads go to BIOS ROM)
|
||||
{
|
||||
state->membank("bios_ec000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x2c000);
|
||||
}
|
||||
|
||||
if (data & 1) // enable RAM access to region 0xe8000 - 0xebfff
|
||||
{
|
||||
state->membank("bios_e8000")->set_base(state->m_bios_e8000_ram);
|
||||
}
|
||||
else // disable RAM access (reads go to BIOS ROM)
|
||||
{
|
||||
state->membank("bios_e8000")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x28000);
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -243,13 +295,57 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(savquest_state::bios_ram_w)
|
||||
WRITE32_MEMBER(savquest_state::bios_f0000_ram_w)
|
||||
{
|
||||
//if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
|
||||
#if 1
|
||||
if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_ram + offset);
|
||||
COMBINE_DATA(m_bios_f0000_ram + offset);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(savquest_state::bios_e0000_ram_w)
|
||||
{
|
||||
//if (m_mxtc_config_reg[0x5e] & 2) // write to RAM if this region is write-enabled
|
||||
#if 1
|
||||
if (m_mxtc_config_reg[0x5e] & 2) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_e0000_ram + offset);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(savquest_state::bios_e4000_ram_w)
|
||||
{
|
||||
//if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
|
||||
#if 1
|
||||
if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_e4000_ram + offset);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(savquest_state::bios_e8000_ram_w)
|
||||
{
|
||||
//if (m_mxtc_config_reg[0x5f] & 2) // write to RAM if this region is write-enabled
|
||||
#if 1
|
||||
if (m_mxtc_config_reg[0x5f] & 2) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_e8000_ram + offset);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(savquest_state::bios_ec000_ram_w)
|
||||
{
|
||||
//if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
|
||||
#if 1
|
||||
if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
|
||||
{
|
||||
COMBINE_DATA(m_bios_ec000_ram + offset);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -398,8 +494,11 @@ static ADDRESS_MAP_START(savquest_map, AS_PROGRAM, 32, savquest_state)
|
||||
AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
|
||||
AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
|
||||
AM_RANGE(0x000c0000, 0x000c7fff) AM_ROM AM_REGION("video_bios", 0)
|
||||
AM_RANGE(0x000e0000, 0x000fffff) AM_ROMBANK("bank1")
|
||||
AM_RANGE(0x000e0000, 0x000fffff) AM_WRITE(bios_ram_w)
|
||||
AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_f0000") AM_WRITE(bios_f0000_ram_w)
|
||||
AM_RANGE(0x000e0000, 0x000e3fff) AM_ROMBANK("bios_e0000") AM_WRITE(bios_e0000_ram_w)
|
||||
AM_RANGE(0x000e4000, 0x000e7fff) AM_ROMBANK("bios_e4000") AM_WRITE(bios_e4000_ram_w)
|
||||
AM_RANGE(0x000e8000, 0x000ebfff) AM_ROMBANK("bios_e8000") AM_WRITE(bios_e8000_ram_w)
|
||||
AM_RANGE(0x000ec000, 0x000effff) AM_ROMBANK("bios_ec000") AM_WRITE(bios_ec000_ram_w)
|
||||
AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
|
||||
// AM_RANGE(0x02000000, 0x02000003) // protection dongle lies there?
|
||||
AM_RANGE(0xfffc0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
|
||||
@ -467,7 +566,7 @@ static const struct pic8259_interface savquest_pic8259_1_config =
|
||||
{
|
||||
DEVCB_DRIVER_LINE_MEMBER(savquest_state,savquest_pic8259_1_set_int_line),
|
||||
DEVCB_LINE_VCC,
|
||||
DEVCB_MEMBER(savquest_state,get_slave_ack)
|
||||
DEVCB_DRIVER_MEMBER(savquest_state,get_slave_ack)
|
||||
};
|
||||
|
||||
static const struct pic8259_interface savquest_pic8259_2_config =
|
||||
@ -515,7 +614,11 @@ static IRQ_CALLBACK(irq_callback)
|
||||
|
||||
void savquest_state::machine_start()
|
||||
{
|
||||
m_bios_ram = auto_alloc_array(machine(), UINT32, 0x20000/4);
|
||||
m_bios_f0000_ram = auto_alloc_array(machine(), UINT32, 0x10000/4);
|
||||
m_bios_e0000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_bios_e4000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_bios_e8000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
m_bios_ec000_ram = auto_alloc_array(machine(), UINT32, 0x4000/4);
|
||||
|
||||
init_pc_common(machine(), PCCOMMON_KEYBOARD_AT, savquest_set_keyb_int);
|
||||
|
||||
@ -527,7 +630,11 @@ void savquest_state::machine_start()
|
||||
|
||||
void savquest_state::machine_reset()
|
||||
{
|
||||
machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
|
||||
machine().root_device().membank("bios_f0000")->set_base(machine().root_device().memregion("bios")->base() + 0x30000);
|
||||
machine().root_device().membank("bios_e0000")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
|
||||
machine().root_device().membank("bios_e4000")->set_base(machine().root_device().memregion("bios")->base() + 0x24000);
|
||||
machine().root_device().membank("bios_e8000")->set_base(machine().root_device().memregion("bios")->base() + 0x28000);
|
||||
machine().root_device().membank("bios_ec000")->set_base(machine().root_device().memregion("bios")->base() + 0x2c000);
|
||||
}
|
||||
|
||||
static MACHINE_CONFIG_START( savquest, savquest_state )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user