Pointer-ified the TMS32031 core.
This commit is contained in:
Aaron Giles
parent
fae2eb291a
commit
9a0493f14a
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
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/***************************************************************************
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tms32031.c
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tms->c
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Core implementation for the portable TMS32C031 emulator.
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Written by Aaron Giles
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@ -72,7 +72,7 @@ enum
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#define CCFLAG 0x1000
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#define GIEFLAG 0x2000
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#define IREG(rnum) (tms32031.r[rnum].i32[0])
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#define IREG(T,rnum) ((T)->r[rnum].i32[0])
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@ -80,7 +80,16 @@ enum
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STRUCTURES & TYPEDEFS
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***************************************************************************/
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union genreg
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typedef union _int_double int_double;
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union _int_double
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{
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double d;
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float f[2];
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UINT32 i[2];
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};
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typedef union _tmsreg tmsreg;
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union _tmsreg
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{
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UINT32 i32[2];
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UINT16 i16[4];
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@ -88,30 +97,31 @@ union genreg
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};
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/* TMS34031 Registers */
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typedef struct
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typedef struct _tms32031_state tms32031_state;
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struct _tms32031_state
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{
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/* core registers */
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UINT32 pc;
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union genreg r[36];
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UINT32 bkmask;
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UINT32 pc;
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tmsreg r[36];
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UINT32 bkmask;
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/* internal stuff */
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UINT32 op;
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UINT16 irq_state;
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UINT8 delayed;
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UINT8 irq_pending;
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UINT8 mcu_mode;
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UINT8 is_32032;
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UINT8 is_idling;
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int interrupt_cycles;
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UINT16 irq_state;
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UINT8 delayed;
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UINT8 irq_pending;
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UINT8 mcu_mode;
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UINT8 is_32032;
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UINT8 is_idling;
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int icount;
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UINT32 bootoffset;
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void (*xf0_w)(UINT8 val);
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void (*xf1_w)(UINT8 val);
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void (*iack_w)(UINT8 val, offs_t addr);
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cpu_irq_callback irq_callback;
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UINT32 bootoffset;
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tms32031_xf_func xf0_w;
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tms32031_xf_func xf1_w;
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tms32031_iack_func iack_w;
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cpu_irq_callback irq_callback;
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const device_config *device;
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} tms32031_regs;
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const address_space *program;
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};
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@ -119,24 +129,8 @@ typedef struct
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FUNCTION PROTOTYPES
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***************************************************************************/
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static void trap(int trapnum);
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static UINT32 boot_loader(UINT32 boot_rom_addr);
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/***************************************************************************
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PUBLIC GLOBAL VARIABLES
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***************************************************************************/
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static int tms32031_icount;
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/***************************************************************************
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PRIVATE GLOBAL VARIABLES
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***************************************************************************/
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static tms32031_regs tms32031;
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static void trap(tms32031_state *tms, int trapnum);
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static UINT32 boot_loader(tms32031_state *tms, UINT32 boot_rom_addr);
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@ -144,12 +138,11 @@ static tms32031_regs tms32031;
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MEMORY ACCESSORS
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***************************************************************************/
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#define ROPCODE(pc) program_decrypted_read_dword((pc) << 2)
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#define OP tms32031.op
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#define ROPCODE(T,pc) memory_decrypted_read_dword((T)->program, (pc) << 2)
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#define RMEM(T,addr) memory_read_dword_32le((T)->program, (addr) << 2)
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#define WMEM(T,addr,data) memory_write_dword_32le((T)->program, (addr) << 2, data)
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#define RMEM(addr) program_read_dword_32le((addr) << 2)
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#define WMEM(addr,data) program_write_dword_32le((addr) << 2, data)
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#define UPDATEPC(addr) change_pc((addr) << 2)
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@ -162,15 +155,12 @@ static tms32031_regs tms32031;
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#define SET_MANTISSA(r,v) ((r)->i32[0] = (v))
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#define SET_EXPONENT(r,v) ((r)->i32[1] = (v))
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typedef union int_double
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{
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double d;
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float f[2];
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UINT32 i[2];
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} int_double;
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/***************************************************************************
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CONVERSION FUNCTIONS
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***************************************************************************/
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static float dsp_to_float(union genreg *fp)
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static float dsp_to_float(tmsreg *fp)
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{
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int_double id;
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@ -191,7 +181,7 @@ static float dsp_to_float(union genreg *fp)
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}
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static double dsp_to_double(union genreg *fp)
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static double dsp_to_double(tmsreg *fp)
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{
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int_double id;
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@ -214,7 +204,7 @@ static double dsp_to_double(union genreg *fp)
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}
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static void double_to_dsp(double val, union genreg *result)
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static void double_to_dsp(double val, tmsreg *result)
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{
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int mantissa, exponent;
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int_double id;
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@ -255,7 +245,7 @@ static void double_to_dsp(double val, union genreg *result)
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float convert_tms3203x_fp_to_float(UINT32 floatdata)
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{
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union genreg gen;
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tmsreg gen;
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SET_MANTISSA(&gen, floatdata << 8);
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SET_EXPONENT(&gen, (INT32)floatdata >> 24);
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@ -266,7 +256,7 @@ float convert_tms3203x_fp_to_float(UINT32 floatdata)
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double convert_tms3203x_fp_to_double(UINT32 floatdata)
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{
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union genreg gen;
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tmsreg gen;
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SET_MANTISSA(&gen, floatdata << 8);
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SET_EXPONENT(&gen, (INT32)floatdata >> 24);
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@ -277,7 +267,7 @@ double convert_tms3203x_fp_to_double(UINT32 floatdata)
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UINT32 convert_float_to_tms3203x_fp(float fval)
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{
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union genreg gen;
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tmsreg gen;
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double_to_dsp(fval, &gen);
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return (EXPONENT(&gen) << 24) | ((UINT32)MANTISSA(&gen) >> 8);
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@ -286,7 +276,7 @@ UINT32 convert_float_to_tms3203x_fp(float fval)
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UINT32 convert_double_to_tms3203x_fp(double dval)
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{
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union genreg gen;
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tmsreg gen;
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double_to_dsp(dval, &gen);
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return (EXPONENT(&gen) << 24) | ((UINT32)MANTISSA(&gen) >> 8);
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@ -294,41 +284,19 @@ UINT32 convert_double_to_tms3203x_fp(double dval)
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/***************************************************************************
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EXECEPTION HANDLING
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***************************************************************************/
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#ifdef UNUSED_FUNCTION
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INLINE void generate_exception(int exception)
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{
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}
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INLINE void invalid_instruction(UINT32 op)
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{
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}
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#endif
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/***************************************************************************
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IRQ HANDLING
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***************************************************************************/
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static void check_irqs(void)
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static void check_irqs(tms32031_state *tms)
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{
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int whichtrap = 0;
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UINT16 validints;
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int i;
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/* external interrupts are level-sensitive on the '31 and can be
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configured as such on the '32; in that case, if the external
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signal is high, we need to update the value in IF accordingly */
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if (!tms32031.is_32032 || (IREG(TMR_ST) & 0x4000) == 0)
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IREG(TMR_IF) |= tms32031.irq_state & 0x0f;
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/* determine if we have any live interrupts */
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validints = IREG(TMR_IF) & IREG(TMR_IE) & 0x0fff;
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if (validints == 0 || (IREG(TMR_ST) & GIEFLAG) == 0)
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validints = IREG(tms, TMR_IF) & IREG(tms, TMR_IE) & 0x0fff;
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if (validints == 0 || (IREG(tms, TMR_ST) & GIEFLAG) == 0)
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return;
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/* find the lowest signalled value */
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@ -340,26 +308,26 @@ static void check_irqs(void)
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}
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/* no longer idling if we get here */
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tms32031.is_idling = FALSE;
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if (!tms32031.delayed)
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tms->is_idling = FALSE;
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if (!tms->delayed)
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{
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UINT16 intmask = 1 << (whichtrap - 1);
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/* bit in IF is cleared when interrupt is taken */
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IREG(TMR_IF) &= ~intmask;
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trap(whichtrap);
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IREG(tms, TMR_IF) &= ~intmask;
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trap(tms, whichtrap);
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/* after auto-clearing the interrupt bit, we need to re-trigger
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level-sensitive interrupts */
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if (!tms32031.is_32032 || (IREG(TMR_ST) & 0x4000) == 0)
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IREG(TMR_IF) |= tms32031.irq_state & 0x0f;
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if (!tms->is_32032 || (IREG(tms, TMR_ST) & 0x4000) == 0)
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IREG(tms, TMR_IF) |= tms->irq_state & 0x0f;
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}
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else
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tms32031.irq_pending = TRUE;
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tms->irq_pending = TRUE;
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}
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static void set_irq_line(int irqline, int state)
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static void set_irq_line(tms32031_state *tms, int irqline, int state)
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{
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UINT16 intmask = 1 << irqline;
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@ -370,14 +338,17 @@ static void set_irq_line(int irqline, int state)
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/* update the external state */
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if (state == ASSERT_LINE)
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{
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tms32031.irq_state |= intmask;
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IREG(TMR_IF) |= intmask;
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tms->irq_state |= intmask;
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IREG(tms, TMR_IF) |= intmask;
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}
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else
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tms32031.irq_state &= ~intmask;
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tms->irq_state &= ~intmask;
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/* check for IRQs */
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check_irqs();
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/* external interrupts are level-sensitive on the '31 and can be
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configured as such on the '32; in that case, if the external
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signal is high, we need to update the value in IF accordingly */
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if (!tms->is_32032 || (IREG(tms, TMR_ST) & 0x4000) == 0)
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IREG(tms, TMR_IF) |= tms->irq_state & 0x0f;
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}
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@ -388,21 +359,11 @@ static void set_irq_line(int irqline, int state)
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static CPU_GET_CONTEXT( tms32031 )
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{
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/* copy the context */
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if (dst)
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*(tms32031_regs *)dst = tms32031;
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}
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static CPU_SET_CONTEXT( tms32031 )
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{
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/* copy the context */
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if (src)
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tms32031 = *(tms32031_regs *)src;
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UPDATEPC(tms32031.pc);
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/* check for IRQs */
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check_irqs();
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}
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@ -413,69 +374,67 @@ static CPU_SET_CONTEXT( tms32031 )
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static CPU_INIT( tms32031 )
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{
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const struct tms32031_config *configdata = device->static_config;
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const tms32031_config *configdata = device->static_config;
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tms32031_state *tms = device->token;
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int i;
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char namebuf[30];
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tms32031.irq_callback = irqcallback;
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tms32031.device = device;
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tms->irq_callback = irqcallback;
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tms->device = device;
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tms->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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/* copy in the xf write routines */
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tms32031.bootoffset = configdata ? configdata->bootoffset : 0;
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if (configdata)
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tms->bootoffset = (configdata != NULL) ? configdata->bootoffset : 0;
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if (configdata != NULL)
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{
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tms32031.xf0_w = configdata->xf0_w;
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tms32031.xf1_w = configdata->xf1_w;
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tms32031.iack_w = configdata->iack_w;
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tms->xf0_w = configdata->xf0_w;
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tms->xf1_w = configdata->xf1_w;
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tms->iack_w = configdata->iack_w;
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}
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state_save_register_item("tms32031", device->tag, 0, tms32031.pc);
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for (i=0;i<36;i++)
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{
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sprintf(namebuf,"tms32031.r[%d]",i);
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state_save_register_generic("tms32031", device->tag, 0, namebuf, tms32031.r[i].i8, UINT8, 8);
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}
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state_save_register_item("tms32031", device->tag, 0, tms32031.bkmask);
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state_save_register_item("tms32031", device->tag, 0, tms32031.op);
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state_save_register_item("tms32031", device->tag, 0, tms32031.irq_state);
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state_save_register_item("tms32031", device->tag, 0, tms32031.delayed);
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state_save_register_item("tms32031", device->tag, 0, tms32031.irq_pending);
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state_save_register_item("tms32031", device->tag, 0, tms32031.mcu_mode);
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state_save_register_item("tms32031", device->tag, 0, tms32031.is_idling);
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state_save_register_item("tms32031", device->tag, 0, tms32031.interrupt_cycles);
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state_save_register_item("tms32031", device->tag, 0, tms->pc);
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for (i = 0; i < 36; i++)
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state_save_register_generic("tms32031", device->tag, i, "reg", tms->r[i].i8, UINT8, 8);
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state_save_register_item("tms32031", device->tag, 0, tms->bkmask);
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state_save_register_item("tms32031", device->tag, 0, tms->irq_state);
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state_save_register_item("tms32031", device->tag, 0, tms->delayed);
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state_save_register_item("tms32031", device->tag, 0, tms->irq_pending);
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state_save_register_item("tms32031", device->tag, 0, tms->mcu_mode);
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state_save_register_item("tms32031", device->tag, 0, tms->is_idling);
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}
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static CPU_RESET( tms32031 )
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{
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tms32031_state *tms = device->token;
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/* if we have a config struct, get the boot ROM address */
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if (tms32031.bootoffset)
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if (tms->bootoffset)
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{
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tms32031.mcu_mode = TRUE;
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tms32031.pc = boot_loader(tms32031.bootoffset);
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tms->mcu_mode = TRUE;
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tms->pc = boot_loader(tms, tms->bootoffset);
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}
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else
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{
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tms32031.mcu_mode = FALSE;
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tms32031.pc = RMEM(0);
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tms->mcu_mode = FALSE;
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tms->pc = RMEM(tms, 0);
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}
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tms32031.is_32032 = FALSE;
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tms->is_32032 = FALSE;
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/* reset some registers */
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IREG(TMR_IE) = 0;
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IREG(TMR_IF) = 0;
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IREG(TMR_ST) = 0;
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IREG(TMR_IOF) = 0;
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IREG(tms, TMR_IE) = 0;
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IREG(tms, TMR_IF) = 0;
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IREG(tms, TMR_ST) = 0;
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IREG(tms, TMR_IOF) = 0;
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/* reset internal stuff */
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tms32031.delayed = tms32031.irq_pending = FALSE;
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tms32031.is_idling = FALSE;
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tms->delayed = tms->irq_pending = FALSE;
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tms->is_idling = FALSE;
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}
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static CPU_RESET( tms32032 )
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{
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tms32031_state *tms = device->token;
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CPU_RESET_CALL(tms32031);
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tms32031.is_32032 = TRUE;
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tms->is_32032 = TRUE;
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}
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@ -509,80 +468,75 @@ static CPU_EXIT( tms32031 )
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static CPU_EXECUTE( tms32031 )
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{
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/* count cycles and interrupt cycles */
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tms32031_icount = cycles;
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tms32031_icount -= tms32031.interrupt_cycles;
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tms32031.interrupt_cycles = 0;
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tms32031_state *tms = device->token;
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/* check IRQs up front */
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check_irqs();
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tms->icount = cycles;
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check_irqs(tms);
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/* if we're idling, just eat the cycles */
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if (tms32031.is_idling)
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return tms32031_icount;
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if (tms->is_idling)
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return tms->icount;
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if ((device->machine->debug_flags & DEBUG_FLAG_ENABLED) == 0)
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{
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while (tms32031_icount > 0)
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while (tms->icount > 0)
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{
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if ((IREG(TMR_ST) & RMFLAG) && tms32031.pc == IREG(TMR_RE) + 1)
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if ((IREG(tms, TMR_ST) & RMFLAG) && tms->pc == IREG(tms, TMR_RE) + 1)
|
||||
{
|
||||
if ((INT32)--IREG(TMR_RC) >= 0)
|
||||
tms32031.pc = IREG(TMR_RS);
|
||||
if ((INT32)--IREG(tms, TMR_RC) >= 0)
|
||||
tms->pc = IREG(tms, TMR_RS);
|
||||
else
|
||||
{
|
||||
IREG(TMR_ST) &= ~RMFLAG;
|
||||
if (tms32031.delayed)
|
||||
IREG(tms, TMR_ST) &= ~RMFLAG;
|
||||
if (tms->delayed)
|
||||
{
|
||||
tms32031.delayed = FALSE;
|
||||
if (tms32031.irq_pending)
|
||||
tms->delayed = FALSE;
|
||||
if (tms->irq_pending)
|
||||
{
|
||||
tms32031.irq_pending = FALSE;
|
||||
check_irqs();
|
||||
tms->irq_pending = FALSE;
|
||||
check_irqs(tms);
|
||||
}
|
||||
}
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
execute_one();
|
||||
execute_one(tms);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while (tms32031_icount > 0)
|
||||
while (tms->icount > 0)
|
||||
{
|
||||
if (IREG(TMR_SP) & 0xff000000)
|
||||
if (IREG(tms, TMR_SP) & 0xff000000)
|
||||
debugger_break(device->machine);
|
||||
if ((IREG(TMR_ST) & RMFLAG) && tms32031.pc == IREG(TMR_RE) + 1)
|
||||
if ((IREG(tms, TMR_ST) & RMFLAG) && tms->pc == IREG(tms, TMR_RE) + 1)
|
||||
{
|
||||
if ((INT32)--IREG(TMR_RC) >= 0)
|
||||
tms32031.pc = IREG(TMR_RS);
|
||||
if ((INT32)--IREG(tms, TMR_RC) >= 0)
|
||||
tms->pc = IREG(tms, TMR_RS);
|
||||
else
|
||||
{
|
||||
IREG(TMR_ST) &= ~RMFLAG;
|
||||
if (tms32031.delayed)
|
||||
IREG(tms, TMR_ST) &= ~RMFLAG;
|
||||
if (tms->delayed)
|
||||
{
|
||||
tms32031.delayed = FALSE;
|
||||
if (tms32031.irq_pending)
|
||||
tms->delayed = FALSE;
|
||||
if (tms->irq_pending)
|
||||
{
|
||||
tms32031.irq_pending = FALSE;
|
||||
check_irqs();
|
||||
tms->irq_pending = FALSE;
|
||||
check_irqs(tms);
|
||||
}
|
||||
}
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
debugger_instruction_hook(device->machine, tms32031.pc);
|
||||
execute_one();
|
||||
debugger_instruction_hook(device->machine, tms->pc);
|
||||
execute_one(tms);
|
||||
}
|
||||
}
|
||||
|
||||
tms32031_icount -= tms32031.interrupt_cycles;
|
||||
tms32031.interrupt_cycles = 0;
|
||||
|
||||
return cycles - tms32031_icount;
|
||||
return cycles - tms->icount;
|
||||
}
|
||||
|
||||
|
||||
@ -604,7 +558,7 @@ static CPU_DISASSEMBLE( tms32031 )
|
||||
BOOT LOADER
|
||||
***************************************************************************/
|
||||
|
||||
static UINT32 boot_loader(UINT32 boot_rom_addr)
|
||||
static UINT32 boot_loader(tms32031_state *tms, UINT32 boot_rom_addr)
|
||||
{
|
||||
UINT32 bits, control, advance;
|
||||
UINT32 start_offset = 0;
|
||||
@ -612,7 +566,7 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
|
||||
int first = 1, i;
|
||||
|
||||
/* read the size of the data */
|
||||
bits = RMEM(boot_rom_addr);
|
||||
bits = RMEM(tms, boot_rom_addr);
|
||||
if (bits != 8 && bits != 16 && bits != 32)
|
||||
return 0;
|
||||
datamask = 0xffffffffUL >> (32 - bits);
|
||||
@ -620,9 +574,9 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
|
||||
boot_rom_addr += advance;
|
||||
|
||||
/* read the control register */
|
||||
control = RMEM(boot_rom_addr++) & datamask;
|
||||
control = RMEM(tms, boot_rom_addr++) & datamask;
|
||||
for (i = 1; i < advance; i++)
|
||||
control |= (RMEM(boot_rom_addr++) & datamask) << (bits * i);
|
||||
control |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
|
||||
|
||||
/* now parse the data */
|
||||
while (1)
|
||||
@ -630,18 +584,18 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
|
||||
UINT32 offs, len;
|
||||
|
||||
/* read the length of this section */
|
||||
len = RMEM(boot_rom_addr++) & datamask;
|
||||
len = RMEM(tms, boot_rom_addr++) & datamask;
|
||||
for (i = 1; i < advance; i++)
|
||||
len |= (RMEM(boot_rom_addr++) & datamask) << (bits * i);
|
||||
len |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
|
||||
|
||||
/* stop at 0 */
|
||||
if (len == 0)
|
||||
return start_offset;
|
||||
|
||||
/* read the destination offset of this section */
|
||||
offs = RMEM(boot_rom_addr++) & datamask;
|
||||
offs = RMEM(tms, boot_rom_addr++) & datamask;
|
||||
for (i = 1; i < advance; i++)
|
||||
offs |= (RMEM(boot_rom_addr++) & datamask) << (bits * i);
|
||||
offs |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
|
||||
|
||||
/* if this is the first block, that's where we boot to */
|
||||
if (first)
|
||||
@ -656,12 +610,12 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
|
||||
UINT32 data;
|
||||
|
||||
/* extract the 32-bit word */
|
||||
data = RMEM(boot_rom_addr++) & datamask;
|
||||
data = RMEM(tms, boot_rom_addr++) & datamask;
|
||||
for (i = 1; i < advance; i++)
|
||||
data |= (RMEM(boot_rom_addr++) & datamask) << (bits * i);
|
||||
data |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
|
||||
|
||||
/* write it out */
|
||||
WMEM(offs++, data);
|
||||
WMEM(tms, offs++, data);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -674,61 +628,62 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
|
||||
|
||||
static CPU_SET_INFO( tms32031 )
|
||||
{
|
||||
tms32031_state *tms = device->token;
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are set as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: set_irq_line(TMS32031_IRQ0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: set_irq_line(TMS32031_IRQ1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: set_irq_line(TMS32031_IRQ2, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: set_irq_line(TMS32031_IRQ3, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: set_irq_line(TMS32031_XINT0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: set_irq_line(TMS32031_RINT0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: set_irq_line(TMS32031_XINT1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: set_irq_line(TMS32031_RINT1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: set_irq_line(TMS32031_TINT0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: set_irq_line(TMS32031_TINT1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: set_irq_line(TMS32031_DINT, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: set_irq_line(TMS32031_DINT1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: set_irq_line(tms, TMS32031_IRQ0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: set_irq_line(tms, TMS32031_IRQ1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: set_irq_line(tms, TMS32031_IRQ2, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: set_irq_line(tms, TMS32031_IRQ3, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: set_irq_line(tms, TMS32031_XINT0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: set_irq_line(tms, TMS32031_RINT0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: set_irq_line(tms, TMS32031_XINT1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: set_irq_line(tms, TMS32031_RINT1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: set_irq_line(tms, TMS32031_TINT0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: set_irq_line(tms, TMS32031_TINT1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: set_irq_line(tms, TMS32031_DINT, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: set_irq_line(tms, TMS32031_DINT1, info->i); break;
|
||||
|
||||
case CPUINFO_INT_PC:
|
||||
case CPUINFO_INT_REGISTER + TMS32031_PC: tms32031.pc = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0: IREG(TMR_R0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1: IREG(TMR_R1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2: IREG(TMR_R2) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3: IREG(TMR_R3) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4: IREG(TMR_R4) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5: IREG(TMR_R5) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6: IREG(TMR_R6) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7: IREG(TMR_R7) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R0]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R1]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R2]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R3]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R4]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R5]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R6]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R7]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR0: IREG(TMR_AR0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR1: IREG(TMR_AR1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR2: IREG(TMR_AR2) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR3: IREG(TMR_AR3) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR4: IREG(TMR_AR4) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR5: IREG(TMR_AR5) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR6: IREG(TMR_AR6) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR7: IREG(TMR_AR7) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_DP: IREG(TMR_DP) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR0: IREG(TMR_IR0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR1: IREG(TMR_IR1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_BK: IREG(TMR_BK) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_PC: tms->pc = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0: IREG(tms, TMR_R0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1: IREG(tms, TMR_R1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2: IREG(tms, TMR_R2) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3: IREG(tms, TMR_R3) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4: IREG(tms, TMR_R4) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5: IREG(tms, TMR_R5) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6: IREG(tms, TMR_R6) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7: IREG(tms, TMR_R7) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R0]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R1]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R2]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R3]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R4]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R5]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R6]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R7]); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR0: IREG(tms, TMR_AR0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR1: IREG(tms, TMR_AR1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR2: IREG(tms, TMR_AR2) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR3: IREG(tms, TMR_AR3) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR4: IREG(tms, TMR_AR4) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR5: IREG(tms, TMR_AR5) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR6: IREG(tms, TMR_AR6) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR7: IREG(tms, TMR_AR7) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_DP: IREG(tms, TMR_DP) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR0: IREG(tms, TMR_IR0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR1: IREG(tms, TMR_IR1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_BK: IREG(tms, TMR_BK) = info->i; break;
|
||||
case CPUINFO_INT_SP:
|
||||
case CPUINFO_INT_REGISTER + TMS32031_SP: IREG(TMR_SP) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_ST: IREG(TMR_ST) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IE: IREG(TMR_IE) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IF: IREG(TMR_IF) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IOF: IREG(TMR_IOF) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RS: IREG(TMR_RS) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RE: IREG(TMR_RE) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RC: IREG(TMR_RC) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_SP: IREG(tms, TMR_SP) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_ST: IREG(tms, TMR_ST) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IE: IREG(tms, TMR_IE) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IF: IREG(tms, TMR_IF) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IOF: IREG(tms, TMR_IOF) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RS: IREG(tms, TMR_RS) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RE: IREG(tms, TMR_RE) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RC: IREG(tms, TMR_RC) = info->i; break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -752,12 +707,13 @@ ADDRESS_MAP_END
|
||||
|
||||
CPU_GET_INFO( tms32031 )
|
||||
{
|
||||
tms32031_state *tms = (device != NULL) ? device->token : NULL;
|
||||
float ftemp;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32031); break;
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32031_state); break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 11; break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
||||
@ -778,61 +734,61 @@ CPU_GET_INFO( tms32031 )
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
|
||||
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ2)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ3)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: info->i = (IREG(TMR_IF) & (1 << TMS32031_XINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: info->i = (IREG(TMR_IF) & (1 << TMS32031_RINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_XINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_RINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: info->i = (IREG(TMR_IF) & (1 << TMS32031_TINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_TINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: info->i = (IREG(TMR_IF) & (1 << TMS32031_DINT)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_DINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ2)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ3)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_XINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_RINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_XINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_RINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_TINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_TINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_DINT)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_DINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
|
||||
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
|
||||
|
||||
case CPUINFO_INT_PC:
|
||||
case CPUINFO_INT_REGISTER + TMS32031_PC: info->i = tms32031.pc; break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_PC: info->i = tms->pc; break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0: info->i = IREG(TMR_R0); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1: info->i = IREG(TMR_R1); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2: info->i = IREG(TMR_R2); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3: info->i = IREG(TMR_R3); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4: info->i = IREG(TMR_R4); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5: info->i = IREG(TMR_R5); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6: info->i = IREG(TMR_R6); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7: info->i = IREG(TMR_R7); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0F: ftemp = dsp_to_double(&tms32031.r[TMR_R0]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1F: ftemp = dsp_to_double(&tms32031.r[TMR_R1]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2F: ftemp = dsp_to_double(&tms32031.r[TMR_R2]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3F: ftemp = dsp_to_double(&tms32031.r[TMR_R3]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4F: ftemp = dsp_to_double(&tms32031.r[TMR_R4]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5F: ftemp = dsp_to_double(&tms32031.r[TMR_R5]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6F: ftemp = dsp_to_double(&tms32031.r[TMR_R6]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7F: ftemp = dsp_to_double(&tms32031.r[TMR_R7]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR0: info->i = IREG(TMR_AR0); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR1: info->i = IREG(TMR_AR1); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR2: info->i = IREG(TMR_AR2); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR3: info->i = IREG(TMR_AR3); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR4: info->i = IREG(TMR_AR4); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR5: info->i = IREG(TMR_AR5); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR6: info->i = IREG(TMR_AR6); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR7: info->i = IREG(TMR_AR7); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_DP: info->i = IREG(TMR_DP); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR0: info->i = IREG(TMR_IR0); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR1: info->i = IREG(TMR_IR1); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_BK: info->i = IREG(TMR_BK); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0: info->i = IREG(tms, TMR_R0); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1: info->i = IREG(tms, TMR_R1); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2: info->i = IREG(tms, TMR_R2); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3: info->i = IREG(tms, TMR_R3); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4: info->i = IREG(tms, TMR_R4); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5: info->i = IREG(tms, TMR_R5); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6: info->i = IREG(tms, TMR_R6); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7: info->i = IREG(tms, TMR_R7); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R0F: ftemp = dsp_to_double(&tms->r[TMR_R0]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R1F: ftemp = dsp_to_double(&tms->r[TMR_R1]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R2F: ftemp = dsp_to_double(&tms->r[TMR_R2]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R3F: ftemp = dsp_to_double(&tms->r[TMR_R3]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R4F: ftemp = dsp_to_double(&tms->r[TMR_R4]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R5F: ftemp = dsp_to_double(&tms->r[TMR_R5]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R6F: ftemp = dsp_to_double(&tms->r[TMR_R6]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_R7F: ftemp = dsp_to_double(&tms->r[TMR_R7]); info->i = f2u(ftemp); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR0: info->i = IREG(tms, TMR_AR0); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR1: info->i = IREG(tms, TMR_AR1); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR2: info->i = IREG(tms, TMR_AR2); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR3: info->i = IREG(tms, TMR_AR3); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR4: info->i = IREG(tms, TMR_AR4); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR5: info->i = IREG(tms, TMR_AR5); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR6: info->i = IREG(tms, TMR_AR6); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_AR7: info->i = IREG(tms, TMR_AR7); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_DP: info->i = IREG(tms, TMR_DP); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR0: info->i = IREG(tms, TMR_IR0); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IR1: info->i = IREG(tms, TMR_IR1); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_BK: info->i = IREG(tms, TMR_BK); break;
|
||||
case CPUINFO_INT_SP:
|
||||
case CPUINFO_INT_REGISTER + TMS32031_SP: info->i = IREG(TMR_SP); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_ST: info->i = IREG(TMR_ST); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IE: info->i = IREG(TMR_IE); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IF: info->i = IREG(TMR_IF); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IOF: info->i = IREG(TMR_IOF); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RS: info->i = IREG(TMR_RS); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RE: info->i = IREG(TMR_RE); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RC: info->i = IREG(TMR_RC); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_SP: info->i = IREG(tms, TMR_SP); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_ST: info->i = IREG(tms, TMR_ST); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IE: info->i = IREG(tms, TMR_IE); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IF: info->i = IREG(tms, TMR_IF); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_IOF: info->i = IREG(tms, TMR_IOF); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RS: info->i = IREG(tms, TMR_RS); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RE: info->i = IREG(tms, TMR_RE); break;
|
||||
case CPUINFO_INT_REGISTER + TMS32031_RC: info->i = IREG(tms, TMR_RC); break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32031); break;
|
||||
@ -844,7 +800,7 @@ CPU_GET_INFO( tms32031 )
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms32031); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32031); break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &tms32031_icount; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &tms->icount; break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(internal_32031); break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
@ -856,7 +812,7 @@ CPU_GET_INFO( tms32031 )
|
||||
|
||||
case CPUINFO_STR_FLAGS:
|
||||
{
|
||||
UINT32 temp = tms32031.r[TMR_ST].i32[0];
|
||||
UINT32 temp = tms->r[TMR_ST].i32[0];
|
||||
sprintf(info->s, "%c%c%c%c%c%c%c%c",
|
||||
(temp & 0x80) ? 'O':'.',
|
||||
(temp & 0x40) ? 'U':'.',
|
||||
@ -869,44 +825,44 @@ CPU_GET_INFO( tms32031 )
|
||||
break;
|
||||
}
|
||||
|
||||
case CPUINFO_STR_REGISTER + TMS32031_PC: sprintf(info->s, "PC: %08X", tms32031.pc); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_PC: sprintf(info->s, "PC: %08X", tms->pc); break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R0: sprintf(info->s, " R0:%08X", tms32031.r[TMR_R0].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R1: sprintf(info->s, " R1:%08X", tms32031.r[TMR_R1].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R2: sprintf(info->s, " R2:%08X", tms32031.r[TMR_R2].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R3: sprintf(info->s, " R3:%08X", tms32031.r[TMR_R3].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R4: sprintf(info->s, " R4:%08X", tms32031.r[TMR_R4].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R5: sprintf(info->s, " R5:%08X", tms32031.r[TMR_R5].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R6: sprintf(info->s, " R6:%08X", tms32031.r[TMR_R6].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R7: sprintf(info->s, " R7:%08X", tms32031.r[TMR_R7].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R0F: sprintf(info->s, "R0F:!%12g", dsp_to_double(&tms32031.r[TMR_R0])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R1F: sprintf(info->s, "R1F:!%12g", dsp_to_double(&tms32031.r[TMR_R1])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R2F: sprintf(info->s, "R2F:!%12g", dsp_to_double(&tms32031.r[TMR_R2])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R3F: sprintf(info->s, "R3F:!%12g", dsp_to_double(&tms32031.r[TMR_R3])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R4F: sprintf(info->s, "R4F:!%12g", dsp_to_double(&tms32031.r[TMR_R4])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R5F: sprintf(info->s, "R5F:!%12g", dsp_to_double(&tms32031.r[TMR_R5])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R6F: sprintf(info->s, "R6F:!%12g", dsp_to_double(&tms32031.r[TMR_R6])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R7F: sprintf(info->s, "R7F:!%12g", dsp_to_double(&tms32031.r[TMR_R7])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR0: sprintf(info->s, "AR0:%08X", tms32031.r[TMR_AR0].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR1: sprintf(info->s, "AR1:%08X", tms32031.r[TMR_AR1].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR2: sprintf(info->s, "AR2:%08X", tms32031.r[TMR_AR2].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR3: sprintf(info->s, "AR3:%08X", tms32031.r[TMR_AR3].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR4: sprintf(info->s, "AR4:%08X", tms32031.r[TMR_AR4].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR5: sprintf(info->s, "AR5:%08X", tms32031.r[TMR_AR5].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR6: sprintf(info->s, "AR6:%08X", tms32031.r[TMR_AR6].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR7: sprintf(info->s, "AR7:%08X", tms32031.r[TMR_AR7].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_DP: sprintf(info->s, " DP:%02X", tms32031.r[TMR_DP].i8[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IR0: sprintf(info->s, "IR0:%08X", tms32031.r[TMR_IR0].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IR1: sprintf(info->s, "IR1:%08X", tms32031.r[TMR_IR1].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_BK: sprintf(info->s, " BK:%08X", tms32031.r[TMR_BK].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_SP: sprintf(info->s, " SP:%08X", tms32031.r[TMR_SP].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_ST: sprintf(info->s, " ST:%08X", tms32031.r[TMR_ST].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IE: sprintf(info->s, " IE:%08X", tms32031.r[TMR_IE].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IF: sprintf(info->s, " IF:%08X", tms32031.r[TMR_IF].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IOF: sprintf(info->s, "IOF:%08X", tms32031.r[TMR_IOF].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_RS: sprintf(info->s, " RS:%08X", tms32031.r[TMR_RS].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_RE: sprintf(info->s, " RE:%08X", tms32031.r[TMR_RE].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_RC: sprintf(info->s, " RC:%08X", tms32031.r[TMR_RC].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R0: sprintf(info->s, " R0:%08X", tms->r[TMR_R0].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R1: sprintf(info->s, " R1:%08X", tms->r[TMR_R1].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R2: sprintf(info->s, " R2:%08X", tms->r[TMR_R2].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R3: sprintf(info->s, " R3:%08X", tms->r[TMR_R3].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R4: sprintf(info->s, " R4:%08X", tms->r[TMR_R4].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R5: sprintf(info->s, " R5:%08X", tms->r[TMR_R5].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R6: sprintf(info->s, " R6:%08X", tms->r[TMR_R6].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R7: sprintf(info->s, " R7:%08X", tms->r[TMR_R7].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R0F: sprintf(info->s, "R0F:!%12g", dsp_to_double(&tms->r[TMR_R0])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R1F: sprintf(info->s, "R1F:!%12g", dsp_to_double(&tms->r[TMR_R1])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R2F: sprintf(info->s, "R2F:!%12g", dsp_to_double(&tms->r[TMR_R2])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R3F: sprintf(info->s, "R3F:!%12g", dsp_to_double(&tms->r[TMR_R3])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R4F: sprintf(info->s, "R4F:!%12g", dsp_to_double(&tms->r[TMR_R4])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R5F: sprintf(info->s, "R5F:!%12g", dsp_to_double(&tms->r[TMR_R5])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R6F: sprintf(info->s, "R6F:!%12g", dsp_to_double(&tms->r[TMR_R6])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_R7F: sprintf(info->s, "R7F:!%12g", dsp_to_double(&tms->r[TMR_R7])); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR0: sprintf(info->s, "AR0:%08X", tms->r[TMR_AR0].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR1: sprintf(info->s, "AR1:%08X", tms->r[TMR_AR1].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR2: sprintf(info->s, "AR2:%08X", tms->r[TMR_AR2].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR3: sprintf(info->s, "AR3:%08X", tms->r[TMR_AR3].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR4: sprintf(info->s, "AR4:%08X", tms->r[TMR_AR4].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR5: sprintf(info->s, "AR5:%08X", tms->r[TMR_AR5].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR6: sprintf(info->s, "AR6:%08X", tms->r[TMR_AR6].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_AR7: sprintf(info->s, "AR7:%08X", tms->r[TMR_AR7].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_DP: sprintf(info->s, " DP:%02X", tms->r[TMR_DP].i8[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IR0: sprintf(info->s, "IR0:%08X", tms->r[TMR_IR0].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IR1: sprintf(info->s, "IR1:%08X", tms->r[TMR_IR1].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_BK: sprintf(info->s, " BK:%08X", tms->r[TMR_BK].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_SP: sprintf(info->s, " SP:%08X", tms->r[TMR_SP].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_ST: sprintf(info->s, " ST:%08X", tms->r[TMR_ST].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IE: sprintf(info->s, " IE:%08X", tms->r[TMR_IE].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IF: sprintf(info->s, " IF:%08X", tms->r[TMR_IF].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_IOF: sprintf(info->s, "IOF:%08X", tms->r[TMR_IOF].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_RS: sprintf(info->s, " RS:%08X", tms->r[TMR_RS].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_RE: sprintf(info->s, " RE:%08X", tms->r[TMR_RE].i32[0]); break;
|
||||
case CPUINFO_STR_REGISTER + TMS32031_RC: sprintf(info->s, " RC:%08X", tms->r[TMR_RC].i32[0]); break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -18,12 +18,17 @@
|
||||
TYPE DEFINITIONS
|
||||
***************************************************************************/
|
||||
|
||||
struct tms32031_config
|
||||
typedef void (*tms32031_xf_func)(const device_config *device, UINT8 val);
|
||||
typedef void (*tms32031_iack_func)(const device_config *device, UINT8 val, offs_t address);
|
||||
|
||||
|
||||
typedef struct _tms32031_config tms32031_config;
|
||||
struct _tms32031_config
|
||||
{
|
||||
UINT32 bootoffset;
|
||||
void (*xf0_w)(UINT8 val);
|
||||
void (*xf1_w)(UINT8 val);
|
||||
void (*iack_w)(UINT8 val, offs_t addr);
|
||||
UINT32 bootoffset;
|
||||
tms32031_xf_func xf0_w;
|
||||
tms32031_xf_func xf1_w;
|
||||
tms32031_iack_func iack_w;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -602,7 +602,7 @@ static WRITE32_HANDLER( speedup_w )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static const struct tms32031_config cage_config =
|
||||
static const tms32031_config cage_config =
|
||||
{
|
||||
0x400000
|
||||
};
|
||||
|
||||
@ -409,10 +409,10 @@ static WRITE32_HANDLER( tms_m68k_ram_w )
|
||||
}
|
||||
|
||||
|
||||
static void iack_w(UINT8 state, offs_t addr)
|
||||
static void iack_w(const device_config *device, UINT8 state, offs_t addr)
|
||||
{
|
||||
logerror("iack_w(%d) - %06X\n", state, addr);
|
||||
cpu_set_input_line(Machine->cpu[1], 0, CLEAR_LINE);
|
||||
cpu_set_input_line(device, 0, CLEAR_LINE);
|
||||
}
|
||||
|
||||
|
||||
@ -908,7 +908,7 @@ INPUT_PORTS_END
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static const struct tms32031_config tms_config =
|
||||
static const tms32031_config tms_config =
|
||||
{
|
||||
0x1000,
|
||||
0,
|
||||
|
||||
@ -459,7 +459,7 @@ static WRITE32_HANDLER( midvplus_misc_w )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static void midvplus_xf1_w(UINT8 val)
|
||||
static void midvplus_xf1_w(const device_config *device, UINT8 val)
|
||||
{
|
||||
static int lastval;
|
||||
// mame_printf_debug("xf1_w = %d\n", val);
|
||||
@ -509,7 +509,7 @@ static ADDRESS_MAP_START( midvunit_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
static const struct tms32031_config midvplus_config = { 0, NULL, midvplus_xf1_w };
|
||||
static const tms32031_config midvplus_config = { 0, NULL, midvplus_xf1_w };
|
||||
|
||||
static ADDRESS_MAP_START( midvplus_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
AM_RANGE(0x000000, 0x01ffff) AM_RAM AM_BASE(&ram_base)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user