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Pointer-ified the TMS32031 core.

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This commit is contained in:
Aaron Giles 2008-11-20 18:20:59 +00:00
parent fae2eb291a
commit 9a0493f14a
6 changed files with 3008 additions and 2951 deletions
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5324
src/emu/cpu/tms32031/32031ops.c
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586
src/emu/cpu/tms32031/tms32031.c
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@ -1,6 +1,6 @@
/*************************************************************************** /***************************************************************************
tms32031.c tms->c
Core implementation for the portable TMS32C031 emulator. Core implementation for the portable TMS32C031 emulator.
Written by Aaron Giles Written by Aaron Giles
@ -72,7 +72,7 @@ enum
#define CCFLAG 0x1000 #define CCFLAG 0x1000
#define GIEFLAG 0x2000 #define GIEFLAG 0x2000
#define IREG(rnum) (tms32031.r[rnum].i32[0]) #define IREG(T,rnum) ((T)->r[rnum].i32[0])
@ -80,7 +80,16 @@ enum
STRUCTURES & TYPEDEFS STRUCTURES & TYPEDEFS
***************************************************************************/ ***************************************************************************/
union genreg typedef union _int_double int_double;
union _int_double
{
double d;
float f[2];
UINT32 i[2];
};
typedef union _tmsreg tmsreg;
union _tmsreg
{ {
UINT32 i32[2]; UINT32 i32[2];
UINT16 i16[4]; UINT16 i16[4];
@ -88,30 +97,31 @@ union genreg
}; };
/* TMS34031 Registers */ /* TMS34031 Registers */
typedef struct typedef struct _tms32031_state tms32031_state;
struct _tms32031_state
{ {
/* core registers */ /* core registers */
UINT32 pc; UINT32 pc;
union genreg r[36]; tmsreg r[36];
UINT32 bkmask; UINT32 bkmask;
/* internal stuff */ /* internal stuff */
UINT32 op;
UINT16 irq_state; UINT16 irq_state;
UINT8 delayed; UINT8 delayed;
UINT8 irq_pending; UINT8 irq_pending;
UINT8 mcu_mode; UINT8 mcu_mode;
UINT8 is_32032; UINT8 is_32032;
UINT8 is_idling; UINT8 is_idling;
int interrupt_cycles; int icount;
UINT32 bootoffset; UINT32 bootoffset;
void (*xf0_w)(UINT8 val); tms32031_xf_func xf0_w;
void (*xf1_w)(UINT8 val); tms32031_xf_func xf1_w;
void (*iack_w)(UINT8 val, offs_t addr); tms32031_iack_func iack_w;
cpu_irq_callback irq_callback; cpu_irq_callback irq_callback;
const device_config *device; const device_config *device;
} tms32031_regs; const address_space *program;
};
@ -119,24 +129,8 @@ typedef struct
FUNCTION PROTOTYPES FUNCTION PROTOTYPES
***************************************************************************/ ***************************************************************************/
static void trap(int trapnum); static void trap(tms32031_state *tms, int trapnum);
static UINT32 boot_loader(UINT32 boot_rom_addr); static UINT32 boot_loader(tms32031_state *tms, UINT32 boot_rom_addr);
/***************************************************************************
PUBLIC GLOBAL VARIABLES
***************************************************************************/
static int tms32031_icount;
/***************************************************************************
PRIVATE GLOBAL VARIABLES
***************************************************************************/
static tms32031_regs tms32031;
@ -144,12 +138,11 @@ static tms32031_regs tms32031;
MEMORY ACCESSORS MEMORY ACCESSORS
***************************************************************************/ ***************************************************************************/
#define ROPCODE(pc) program_decrypted_read_dword((pc) << 2) #define ROPCODE(T,pc) memory_decrypted_read_dword((T)->program, (pc) << 2)
#define OP tms32031.op
#define RMEM(T,addr) memory_read_dword_32le((T)->program, (addr) << 2)
#define WMEM(T,addr,data) memory_write_dword_32le((T)->program, (addr) << 2, data)
#define RMEM(addr) program_read_dword_32le((addr) << 2)
#define WMEM(addr,data) program_write_dword_32le((addr) << 2, data)
#define UPDATEPC(addr) change_pc((addr) << 2)
@ -162,15 +155,12 @@ static tms32031_regs tms32031;
#define SET_MANTISSA(r,v) ((r)->i32[0] = (v)) #define SET_MANTISSA(r,v) ((r)->i32[0] = (v))
#define SET_EXPONENT(r,v) ((r)->i32[1] = (v)) #define SET_EXPONENT(r,v) ((r)->i32[1] = (v))
typedef union int_double
{
double d;
float f[2];
UINT32 i[2];
} int_double;
/***************************************************************************
CONVERSION FUNCTIONS
***************************************************************************/
static float dsp_to_float(union genreg *fp) static float dsp_to_float(tmsreg *fp)
{ {
int_double id; int_double id;
@ -191,7 +181,7 @@ static float dsp_to_float(union genreg *fp)
} }
static double dsp_to_double(union genreg *fp) static double dsp_to_double(tmsreg *fp)
{ {
int_double id; int_double id;
@ -214,7 +204,7 @@ static double dsp_to_double(union genreg *fp)
} }
static void double_to_dsp(double val, union genreg *result) static void double_to_dsp(double val, tmsreg *result)
{ {
int mantissa, exponent; int mantissa, exponent;
int_double id; int_double id;
@ -255,7 +245,7 @@ static void double_to_dsp(double val, union genreg *result)
float convert_tms3203x_fp_to_float(UINT32 floatdata) float convert_tms3203x_fp_to_float(UINT32 floatdata)
{ {
union genreg gen; tmsreg gen;
SET_MANTISSA(&gen, floatdata << 8); SET_MANTISSA(&gen, floatdata << 8);
SET_EXPONENT(&gen, (INT32)floatdata >> 24); SET_EXPONENT(&gen, (INT32)floatdata >> 24);
@ -266,7 +256,7 @@ float convert_tms3203x_fp_to_float(UINT32 floatdata)
double convert_tms3203x_fp_to_double(UINT32 floatdata) double convert_tms3203x_fp_to_double(UINT32 floatdata)
{ {
union genreg gen; tmsreg gen;
SET_MANTISSA(&gen, floatdata << 8); SET_MANTISSA(&gen, floatdata << 8);
SET_EXPONENT(&gen, (INT32)floatdata >> 24); SET_EXPONENT(&gen, (INT32)floatdata >> 24);
@ -277,7 +267,7 @@ double convert_tms3203x_fp_to_double(UINT32 floatdata)
UINT32 convert_float_to_tms3203x_fp(float fval) UINT32 convert_float_to_tms3203x_fp(float fval)
{ {
union genreg gen; tmsreg gen;
double_to_dsp(fval, &gen); double_to_dsp(fval, &gen);
return (EXPONENT(&gen) << 24) | ((UINT32)MANTISSA(&gen) >> 8); return (EXPONENT(&gen) << 24) | ((UINT32)MANTISSA(&gen) >> 8);
@ -286,7 +276,7 @@ UINT32 convert_float_to_tms3203x_fp(float fval)
UINT32 convert_double_to_tms3203x_fp(double dval) UINT32 convert_double_to_tms3203x_fp(double dval)
{ {
union genreg gen; tmsreg gen;
double_to_dsp(dval, &gen); double_to_dsp(dval, &gen);
return (EXPONENT(&gen) << 24) | ((UINT32)MANTISSA(&gen) >> 8); return (EXPONENT(&gen) << 24) | ((UINT32)MANTISSA(&gen) >> 8);
@ -294,41 +284,19 @@ UINT32 convert_double_to_tms3203x_fp(double dval)
/***************************************************************************
EXECEPTION HANDLING
***************************************************************************/
#ifdef UNUSED_FUNCTION
INLINE void generate_exception(int exception)
{
}
INLINE void invalid_instruction(UINT32 op)
{
}
#endif
/*************************************************************************** /***************************************************************************
IRQ HANDLING IRQ HANDLING
***************************************************************************/ ***************************************************************************/
static void check_irqs(void) static void check_irqs(tms32031_state *tms)
{ {
int whichtrap = 0; int whichtrap = 0;
UINT16 validints; UINT16 validints;
int i; int i;
/* external interrupts are level-sensitive on the '31 and can be
configured as such on the '32; in that case, if the external
signal is high, we need to update the value in IF accordingly */
if (!tms32031.is_32032 || (IREG(TMR_ST) & 0x4000) == 0)
IREG(TMR_IF) |= tms32031.irq_state & 0x0f;
/* determine if we have any live interrupts */ /* determine if we have any live interrupts */
validints = IREG(TMR_IF) & IREG(TMR_IE) & 0x0fff; validints = IREG(tms, TMR_IF) & IREG(tms, TMR_IE) & 0x0fff;
if (validints == 0 || (IREG(TMR_ST) & GIEFLAG) == 0) if (validints == 0 || (IREG(tms, TMR_ST) & GIEFLAG) == 0)
return; return;
/* find the lowest signalled value */ /* find the lowest signalled value */
@ -340,26 +308,26 @@ static void check_irqs(void)
} }
/* no longer idling if we get here */ /* no longer idling if we get here */
tms32031.is_idling = FALSE; tms->is_idling = FALSE;
if (!tms32031.delayed) if (!tms->delayed)
{ {
UINT16 intmask = 1 << (whichtrap - 1); UINT16 intmask = 1 << (whichtrap - 1);
/* bit in IF is cleared when interrupt is taken */ /* bit in IF is cleared when interrupt is taken */
IREG(TMR_IF) &= ~intmask; IREG(tms, TMR_IF) &= ~intmask;
trap(whichtrap); trap(tms, whichtrap);
/* after auto-clearing the interrupt bit, we need to re-trigger /* after auto-clearing the interrupt bit, we need to re-trigger
level-sensitive interrupts */ level-sensitive interrupts */
if (!tms32031.is_32032 || (IREG(TMR_ST) & 0x4000) == 0) if (!tms->is_32032 || (IREG(tms, TMR_ST) & 0x4000) == 0)
IREG(TMR_IF) |= tms32031.irq_state & 0x0f; IREG(tms, TMR_IF) |= tms->irq_state & 0x0f;
} }
else else
tms32031.irq_pending = TRUE; tms->irq_pending = TRUE;
} }
static void set_irq_line(int irqline, int state) static void set_irq_line(tms32031_state *tms, int irqline, int state)
{ {
UINT16 intmask = 1 << irqline; UINT16 intmask = 1 << irqline;
@ -370,14 +338,17 @@ static void set_irq_line(int irqline, int state)
/* update the external state */ /* update the external state */
if (state == ASSERT_LINE) if (state == ASSERT_LINE)
{ {
tms32031.irq_state |= intmask; tms->irq_state |= intmask;
IREG(TMR_IF) |= intmask; IREG(tms, TMR_IF) |= intmask;
} }
else else
tms32031.irq_state &= ~intmask; tms->irq_state &= ~intmask;
/* check for IRQs */ /* external interrupts are level-sensitive on the '31 and can be
check_irqs(); configured as such on the '32; in that case, if the external
signal is high, we need to update the value in IF accordingly */
if (!tms->is_32032 || (IREG(tms, TMR_ST) & 0x4000) == 0)
IREG(tms, TMR_IF) |= tms->irq_state & 0x0f;
} }
@ -388,21 +359,11 @@ static void set_irq_line(int irqline, int state)
static CPU_GET_CONTEXT( tms32031 ) static CPU_GET_CONTEXT( tms32031 )
{ {
/* copy the context */
if (dst)
*(tms32031_regs *)dst = tms32031;
} }
static CPU_SET_CONTEXT( tms32031 ) static CPU_SET_CONTEXT( tms32031 )
{ {
/* copy the context */
if (src)
tms32031 = *(tms32031_regs *)src;
UPDATEPC(tms32031.pc);
/* check for IRQs */
check_irqs();
} }
@ -413,69 +374,67 @@ static CPU_SET_CONTEXT( tms32031 )
static CPU_INIT( tms32031 ) static CPU_INIT( tms32031 )
{ {
const struct tms32031_config *configdata = device->static_config; const tms32031_config *configdata = device->static_config;
tms32031_state *tms = device->token;
int i; int i;
char namebuf[30];
tms32031.irq_callback = irqcallback; tms->irq_callback = irqcallback;
tms32031.device = device; tms->device = device;
tms->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
/* copy in the xf write routines */ /* copy in the xf write routines */
tms32031.bootoffset = configdata ? configdata->bootoffset : 0; tms->bootoffset = (configdata != NULL) ? configdata->bootoffset : 0;
if (configdata) if (configdata != NULL)
{ {
tms32031.xf0_w = configdata->xf0_w; tms->xf0_w = configdata->xf0_w;
tms32031.xf1_w = configdata->xf1_w; tms->xf1_w = configdata->xf1_w;
tms32031.iack_w = configdata->iack_w; tms->iack_w = configdata->iack_w;
} }
state_save_register_item("tms32031", device->tag, 0, tms32031.pc); state_save_register_item("tms32031", device->tag, 0, tms->pc);
for (i = 0; i < 36; i++) for (i = 0; i < 36; i++)
{ state_save_register_generic("tms32031", device->tag, i, "reg", tms->r[i].i8, UINT8, 8);
sprintf(namebuf,"tms32031.r[%d]",i); state_save_register_item("tms32031", device->tag, 0, tms->bkmask);
state_save_register_generic("tms32031", device->tag, 0, namebuf, tms32031.r[i].i8, UINT8, 8); state_save_register_item("tms32031", device->tag, 0, tms->irq_state);
} state_save_register_item("tms32031", device->tag, 0, tms->delayed);
state_save_register_item("tms32031", device->tag, 0, tms32031.bkmask); state_save_register_item("tms32031", device->tag, 0, tms->irq_pending);
state_save_register_item("tms32031", device->tag, 0, tms32031.op); state_save_register_item("tms32031", device->tag, 0, tms->mcu_mode);
state_save_register_item("tms32031", device->tag, 0, tms32031.irq_state); state_save_register_item("tms32031", device->tag, 0, tms->is_idling);
state_save_register_item("tms32031", device->tag, 0, tms32031.delayed);
state_save_register_item("tms32031", device->tag, 0, tms32031.irq_pending);
state_save_register_item("tms32031", device->tag, 0, tms32031.mcu_mode);
state_save_register_item("tms32031", device->tag, 0, tms32031.is_idling);
state_save_register_item("tms32031", device->tag, 0, tms32031.interrupt_cycles);
} }
static CPU_RESET( tms32031 ) static CPU_RESET( tms32031 )
{ {
tms32031_state *tms = device->token;
/* if we have a config struct, get the boot ROM address */ /* if we have a config struct, get the boot ROM address */
if (tms32031.bootoffset) if (tms->bootoffset)
{ {
tms32031.mcu_mode = TRUE; tms->mcu_mode = TRUE;
tms32031.pc = boot_loader(tms32031.bootoffset); tms->pc = boot_loader(tms, tms->bootoffset);
} }
else else
{ {
tms32031.mcu_mode = FALSE; tms->mcu_mode = FALSE;
tms32031.pc = RMEM(0); tms->pc = RMEM(tms, 0);
} }
tms32031.is_32032 = FALSE; tms->is_32032 = FALSE;
/* reset some registers */ /* reset some registers */
IREG(TMR_IE) = 0; IREG(tms, TMR_IE) = 0;
IREG(TMR_IF) = 0; IREG(tms, TMR_IF) = 0;
IREG(TMR_ST) = 0; IREG(tms, TMR_ST) = 0;
IREG(TMR_IOF) = 0; IREG(tms, TMR_IOF) = 0;
/* reset internal stuff */ /* reset internal stuff */
tms32031.delayed = tms32031.irq_pending = FALSE; tms->delayed = tms->irq_pending = FALSE;
tms32031.is_idling = FALSE; tms->is_idling = FALSE;
} }
static CPU_RESET( tms32032 ) static CPU_RESET( tms32032 )
{ {
tms32031_state *tms = device->token;
CPU_RESET_CALL(tms32031); CPU_RESET_CALL(tms32031);
tms32031.is_32032 = TRUE; tms->is_32032 = TRUE;
} }
@ -509,80 +468,75 @@ static CPU_EXIT( tms32031 )
static CPU_EXECUTE( tms32031 ) static CPU_EXECUTE( tms32031 )
{ {
/* count cycles and interrupt cycles */ tms32031_state *tms = device->token;
tms32031_icount = cycles;
tms32031_icount -= tms32031.interrupt_cycles;
tms32031.interrupt_cycles = 0;
/* check IRQs up front */ /* check IRQs up front */
check_irqs(); tms->icount = cycles;
check_irqs(tms);
/* if we're idling, just eat the cycles */ /* if we're idling, just eat the cycles */
if (tms32031.is_idling) if (tms->is_idling)
return tms32031_icount; return tms->icount;
if ((device->machine->debug_flags & DEBUG_FLAG_ENABLED) == 0) if ((device->machine->debug_flags & DEBUG_FLAG_ENABLED) == 0)
{ {
while (tms32031_icount > 0) while (tms->icount > 0)
{ {
if ((IREG(TMR_ST) & RMFLAG) && tms32031.pc == IREG(TMR_RE) + 1) if ((IREG(tms, TMR_ST) & RMFLAG) && tms->pc == IREG(tms, TMR_RE) + 1)
{ {
if ((INT32)--IREG(TMR_RC) >= 0) if ((INT32)--IREG(tms, TMR_RC) >= 0)
tms32031.pc = IREG(TMR_RS); tms->pc = IREG(tms, TMR_RS);
else else
{ {
IREG(TMR_ST) &= ~RMFLAG; IREG(tms, TMR_ST) &= ~RMFLAG;
if (tms32031.delayed) if (tms->delayed)
{ {
tms32031.delayed = FALSE; tms->delayed = FALSE;
if (tms32031.irq_pending) if (tms->irq_pending)
{ {
tms32031.irq_pending = FALSE; tms->irq_pending = FALSE;
check_irqs(); check_irqs(tms);
} }
} }
} }
continue; continue;
} }
execute_one(); execute_one(tms);
} }
} }
else else
{ {
while (tms32031_icount > 0) while (tms->icount > 0)
{ {
if (IREG(TMR_SP) & 0xff000000) if (IREG(tms, TMR_SP) & 0xff000000)
debugger_break(device->machine); debugger_break(device->machine);
if ((IREG(TMR_ST) & RMFLAG) && tms32031.pc == IREG(TMR_RE) + 1) if ((IREG(tms, TMR_ST) & RMFLAG) && tms->pc == IREG(tms, TMR_RE) + 1)
{ {
if ((INT32)--IREG(TMR_RC) >= 0) if ((INT32)--IREG(tms, TMR_RC) >= 0)
tms32031.pc = IREG(TMR_RS); tms->pc = IREG(tms, TMR_RS);
else else
{ {
IREG(TMR_ST) &= ~RMFLAG; IREG(tms, TMR_ST) &= ~RMFLAG;
if (tms32031.delayed) if (tms->delayed)
{ {
tms32031.delayed = FALSE; tms->delayed = FALSE;
if (tms32031.irq_pending) if (tms->irq_pending)
{ {
tms32031.irq_pending = FALSE; tms->irq_pending = FALSE;
check_irqs(); check_irqs(tms);
} }
} }
} }
continue; continue;
} }
debugger_instruction_hook(device->machine, tms32031.pc); debugger_instruction_hook(device->machine, tms->pc);
execute_one(); execute_one(tms);
} }
} }
tms32031_icount -= tms32031.interrupt_cycles; return cycles - tms->icount;
tms32031.interrupt_cycles = 0;
return cycles - tms32031_icount;
} }
@ -604,7 +558,7 @@ static CPU_DISASSEMBLE( tms32031 )
BOOT LOADER BOOT LOADER
***************************************************************************/ ***************************************************************************/
static UINT32 boot_loader(UINT32 boot_rom_addr) static UINT32 boot_loader(tms32031_state *tms, UINT32 boot_rom_addr)
{ {
UINT32 bits, control, advance; UINT32 bits, control, advance;
UINT32 start_offset = 0; UINT32 start_offset = 0;
@ -612,7 +566,7 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
int first = 1, i; int first = 1, i;
/* read the size of the data */ /* read the size of the data */
bits = RMEM(boot_rom_addr); bits = RMEM(tms, boot_rom_addr);
if (bits != 8 && bits != 16 && bits != 32) if (bits != 8 && bits != 16 && bits != 32)
return 0; return 0;
datamask = 0xffffffffUL >> (32 - bits); datamask = 0xffffffffUL >> (32 - bits);
@ -620,9 +574,9 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
boot_rom_addr += advance; boot_rom_addr += advance;
/* read the control register */ /* read the control register */
control = RMEM(boot_rom_addr++) & datamask; control = RMEM(tms, boot_rom_addr++) & datamask;
for (i = 1; i < advance; i++) for (i = 1; i < advance; i++)
control |= (RMEM(boot_rom_addr++) & datamask) << (bits * i); control |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
/* now parse the data */ /* now parse the data */
while (1) while (1)
@ -630,18 +584,18 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
UINT32 offs, len; UINT32 offs, len;
/* read the length of this section */ /* read the length of this section */
len = RMEM(boot_rom_addr++) & datamask; len = RMEM(tms, boot_rom_addr++) & datamask;
for (i = 1; i < advance; i++) for (i = 1; i < advance; i++)
len |= (RMEM(boot_rom_addr++) & datamask) << (bits * i); len |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
/* stop at 0 */ /* stop at 0 */
if (len == 0) if (len == 0)
return start_offset; return start_offset;
/* read the destination offset of this section */ /* read the destination offset of this section */
offs = RMEM(boot_rom_addr++) & datamask; offs = RMEM(tms, boot_rom_addr++) & datamask;
for (i = 1; i < advance; i++) for (i = 1; i < advance; i++)
offs |= (RMEM(boot_rom_addr++) & datamask) << (bits * i); offs |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
/* if this is the first block, that's where we boot to */ /* if this is the first block, that's where we boot to */
if (first) if (first)
@ -656,12 +610,12 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
UINT32 data; UINT32 data;
/* extract the 32-bit word */ /* extract the 32-bit word */
data = RMEM(boot_rom_addr++) & datamask; data = RMEM(tms, boot_rom_addr++) & datamask;
for (i = 1; i < advance; i++) for (i = 1; i < advance; i++)
data |= (RMEM(boot_rom_addr++) & datamask) << (bits * i); data |= (RMEM(tms, boot_rom_addr++) & datamask) << (bits * i);
/* write it out */ /* write it out */
WMEM(offs++, data); WMEM(tms, offs++, data);
} }
} }
} }
@ -674,61 +628,62 @@ static UINT32 boot_loader(UINT32 boot_rom_addr)
static CPU_SET_INFO( tms32031 ) static CPU_SET_INFO( tms32031 )
{ {
tms32031_state *tms = device->token;
switch (state) switch (state)
{ {
/* --- the following bits of info are set as 64-bit signed integers --- */ /* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: set_irq_line(TMS32031_IRQ0, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: set_irq_line(tms, TMS32031_IRQ0, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: set_irq_line(TMS32031_IRQ1, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: set_irq_line(tms, TMS32031_IRQ1, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: set_irq_line(TMS32031_IRQ2, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: set_irq_line(tms, TMS32031_IRQ2, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: set_irq_line(TMS32031_IRQ3, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: set_irq_line(tms, TMS32031_IRQ3, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: set_irq_line(TMS32031_XINT0, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: set_irq_line(tms, TMS32031_XINT0, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: set_irq_line(TMS32031_RINT0, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: set_irq_line(tms, TMS32031_RINT0, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: set_irq_line(TMS32031_XINT1, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: set_irq_line(tms, TMS32031_XINT1, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: set_irq_line(TMS32031_RINT1, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: set_irq_line(tms, TMS32031_RINT1, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: set_irq_line(TMS32031_TINT0, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: set_irq_line(tms, TMS32031_TINT0, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: set_irq_line(TMS32031_TINT1, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: set_irq_line(tms, TMS32031_TINT1, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: set_irq_line(TMS32031_DINT, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: set_irq_line(tms, TMS32031_DINT, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: set_irq_line(TMS32031_DINT1, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: set_irq_line(tms, TMS32031_DINT1, info->i); break;
case CPUINFO_INT_PC: case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + TMS32031_PC: tms32031.pc = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_PC: tms->pc = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R0: IREG(TMR_R0) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R0: IREG(tms, TMR_R0) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R1: IREG(TMR_R1) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R1: IREG(tms, TMR_R1) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R2: IREG(TMR_R2) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R2: IREG(tms, TMR_R2) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R3: IREG(TMR_R3) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R3: IREG(tms, TMR_R3) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R4: IREG(TMR_R4) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R4: IREG(tms, TMR_R4) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R5: IREG(TMR_R5) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R5: IREG(tms, TMR_R5) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R6: IREG(TMR_R6) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R6: IREG(tms, TMR_R6) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R7: IREG(TMR_R7) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_R7: IREG(tms, TMR_R7) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_R0F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R0]); break; case CPUINFO_INT_REGISTER + TMS32031_R0F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R0]); break;
case CPUINFO_INT_REGISTER + TMS32031_R1F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R1]); break; case CPUINFO_INT_REGISTER + TMS32031_R1F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R1]); break;
case CPUINFO_INT_REGISTER + TMS32031_R2F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R2]); break; case CPUINFO_INT_REGISTER + TMS32031_R2F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R2]); break;
case CPUINFO_INT_REGISTER + TMS32031_R3F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R3]); break; case CPUINFO_INT_REGISTER + TMS32031_R3F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R3]); break;
case CPUINFO_INT_REGISTER + TMS32031_R4F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R4]); break; case CPUINFO_INT_REGISTER + TMS32031_R4F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R4]); break;
case CPUINFO_INT_REGISTER + TMS32031_R5F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R5]); break; case CPUINFO_INT_REGISTER + TMS32031_R5F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R5]); break;
case CPUINFO_INT_REGISTER + TMS32031_R6F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R6]); break; case CPUINFO_INT_REGISTER + TMS32031_R6F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R6]); break;
case CPUINFO_INT_REGISTER + TMS32031_R7F: double_to_dsp(*(float *)&info->i, &tms32031.r[TMR_R7]); break; case CPUINFO_INT_REGISTER + TMS32031_R7F: double_to_dsp(*(float *)&info->i, &tms->r[TMR_R7]); break;
case CPUINFO_INT_REGISTER + TMS32031_AR0: IREG(TMR_AR0) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR0: IREG(tms, TMR_AR0) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_AR1: IREG(TMR_AR1) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR1: IREG(tms, TMR_AR1) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_AR2: IREG(TMR_AR2) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR2: IREG(tms, TMR_AR2) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_AR3: IREG(TMR_AR3) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR3: IREG(tms, TMR_AR3) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_AR4: IREG(TMR_AR4) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR4: IREG(tms, TMR_AR4) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_AR5: IREG(TMR_AR5) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR5: IREG(tms, TMR_AR5) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_AR6: IREG(TMR_AR6) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR6: IREG(tms, TMR_AR6) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_AR7: IREG(TMR_AR7) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_AR7: IREG(tms, TMR_AR7) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_DP: IREG(TMR_DP) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_DP: IREG(tms, TMR_DP) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_IR0: IREG(TMR_IR0) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_IR0: IREG(tms, TMR_IR0) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_IR1: IREG(TMR_IR1) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_IR1: IREG(tms, TMR_IR1) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_BK: IREG(TMR_BK) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_BK: IREG(tms, TMR_BK) = info->i; break;
case CPUINFO_INT_SP: case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + TMS32031_SP: IREG(TMR_SP) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_SP: IREG(tms, TMR_SP) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_ST: IREG(TMR_ST) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_ST: IREG(tms, TMR_ST) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_IE: IREG(TMR_IE) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_IE: IREG(tms, TMR_IE) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_IF: IREG(TMR_IF) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_IF: IREG(tms, TMR_IF) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_IOF: IREG(TMR_IOF) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_IOF: IREG(tms, TMR_IOF) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_RS: IREG(TMR_RS) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_RS: IREG(tms, TMR_RS) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_RE: IREG(TMR_RE) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_RE: IREG(tms, TMR_RE) = info->i; break;
case CPUINFO_INT_REGISTER + TMS32031_RC: IREG(TMR_RC) = info->i; break; case CPUINFO_INT_REGISTER + TMS32031_RC: IREG(tms, TMR_RC) = info->i; break;
} }
} }
@ -752,12 +707,13 @@ ADDRESS_MAP_END
CPU_GET_INFO( tms32031 ) CPU_GET_INFO( tms32031 )
{ {
tms32031_state *tms = (device != NULL) ? device->token : NULL;
float ftemp; float ftemp;
switch (state) switch (state)
{ {
/* --- the following bits of info are returned as 64-bit signed integers --- */ /* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32031); break; case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32031_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 11; break; case CPUINFO_INT_INPUT_LINES: info->i = 11; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
@ -778,61 +734,61 @@ CPU_GET_INFO( tms32031 )
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ0)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ0)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ1)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ1)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ2)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ2: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ2)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: info->i = (IREG(TMR_IF) & (1 << TMS32031_IRQ3)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_IRQ3: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_IRQ3)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: info->i = (IREG(TMR_IF) & (1 << TMS32031_XINT0)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_XINT0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_XINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: info->i = (IREG(TMR_IF) & (1 << TMS32031_RINT0)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_RINT0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_RINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_XINT1)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_XINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_XINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_RINT1)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_RINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_RINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: info->i = (IREG(TMR_IF) & (1 << TMS32031_TINT0)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_TINT0: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_TINT0)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_TINT1)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_TINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_TINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: info->i = (IREG(TMR_IF) & (1 << TMS32031_DINT)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_DINT: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_DINT)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: info->i = (IREG(TMR_IF) & (1 << TMS32031_DINT1)) ? ASSERT_LINE : CLEAR_LINE; break; case CPUINFO_INT_INPUT_STATE + TMS32031_DINT1: info->i = (IREG(tms, TMR_IF) & (1 << TMS32031_DINT1)) ? ASSERT_LINE : CLEAR_LINE; break;
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
case CPUINFO_INT_PC: case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + TMS32031_PC: info->i = tms32031.pc; break; case CPUINFO_INT_REGISTER + TMS32031_PC: info->i = tms->pc; break;
case CPUINFO_INT_REGISTER + TMS32031_R0: info->i = IREG(TMR_R0); break; case CPUINFO_INT_REGISTER + TMS32031_R0: info->i = IREG(tms, TMR_R0); break;
case CPUINFO_INT_REGISTER + TMS32031_R1: info->i = IREG(TMR_R1); break; case CPUINFO_INT_REGISTER + TMS32031_R1: info->i = IREG(tms, TMR_R1); break;
case CPUINFO_INT_REGISTER + TMS32031_R2: info->i = IREG(TMR_R2); break; case CPUINFO_INT_REGISTER + TMS32031_R2: info->i = IREG(tms, TMR_R2); break;
case CPUINFO_INT_REGISTER + TMS32031_R3: info->i = IREG(TMR_R3); break; case CPUINFO_INT_REGISTER + TMS32031_R3: info->i = IREG(tms, TMR_R3); break;
case CPUINFO_INT_REGISTER + TMS32031_R4: info->i = IREG(TMR_R4); break; case CPUINFO_INT_REGISTER + TMS32031_R4: info->i = IREG(tms, TMR_R4); break;
case CPUINFO_INT_REGISTER + TMS32031_R5: info->i = IREG(TMR_R5); break; case CPUINFO_INT_REGISTER + TMS32031_R5: info->i = IREG(tms, TMR_R5); break;
case CPUINFO_INT_REGISTER + TMS32031_R6: info->i = IREG(TMR_R6); break; case CPUINFO_INT_REGISTER + TMS32031_R6: info->i = IREG(tms, TMR_R6); break;
case CPUINFO_INT_REGISTER + TMS32031_R7: info->i = IREG(TMR_R7); break; case CPUINFO_INT_REGISTER + TMS32031_R7: info->i = IREG(tms, TMR_R7); break;
case CPUINFO_INT_REGISTER + TMS32031_R0F: ftemp = dsp_to_double(&tms32031.r[TMR_R0]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R0F: ftemp = dsp_to_double(&tms->r[TMR_R0]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_R1F: ftemp = dsp_to_double(&tms32031.r[TMR_R1]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R1F: ftemp = dsp_to_double(&tms->r[TMR_R1]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_R2F: ftemp = dsp_to_double(&tms32031.r[TMR_R2]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R2F: ftemp = dsp_to_double(&tms->r[TMR_R2]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_R3F: ftemp = dsp_to_double(&tms32031.r[TMR_R3]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R3F: ftemp = dsp_to_double(&tms->r[TMR_R3]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_R4F: ftemp = dsp_to_double(&tms32031.r[TMR_R4]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R4F: ftemp = dsp_to_double(&tms->r[TMR_R4]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_R5F: ftemp = dsp_to_double(&tms32031.r[TMR_R5]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R5F: ftemp = dsp_to_double(&tms->r[TMR_R5]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_R6F: ftemp = dsp_to_double(&tms32031.r[TMR_R6]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R6F: ftemp = dsp_to_double(&tms->r[TMR_R6]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_R7F: ftemp = dsp_to_double(&tms32031.r[TMR_R7]); info->i = f2u(ftemp); break; case CPUINFO_INT_REGISTER + TMS32031_R7F: ftemp = dsp_to_double(&tms->r[TMR_R7]); info->i = f2u(ftemp); break;
case CPUINFO_INT_REGISTER + TMS32031_AR0: info->i = IREG(TMR_AR0); break; case CPUINFO_INT_REGISTER + TMS32031_AR0: info->i = IREG(tms, TMR_AR0); break;
case CPUINFO_INT_REGISTER + TMS32031_AR1: info->i = IREG(TMR_AR1); break; case CPUINFO_INT_REGISTER + TMS32031_AR1: info->i = IREG(tms, TMR_AR1); break;
case CPUINFO_INT_REGISTER + TMS32031_AR2: info->i = IREG(TMR_AR2); break; case CPUINFO_INT_REGISTER + TMS32031_AR2: info->i = IREG(tms, TMR_AR2); break;
case CPUINFO_INT_REGISTER + TMS32031_AR3: info->i = IREG(TMR_AR3); break; case CPUINFO_INT_REGISTER + TMS32031_AR3: info->i = IREG(tms, TMR_AR3); break;
case CPUINFO_INT_REGISTER + TMS32031_AR4: info->i = IREG(TMR_AR4); break; case CPUINFO_INT_REGISTER + TMS32031_AR4: info->i = IREG(tms, TMR_AR4); break;
case CPUINFO_INT_REGISTER + TMS32031_AR5: info->i = IREG(TMR_AR5); break; case CPUINFO_INT_REGISTER + TMS32031_AR5: info->i = IREG(tms, TMR_AR5); break;
case CPUINFO_INT_REGISTER + TMS32031_AR6: info->i = IREG(TMR_AR6); break; case CPUINFO_INT_REGISTER + TMS32031_AR6: info->i = IREG(tms, TMR_AR6); break;
case CPUINFO_INT_REGISTER + TMS32031_AR7: info->i = IREG(TMR_AR7); break; case CPUINFO_INT_REGISTER + TMS32031_AR7: info->i = IREG(tms, TMR_AR7); break;
case CPUINFO_INT_REGISTER + TMS32031_DP: info->i = IREG(TMR_DP); break; case CPUINFO_INT_REGISTER + TMS32031_DP: info->i = IREG(tms, TMR_DP); break;
case CPUINFO_INT_REGISTER + TMS32031_IR0: info->i = IREG(TMR_IR0); break; case CPUINFO_INT_REGISTER + TMS32031_IR0: info->i = IREG(tms, TMR_IR0); break;
case CPUINFO_INT_REGISTER + TMS32031_IR1: info->i = IREG(TMR_IR1); break; case CPUINFO_INT_REGISTER + TMS32031_IR1: info->i = IREG(tms, TMR_IR1); break;
case CPUINFO_INT_REGISTER + TMS32031_BK: info->i = IREG(TMR_BK); break; case CPUINFO_INT_REGISTER + TMS32031_BK: info->i = IREG(tms, TMR_BK); break;
case CPUINFO_INT_SP: case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + TMS32031_SP: info->i = IREG(TMR_SP); break; case CPUINFO_INT_REGISTER + TMS32031_SP: info->i = IREG(tms, TMR_SP); break;
case CPUINFO_INT_REGISTER + TMS32031_ST: info->i = IREG(TMR_ST); break; case CPUINFO_INT_REGISTER + TMS32031_ST: info->i = IREG(tms, TMR_ST); break;
case CPUINFO_INT_REGISTER + TMS32031_IE: info->i = IREG(TMR_IE); break; case CPUINFO_INT_REGISTER + TMS32031_IE: info->i = IREG(tms, TMR_IE); break;
case CPUINFO_INT_REGISTER + TMS32031_IF: info->i = IREG(TMR_IF); break; case CPUINFO_INT_REGISTER + TMS32031_IF: info->i = IREG(tms, TMR_IF); break;
case CPUINFO_INT_REGISTER + TMS32031_IOF: info->i = IREG(TMR_IOF); break; case CPUINFO_INT_REGISTER + TMS32031_IOF: info->i = IREG(tms, TMR_IOF); break;
case CPUINFO_INT_REGISTER + TMS32031_RS: info->i = IREG(TMR_RS); break; case CPUINFO_INT_REGISTER + TMS32031_RS: info->i = IREG(tms, TMR_RS); break;
case CPUINFO_INT_REGISTER + TMS32031_RE: info->i = IREG(TMR_RE); break; case CPUINFO_INT_REGISTER + TMS32031_RE: info->i = IREG(tms, TMR_RE); break;
case CPUINFO_INT_REGISTER + TMS32031_RC: info->i = IREG(TMR_RC); break; case CPUINFO_INT_REGISTER + TMS32031_RC: info->i = IREG(tms, TMR_RC); break;
/* --- the following bits of info are returned as pointers to data or functions --- */ /* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32031); break; case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32031); break;
@ -844,7 +800,7 @@ CPU_GET_INFO( tms32031 )
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms32031); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms32031); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32031); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32031); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &tms32031_icount; break; case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &tms->icount; break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(internal_32031); break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(internal_32031); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */ /* --- the following bits of info are returned as NULL-terminated strings --- */
@ -856,7 +812,7 @@ CPU_GET_INFO( tms32031 )
case CPUINFO_STR_FLAGS: case CPUINFO_STR_FLAGS:
{ {
UINT32 temp = tms32031.r[TMR_ST].i32[0]; UINT32 temp = tms->r[TMR_ST].i32[0];
sprintf(info->s, "%c%c%c%c%c%c%c%c", sprintf(info->s, "%c%c%c%c%c%c%c%c",
(temp & 0x80) ? 'O':'.', (temp & 0x80) ? 'O':'.',
(temp & 0x40) ? 'U':'.', (temp & 0x40) ? 'U':'.',
@ -869,44 +825,44 @@ CPU_GET_INFO( tms32031 )
break; break;
} }
case CPUINFO_STR_REGISTER + TMS32031_PC: sprintf(info->s, "PC: %08X", tms32031.pc); break; case CPUINFO_STR_REGISTER + TMS32031_PC: sprintf(info->s, "PC: %08X", tms->pc); break;
case CPUINFO_STR_REGISTER + TMS32031_R0: sprintf(info->s, " R0:%08X", tms32031.r[TMR_R0].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R0: sprintf(info->s, " R0:%08X", tms->r[TMR_R0].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R1: sprintf(info->s, " R1:%08X", tms32031.r[TMR_R1].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R1: sprintf(info->s, " R1:%08X", tms->r[TMR_R1].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R2: sprintf(info->s, " R2:%08X", tms32031.r[TMR_R2].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R2: sprintf(info->s, " R2:%08X", tms->r[TMR_R2].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R3: sprintf(info->s, " R3:%08X", tms32031.r[TMR_R3].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R3: sprintf(info->s, " R3:%08X", tms->r[TMR_R3].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R4: sprintf(info->s, " R4:%08X", tms32031.r[TMR_R4].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R4: sprintf(info->s, " R4:%08X", tms->r[TMR_R4].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R5: sprintf(info->s, " R5:%08X", tms32031.r[TMR_R5].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R5: sprintf(info->s, " R5:%08X", tms->r[TMR_R5].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R6: sprintf(info->s, " R6:%08X", tms32031.r[TMR_R6].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R6: sprintf(info->s, " R6:%08X", tms->r[TMR_R6].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R7: sprintf(info->s, " R7:%08X", tms32031.r[TMR_R7].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_R7: sprintf(info->s, " R7:%08X", tms->r[TMR_R7].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_R0F: sprintf(info->s, "R0F:!%12g", dsp_to_double(&tms32031.r[TMR_R0])); break; case CPUINFO_STR_REGISTER + TMS32031_R0F: sprintf(info->s, "R0F:!%12g", dsp_to_double(&tms->r[TMR_R0])); break;
case CPUINFO_STR_REGISTER + TMS32031_R1F: sprintf(info->s, "R1F:!%12g", dsp_to_double(&tms32031.r[TMR_R1])); break; case CPUINFO_STR_REGISTER + TMS32031_R1F: sprintf(info->s, "R1F:!%12g", dsp_to_double(&tms->r[TMR_R1])); break;
case CPUINFO_STR_REGISTER + TMS32031_R2F: sprintf(info->s, "R2F:!%12g", dsp_to_double(&tms32031.r[TMR_R2])); break; case CPUINFO_STR_REGISTER + TMS32031_R2F: sprintf(info->s, "R2F:!%12g", dsp_to_double(&tms->r[TMR_R2])); break;
case CPUINFO_STR_REGISTER + TMS32031_R3F: sprintf(info->s, "R3F:!%12g", dsp_to_double(&tms32031.r[TMR_R3])); break; case CPUINFO_STR_REGISTER + TMS32031_R3F: sprintf(info->s, "R3F:!%12g", dsp_to_double(&tms->r[TMR_R3])); break;
case CPUINFO_STR_REGISTER + TMS32031_R4F: sprintf(info->s, "R4F:!%12g", dsp_to_double(&tms32031.r[TMR_R4])); break; case CPUINFO_STR_REGISTER + TMS32031_R4F: sprintf(info->s, "R4F:!%12g", dsp_to_double(&tms->r[TMR_R4])); break;
case CPUINFO_STR_REGISTER + TMS32031_R5F: sprintf(info->s, "R5F:!%12g", dsp_to_double(&tms32031.r[TMR_R5])); break; case CPUINFO_STR_REGISTER + TMS32031_R5F: sprintf(info->s, "R5F:!%12g", dsp_to_double(&tms->r[TMR_R5])); break;
case CPUINFO_STR_REGISTER + TMS32031_R6F: sprintf(info->s, "R6F:!%12g", dsp_to_double(&tms32031.r[TMR_R6])); break; case CPUINFO_STR_REGISTER + TMS32031_R6F: sprintf(info->s, "R6F:!%12g", dsp_to_double(&tms->r[TMR_R6])); break;
case CPUINFO_STR_REGISTER + TMS32031_R7F: sprintf(info->s, "R7F:!%12g", dsp_to_double(&tms32031.r[TMR_R7])); break; case CPUINFO_STR_REGISTER + TMS32031_R7F: sprintf(info->s, "R7F:!%12g", dsp_to_double(&tms->r[TMR_R7])); break;
case CPUINFO_STR_REGISTER + TMS32031_AR0: sprintf(info->s, "AR0:%08X", tms32031.r[TMR_AR0].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR0: sprintf(info->s, "AR0:%08X", tms->r[TMR_AR0].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_AR1: sprintf(info->s, "AR1:%08X", tms32031.r[TMR_AR1].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR1: sprintf(info->s, "AR1:%08X", tms->r[TMR_AR1].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_AR2: sprintf(info->s, "AR2:%08X", tms32031.r[TMR_AR2].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR2: sprintf(info->s, "AR2:%08X", tms->r[TMR_AR2].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_AR3: sprintf(info->s, "AR3:%08X", tms32031.r[TMR_AR3].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR3: sprintf(info->s, "AR3:%08X", tms->r[TMR_AR3].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_AR4: sprintf(info->s, "AR4:%08X", tms32031.r[TMR_AR4].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR4: sprintf(info->s, "AR4:%08X", tms->r[TMR_AR4].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_AR5: sprintf(info->s, "AR5:%08X", tms32031.r[TMR_AR5].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR5: sprintf(info->s, "AR5:%08X", tms->r[TMR_AR5].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_AR6: sprintf(info->s, "AR6:%08X", tms32031.r[TMR_AR6].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR6: sprintf(info->s, "AR6:%08X", tms->r[TMR_AR6].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_AR7: sprintf(info->s, "AR7:%08X", tms32031.r[TMR_AR7].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_AR7: sprintf(info->s, "AR7:%08X", tms->r[TMR_AR7].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_DP: sprintf(info->s, " DP:%02X", tms32031.r[TMR_DP].i8[0]); break; case CPUINFO_STR_REGISTER + TMS32031_DP: sprintf(info->s, " DP:%02X", tms->r[TMR_DP].i8[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_IR0: sprintf(info->s, "IR0:%08X", tms32031.r[TMR_IR0].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_IR0: sprintf(info->s, "IR0:%08X", tms->r[TMR_IR0].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_IR1: sprintf(info->s, "IR1:%08X", tms32031.r[TMR_IR1].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_IR1: sprintf(info->s, "IR1:%08X", tms->r[TMR_IR1].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_BK: sprintf(info->s, " BK:%08X", tms32031.r[TMR_BK].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_BK: sprintf(info->s, " BK:%08X", tms->r[TMR_BK].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_SP: sprintf(info->s, " SP:%08X", tms32031.r[TMR_SP].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_SP: sprintf(info->s, " SP:%08X", tms->r[TMR_SP].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_ST: sprintf(info->s, " ST:%08X", tms32031.r[TMR_ST].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_ST: sprintf(info->s, " ST:%08X", tms->r[TMR_ST].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_IE: sprintf(info->s, " IE:%08X", tms32031.r[TMR_IE].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_IE: sprintf(info->s, " IE:%08X", tms->r[TMR_IE].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_IF: sprintf(info->s, " IF:%08X", tms32031.r[TMR_IF].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_IF: sprintf(info->s, " IF:%08X", tms->r[TMR_IF].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_IOF: sprintf(info->s, "IOF:%08X", tms32031.r[TMR_IOF].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_IOF: sprintf(info->s, "IOF:%08X", tms->r[TMR_IOF].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_RS: sprintf(info->s, " RS:%08X", tms32031.r[TMR_RS].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_RS: sprintf(info->s, " RS:%08X", tms->r[TMR_RS].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_RE: sprintf(info->s, " RE:%08X", tms32031.r[TMR_RE].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_RE: sprintf(info->s, " RE:%08X", tms->r[TMR_RE].i32[0]); break;
case CPUINFO_STR_REGISTER + TMS32031_RC: sprintf(info->s, " RC:%08X", tms32031.r[TMR_RC].i32[0]); break; case CPUINFO_STR_REGISTER + TMS32031_RC: sprintf(info->s, " RC:%08X", tms->r[TMR_RC].i32[0]); break;
} }
} }

13
src/emu/cpu/tms32031/tms32031.h
View File

@ -18,12 +18,17 @@
TYPE DEFINITIONS TYPE DEFINITIONS
***************************************************************************/ ***************************************************************************/
struct tms32031_config typedef void (*tms32031_xf_func)(const device_config *device, UINT8 val);
typedef void (*tms32031_iack_func)(const device_config *device, UINT8 val, offs_t address);
typedef struct _tms32031_config tms32031_config;
struct _tms32031_config
{ {
UINT32 bootoffset; UINT32 bootoffset;
void (*xf0_w)(UINT8 val); tms32031_xf_func xf0_w;
void (*xf1_w)(UINT8 val); tms32031_xf_func xf1_w;
void (*iack_w)(UINT8 val, offs_t addr); tms32031_iack_func iack_w;
}; };

2
src/mame/audio/cage.c
View File

@ -602,7 +602,7 @@ static WRITE32_HANDLER( speedup_w )
* *
*************************************/ *************************************/
static const struct tms32031_config cage_config = static const tms32031_config cage_config =
{ {
0x400000 0x400000
}; };

6
src/mame/drivers/gaelco3d.c
View File

@ -409,10 +409,10 @@ static WRITE32_HANDLER( tms_m68k_ram_w )
} }
static void iack_w(UINT8 state, offs_t addr) static void iack_w(const device_config *device, UINT8 state, offs_t addr)
{ {
logerror("iack_w(%d) - %06X\n", state, addr); logerror("iack_w(%d) - %06X\n", state, addr);
cpu_set_input_line(Machine->cpu[1], 0, CLEAR_LINE); cpu_set_input_line(device, 0, CLEAR_LINE);
} }
@ -908,7 +908,7 @@ INPUT_PORTS_END
* *
*************************************/ *************************************/
static const struct tms32031_config tms_config = static const tms32031_config tms_config =
{ {
0x1000, 0x1000,
0, 0,

4
src/mame/drivers/midvunit.c
View File

@ -459,7 +459,7 @@ static WRITE32_HANDLER( midvplus_misc_w )
* *
*************************************/ *************************************/
static void midvplus_xf1_w(UINT8 val) static void midvplus_xf1_w(const device_config *device, UINT8 val)
{ {
static int lastval; static int lastval;
// mame_printf_debug("xf1_w = %d\n", val); // mame_printf_debug("xf1_w = %d\n", val);
@ -509,7 +509,7 @@ static ADDRESS_MAP_START( midvunit_map, ADDRESS_SPACE_PROGRAM, 32 )
ADDRESS_MAP_END ADDRESS_MAP_END
static const struct tms32031_config midvplus_config = { 0, NULL, midvplus_xf1_w }; static const tms32031_config midvplus_config = { 0, NULL, midvplus_xf1_w };
static ADDRESS_MAP_START( midvplus_map, ADDRESS_SPACE_PROGRAM, 32 ) static ADDRESS_MAP_START( midvplus_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x000000, 0x01ffff) AM_RAM AM_BASE(&ram_base) AM_RANGE(0x000000, 0x01ffff) AM_RAM AM_BASE(&ram_base)