preparation for some fruit machine work I'm doing (nw)

.gitattributes

@@ -1289,6 +1289,8 @@ src/emu/machine/mc68901.c svneol=native#text/plain
 src/emu/machine/mc68901.h svneol=native#text/plain
 src/emu/machine/mccs1850.c svneol=native#text/plain
 src/emu/machine/mccs1850.h svneol=native#text/plain
+src/emu/machine/mcf5206e.c svneol=native#text/plain
+src/emu/machine/mcf5206e.h svneol=native#text/plain
 src/emu/machine/microtch.c svneol=native#text/plain
 src/emu/machine/microtch.h svneol=native#text/plain
 src/emu/machine/mm58274c.c svneol=native#text/plain

src/emu/emu.mak

@@ -228,6 +228,7 @@ EMUMACHINEOBJS = \
 	$(EMUMACHINE)/mc6854.o      \
 	$(EMUMACHINE)/mc68901.o     \
 	$(EMUMACHINE)/mccs1850.o    \
+	$(EMUMACHINE)/mcf5206e.o    \
 	$(EMUMACHINE)/microtch.o    \
 	$(EMUMACHINE)/mm58274c.o    \
 	$(EMUMACHINE)/mm74c922.o    \

src/emu/machine/mcf5206e.c

@@ -0,0 +1,218 @@
+/* Modern device for the MCF5206e Peripherals
+ this can be hooked properly to the CPU once the CPU is a modern device too
+*/
+
+#include "emu.h"
+#include "mcf5206e.h"
+
+
+//**************************************************************************
+//  LIVE DEVICE
+//**************************************************************************
+
+// device type definition
+const device_type MCF5206E_PERIPHERAL = &device_creator<mcf5206e_peripheral_device>;
+
+//-------------------------------------------------
+//  mcf5206e_peripheral_device - constructor
+//-------------------------------------------------
+
+mcf5206e_peripheral_device::mcf5206e_peripheral_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+	: device_t(mconfig, MCF5206E_PERIPHERAL, "MCF5206E Peripheral", tag, owner, clock)
+{
+}
+
+//-------------------------------------------------
+//  device_config_complete - perform any
+//  operations now that the configuration is
+//  complete
+//-------------------------------------------------
+
+void mcf5206e_peripheral_device::device_config_complete()
+{
+
+}
+
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void mcf5206e_peripheral_device::device_start()
+{
+
+}
+
+
+
+READ32_MEMBER(mcf5206e_peripheral_device::dev_r)
+{
+	return 0;
+}
+
+WRITE32_MEMBER(mcf5206e_peripheral_device::dev_w)
+{
+
+}
+
+
+// ColdFire peripherals
+
+enum {
+	CF_PPDAT    =   0x1c8/4,
+	CF_MBSR     =   0x1ec/4
+};
+
+WRITE32_MEMBER(mcf5206e_peripheral_device::seta2_coldfire_regs_w)
+{
+	COMBINE_DATA( &m_coldfire_regs[offset] );
+}
+
+READ32_MEMBER(mcf5206e_peripheral_device::seta2_coldfire_regs_r)
+{
+	switch( offset )
+	{
+		case CF_MBSR:
+			return machine().rand();
+
+		case CF_PPDAT:
+			return ioport(":BATTERY")->read() << 16;
+	}
+
+	return m_coldfire_regs[offset];
+}
+
+/*
+
+ADDRESS                 REG         WIDTH   NAME/DESCRIPTION                                    INIT VALUE (MR=Master Reset, NR=Normal Reset)       Read or Write access
+
+op MOVEC with $C0F		MBAR		32		Module Base Address Register						uninit (except V=0)									W
+$003					SIMR		8		SIM Configuration Register							C0													R/W
+$014					ICR1		8		Interrupt Control Register 1 - External IRQ1/IPL1	04													R/W
+$015					ICR2		8		Interrupt Control Register 2 - External IPL2		08													R/W
+$016					ICR3		8		Interrupt Control Register 3 - External IPL3		0C													R/W
+$017					ICR4		8		Interrupt Control Register 4 - External IRQ4/IPL4	10													R/W
+$018					ICR5		8		Interrupt Control Register 5 - External IPL5		14													R/W
+$019					ICR6		8		Interrupt Control Register 6 - External IPL6		18													R/W
+$01A					ICR7		8		Interrupt Control Register 7 - External IRQ7/IPL7	1C													R/W
+$01B					ICR8		8		Interrupt Control Register 8 - SWT					1C													R/W
+$01C					ICR9		8		Interrupt Control Register 9 - Timer 1 Interrupt	80													R/W
+$01D					ICR10		8		Interrupt Control Register 10 - Timer 2 Interrupt	80													R/W
+$01E					ICR11		8		Interrupt Control Register 11 - MBUS Interrupt		80													R/W
+$01F					ICR12		8		Interrupt Control Register 12 - UART 1 Interrupt	00													R/W
+$020					ICR13		8		Interrupt Control Register 13 - UART 2 Interrupt	00													R/W
+$036					IMR			16		Interrupt Mask Register								3FFE												R/W
+$03A					IPR			16		Interrupt Pending Register							0000												R
+$040					RSR			8		Reset Status Register								80 / 20												R/W
+$041					SYPCR		8		System Protection Control Register					00													R/W
+$042					SWIVR		8		Software Watchdog Interrupt Vector Register			0F													R/W
+$043					SWSR		8		Software Watchdog Service Register					uninit												W
+$046					DCRR		16		DRAM Controller Refresh								MR 0000   - NR uninit								R/W
+$04A					DCTR		16		DRAM Controller Timing Register						MR 0000   - NR uninit								R/W
+$04C					DCAR0		16		DRAM Controller 0 Address Register					MR uninit - NR uninit								R/W
+$050					DCMR0		32		DRAM Controller 0 Mask Register						MR uninit - NR uninit								R/W
+$057					DCCR0		8		DRAM Controller 0 Control Register					MR 00     - NR 00									R/W
+$058					DCAR1		16		DRAM Controller 1 Address Register					MR uninit - NR uninit								R/W
+$05C					DCMR1		32		DRAM Controller 1 Mask Register						MR uninit - NR uninit								R/W
+$063					DCCR1		8		DRAM Controller 1 Control Register					MR 00     - NR 00									R/W
+--------- CHIP SELECTS -----------
+$064					CSAR0		16		Chip-Select 0 Address Register						0000												R/W
+$068					CSMR0		32		Chip-Select 0 Mask Register							00000000											R/W
+$06E					CSCR0		16		Chip-Select 0 Control Register						3C1F, 3C5F, 3C9F, 3CDF, 3D1F, 3D5F, 3D9F, 3DDF		R/W
+                                                                                                AA set by IRQ 7 at reset									
+																								PS1 set by IRQ 4 at reset
+																								PS0 set by IRQ 1 at reset		
+$070					CSAR1		16		Chip-Select 1 Address Register						uninit												R/W
+$074					CSMR1		32		Chip-Select 1 Mask Register							uninit												R/W
+$07A					CSCR1		16		Chip-Select 1 Control Register						uninit *1											R/W
+$07C					CSAR2		16		Chip-Select 2 Address Register						uninit												R/W
+$080					CSMR2		32		Chip-Select 2 Mask Register							uninit												R/W
+$086					CSCR2		16		Chip-Select 2 Control Register						uninit *1											R/W
+$088					CSAR3		16		Chip-Select 3 Address Register						uninit												R/W
+$08C					CSMR3		32		Chip-Select 3 Mask Register							uninit												R/W
+$092					CSCR3		16		Chip-Select 3 Control Register						uninit *1											R/W
+$094					CSAR4		16		Chip-Select 4 Address Register						uninit												R/W
+$098					CSMR4		32		Chip-Select 4 Mask Register							uninit												R/W
+$09E					CSCR4		16		Chip-Select 4 Control Register						uninit *1											R/W
+$0A0					CSAR5		16		Chip-Select 5 Address Register						uninit												R/W
+$0A4					CSMR5		32		Chip-Select 5 Mask Register							uninit												R/W
+$0AA					CSCR5		16		Chip-Select 5 Control Register						uninit *1											R/W
+$0AC					CSAR6		16		Chip-Select 6 Address Register						uninit												R/W
+$0B0					CSMR6		32		Chip-Select 6 Mask Register							uninit												R/W
+$0B6					CSCR6		16		Chip-Select 6 Control Register						uninit *1											R/W
+$0B8					CSAR7		16		Chip-Select 7 Address Register						uninit												R/W
+$0BC					CSMR7		32		Chip-Select 7 Mask Register							uninit												R/W
+$0C2					CSCR7		16		Chip-Select 7 Control Register						uninit *1											R/W
+$0C6					DMCR		16		Default Memory Control Register						0000												R/W
+$0CA					PAR			16		Pin Assignment Register								00													R/W
+--------- TIMER MODULE -----------
+$100					TMR1		16		Timer 1 Mode Register								0000												R/W
+$104					TRR1		16		Timer 1 Reference Register							FFFF												R/W
+$108					TCR1		16		Timer 1 Capture Register							0000												R
+$10C					TCN1		16		Timer 1 Counter										0000												R/W
+$111					TER1		8		Timer 1 Event Register								00													R/W
+$120					TMR2		16		Timer 2 Mode Register								0000												R/W
+$124					TRR2		16		Timer 2 Reference Register							FFFF												R/W
+$128					TCR2		16		Timer 2 Capture Register							0000												R
+$12C					TCN2		16		Timer 2 Counter										0000												R/W
+$131					TER2		8		Timer 2 Event Register								00													R/W
+------------ UART SERIAL PORTS  -----------
+$140					UMR1,2		8		UART 1 Mode Registers								00													R/W
+$144					USR			8		UART 1 Status Register								00		 											R
+						UCSR		8		UART 1 Clock-Select Register						DD													W
+$148					UCR			8		UART 1 Command Register								00													W
+$14C					URB			8		UART 1 Receive Buffer								FF													R
+						UTB			8		UART 1 Transmit Buffer								00													W
+$150					UIPCR		8		UART Input Port Change Register						0F													R
+						UACR		8		UART 1 Auxilary Control Register					00													W
+$154					UISR		8		UART 1 Interrupt Status Register					00													R
+						UIMR		8		UART 1 Interrupt Mask Register						00													W
+$158					UBG1		8		UART 1 Baud Rate Generator Prescale MSB				uninit												W
+$15C					UBG2		8		UART 1 Baud Rate Generator Prescale LSB				uninit												W
+$170					UIVR		8		UART 1 Interrupt Vector Register					0F													R/W
+$174					UIP			8		UART 1 Input Port Register							FF													R
+$178					UOP1		8		UART 1 Output Port Bit Set CMD						UOP1[7-1]=undef; UOP1=0								W
+$17C					UOP0		8		UART 1 Output Port Bit Reset CMD					uninit												W
+
+$180					UMR1,2		8		UART 2 Mode Registers								00													R/W
+$184					USR			8		UART 2 Status Register								00													R
+						UCSR		8		UART 2 Clock-Select Register						DD													W
+$188					UCR			8		UART 2 Command Register								00													W
+$18C					URB			8		UART 2 Receive Buffer								FF													R
+						UTB			8		UART 2 Transmit Buffer								00													W
+$190					UIPCR		8		UART 2 Input Port Change Register					0F													R
+						UACR		8		UART 2 Auxilary Control Register					00													W
+$194					UISR		8		UART 2 Interrupt Status Register					00													R
+						UIMR		8		UART 2 Interrupt Mask Register						00													W
+$198					UBG1		8		UART 2 Baud Rate Generator Prescale MSB				uninit												R/W
+$19C					UBG2		8		UART 2 Barud Rate Generator Prescale LSB			uninit												R/W
+$1B0					UIVR		8		UART 2 Interrupt Vector Register					0F													R/W
+$1B4					UIP			8		UART 2 Input Port Register							FF													R
+$1B8					UOP1		8		UART 2 Output Port Bit Set CMD						UOP1[7-1]=undef; UOP1=0								W
+$1BC					UOP0		8		UART 2 Output Port Bit Reset CMD					uninit												W
+
+$1C5					PPDDR		8		Port A Data Direction Register						00													R/W
+$1C9					PPDAT		8		Port A Data Register								00													R/W
+------------ MBUS  -----------
+$1E0					MADR		8		M-Bus Address Register								00													R/W
+$1E4					MFDR		8		M-Bus Frequency Divider Register					00													R/W
+$1E8					MBCR		8		M-Bus Control Register								00													R/W
+$1EC					MBSR		8		M-Bus Status Register								00													R/W
+$1F0					MBDR		8		M-Bus Data I/O Register								00													R/W
+------------ DMA Controller -----------
+$200					DMASAR0		32		Source Address Register 0							00													R/W
+$204					DMADAR0		32		Destination Address Register 0						00													R/W
+$208					DCR0		16		DMA Control Register 0								00													R/W
+$20C					BCR0		16		Byte Count Register 0								00													R/W
+$210					DSR0		8		Status Register 0									00													R/W
+$214					DIVR0		8		Interrupt Vector Register 0							0F													R/W
+$240					DMASAR1		32		Source Address Register 1							00													R/W
+$244					DMADAR1		32		Destination Address Register 1						00													R/W
+$248					DCR1		16		DMA Control Register 1								00													R/W
+$24C					BCR1		16		Byte Count Register 1								00													R/W
+$250					DSR1		8		Status Register 1									00													R/W
+$254					DIVR1		8		Interrupt Vector Register 1							0F													R/W
+
+*1 - uninit except BRST=ASET=WRAH=RDAH=WR=RD=0
+
+*/

src/emu/machine/mcf5206e.h

@@ -0,0 +1,59 @@
+/***************************************************************************
+
+    Konami 033906
+
+***************************************************************************/
+
+#pragma once
+
+#ifndef __MCF5206E_PERIPHERAL_H__
+#define __MCF5206E_PERIPHERAL_H__
+
+#include "emu.h"
+
+
+
+/***************************************************************************
+    DEVICE CONFIGURATION MACROS
+***************************************************************************/
+
+#define MCFG_MCF5206E_PERIPHERAL_ADD(_tag) \
+	MCFG_DEVICE_ADD(_tag, MCF5206E_PERIPHERAL, 0) \
+
+
+/***************************************************************************
+    TYPE DEFINITIONS
+***************************************************************************/
+
+
+
+// ======================> mcf5206e_peripheral_device
+
+class mcf5206e_peripheral_device :  public device_t
+{
+public:
+	// construction/destruction
+	mcf5206e_peripheral_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+	DECLARE_READ32_MEMBER( dev_r );
+	DECLARE_WRITE32_MEMBER( dev_w );
+	DECLARE_READ32_MEMBER( seta2_coldfire_regs_r );
+	DECLARE_WRITE32_MEMBER( seta2_coldfire_regs_w );
+
+protected:
+	// device-level overrides
+	virtual void device_config_complete();
+	virtual void device_start();
+	virtual void device_reset() { }
+	virtual void device_post_load() { }
+	virtual void device_clock_changed() { }
+	UINT32 m_coldfire_regs[0x400/4];
+
+private:
+};
+
+
+// device type definition
+extern const device_type MCF5206E_PERIPHERAL;
+
+#endif  /* __MCF5206E_PERIPHERAL_H__ */

src/mame/drivers/bfm_sc5.c

@@ -11,17 +11,33 @@
 
 #include "emu.h"
 #include "includes/bfm_sc5.h"
+#include "machine/mcf5206e.h"
 
 
 static ADDRESS_MAP_START( sc5_map, AS_PROGRAM, 32, bfm_sc5_state )
 	AM_RANGE(0x00000000, 0x002fffff) AM_ROM
 	AM_RANGE(0x01000000, 0x0100ffff) AM_RAM
-	AM_RANGE(0x40000000, 0x40000fff) AM_RAM
+	AM_RANGE(0x40000000, 0x4000ffff) AM_RAM
+
+	AM_RANGE(0xffff0000, 0xffff03ff) AM_DEVREADWRITE("maincpu_onboard", mcf5206e_peripheral_device, dev_r, dev_w) // technically this can be moved with MBAR
 ADDRESS_MAP_END
 
 INPUT_PORTS_START( bfm_sc5 )
 INPUT_PORTS_END
 
+
+
+WRITE_LINE_MEMBER(bfm_sc5_state::bfm_sc5_ym_irqhandler)
+{
+	logerror("YMZ280 is generating an interrupt. State=%08x\n",state);
+}
+
+static const ymz280b_interface ymz280b_config =
+{
+	DEVCB_DRIVER_LINE_MEMBER(bfm_sc5_state,bfm_sc5_ym_irqhandler)
+};
+
+
 INTERRUPT_GEN_MEMBER(bfm_sc5_state::sc5_fake_timer_int)
 {
 	// this should be coming from the Timer / SIM modules of the Coldfire
@@ -32,7 +48,12 @@ MACHINE_CONFIG_START( bfm_sc5, bfm_sc5_state )
 	MCFG_CPU_ADD("maincpu", MCF5206E, 40000000) /* MCF5206eFT */
 	MCFG_CPU_PROGRAM_MAP(sc5_map)
 	MCFG_CPU_PERIODIC_INT_DRIVER(bfm_sc5_state, sc5_fake_timer_int, 1000)
+	MCFG_MCF5206E_PERIPHERAL_ADD("maincpu_onboard")
 
-	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
+	/* sound hardware */
-	/* unknown sound */
+	MCFG_SPEAKER_STANDARD_MONO("mono")
+
+	MCFG_SOUND_ADD("ymz", YMZ280B, 16000000) // ?? Mhz
+	MCFG_SOUND_CONFIG(ymz280b_config)
+	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
 MACHINE_CONFIG_END

src/mame/drivers/gamtor.c

@@ -27,6 +27,7 @@
 #include "emu.h"
 #include "cpu/m68000/m68000.h"
 #include "video/pc_vga.h"
+#include "machine/mcf5206e.h"
 
 class gaminator_state : public driver_device
 {
@@ -77,6 +78,7 @@ static MACHINE_CONFIG_START( gaminator, gaminator_state )
 	MCFG_CPU_ADD("maincpu", MCF5206E, 40000000) /* definitely Coldfire, model / clock uncertain */
 	MCFG_CPU_PROGRAM_MAP(gaminator_map)
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", gaminator_state,  irq6_line_hold) // irq6 seems to be needed to get past the ROM checking
+	MCFG_MCF5206E_PERIPHERAL_ADD("maincpu_onboard")
 
 	MCFG_FRAGMENT_ADD( pcvideo_gamtor_vga )
 

src/mame/drivers/seta2.c

@@ -116,6 +116,7 @@ reelquak:
 #include "machine/eeprom.h"
 #include "machine/nvram.h"
 #include "machine/ticket.h"
+#include "machine/mcf5206e.h"
 
 /***************************************************************************
 
@@ -545,31 +546,6 @@ READ16_MEMBER(seta2_state::spriteram16_word_r)
 
 // Main CPU
 
-// ColdFire peripherals
-
-enum {
-	CF_PPDAT    =   0x1c8/4,
-	CF_MBSR     =   0x1ec/4
-};
-
-WRITE32_MEMBER(seta2_state::coldfire_regs_w)
-{
-	COMBINE_DATA( &m_coldfire_regs[offset] );
-}
-
-READ32_MEMBER(seta2_state::coldfire_regs_r)
-{
-	switch( offset )
-	{
-		case CF_MBSR:
-			return machine().rand();
-
-		case CF_PPDAT:
-			return ioport("BATTERY")->read() << 16;
-	}
-
-	return m_coldfire_regs[offset];
-}
 
 READ32_MEMBER(seta2_state::funcube_debug_r)
 {
@@ -615,7 +591,7 @@ static ADDRESS_MAP_START( funcube_map, AS_PROGRAM, 32, seta2_state )
 
 	AM_RANGE( 0x00c00000, 0x00c002ff ) AM_READWRITE(funcube_nvram_dword_r, funcube_nvram_dword_w )
 
-	AM_RANGE(0xf0000000, 0xf00001ff ) AM_READWRITE(coldfire_regs_r, coldfire_regs_w ) AM_SHARE("coldfire_regs") // Module
+	AM_RANGE(0xf0000000, 0xf00001ff) AM_DEVREADWRITE("maincpu_onboard", mcf5206e_peripheral_device, seta2_coldfire_regs_r, seta2_coldfire_regs_w) // technically this can be moved with MBAR
 	AM_RANGE(0xffffe000, 0xffffffff ) AM_RAM    // SRAM
 ADDRESS_MAP_END
 
@@ -634,7 +610,7 @@ static ADDRESS_MAP_START( funcube2_map, AS_PROGRAM, 32, seta2_state )
 
 	AM_RANGE( 0x00c00000, 0x00c002ff ) AM_READWRITE(funcube_nvram_dword_r, funcube_nvram_dword_w )
 
-	AM_RANGE(0xf0000000, 0xf00001ff ) AM_READWRITE(coldfire_regs_r, coldfire_regs_w ) AM_SHARE("coldfire_regs") // Module
+	AM_RANGE(0xf0000000, 0xf00001ff) AM_DEVREADWRITE("maincpu_onboard", mcf5206e_peripheral_device, seta2_coldfire_regs_r, seta2_coldfire_regs_w) // technically this can be moved with MBAR
 	AM_RANGE(0xffffe000, 0xffffffff ) AM_RAM    // SRAM
 ADDRESS_MAP_END
 
@@ -2212,6 +2188,8 @@ static MACHINE_CONFIG_START( funcube, seta2_state )
 	MCFG_CPU_IO_MAP(funcube_sub_io)
 	MCFG_CPU_PERIODIC_INT_DRIVER(seta2_state, funcube_sub_timer_irq,  60*10)
 
+	MCFG_MCF5206E_PERIPHERAL_ADD("maincpu_onboard")
+
 	MCFG_NVRAM_ADD_0FILL("nvram")
 
 	MCFG_MACHINE_RESET_OVERRIDE(seta2_state, funcube )

src/mame/includes/bfm_sc5.h

@@ -16,4 +16,6 @@ protected:
 public:
 	DECLARE_DRIVER_INIT(sc5);
 	INTERRUPT_GEN_MEMBER(sc5_fake_timer_int);
+	DECLARE_WRITE_LINE_MEMBER(bfm_sc5_ym_irqhandler);
+
 };

src/mame/includes/seta2.h

@@ -10,7 +10,6 @@ public:
 			m_nvram(*this, "nvram") ,
 		m_spriteram(*this, "spriteram", 0),
 		m_vregs(*this, "vregs", 0),
-		m_coldfire_regs(*this, "coldfire_regs"),
 		m_funcube_outputs(*this, "funcube_outputs"),
 		m_funcube_leds(*this, "funcube_leds"),
 		m_oki(*this, "oki"),
@@ -21,7 +20,6 @@ public:
 
 	optional_shared_ptr<UINT16> m_spriteram;
 	optional_shared_ptr<UINT16> m_vregs;
-	optional_shared_ptr<UINT32> m_coldfire_regs;
 
 	optional_shared_ptr<UINT8> m_funcube_outputs;
 	optional_shared_ptr<UINT8> m_funcube_leds;