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https://github.com/holub/mame
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New NOT WORKING machine [Robbbert]
================================== Datamax 8000 placeholder for next dev cycle.
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Robbbert
parent
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commit
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@ -3098,6 +3098,7 @@ files {
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MAME_DIR .. "src/mame/drivers/dim68k.cpp",
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MAME_DIR .. "src/mame/drivers/dm7000.cpp",
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MAME_DIR .. "src/mame/includes/dm7000.h",
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MAME_DIR .. "src/mame/drivers/dmax8000.cpp",
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MAME_DIR .. "src/mame/drivers/dmv.cpp",
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MAME_DIR .. "src/mame/machine/dmv_keyb.cpp",
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MAME_DIR .. "src/mame/machine/dmv_keyb.h",
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214
src/mame/drivers/dmax8000.cpp
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214
src/mame/drivers/dmax8000.cpp
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// license:BSD-3-Clause
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// copyright-holders:Robbbert
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/******************************************************************************************************************
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Datamax 8000
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2016-07-24 Skeleton driver
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This computer was designed and made by Datamax Pty Ltd, in Manly, Sydney, Australia.
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It could have up to 4x 8 inch floppy drives, in the IBM format.
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There were a bunch of optional extras such as 256kB RAM, numeric coprocessor, RTC, etc.
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ToDo:
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- Everything... there are partial schematics, but there's still a lot of guesswork.
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****************************************************************************************************************/
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#include "machine/wd_fdc.h"
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#include "cpu/z80/z80daisy.h"
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#include "machine/z80pio.h"
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#include "machine/z80dart.h"
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#include "machine/z80ctc.h"
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#include "machine/terminal.h"
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class dmax8000_state : public driver_device
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{
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public:
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dmax8000_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_terminal(*this, "terminal")
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, m_fdc(*this, "fdc")
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{
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}
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DECLARE_DRIVER_INIT(dmax8000);
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DECLARE_MACHINE_RESET(dmax8000);
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DECLARE_READ8_MEMBER(port80_r);
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DECLARE_READ8_MEMBER(port81_r);
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DECLARE_WRITE8_MEMBER(port40_w);
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DECLARE_WRITE8_MEMBER(kbd_put);
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DECLARE_WRITE_LINE_MEMBER(ctc_z0_w);
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DECLARE_WRITE_LINE_MEMBER(ctc_z1_w);
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DECLARE_WRITE_LINE_MEMBER(ctc_z2_w);
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private:
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UINT8 m_term_data;
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required_device<cpu_device> m_maincpu;
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required_device<generic_terminal_device> m_terminal;
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required_device<fd1793_t> m_fdc;
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};
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WRITE8_MEMBER( dmax8000_state::port40_w )
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{
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membank("bankr0")->set_entry(BIT(data, 0));
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}
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READ8_MEMBER( dmax8000_state::port80_r )
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{
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UINT8 ret = m_term_data;
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m_term_data = 0;
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return ret;
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}
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READ8_MEMBER( dmax8000_state::port81_r )
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{
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return (m_term_data) ? 13 : 12;
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}
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static ADDRESS_MAP_START(dmax8000_mem, AS_PROGRAM, 8, dmax8000_state)
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AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0")
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AM_RANGE(0x1000, 0xffff) AM_RAM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(dmax8000_io, AS_IO, 8, dmax8000_state)
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("fdc", fd1793_t, read, write)
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//AM_RANGE(0x04, 0x07) AM_DEVREADWRITE("dart1", z80dart_device, ba_cd_r, ba_cd_w)
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AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
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AM_RANGE(0x0c, 0x0f) AM_DEVREADWRITE("pio1", z80pio_device, read, write)
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AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("pio2", z80pio_device, read, write)
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//AM_RANGE(0x14, 0x17) AM_WRITE(port14_r)
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//AM_RANGE(0x18, 0x19) AM_MIRROR(2) AM_DEVREADWRITE("am9512", am9512_device, read, write) // optional numeric coprocessor
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//AM_RANGE(0x1c, 0x1d) AM_MIRROR(2) // optional hard disk controller (1C=status, 1D=data)
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AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("dart2", z80dart_device, ba_cd_r, ba_cd_w)
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AM_RANGE(0x40, 0x40) AM_WRITE(port40_w) // memory bank control
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//AM_RANGE(0x60, 0x67) // optional IEEE488 GPIB
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//AM_RANGE(0x70, 0x7f) AM_DEVREADWRITE("rtc", mm58274c_device, read, write) // optional RTC
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AM_RANGE(0x04, 0x04) AM_READ(port80_r) AM_DEVWRITE("terminal", generic_terminal_device, write)
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AM_RANGE(0x05, 0x05) AM_READ(port81_r)
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ADDRESS_MAP_END
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/* Input ports */
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static INPUT_PORTS_START( dmax8000 )
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INPUT_PORTS_END
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/* Z80 Daisy Chain */
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// order unknown
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static const z80_daisy_config daisy_chain[] =
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{
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{ "pio1" },
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{ "pio2" },
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{ "dart1" },
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{ "dart2" },
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{ "ctc" },
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{ nullptr }
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};
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/* Z80-CTC Interface */
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WRITE_LINE_MEMBER( dmax8000_state::ctc_z0_w )
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{
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// guess this generates clock for z80dart
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}
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WRITE_LINE_MEMBER( dmax8000_state::ctc_z1_w )
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{
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}
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WRITE_LINE_MEMBER( dmax8000_state::ctc_z2_w )
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{
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}
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/* after the first 4 bytes have been read from ROM, switch the ram back in */
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MACHINE_RESET_MEMBER( dmax8000_state, dmax8000 )
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{
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membank("bankr0")->set_entry(0); // point at rom
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membank("bankw0")->set_entry(0); // always write to ram
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}
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DRIVER_INIT_MEMBER( dmax8000_state, dmax8000 )
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{
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UINT8 *main = memregion("maincpu")->base();
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membank("bankr0")->configure_entry(1, &main[0x0000]);
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membank("bankr0")->configure_entry(0, &main[0x10000]);
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membank("bankw0")->configure_entry(0, &main[0x0000]);
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}
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static SLOT_INTERFACE_START( floppies )
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SLOT_INTERFACE( "drive0", FLOPPY_8_DSDD )
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SLOT_INTERFACE_END
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WRITE8_MEMBER( dmax8000_state::kbd_put )
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{
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m_term_data = data;
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}
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static MACHINE_CONFIG_START( dmax8000, dmax8000_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", Z80, XTAL_4MHz ) // no idea what crystal is used, but 4MHz clock is confirmed
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MCFG_CPU_PROGRAM_MAP(dmax8000_mem)
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MCFG_CPU_IO_MAP(dmax8000_io)
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MCFG_Z80_DAISY_CHAIN(daisy_chain)
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MCFG_MACHINE_RESET_OVERRIDE(dmax8000_state, dmax8000)
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MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0)
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MCFG_GENERIC_TERMINAL_KEYBOARD_CB(WRITE8(dmax8000_state, kbd_put))
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MCFG_DEVICE_ADD("ctc", Z80CTC, XTAL_4MHz)
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MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_Z80CTC_ZC0_CB(WRITELINE(dmax8000_state, ctc_z0_w))
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MCFG_Z80CTC_ZC1_CB(WRITELINE(dmax8000_state, ctc_z1_w))
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MCFG_Z80CTC_ZC2_CB(WRITELINE(dmax8000_state, ctc_z2_w))
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MCFG_Z80DART_ADD("dart1", XTAL_4MHz, 0, 0, 0, 0 )
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//MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232", rs232_port_device, write_txd))
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//MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
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//MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232", rs232_port_device, write_rts))
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MCFG_Z80DART_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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//MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "terminal")
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//MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart", z80dart_device, write_rxd))
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//MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart", z80dart_device, write_dsr))
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//MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart", z80dart_device, write_cts))
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//MCFG_DEVICE_CARD_DEVICE_INPUT_DEFAULTS("terminal", dmax8000 )
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MCFG_Z80DART_ADD("dart2", XTAL_4MHz, 0, 0, 0, 0 )
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MCFG_Z80DART_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_DEVICE_ADD("pio1", Z80PIO, XTAL_4MHz)
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MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_DEVICE_ADD("pio2", Z80PIO, XTAL_4MHz)
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MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_FD1793_ADD("fdc", XTAL_2MHz)
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//MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(dmax8000_state, fdc_intrq_w))
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//MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(dmax8000_state, fdc_drq_w))
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MCFG_FLOPPY_DRIVE_ADD("fdc:0", floppies, "drive0", floppy_image_device::default_floppy_formats)
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MCFG_FLOPPY_DRIVE_SOUND(true)
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MACHINE_CONFIG_END
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/* ROM definition */
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ROM_START( dmax8000 )
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ROM_REGION( 0x11000, "maincpu", 0 )
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ROM_LOAD( "rev1_0.rom", 0x10000, 0x001000, CRC(acbec83f) SHA1(fce0a4307a791250dbdc6bb6a190f7fec3619d82) )
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// ROM_LOAD( "rev1_1.rom", 0x10000, 0x001000, CRC(2eb98a61) SHA1(cdd9a58f63ee7e3d3dd1c4ae3fd4376b308fd10f) ) // this is a hacked rom to speed up the serial port
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ROM_END
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/* Driver */
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/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
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COMP( 1981, dmax8000, 0, 0, dmax8000, dmax8000, dmax8000_state, dmax8000, "Datamax", "Datamax 8000", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
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@ -11039,6 +11039,9 @@ dm500 //
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dm5620 //
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dm7000 //
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@source:dmax8000.cpp
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dmax8000 //
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@source:dmndrby.cpp
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dmndrby // G4001 'DD' (c) 1986
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dmndrbya // G4001 'DD' (c) 1986
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@ -144,6 +144,7 @@ didact.cpp
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digel804.cpp
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dim68k.cpp
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dm7000.cpp
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dmax8000.cpp
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dms5000.cpp
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dms86.cpp
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dmv.cpp
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