diff --git a/src/devices/bus/vme/vme.cpp b/src/devices/bus/vme/vme.cpp index 342596f10bf..381b7e3075e 100644 --- a/src/devices/bus/vme/vme.cpp +++ b/src/devices/bus/vme/vme.cpp @@ -1,7 +1,7 @@ // license:BSD-3-Clause // copyright-holders:Joakim Larsson Edstrom /* - * vme.c + * vme.cpp * * The Versabus-E was standardized as the VME bus by VITA 1981 for Europe * in the single or double Euroboard form factor. Several standard revs has @@ -221,19 +221,21 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read8_delegate rhan { cpu_device *m_maincpu = machine().device("maincpu"); - // printf("%s", __func__); - int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width; + LOG("%s width:%d\n", FUNCNAME, buswidth); switch(buswidth) { - case 32: - m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask); - break; - case 64: - m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, ((uint64_t)mask<<32)|mask); - break; - default: - fatalerror("VME_P1: Bus width %d not supported\n", buswidth); + case 32: + logerror("A32:D8 handler requires a P2 connector - not implemented yet\n"); + break; + case 24: + m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask); + break; + case 16: + m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0xffff)); + break; + default: + fatalerror("VME_P1 D8: Bus width %d not supported\n", buswidth); } } @@ -241,16 +243,20 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read16_delegate rha { cpu_device *m_maincpu = machine().device("maincpu"); int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width; + LOG("%s width:%d\n", FUNCNAME, buswidth); switch(buswidth) { - case 32: - m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask); - break; - case 64: - m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, ((uint64_t)mask<<32)|mask); - break; - default: - fatalerror("VME_P1: Bus width %d not supported\n", buswidth); + case 32: + logerror("A32:D16 handler requires a P2 connector - not implemented yet\n"); + break; + case 24: + m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask); + break; + case 16: + m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0xffff)); + break; + default: + fatalerror("VME_P1 D16: Bus width %d not supported\n", buswidth); } } @@ -258,16 +264,22 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read32_delegate rha { cpu_device *m_maincpu = machine().device("maincpu"); int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width; + LOG("%s width:%d\n", FUNCNAME, buswidth); switch(buswidth) { - case 32: - m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask); - break; - case 64: - m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, ((uint64_t)mask<<32)|mask); - break; - default: - fatalerror("VME_P1: Bus width %d not supported\n", buswidth); + case 32: + logerror("A32:D32 handler requires a P2 connector - not implemented yet\n"); + break; + case 24: + logerror("A24:D32 handler requires a P2 connector - not implemented yet\n"); + // m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask); + break; + case 16: + logerror("A16:D32 handler requires a P2 connector - not implemented yet\n"); + // m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0xffff)); + break; + default: + fatalerror("VME_P1 D32: Bus width %d not supported\n", buswidth); } } diff --git a/src/devices/machine/z80sio.cpp b/src/devices/machine/z80sio.cpp index bfdf250c263..097891e5991 100644 --- a/src/devices/machine/z80sio.cpp +++ b/src/devices/machine/z80sio.cpp @@ -53,26 +53,37 @@ // MACROS / CONSTANTS //************************************************************************** -#define VERBOSE 0 +#define LOG_GENERAL 0x001 +#define LOG_SETUP 0x002 +#define LOG_PRINTF 0x004 +#define LOG_READ 0x008 +#define LOG_INT 0x010 +#define LOG_TX 0x020 +#define LOG_RCV 0x040 +#define LOG_CTS 0x080 +#define LOG_DCD 0x100 -#define LOGPRINT(x) { do { if (VERBOSE) logerror x; } while (0); } -#define LOG(x) {} -#define LOGR(x) {} -#define LOGSETUP(x) {} LOGPRINT(x) -#define LOGINT(x) {} -#define LOGTX(x) {} -#define LOGRCV(x) {} -#define LOGCTS(x) {} LOGPRINT(x) -#define LOGDCD(x) {} LOGPRINT(x) -#if VERBOSE == 2 +#define VERBOSE 0 //(LOG_PRINTF | LOG_SETUP | LOG_GENERAL) + +#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0) +#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0) + +#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__) +#define LOGR(...) LOGMASK(LOG_READ, __VA_ARGS__) +#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__) +#define LOGINT(...) LOGMASK(LOG_INT, __VA_ARGS__) +#define LOGTX(...) LOGMASK(LOG_TX, __VA_ARGS__) +#define LOGRCV(...) LOGMASK(LOG_RCV, __VA_ARGS__) +#define LOGCTS(...) LOGMASK(LOG_CTS, __VA_ARGS__) +#define LOGDCD(...) LOGMASK(LOG_DCD, __VA_ARGS__) + +#if VERBOSE & LOG_PRINTF #define logerror printf #endif #ifdef _MSC_VER -#define LLFORMAT "%I64%" #define FUNCNAME __func__ #else -#define LLFORMAT "%lld" #define FUNCNAME __PRETTY_FUNCTION__ #endif @@ -178,7 +189,7 @@ upd7201N_device::upd7201N_device(const machine_config &mconfig, const char *tag, //------------------------------------------------- void z80sio_device::device_start() { - LOG(("%s\n", FUNCNAME)); + LOG("%s\n", FUNCNAME); // resolve callbacks m_out_txda_cb.resolve_safe(); m_out_dtra_cb.resolve_safe(); @@ -214,7 +225,7 @@ void z80sio_device::device_start() //------------------------------------------------- void z80sio_device::device_reset() { - LOG(("%s \"%s\" \n", FUNCNAME, tag())); + LOG("%s \"%s\" \n", FUNCNAME, tag()); m_chanA->reset(); m_chanB->reset(); @@ -229,9 +240,9 @@ int z80sio_device::z80daisy_irq_state() int i; - LOGINT(("%s %s A:%d%d%d%d B:%d%d%d%d ",FUNCNAME, tag(), + LOGINT("%s %s A:%d%d%d%d B:%d%d%d%d ",FUNCNAME, tag(), m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], - m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); + m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]); // loop over all interrupt sources for (i = 0; i < 8; i++) @@ -245,7 +256,7 @@ int z80sio_device::z80daisy_irq_state() state |= m_int_state[i]; } - LOGINT(("Interrupt State %u\n", state)); + LOGINT("Interrupt State %u\n", state); return state; } @@ -258,7 +269,7 @@ int z80sio_device::z80daisy_irq_ack() { int i; - LOGINT(("%s %s \n",FUNCNAME, tag())); + LOGINT("%s %s \n",FUNCNAME, tag()); // loop over all interrupt sources for (i = 0; i < 8; i++) @@ -271,7 +282,7 @@ int z80sio_device::z80daisy_irq_ack() m_chanA->m_rr0 &= ~z80sio_channel::RR0_INTERRUPT_PENDING; check_interrupts(); - //LOG(("%s %s \n",FUNCNAME, tag(), m_chanB->m_rr2)); + //LOG("%s %s \n",FUNCNAME, tag(), m_chanB->m_rr2); return m_chanB->m_rr2; } @@ -290,7 +301,7 @@ void z80sio_device::z80daisy_irq_reti() { int i; - LOGINT(("%s %s \n",FUNCNAME, tag())); + LOGINT("%s %s \n",FUNCNAME, tag()); // loop over all interrupt sources for (i = 0; i < 8; i++) @@ -314,7 +325,7 @@ void z80sio_device::z80daisy_irq_reti() //------------------------------------------------- void z80sio_device::check_interrupts() { - LOGINT(("%s %s \n",FUNCNAME, tag())); + LOGINT("%s %s \n",FUNCNAME, tag()); int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE; m_out_int_cb(state); } @@ -325,7 +336,7 @@ void z80sio_device::check_interrupts() //------------------------------------------------- void z80sio_device::reset_interrupts() { - LOGINT(("%s %s \n",FUNCNAME, tag())); + LOGINT("%s %s \n",FUNCNAME, tag()); // reset internal interrupt sources for (auto & elem : m_int_state) { @@ -344,7 +355,7 @@ void z80sio_device::trigger_interrupt(int index, int state) uint8_t vector = m_chanB->m_wr2; int priority; - LOGINT(("%s %s \n",FUNCNAME, tag())); + LOGINT("%s %s \n",FUNCNAME, tag()); #if 0 if((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201)) @@ -412,7 +423,7 @@ void z80sio_device::trigger_interrupt(int index, int state) //------------------------------------------------- int z80sio_device::m1_r() { - LOGINT(("%s %s \n",FUNCNAME, tag())); + LOGINT("%s %s \n",FUNCNAME, tag()); return z80daisy_irq_ack(); } @@ -426,7 +437,7 @@ READ8_MEMBER( z80sio_device::cd_ba_r ) int cd = BIT(offset, 1); z80sio_channel *channel = ba ? m_chanB : m_chanA; - //LOG(("%s %s %c %s read\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" )); + //LOG("%s %s %c %s read\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ); return cd ? channel->control_read() : channel->data_read(); } @@ -441,7 +452,7 @@ WRITE8_MEMBER( z80sio_device::cd_ba_w ) int cd = BIT(offset, 1); z80sio_channel *channel = ba ? m_chanB : m_chanA; - LOG(("%s %s %c %s write\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" )); + LOG("%s %s %c %s write\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ); if (cd) channel->control_write(data); @@ -459,7 +470,7 @@ READ8_MEMBER( z80sio_device::ba_cd_r ) int cd = BIT(offset, 0); z80sio_channel *channel = ba ? m_chanB : m_chanA; - //LOG(("%s %s %c %s read\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" )); + //LOG("%s %s %c %s read\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ); return cd ? channel->control_read() : channel->data_read(); } @@ -474,7 +485,7 @@ WRITE8_MEMBER( z80sio_device::ba_cd_w ) int cd = BIT(offset, 0); z80sio_channel *channel = ba ? m_chanB : m_chanA; - LOG(("%s %s %c %s write\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" )); + LOG("%s %s %c %s write\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ); if (cd) channel->control_write(data); @@ -508,7 +519,7 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d m_rts(0), m_sync(0) { - LOG(("%s\n",FUNCNAME)); + LOG("%s\n",FUNCNAME); // Reset all registers m_rr0 = m_rr1 = m_rr2 = 0; m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = 0; @@ -526,7 +537,7 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d //------------------------------------------------- void z80sio_channel::device_start() { - LOG(("%s\n",FUNCNAME)); + LOG("%s\n",FUNCNAME); m_uart = downcast(owner()); m_index = m_uart->get_channel_index(this); m_variant = ((z80sio_device *)m_owner)->m_variant; @@ -569,7 +580,7 @@ void z80sio_channel::device_start() //------------------------------------------------- void z80sio_channel::device_reset() { - LOG(("%s\n", FUNCNAME)); + LOG("%s\n", FUNCNAME); // Reset RS232 emulation receive_register_reset(); @@ -606,7 +617,7 @@ void z80sio_channel::tra_callback() { if (!(m_wr5 & WR5_TX_ENABLE)) { - LOG(("%s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG("%s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5); // transmit mark if (m_index == z80sio_device::CHANNEL_A) m_uart->m_out_txda_cb(1); @@ -615,7 +626,7 @@ void z80sio_channel::tra_callback() } else if (m_wr5 & WR5_SEND_BREAK) { - LOG(("%s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG("%s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5); // transmit break if (m_index == z80sio_device::CHANNEL_A) m_uart->m_out_txda_cb(0); @@ -626,7 +637,7 @@ void z80sio_channel::tra_callback() { int db = transmit_register_get_data_bit(); - LOG(("%s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5)); + LOG("%s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5); // transmit data if (m_index == z80sio_device::CHANNEL_A) m_uart->m_out_txda_cb(db); @@ -635,7 +646,7 @@ void z80sio_channel::tra_callback() } else { - LOG(("%s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG("%s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5); logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index); } } @@ -646,10 +657,10 @@ void z80sio_channel::tra_callback() //------------------------------------------------- void z80sio_channel::tra_complete() { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); if ((m_wr5 & WR5_TX_ENABLE) && !(m_wr5 & WR5_SEND_BREAK) && !(m_rr0 & RR0_TX_BUFFER_EMPTY)) { - LOG(("%s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_tx_data, m_wr5)); + LOG("%s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_tx_data, m_wr5); transmit_register_setup(m_tx_data); @@ -661,7 +672,7 @@ void z80sio_channel::tra_complete() } else if (m_wr5 & WR5_SEND_BREAK) { - LOG(("%s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG("%s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5); // transmit break if (m_index == z80sio_device::CHANNEL_A) m_uart->m_out_txda_cb(0); @@ -670,7 +681,7 @@ void z80sio_channel::tra_complete() } else { - LOG(("%s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG("%s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5); // transmit mark if (m_index == z80sio_device::CHANNEL_A) m_uart->m_out_txda_cb(1); @@ -681,7 +692,7 @@ void z80sio_channel::tra_complete() // if transmit buffer is empty if (m_rr0 & RR0_TX_BUFFER_EMPTY) { - LOG(("%s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG("%s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5); // then all characters have been sent m_rr1 |= RR1_ALL_SENT; @@ -699,13 +710,13 @@ void z80sio_channel::rcv_callback() { if (m_wr3 & WR3_RX_ENABLE) { - LOG(("%s() \"%s \"Channel %c Received Data Bit %d\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd)); + LOG("%s() \"%s \"Channel %c Received Data Bit %d\n", FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd); receive_register_update_bit(m_rxd); } #if 0 else { - LOG(("%s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", FUNCNAME, m_owner->tag(), 'A' + m_index)); + LOG("%s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", FUNCNAME, m_owner->tag(), 'A' + m_index); logerror("Z80SIO %s() \"%s \"Channel %c Received data dit but receiver is disabled\n", __func__, m_owner->tag(), 'A' + m_index); } #endif @@ -721,7 +732,7 @@ void z80sio_channel::rcv_complete() receive_register_extract(); data = get_received_char(); - LOG(("%s() \"%s \"Channel %c Received Data %02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, data)); + LOG("%s() \"%s \"Channel %c Received Data %02x\n", FUNCNAME, m_owner->tag(), 'A' + m_index, data); receive_data(data); } @@ -732,7 +743,7 @@ void z80sio_channel::rcv_complete() int z80sio_channel::get_clock_mode() { - //LOG(("%s %s\n",FUNCNAME, tag())); + //LOG("%s %s\n",FUNCNAME, tag()); int clocks = 1; switch (m_wr4 & WR4_CLOCK_RATE_MASK) @@ -759,7 +770,7 @@ CR5 = m_wr5 and SR1 = m_rr1 void z80sio_channel::set_rts(int state) { - LOG(("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index)); + LOG("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index); if (m_index == z80sio_device::CHANNEL_A) m_uart->m_out_rtsa_cb(state); else @@ -768,8 +779,8 @@ void z80sio_channel::set_rts(int state) void z80sio_channel::update_rts() { - // LOG(("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index)); - LOG(("%s() \"%s\" Channel %c \n", FUNCNAME, m_owner->tag(), 'A' + m_index)); + // LOG("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index); + LOG("%s() \"%s\" Channel %c \n", FUNCNAME, m_owner->tag(), 'A' + m_index); if (m_wr5 & WR5_RTS) { // when the RTS bit is set, the _RTS output goes low @@ -792,7 +803,7 @@ void z80sio_channel::update_rts() device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits() { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); switch (m_wr4 & WR4_STOP_BITS_MASK) { case WR4_STOP_BITS_1: return STOP_BITS_1; @@ -810,7 +821,7 @@ device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits() int z80sio_channel::get_rx_word_length() { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); int bits = 5; switch (m_wr3 & WR3_RX_WORD_LENGTH_MASK) @@ -831,7 +842,7 @@ int z80sio_channel::get_rx_word_length() int z80sio_channel::get_tx_word_length() { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); int bits = 5; switch (m_wr5 & WR5_TX_WORD_LENGTH_MASK) @@ -851,7 +862,7 @@ int z80sio_channel::get_tx_word_length() * Break/Abort latch. */ uint8_t z80sio_channel::do_sioreg_rr0() { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); return m_rr0; } /* @@ -859,7 +870,7 @@ uint8_t z80sio_channel::do_sioreg_rr0() * codes for the I-Field in the SDLC Receive Mode. */ uint8_t z80sio_channel::do_sioreg_rr1() { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); return m_rr1; } /* @@ -872,7 +883,7 @@ no interrupts are pending, the vector is modified with V3 = 0, V2 = 1, and V1 = 1. This register is read only through Channel B. */ uint8_t z80sio_channel::do_sioreg_rr2() { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); // channel B only return m_index == z80sio_device::CHANNEL_B ? m_rr2 : 0; } @@ -887,7 +898,7 @@ uint8_t z80sio_channel::control_read() uint8_t data = 0; uint8_t reg = m_wr0 & WR0_REGISTER_MASK; - //LOG(("%s %s\n",FUNCNAME, tag())); + //LOG("%s %s\n",FUNCNAME, tag()); if (reg != 0) { // mask out register index @@ -901,7 +912,7 @@ uint8_t z80sio_channel::control_read() case REG_RR2_INTERRUPT_VECT: data = do_sioreg_rr2(); break; default: logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); - LOG(("%s %s unsupported register:%02x\n",FUNCNAME, tag(), reg)); + LOG("%s %s unsupported register:%02x\n",FUNCNAME, tag(), reg); } return data; @@ -911,20 +922,20 @@ uint8_t z80sio_channel::control_read() Handle the WR0 CRC Reset/Init bits separatelly, needed by derived devices separatelly from the commands */ void z80sio_channel::do_sioreg_wr0_resets(uint8_t data) { - LOG(("%s %s\n",FUNCNAME, tag())); + LOG("%s %s\n",FUNCNAME, tag()); switch (data & WR0_CRC_RESET_CODE_MASK) { case WR0_CRC_RESET_NULL: - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", m_owner->tag(), 'A' + m_index); break; case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */ - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", m_owner->tag(), 'A' + m_index); break; case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */ - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", m_owner->tag(), 'A' + m_index); break; case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the SRO register) */ - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", m_owner->tag(), 'A' + m_index); break; default: /* Will not happen unless someone messes with the mask */ logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK); @@ -937,7 +948,7 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data) switch (data & WR0_COMMAND_MASK) { case WR0_NULL: - LOG(("Z80SIO \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index); break; case WR0_RESET_EXT_STATUS: // reset external/status interrupt @@ -949,35 +960,35 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data) if (m_sync) m_rr0 |= RR0_SYNC_HUNT; if (m_cts) m_rr0 |= RR0_CTS; - LOG(("Z80SIO \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index); break; case WR0_CHANNEL_RESET: // channel reset - LOG(("Z80SIO \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index); device_reset(); break; case WR0_ENABLE_INT_NEXT_RX: // enable interrupt on next receive character - LOG(("Z80SIO \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index); m_rx_first = 1; break; case WR0_RESET_TX_INT: // reset transmitter interrupt pending - LOG(("Z80SIO \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index); logerror("Z80SIO \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index); break; case WR0_ERROR_RESET: // error reset - LOG(("Z80SIO \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index); m_rr1 &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR); break; case WR0_RETURN_FROM_INT: // return from interrupt - LOG(("Z80SIO \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index); m_uart->z80daisy_irq_reti(); break; default: - LOG(("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK)); + LOG("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK); } do_sioreg_wr0_resets(data); @@ -987,29 +998,29 @@ void z80sio_channel::do_sioreg_wr1(uint8_t data) { /* TODO: implement vector modifications when WR1 bit D2 is changed */ m_wr1 = data; - LOG(("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait")); - LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit")); + LOG("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait"); + LOG("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit"); switch (data & WR1_RX_INT_MODE_MASK) { case WR1_RX_INT_DISABLE: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index); break; case WR1_RX_INT_FIRST: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index); break; case WR1_RX_INT_ALL_PARITY: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index); break; case WR1_RX_INT_ALL: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index)); + LOG("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index); break; } } @@ -1025,45 +1036,45 @@ void z80sio_channel::do_sioreg_wr2(uint8_t data) m_rr2 = m_wr2; } m_uart->check_interrupts(); - LOG(("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data)); + LOG("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data); } void z80sio_channel::do_sioreg_wr3(uint8_t data) { m_wr3 = data; - LOG(("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length())); + LOG("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length()); } void z80sio_channel::do_sioreg_wr4(uint8_t data) { m_wr4 = data; - LOG(("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd")); - LOG(("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits()))); - LOG(("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode())); + LOG("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd"); + LOG("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits())); + LOG("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode()); } void z80sio_channel::do_sioreg_wr5(uint8_t data) { m_wr5 = data; - LOG(("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length())); - LOG(("Z80SIO \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0)); + LOG("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length()); + LOG("Z80SIO \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0); + LOG("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0); } void z80sio_channel::do_sioreg_wr6(uint8_t data) { - LOG(("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data)); + LOG("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data); m_sync = (m_sync & 0xff00) | data; } void z80sio_channel::do_sioreg_wr7(uint8_t data) { - LOG(("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data)); + LOG("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data); m_sync = (data << 8) | (m_sync & 0xff); } @@ -1076,12 +1087,12 @@ void z80sio_channel::control_write(uint8_t data) if (reg != 0) { - LOGSETUP((" * %s %c Reg %02x <- %02x \n", m_owner->tag(), 'A' + m_index, reg, data)); + LOGSETUP(" * %s %c Reg %02x <- %02x \n", m_owner->tag(), 'A' + m_index, reg, data); // mask out register index m_wr0 &= ~WR0_REGISTER_MASK; } - LOG(("\n%s(%02x) reg %02x\n", FUNCNAME, data, reg)); + LOG("\n%s(%02x) reg %02x\n", FUNCNAME, data, reg); switch (reg) { @@ -1124,7 +1135,7 @@ uint8_t z80sio_channel::data_read() } } - LOG(("Z80SIO \"%s\" Channel %c : Data Register Read '%02x'\n", m_owner->tag(), 'A' + m_index, data)); + LOG("Z80SIO \"%s\" Channel %c : Data Register Read '%02x'\n", m_owner->tag(), 'A' + m_index, data); return data; } @@ -1139,7 +1150,7 @@ void z80sio_channel::data_write(uint8_t data) if ((m_wr5 & WR5_TX_ENABLE) && is_transmit_register_empty()) { - LOG(("Z80SIO \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data)); + LOG("Z80SIO \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data); transmit_register_setup(m_tx_data); @@ -1151,7 +1162,7 @@ void z80sio_channel::data_write(uint8_t data) } else { - LOG((" Transmitter %s, data byte dropped\n", m_wr5 & WR5_TX_ENABLE ? "not enabled" : "not emptied")); + LOG(" Transmitter %s, data byte dropped\n", m_wr5 & WR5_TX_ENABLE ? "not enabled" : "not emptied"); m_rr0 &= ~RR0_TX_BUFFER_EMPTY; } @@ -1164,11 +1175,11 @@ void z80sio_channel::data_write(uint8_t data) //------------------------------------------------- void z80sio_channel::receive_data(uint8_t data) { - LOG(("%s(%02x) %s:%c\n",FUNCNAME, data, tag(), 'A' + m_index)); + LOG("%s(%02x) %s:%c\n",FUNCNAME, data, tag(), 'A' + m_index); if (m_rx_fifo == 2) { - LOG((" Overrun detected\n")); + LOG(" Overrun detected\n"); // receive overrun error detected m_rx_error |= RR1_RX_OVERRUN_ERROR; @@ -1214,7 +1225,7 @@ void z80sio_channel::receive_data(uint8_t data) m_uart->trigger_interrupt(m_index, INT_RECEIVE); break; default: - LOG(("No interrupt triggered\n")); + LOG("No interrupt triggered\n"); } } @@ -1226,7 +1237,7 @@ void z80sio_channel::receive_data(uint8_t data) WRITE_LINE_MEMBER( z80sio_channel::cts_w ) { - LOG(("%s(%02x) %s:%c\n",FUNCNAME, state, tag(), 'A' + m_index)); + LOG("%s(%02x) %s:%c\n",FUNCNAME, state, tag(), 'A' + m_index); if (m_cts != state) { @@ -1265,7 +1276,7 @@ WRITE_LINE_MEMBER( z80sio_channel::cts_w ) WRITE_LINE_MEMBER( z80sio_channel::dcd_w ) { - LOG(("Z80SIO \"%s\" Channel %c : DCD %u\n", m_owner->tag(), 'A' + m_index, state)); + LOG("Z80SIO \"%s\" Channel %c : DCD %u\n", m_owner->tag(), 'A' + m_index, state); if (m_dcd != state) { @@ -1303,7 +1314,7 @@ WRITE_LINE_MEMBER( z80sio_channel::dcd_w ) WRITE_LINE_MEMBER( z80sio_channel::sync_w ) { - LOG(("Z80SIO \"%s\" Channel %c : Sync %u\n", m_owner->tag(), 'A' + m_index, state)); + LOG("Z80SIO \"%s\" Channel %c : Sync %u\n", m_owner->tag(), 'A' + m_index, state); if (m_sh != state) { @@ -1336,7 +1347,7 @@ WRITE_LINE_MEMBER( z80sio_channel::sync_w ) WRITE_LINE_MEMBER( z80sio_channel::rxc_w ) { - //LOG(("Z80SIO \"%s\" Channel %c : Receiver Clock Pulse\n", m_owner->tag(), m_index + 'A')); + //LOG("Z80SIO \"%s\" Channel %c : Receiver Clock Pulse\n", m_owner->tag(), m_index + 'A'); int clocks = get_clock_mode(); if (clocks == 1) rx_clock_w(state); @@ -1358,7 +1369,7 @@ WRITE_LINE_MEMBER( z80sio_channel::rxc_w ) WRITE_LINE_MEMBER( z80sio_channel::txc_w ) { - //LOG(("Z80SIO \"%s\" Channel %c : Transmitter Clock Pulse\n", m_owner->tag(), m_index + 'A')); + //LOG("Z80SIO \"%s\" Channel %c : Transmitter Clock Pulse\n", m_owner->tag(), m_index + 'A'); int clocks = get_clock_mode(); if (clocks == 1) tx_clock_w(state); @@ -1383,10 +1394,11 @@ void z80sio_channel::update_serial() stop_bits_t stop_bits = get_stop_bits(); parity_t parity; - LOG(("Z80SIO update_serial\n")); + LOG("%s\n", FUNCNAME); if (m_wr4 & WR4_PARITY_ENABLE) { + LOG("- Parity enabled\n"); if (m_wr4 & WR4_PARITY_EVEN) parity = PARITY_EVEN; else @@ -1401,11 +1413,13 @@ void z80sio_channel::update_serial() if (m_rxc > 0) { + LOG("- RxC:%d/%d = %d\n", m_rxc, clocks, m_rxc / clocks); set_rcv_rate(m_rxc / clocks); } if (m_txc > 0) { + LOG("- TxC:%d/%d = %d\n", m_txc, clocks, m_txc / clocks); set_tra_rate(m_txc / clocks); } receive_register_reset(); // if stop bits is changed from 0, receive register has to be reset @@ -1418,7 +1432,7 @@ void z80sio_channel::update_serial() void z80sio_channel::set_dtr(int state) { - LOG(("%s(%d)\n", FUNCNAME, state)); + LOG("%s(%d)\n", FUNCNAME, state); m_dtr = state; if (m_index == z80sio_device::CHANNEL_A) diff --git a/src/mame/bus/vme/mzr8300.cpp b/src/mame/bus/vme/mzr8300.cpp index cadf5edc505..669f1579b28 100644 --- a/src/mame/bus/vme/mzr8300.cpp +++ b/src/mame/bus/vme/mzr8300.cpp @@ -52,11 +52,16 @@ void vme_mzr8300_card_device::device_start() LOG("%s %s\n", tag(), FUNCNAME); set_vme_p1_device(); - /* Setup r/w handlers for first SIO */ + /* Setup r/w handlers for first SIO in A16 */ uint32_t base = 0xFF0000; - m_vme_p1->install_device(base, base + 3, - read8_delegate(FUNC(z80sio_device::ba_cd_r), subdevice("sio0")), - write8_delegate(FUNC(z80sio_device::ba_cd_w), subdevice("sio0")), 0xffffffff); + m_vme_p1->install_device(base + 0, base + 1, // Channel B - Data + read8_delegate(FUNC(z80sio_device::db_r), subdevice("sio0")), write8_delegate(FUNC(z80sio_device::db_w), subdevice("sio0")), 0x00ff); + m_vme_p1->install_device(base + 2, base + 3, // Channel B - Control + read8_delegate(FUNC(z80sio_device::cb_r), subdevice("sio0")), write8_delegate(FUNC(z80sio_device::cb_w), subdevice("sio0")), 0x00ff); + m_vme_p1->install_device(base + 4, base + 5, // Channel A - Data + read8_delegate(FUNC(z80sio_device::da_r), subdevice("sio0")), write8_delegate(FUNC(z80sio_device::da_w), subdevice("sio0")), 0x00ff); + m_vme_p1->install_device(base + 6, base + 7, // Channel A - Control + read8_delegate(FUNC(z80sio_device::ca_r), subdevice("sio0")), write8_delegate(FUNC(z80sio_device::ca_w), subdevice("sio0")), 0x00ff); } void vme_mzr8300_card_device::device_reset() diff --git a/src/mame/includes/mzr8300.h b/src/mame/includes/mzr8300.h index 29a5014d3d6..1ae01af38c2 100644 --- a/src/mame/includes/mzr8300.h +++ b/src/mame/includes/mzr8300.h @@ -12,25 +12,24 @@ #include "emu.h" #include "bus/vme/vme.h" +#include "machine/z80sio.h" -class vme_p1_mzr8300_device : - public device_t, - public device_vme_p1_card_interface +class vme_p1_mzr8300_device : public device_t, public device_vme_p1_card_interface { public: - // construction/destruction - vme_p1_mzr8300_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - vme_p1_mzr8300_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source); + // construction/destruction + vme_p1_mzr8300_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + vme_p1_mzr8300_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source); - // optional information overrides - virtual machine_config_constructor device_mconfig_additions() const override; + // optional information overrides + virtual machine_config_constructor device_mconfig_additions() const override; - DECLARE_READ8_MEMBER(mzr8300_r); - DECLARE_WRITE8_MEMBER(mzr8300_w); protected: - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; +private: + required_device m_sio0; }; #endif // MZR8300_H diff --git a/src/mame/machine/mzr8300.cpp b/src/mame/machine/mzr8300.cpp index dc939f34dca..9d1541a05ee 100644 --- a/src/mame/machine/mzr8300.cpp +++ b/src/mame/machine/mzr8300.cpp @@ -83,27 +83,47 @@ #include "emu.h" #include "includes/mzr8300.h" #include "machine/z80sio.h" +#include "bus/rs232/rs232.h" #include "machine/clock.h" -#define VERBOSE 0 +#define LOG_GENERAL 0x01 +#define LOG_SETUP 0x02 +#define LOG_PRINTF 0x04 -#define LOGPRINT(...) do { if (VERBOSE) logerror(__VA_ARGS__); } while (0) -#define LOG(...) LOGPRINT(__VA_ARGS__) +#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL) -#if VERBOSE >= 2 +#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0) +#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0) + +#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__) +#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__) + +#if VERBOSE & LOG_PRINTF #define logerror printf #endif #ifdef _MSC_VER -#define LLFORMAT "%I64%" #define FUNCNAME __func__ #else -#define LLFORMAT "%lld" #define FUNCNAME __PRETTY_FUNCTION__ #endif +/* These values are borrowed just to get the terminal going and should be replaced + * once a proper serial board hardware (ie MZ 8300) is found and emulated. */ +#define BAUDGEN_CLOCK XTAL_19_6608MHz /* fake */ +#define SIO_CLOCK (BAUDGEN_CLOCK / 128) /* This will give prompt */ + MACHINE_CONFIG_FRAGMENT( mzr8300 ) - MCFG_Z80SIO_ADD("sio0", XTAL_4MHz, 0, 0, 0, 0 ) + MCFG_UPD7201_ADD("sio0", XTAL_4MHz, SIO_CLOCK, SIO_CLOCK, SIO_CLOCK, SIO_CLOCK ) + + MCFG_Z80SIO_OUT_TXDB_CB(DEVWRITELINE("rs232p1", rs232_port_device, write_txd)) + MCFG_Z80SIO_OUT_DTRB_CB(DEVWRITELINE("rs232p1", rs232_port_device, write_dtr)) + MCFG_Z80SIO_OUT_RTSB_CB(DEVWRITELINE("rs232p1", rs232_port_device, write_rts)) + + MCFG_RS232_PORT_ADD ("rs232p1", default_rs232_devices, "terminal") + MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("sio0", upd7201N_device, rxb_w)) + MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("sio0", upd7201N_device, ctsb_w)) + MCFG_Z80SIO_ADD("sio1", XTAL_4MHz, 0, 0, 0, 0 ) MACHINE_CONFIG_END @@ -115,14 +135,16 @@ machine_config_constructor vme_p1_mzr8300_device::device_mconfig_additions() con } vme_p1_mzr8300_device::vme_p1_mzr8300_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : - device_t(mconfig, VME_P1_MZR8300, "Mizar 8300 quad channel SIO board", tag, owner, clock, "vme_mzr8300", __FILE__) - ,device_vme_p1_card_interface(mconfig, *this) + device_t(mconfig, VME_P1_MZR8300, "Mizar 8300 quad channel SIO board", tag, owner, clock, "vme_mzr8300", __FILE__) + ,device_vme_p1_card_interface(mconfig, *this) + ,m_sio0(*this, "sio0") { } vme_p1_mzr8300_device::vme_p1_mzr8300_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) : - device_t(mconfig, type, name, tag, owner, clock, shortname, source) - ,device_vme_p1_card_interface(mconfig, *this) + device_t(mconfig, type, name, tag, owner, clock, shortname, source) + ,device_vme_p1_card_interface(mconfig, *this) + ,m_sio0(*this, "sio0") { } @@ -131,32 +153,6 @@ vme_p1_mzr8300_device::vme_p1_mzr8300_device(const machine_config &mconfig, devi //------------------------------------------------- void vme_p1_mzr8300_device::device_start() -{ - // uint32_t slotspace; - - // set_nubus_device makes m_slot valid - //set_vme_p1_device(); - - // slotspace = get_slotspace(); - - /* Setup r/w handlers for first SIO */ - // uint32_t base = 0xFF0000; - // m_vme_p1->install_device(base, base + 3, - // read8_delegate(FUNC(vme_p1_mzr8300_device::mzr8300_r), this), - // write8_delegate(FUNC(vme_p1_mzr8300_device::mzr8300_w), this), 0xffffffff); -// read8_delegate(FUNC(z80sio_device::ba_cd_r), subdevice("sio0")), -// write8_delegate(FUNC(z80sio_device::ba_cd_w), subdevice("sio0")), 0xffffffff); -// m_vme_p1->install_device(base + 3, base + 7, -// read8_delegate(FUNC(z80sio_device::ba_cd_r), subdevice("sio1")), -// write8_delegate(FUNC(z80sio_device::ba_cd_w), subdevice("sio1")), 0xffffffff); -} - -READ8_MEMBER(vme_p1_mzr8300_device::mzr8300_r) -{ - return 0; -} - -WRITE8_MEMBER(vme_p1_mzr8300_device::mzr8300_w) { }