apple3: fix 1 MHz mode (nw)

This commit is contained in:
arbee 2018-08-29 07:37:57 -04:00
parent 4e370c8a76
commit 9c0b75ca58

View File

@ -59,6 +59,10 @@
#define ENV_PRIMARYROM (0x02)
#define ENV_ROMENABLE (0x01)
// 14M / 14, but with every 65th cycle stretched which we cannot reasonably emulate
// 2 MHz mode probably has every 33rd cycle stretched but this is currently unproven.
static constexpr XTAL APPLE2_CLOCK(1'021'800);
READ8_MEMBER(apple3_state::apple3_c0xx_r)
{
uint8_t result = 0xFF;
@ -504,7 +508,7 @@ void apple3_state::apple3_update_memory()
logerror("apple3_update_memory(): via_0_b=0x%02x via_1_a=0x0x%02x\n", m_via_0_b, m_via_1_a);
}
m_maincpu->set_unscaled_clock(14.318181_MHz_XTAL / ((m_via_0_a & ENV_SLOWSPEED) ? 14 : 7));
m_maincpu->set_unscaled_clock(((m_via_0_a & ENV_SLOWSPEED) ? APPLE2_CLOCK : (14.318181_MHz_XTAL / 7)));
/* bank 2 (0100-01FF) */
if (!(m_via_0_a & ENV_STACK1XX))