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wtl3132: output callback (nw)
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2157278ff0
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@ -21,7 +21,7 @@
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#define LOG_IO (1U << 2)
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#define LOG_BYPASS (1U << 3)
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#define VERBOSE (LOG_GENERAL|LOG_REGS|LOG_IO|LOG_BYPASS)
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//#define VERBOSE (LOG_GENERAL|LOG_REGS|LOG_IO|LOG_BYPASS)
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#include "logmacro.h"
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ALLOW_SAVE_TYPE(float32_t);
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@ -36,6 +36,7 @@ wtl3132_device::wtl3132_device(machine_config const &mconfig, char const *tag, d
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, m_fpcn_cb(*this)
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, m_fpex_cb(*this)
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, m_zero_cb(*this)
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, m_port_x_cb(*this)
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{
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}
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@ -44,6 +45,7 @@ void wtl3132_device::device_start()
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m_fpcn_cb.resolve_safe();
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m_fpex_cb.resolve_safe();
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m_zero_cb.resolve_safe();
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m_port_x_cb.resolve_safe();
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save_item(NAME(m_fpcn_state));
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save_item(NAME(m_fpex_state));
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@ -286,7 +288,10 @@ void wtl3132_device::stage2(unsigned const index)
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// complete fstore
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if (OPF(code, IOCT) == 2)
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{
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m_x_port = m_x_out;
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// FIXME: work out what should happen when the X port is being
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// read/written in the same cycle
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//m_x_port = m_x_out;
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m_port_x_cb(m_x_out.v);
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LOGMASKED(LOG_IO, "slot %d stage 2 fstore %f\n", index, u2f(m_x_out.v));
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}
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}
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@ -17,6 +17,7 @@ public:
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auto out_fpcn() { return m_fpcn_cb.bind(); }
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auto out_fpex() { return m_fpex_cb.bind(); }
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auto out_zero() { return m_zero_cb.bind(); }
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auto out_port_x() { return m_port_x_cb.bind(); }
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// code and data ports
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void c_port_w(u64 data) { m_c_port = data; }
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@ -119,6 +120,7 @@ private:
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devcb_write_line m_fpcn_cb;
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devcb_write_line m_fpex_cb;
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devcb_write_line m_zero_cb;
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devcb_write32 m_port_x_cb;
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// output line state
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bool m_fpcn_state;
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