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tlcs900: Split derived types into separate files; no need for separate 8-bit and 16-bit maps now (nw)

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This commit is contained in:
AJR 2020-06-18 18:13:31 -04:00
parent 8d9c2d219d
commit 9c36794ded
10 changed files with 2366 additions and 2330 deletions
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4
scripts/src/cpu.lua
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@ -2570,6 +2570,10 @@ if (CPUS["TLCS900"]~=null) then
MAME_DIR .. "src/devices/cpu/tlcs900/tlcs900.cpp",
MAME_DIR .. "src/devices/cpu/tlcs900/tlcs900.h",
MAME_DIR .. "src/devices/cpu/tlcs900/900tbl.hxx",
MAME_DIR .. "src/devices/cpu/tlcs900/tmp95c061.cpp",
MAME_DIR .. "src/devices/cpu/tlcs900/tmp95c061.h",
MAME_DIR .. "src/devices/cpu/tlcs900/tmp95c063.cpp",
MAME_DIR .. "src/devices/cpu/tlcs900/tmp95c063.h",
}
end

2142
src/devices/cpu/tlcs900/tlcs900.cpp
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185
src/devices/cpu/tlcs900/tlcs900.h
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@ -40,10 +40,6 @@ enum
};
DECLARE_DEVICE_TYPE(TMP95C061, tmp95c061_device)
DECLARE_DEVICE_TYPE(TMP95C063, tmp95c063_device)
class tlcs900h_device : public cpu_device
{
public:
@ -610,185 +606,4 @@ protected:
void op_F0();
};
class tmp95c061_device : public tlcs900h_device
{
public:
// construction/destruction
tmp95c061_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// configuration helpers
auto port1_read() { return m_port1_read.bind(); }
auto port1_write() { return m_port1_write.bind(); }
auto port2_write() { return m_port2_write.bind(); }
auto port5_read() { return m_port5_read.bind(); }
auto port5_write() { return m_port5_write.bind(); }
auto port6_write() { return m_port6_write.bind(); }
auto port7_read() { return m_port7_read.bind(); }
auto port7_write() { return m_port7_write.bind(); }
auto port8_read() { return m_port8_read.bind(); }
auto port8_write() { return m_port8_write.bind(); }
auto port9_read() { return m_port9_read.bind(); }
auto porta_read() { return m_porta_read.bind(); }
auto porta_write() { return m_porta_write.bind(); }
auto portb_read() { return m_portb_read.bind(); }
auto portb_write() { return m_portb_write.bind(); }
uint8_t internal_r(offs_t offset);
void internal_w(offs_t offset, uint8_t data);
void tmp95c061_mem16(address_map &map);
void tmp95c061_mem8(address_map &map);
protected:
virtual void device_config_complete() override;
virtual void device_start() override;
virtual void device_reset() override;
virtual void execute_set_input(int inputnum, int state) override;
virtual void tlcs900_check_hdma() override;
virtual void tlcs900_check_irqs() override;
virtual void tlcs900_handle_ad() override;
virtual void tlcs900_handle_timers() override;
void tlcs900_change_tff( int which, int change );
int tlcs900_process_hdma( int channel );
void update_porta();
private:
uint8_t m_to1;
uint8_t m_to3;
// Port 1: 8 bit I/O. Shared with D8-D15
devcb_read8 m_port1_read;
devcb_write8 m_port1_write;
// Port 2: 8 bit output only. Shared with A16-A23
devcb_write8 m_port2_write;
// Port 5: 4 bit I/O. Shared with HWR, BUSRQ, BUSAK, RW
devcb_read8 m_port5_read;
devcb_write8 m_port5_write;
// Port 6: 6 bit I/O. Shared with CS0, CS1, CS3/LCAS, RAS, REFOUT
devcb_read8 m_port6_read;
devcb_write8 m_port6_write;
// Port 7: 8 bit I/O. Shared with PG0-OUT, PG1-OUT
devcb_read8 m_port7_read;
devcb_write8 m_port7_write;
// Port 8: 6 bit I/O. Shared with TXD0, TXD1, RXD0, RXD1, CTS0, SCLK0, SCLK1
devcb_read8 m_port8_read;
devcb_write8 m_port8_write;
// Port 9: 4 bit input only. Shared with AN0-AN3
devcb_read8 m_port9_read;
// Port A: 4 bit I/O. Shared with WAIT, TI0, TO1, TO2
devcb_read8 m_porta_read;
devcb_write8 m_porta_write;
// Port B: 8 bit I/O. Shared with TI4/INT4, TI5/INT5, TI6/INT6, TI7/INT7, TO4, TO5, TO6
devcb_read8 m_portb_read;
devcb_write8 m_portb_write;
};
class tmp95c063_device : public tlcs900h_device
{
public:
// construction/destruction
tmp95c063_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
uint8_t internal_r(offs_t offset);
void internal_w(offs_t offset, uint8_t data);
// configuration helpers
auto port1_read() { return m_port1_read.bind(); }
auto port1_write() { return m_port1_write.bind(); }
auto port2_write() { return m_port2_write.bind(); }
auto port5_read() { return m_port5_read.bind(); }
auto port5_write() { return m_port5_write.bind(); }
auto port6_read() { return m_port6_read.bind(); }
auto port6_write() { return m_port6_write.bind(); }
auto port7_read() { return m_port7_read.bind(); }
auto port7_write() { return m_port7_write.bind(); }
auto port8_read() { return m_port8_read.bind(); }
auto port8_write() { return m_port8_write.bind(); }
auto port9_read() { return m_port9_read.bind(); }
auto port9_write() { return m_port9_write.bind(); }
auto porta_read() { return m_porta_read.bind(); }
auto porta_write() { return m_porta_write.bind(); }
auto portb_read() { return m_portb_read.bind(); }
auto portb_write() { return m_portb_write.bind(); }
auto portc_read() { return m_portc_read.bind(); }
auto portd_read() { return m_portd_read.bind(); }
auto portd_write() { return m_portd_write.bind(); }
auto porte_read() { return m_porte_read.bind(); }
auto porte_write() { return m_porte_write.bind(); }
template <size_t Bit> auto an_read() { return m_an_read[Bit].bind(); }
void tmp95c063_mem16(address_map &map);
void tmp95c063_mem8(address_map &map);
protected:
virtual void device_config_complete() override;
virtual void device_start() override;
virtual void device_reset() override;
virtual void execute_set_input(int inputnum, int state) override;
virtual void tlcs900_check_hdma() override;
virtual void tlcs900_check_irqs() override;
virtual void tlcs900_handle_ad() override;
virtual void tlcs900_handle_timers() override;
private:
// Port 1: 8 bit I/O. Shared with d8-d15
devcb_read8 m_port1_read;
devcb_write8 m_port1_write;
// Port 2: 8 bit output only. Shared with a16-a23
devcb_write8 m_port2_write;
// Port 5: 6 bit I/O
devcb_read8 m_port5_read;
devcb_write8 m_port5_write;
// Port 6: 8 bit I/O. Shared with cs1, cs3 & dram control
devcb_read8 m_port6_read;
devcb_write8 m_port6_write;
// Port 7: 8 bit I/O
devcb_read8 m_port7_read;
devcb_write8 m_port7_write;
// Port 8: 8 bit I/O. Shared with SCOUT, WAIT, NMI2, INT0-INT3
devcb_read8 m_port8_read;
devcb_write8 m_port8_write;
// Port 9: 8 bit I/O. Shared with clock input and output for the 8-bit timers
devcb_read8 m_port9_read;
devcb_write8 m_port9_write;
// Port A: 8 bit I/O. Shared with serial channels 0/1
devcb_read8 m_porta_read;
devcb_write8 m_porta_write;
// Port B: 8 bit I/O. Shared with 16bit timers
devcb_read8 m_portb_read;
devcb_write8 m_portb_write;
// Port C: 8 bit input only. Shared with analogue inputs
devcb_read8 m_portc_read;
// Port D: 5 bit I/O. Shared with int8_t
devcb_read8 m_portd_read;
devcb_write8 m_portd_write;
// Port E: 8 bit I/O.
devcb_read8 m_porte_read;
devcb_write8 m_porte_write;
// analogue inputs, sampled at 10 bits
devcb_read16::array<8> m_an_read;
};
#endif // MAME_CPU_TLCS900_TLCS900_H

1022
src/devices/cpu/tlcs900/tmp95c061.cpp Normal file
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96
src/devices/cpu/tlcs900/tmp95c061.h Normal file
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@ -0,0 +1,96 @@
// license:BSD-3-Clause
// copyright-holders:Wilbert Pol
#ifndef MAME_CPU_TLCS900_TMP95C061_H
#define MAME_CPU_TLCS900_TMP95C061_H
#pragma once
#include "tlcs900.h"
DECLARE_DEVICE_TYPE(TMP95C061, tmp95c061_device)
class tmp95c061_device : public tlcs900h_device
{
public:
// construction/destruction
tmp95c061_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// configuration helpers
auto port1_read() { return m_port1_read.bind(); }
auto port1_write() { return m_port1_write.bind(); }
auto port2_write() { return m_port2_write.bind(); }
auto port5_read() { return m_port5_read.bind(); }
auto port5_write() { return m_port5_write.bind(); }
auto port6_write() { return m_port6_write.bind(); }
auto port7_read() { return m_port7_read.bind(); }
auto port7_write() { return m_port7_write.bind(); }
auto port8_read() { return m_port8_read.bind(); }
auto port8_write() { return m_port8_write.bind(); }
auto port9_read() { return m_port9_read.bind(); }
auto porta_read() { return m_porta_read.bind(); }
auto porta_write() { return m_porta_write.bind(); }
auto portb_read() { return m_portb_read.bind(); }
auto portb_write() { return m_portb_write.bind(); }
protected:
virtual void device_config_complete() override;
virtual void device_start() override;
virtual void device_reset() override;
virtual void execute_set_input(int inputnum, int state) override;
virtual void tlcs900_check_hdma() override;
virtual void tlcs900_check_irqs() override;
virtual void tlcs900_handle_ad() override;
virtual void tlcs900_handle_timers() override;
void tlcs900_change_tff( int which, int change );
int tlcs900_process_hdma( int channel );
void update_porta();
private:
uint8_t internal_r(offs_t offset);
void internal_w(offs_t offset, uint8_t data);
void internal_mem(address_map &map);
uint8_t m_to1;
uint8_t m_to3;
// Port 1: 8 bit I/O. Shared with D8-D15
devcb_read8 m_port1_read;
devcb_write8 m_port1_write;
// Port 2: 8 bit output only. Shared with A16-A23
devcb_write8 m_port2_write;
// Port 5: 4 bit I/O. Shared with HWR, BUSRQ, BUSAK, RW
devcb_read8 m_port5_read;
devcb_write8 m_port5_write;
// Port 6: 6 bit I/O. Shared with CS0, CS1, CS3/LCAS, RAS, REFOUT
devcb_read8 m_port6_read;
devcb_write8 m_port6_write;
// Port 7: 8 bit I/O. Shared with PG0-OUT, PG1-OUT
devcb_read8 m_port7_read;
devcb_write8 m_port7_write;
// Port 8: 6 bit I/O. Shared with TXD0, TXD1, RXD0, RXD1, CTS0, SCLK0, SCLK1
devcb_read8 m_port8_read;
devcb_write8 m_port8_write;
// Port 9: 4 bit input only. Shared with AN0-AN3
devcb_read8 m_port9_read;
// Port A: 4 bit I/O. Shared with WAIT, TI0, TO1, TO2
devcb_read8 m_porta_read;
devcb_write8 m_porta_write;
// Port B: 8 bit I/O. Shared with TI4/INT4, TI5/INT5, TI6/INT6, TI7/INT7, TO4, TO5, TO6
devcb_read8 m_portb_read;
devcb_write8 m_portb_write;
};
#endif // MAME_CPU_TLCS900_TMP95C061_H

1129
src/devices/cpu/tlcs900/tmp95c063.cpp Normal file
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112
src/devices/cpu/tlcs900/tmp95c063.h Normal file
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@ -0,0 +1,112 @@
// license:BSD-3-Clause
// copyright-holders:Wilbert Pol
#ifndef MAME_CPU_TLCS900_TMP95C063_H
#define MAME_CPU_TLCS900_TMP95C063_H
#pragma once
#include "tlcs900.h"
DECLARE_DEVICE_TYPE(TMP95C063, tmp95c063_device)
class tmp95c063_device : public tlcs900h_device
{
public:
// construction/destruction
tmp95c063_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// configuration helpers
auto port1_read() { return m_port1_read.bind(); }
auto port1_write() { return m_port1_write.bind(); }
auto port2_write() { return m_port2_write.bind(); }
auto port5_read() { return m_port5_read.bind(); }
auto port5_write() { return m_port5_write.bind(); }
auto port6_read() { return m_port6_read.bind(); }
auto port6_write() { return m_port6_write.bind(); }
auto port7_read() { return m_port7_read.bind(); }
auto port7_write() { return m_port7_write.bind(); }
auto port8_read() { return m_port8_read.bind(); }
auto port8_write() { return m_port8_write.bind(); }
auto port9_read() { return m_port9_read.bind(); }
auto port9_write() { return m_port9_write.bind(); }
auto porta_read() { return m_porta_read.bind(); }
auto porta_write() { return m_porta_write.bind(); }
auto portb_read() { return m_portb_read.bind(); }
auto portb_write() { return m_portb_write.bind(); }
auto portc_read() { return m_portc_read.bind(); }
auto portd_read() { return m_portd_read.bind(); }
auto portd_write() { return m_portd_write.bind(); }
auto porte_read() { return m_porte_read.bind(); }
auto porte_write() { return m_porte_write.bind(); }
template <size_t Bit> auto an_read() { return m_an_read[Bit].bind(); }
protected:
virtual void device_config_complete() override;
virtual void device_start() override;
virtual void device_reset() override;
virtual void execute_set_input(int inputnum, int state) override;
virtual void tlcs900_check_hdma() override;
virtual void tlcs900_check_irqs() override;
virtual void tlcs900_handle_ad() override;
virtual void tlcs900_handle_timers() override;
private:
uint8_t internal_r(offs_t offset);
void internal_w(offs_t offset, uint8_t data);
void internal_mem(address_map &map);
// Port 1: 8 bit I/O. Shared with d8-d15
devcb_read8 m_port1_read;
devcb_write8 m_port1_write;
// Port 2: 8 bit output only. Shared with a16-a23
devcb_write8 m_port2_write;
// Port 5: 6 bit I/O
devcb_read8 m_port5_read;
devcb_write8 m_port5_write;
// Port 6: 8 bit I/O. Shared with cs1, cs3 & dram control
devcb_read8 m_port6_read;
devcb_write8 m_port6_write;
// Port 7: 8 bit I/O
devcb_read8 m_port7_read;
devcb_write8 m_port7_write;
// Port 8: 8 bit I/O. Shared with SCOUT, WAIT, NMI2, INT0-INT3
devcb_read8 m_port8_read;
devcb_write8 m_port8_write;
// Port 9: 8 bit I/O. Shared with clock input and output for the 8-bit timers
devcb_read8 m_port9_read;
devcb_write8 m_port9_write;
// Port A: 8 bit I/O. Shared with serial channels 0/1
devcb_read8 m_porta_read;
devcb_write8 m_porta_write;
// Port B: 8 bit I/O. Shared with 16bit timers
devcb_read8 m_portb_read;
devcb_write8 m_portb_write;
// Port C: 8 bit input only. Shared with analogue inputs
devcb_read8 m_portc_read;
// Port D: 5 bit I/O. Shared with int8_t
devcb_read8 m_portd_read;
devcb_write8 m_portd_write;
// Port E: 8 bit I/O.
devcb_read8 m_porte_read;
devcb_write8 m_porte_write;
// analogue inputs, sampled at 10 bits
devcb_read16::array<8> m_an_read;
};
#endif // MAME_CPU_TLCS900_TMP95C063_H

2
src/mame/drivers/ngp.cpp
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@ -100,7 +100,7 @@ the Neogeo Pocket.
#include "emu.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"
#include "cpu/tlcs900/tlcs900.h"
#include "cpu/tlcs900/tmp95c061.h"
#include "cpu/z80/z80.h"
#include "sound/t6w28.h"
#include "sound/dac.h"

2
src/mame/drivers/taitopjc.cpp
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@ -85,7 +85,7 @@
#include "emu.h"
#include "cpu/powerpc/ppc.h"
#include "cpu/tlcs900/tlcs900.h"
#include "cpu/tlcs900/tmp95c063.h"
#include "cpu/mn10200/mn10200.h"
#include "cpu/tms32051/tms32051.h"
#include "video/tc0780fpa.h"

2
src/mame/drivers/taitotz.cpp
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@ -175,7 +175,7 @@ Notes:
#include "bus/ata/ataintf.h"
#include "bus/ata/idehd.h"
#include "cpu/powerpc/ppc.h"
#include "cpu/tlcs900/tlcs900.h"
#include "cpu/tlcs900/tmp95c063.h"
#include "machine/nvram.h"
#include "video/poly.h"