Updated the PCI bus device so that PCI buses can be arranged in a tree like in real hardware [Samuele Zannoli]
Chihiro.c Improvements: [Samuele Zannoli] - Fixed the mapping of the bios at the top of the cpu addrsss space - Updated the ram size to 128 megabytes - Added some SMBus handling, to let the bios run - Added placeholders for a few devices on the PCI bus - Added the "jamdis StartAddress,Length" command to the debugger that lets you disassemble the "jam table" instructions used by the bios to do some basic hardware initialization. This time it works for good ;)
This commit is contained in:
Fabio Priuli
parent
4cc59054e0
commit
9c6f743089
@ -81,8 +81,13 @@ struct _pci_bus_state
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running_device * busdevice;
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const pci_bus_config * config;
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running_device * device[32];
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pci_bus_state * siblings[8];
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UINT8 siblings_busnum[8];
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int siblings_count;
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offs_t address;
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INT8 devicenum;
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INT8 devicenum; // device number we are addressing
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INT8 busnum; // pci bus number we are addressing
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pci_bus_state * busnumaddr; // pci bus we are addressing
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};
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@ -93,7 +98,7 @@ struct _pci_bus_state
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/*-------------------------------------------------
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get_safe_token - makes sure that the passed
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in device is, in fact, an IDE controller
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in device is, in fact, a PCI bus
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-------------------------------------------------*/
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INLINE pci_bus_state *get_safe_token(running_device *device)
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@ -123,12 +128,12 @@ READ32_DEVICE_HANDLER( pci_32le_r )
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case 1:
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if (pcibus->devicenum != -1)
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{
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pci_read_func read = pcibus->config->device[pcibus->devicenum].read_callback;
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pci_read_func read = pcibus->busnumaddr->config->device[pcibus->devicenum].read_callback;
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if (read != NULL)
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{
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function = (pcibus->address >> 8) & 0x07;
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reg = (pcibus->address >> 0) & 0xfc;
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result = (*read)(device, pcibus->device[pcibus->devicenum], function, reg, mem_mask);
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result = (*read)(pcibus->busnumaddr->busdevice, pcibus->busnumaddr->device[pcibus->devicenum], function, reg, mem_mask);
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}
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}
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break;
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@ -142,6 +147,26 @@ READ32_DEVICE_HANDLER( pci_32le_r )
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static pci_bus_state *pci_search_bustree(int busnum, int devicenum, pci_bus_state *pcibus)
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{
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int a;
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pci_bus_state *ret;
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if (pcibus->config->busnum == busnum)
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{
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return pcibus;
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}
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for (a = 0; a < pcibus->siblings_count; a++)
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{
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ret = pci_search_bustree(busnum, devicenum, pcibus->siblings[a]);
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if (ret != NULL)
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return ret;
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}
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return NULL;
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}
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WRITE32_DEVICE_HANDLER( pci_32le_w )
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{
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pci_bus_state *pcibus = get_safe_token(device);
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@ -161,20 +186,31 @@ WRITE32_DEVICE_HANDLER( pci_32le_w )
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{
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int busnum = (pcibus->address >> 16) & 0xff;
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int devicenum = (pcibus->address >> 11) & 0x1f;
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pcibus->devicenum = (busnum == pcibus->config->busnum) ? devicenum : -1;
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pcibus->busnumaddr = pci_search_bustree(busnum, devicenum, pcibus);
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if (pcibus->busnumaddr != NULL)
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{
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pcibus->busnum = busnum;
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pcibus->devicenum = devicenum;
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}
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else
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pcibus->devicenum = -1;
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if (LOG_PCI)
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logerror(" bus:%d device:%d\n", busnum, devicenum);
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}
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break;
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case 1:
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if (pcibus->devicenum != -1)
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{
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pci_write_func write = pcibus->config->device[pcibus->devicenum].write_callback;
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pci_write_func write = pcibus->busnumaddr->config->device[pcibus->devicenum].write_callback;
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if (write != NULL)
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{
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int function = (pcibus->address >> 8) & 0x07;
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int reg = (pcibus->address >> 0) & 0xfc;
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(*write)(device, pcibus->device[pcibus->devicenum], function, reg, data, mem_mask);
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(*write)(pcibus->busnumaddr->busdevice, pcibus->busnumaddr->device[pcibus->devicenum], function, reg, data, mem_mask);
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}
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if (LOG_PCI)
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logerror(" function:%d register:%d\n", (pcibus->address >> 8) & 0x07, (pcibus->address >> 0) & 0xfc);
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}
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break;
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}
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@ -186,13 +222,42 @@ READ64_DEVICE_HANDLER(pci_64be_r) { return read64be_with_32le_device_handler(pci
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WRITE64_DEVICE_HANDLER(pci_64be_w) { write64be_with_32le_device_handler(pci_32le_w, device, offset, data, mem_mask); }
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int pci_add_sibling( running_machine *machine, char *pcitag, char *sibling )
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{
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running_device *device1 = machine->device(pcitag);
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running_device *device2 = machine->device(sibling);
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pci_bus_state *pcibus1 = get_safe_token(device1);
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pci_bus_state *pcibus2 = get_safe_token(device2);
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pci_bus_config *config2;
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if ((device1 == NULL) || (device2 == NULL) || (pcibus1 == NULL) || (pcibus2 == NULL))
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return 0;
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if (pcibus1->siblings_count == 8)
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return 0;
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config2 = (pci_bus_config *)downcast<const legacy_device_config_base &>(device2->baseconfig()).inline_config();
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pcibus1->siblings[pcibus1->siblings_count] = get_safe_token(device2);
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pcibus1->siblings_busnum[pcibus1->siblings_count] = config2->busnum;
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pcibus1->siblings_count++;
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return 1;
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}
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/***************************************************************************
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DEVICE INTERFACE
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***************************************************************************/
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static STATE_POSTLOAD( pci_bus_postload )
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{
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pci_bus_state *pcibus = (pci_bus_state *)param;
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if (pcibus->devicenum != -1)
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{
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pcibus->busnumaddr = pci_search_bustree(pcibus->busnum, pcibus->devicenum, pcibus);
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}
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}
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/*-------------------------------------------------
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device start callback
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-------------------------------------------------*/
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@ -219,9 +284,15 @@ static DEVICE_START( pci_bus )
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if (pcibus->config->device[devicenum].devtag != NULL)
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pcibus->device[devicenum] = device->machine->device(pcibus->config->device[devicenum].devtag);
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if (pcibus->config->father != NULL)
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pci_add_sibling(device->machine, (char *)pcibus->config->father, (char *)device->tag());
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/* register pci states */
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state_save_register_device_item(device, 0, pcibus->address);
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state_save_register_device_item(device, 0, pcibus->devicenum);
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state_save_register_device_item(device, 0, pcibus->busnum);
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state_save_register_postload(device->machine, pci_bus_postload, pcibus);
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}
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@ -32,6 +32,7 @@ struct _pci_bus_config
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{
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UINT8 busnum;
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pci_device_entry device[32];
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const char * father;
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};
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@ -49,6 +50,8 @@ struct _pci_bus_config
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MDRV_DEVICE_CONFIG_DATAPTR_ARRAY_MEMBER(pci_bus_config, device, _devnum, pci_device_entry, read_callback, _configread) \
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MDRV_DEVICE_CONFIG_DATAPTR_ARRAY_MEMBER(pci_bus_config, device, _devnum, pci_device_entry, write_callback, _configwrite)
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#define MDRV_PCI_BUS_SIBLING(_father_tag) \
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MDRV_DEVICE_CONFIG_DATAPTR(pci_bus_config, father, _father_tag)
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/***************************************************************************
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@ -61,6 +64,7 @@ WRITE32_DEVICE_HANDLER( pci_32le_w );
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READ64_DEVICE_HANDLER( pci_64be_r );
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WRITE64_DEVICE_HANDLER( pci_64be_w );
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int pci_add_sibling( running_machine *machine, char *pcitag, char *sibling );
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/* ----- device interface ----- */
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@ -36,20 +36,135 @@ Thanks to Alex, Mr Mudkips, and Philip Burke for this info.
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#include "emu.h"
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#include "cpu/i386/i386.h"
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#include "machine/pci.h"
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#include "includes/naomibd.h"
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#include "debug/debugcon.h"
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#include "debug/debugcmd.h"
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static VIDEO_START(chihiro)
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/* jamtable instructions for Chihiro
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St. Instr. Comment
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0x01 POKEPCI PCICONF[OP2] := OP1
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0x02 OUTB PORT[OP2] := OP1
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0x03 POKE MEM[OP2] := OP1
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0x04 BNE IF ACC <> OP2 THEN PC := PC + OP1
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0x05 PEEKPCI ACC := PCICONF[OP2]
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0x06 AND/OR ACC := (ACC & OP2) | OP1
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0x07 BRA PC := PC + OP1
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0x08 INB ACC := PORT[OP2]
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0x09 PEEK ACC := MEM[OP2]
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0xE1 (prefix) execute the instruction code in OP2 with OP2 := OP1, OP1 := ACC
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0xEE END
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*/
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/* jamtable disassembler */
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static void jamtable_disasm(running_machine *machine, address_space *space,UINT32 address,UINT32 size) // 0xff000080 == fff00080
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{
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UINT32 base,addr;
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UINT32 opcode,op1,op2;
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char sop1[16];
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char sop2[16];
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char pcrel[16];
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int prefix;
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addr=address;
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while (1)
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{
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base=addr;
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opcode=space->read_byte(addr);
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addr++;
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op1=space->read_dword(addr);
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addr+=4;
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op2=space->read_dword(addr);
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addr+=4;
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if (opcode == 0xe1)
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{
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opcode=op2 & 255;
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op2=op1;
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//op1=edi;
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sprintf(sop2,"%08X",op2);
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sprintf(sop1,"ACC");
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sprintf(pcrel,"PC+ACC");
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prefix=1;
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}
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else
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{
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sprintf(sop2,"%08X",op2);
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sprintf(sop1,"%08X",op1);
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sprintf(pcrel,"%08X",base+9+op1);
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prefix=0;
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}
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debug_console_printf(machine,"%08X ",base);
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// dl=instr ebx=par1 eax=par2
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switch (opcode)
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{
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case 0x01:
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// if ((op2 & 0xff) == 0x880) op1=op1 & 0xfffffffd
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// out cf8,op2
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// out cfc,op1
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// out cf8,0
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// cf8 (CONFIG_ADDRESS) format:
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// 31 30 24 23 16 15 11 10 8 7 2 1 0
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// +-+----------+------------+---------------+-----------------+-----------------+-+-+
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// | | Reserved | Bus Number | Device Number | Function Number | Register Number |0|0|
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// +-+----------+------------+---------------+-----------------+-----------------+-+-+
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// 31 - Enable bit
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debug_console_printf(machine,"POKEPCI PCICONF[%s]=%s\n",sop2,sop1);
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break;
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case 0x02:
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debug_console_printf(machine,"OUTB PORT[%s]=%s\n",sop2,sop1);
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break;
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case 0x03:
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debug_console_printf(machine,"POKE MEM[%s]=%s\n",sop2,sop1);
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break;
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case 0x04:
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debug_console_printf(machine,"BNE IF ACC != %s THEN PC=%s\n",sop2,pcrel);
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break;
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case 0x05:
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// out cf8,op2
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// in acc,cfc
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debug_console_printf(machine,"PEEKPCI ACC=PCICONF[%s]\n",sop2);
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break;
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case 0x06:
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debug_console_printf(machine,"AND/OR ACC=(ACC & %s) | %s\n",sop2,sop1);
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break;
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case 0x07:
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debug_console_printf(machine,"BRA PC=%s\n",pcrel);
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break;
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case 0x08:
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debug_console_printf(machine,"INB ACC=PORT[%s]\n",sop2);
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break;
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case 0x09:
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debug_console_printf(machine,"PEEK ACC=MEM[%s]\n",sop2);
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break;
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case 0xee:
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debug_console_printf(machine,"END\n");
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break;
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default:
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debug_console_printf(machine,"NOP ????\n");
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break;
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}
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if (opcode == 0xee)
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break;
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if (size <= 9)
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break;
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size-=9;
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}
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}
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static VIDEO_UPDATE(chihiro)
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void jamtable_disasm_command(running_machine *machine, int ref, int params, const char **param)
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{
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address_space *space=machine->firstcpu->space();
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UINT64 addr,size;
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return 0;
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if (params < 2)
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return;
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if (!debug_command_parameter_number(machine, param[0], &addr))
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return;
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if (!debug_command_parameter_number(machine, param[1], &size))
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return;
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jamtable_disasm(machine, space, (UINT32)addr, (UINT32)size);
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}
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/*
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St. Instr. Comment
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0x02 PEEK ACC := MEM[OP1]
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@ -65,32 +180,139 @@ St. Instr. Comment
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0x12 INB ACC := PORT(OP1)
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0xEE END
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*/
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#ifdef UNUSED_FUNCTION
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static READ32_HANDLER( chihiro_jamtable )
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{
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return 0xEEEEEEEE;
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}
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#endif
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static UINT32 dummy_pci_r(running_device *busdevice, running_device *device, int function, int reg, UINT32 mem_mask)
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{
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logerror(" bus:%d function:%d register:%d mask:%08X\n",((pci_bus_config *)downcast<const legacy_device_config_base &>(busdevice->baseconfig()).inline_config())->busnum,function,reg,mem_mask);
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return 0;
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}
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static void dummy_pci_w(running_device *busdevice, running_device *device, int function, int reg, UINT32 data, UINT32 mem_mask)
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{
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logerror(" bus:%d function:%d register:%d data:%08X mask:%08X\n",((pci_bus_config *)downcast<const legacy_device_config_base &>(busdevice->baseconfig()).inline_config())->busnum,function,reg,data,mem_mask);
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}
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static READ32_HANDLER( dummy_r )
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{
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return 0;
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}
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static WRITE32_HANDLER( dummy_w )
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{
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}
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int smbus_cx25871(int command,int rw,int data)
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{
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logerror("cx25871: %d %d %d\n",command,rw,data);
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return 0;
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}
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typedef struct _smbus_state {
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int status;
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int control;
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int address;
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int data;
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int command;
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int rw;
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int (*devices[128])(int command,int rw,int data);
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UINT32 words[256/4];
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} smbus_state;
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smbus_state smbusst;
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void smbus_register_device(int address,int (*handler)(int command,int rw,int data))
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{
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if (address < 128)
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smbusst.devices[address]=handler;
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}
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static READ32_HANDLER( smbus_r )
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{
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if ((offset == 0) && (mem_mask == 0xff)) // 0 smbus status
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smbusst.words[offset] = (smbusst.words[offset] & ~mem_mask) | (smbusst.status << 0);
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if ((offset == 1) && (mem_mask == 0xff0000)) // 6 smbus data
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smbusst.words[offset] = (smbusst.words[offset] & ~mem_mask) | (smbusst.data << 16);
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return smbusst.words[offset];
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}
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static WRITE32_HANDLER( smbus_w )
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{
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COMBINE_DATA(smbusst.words);
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if ((offset == 0) && (mem_mask == 0xff)) // 0 smbus status
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smbusst.status &= ~data;
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if ((offset == 0) && (mem_mask == 0xff0000)) // 2 smbus control
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{
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data=data>>16;
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smbusst.control = data;
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if ((smbusst.control & 6) == 2)
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{
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if (smbusst.devices[smbusst.address & 127])
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if (smbusst.rw == 0)
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smbusst.devices[smbusst.address & 127](smbusst.command,smbusst.rw,smbusst.data);
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else
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smbusst.data=smbusst.devices[smbusst.address & 127](smbusst.command,smbusst.rw,smbusst.data);
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smbusst.status |= 0x10;
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}
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}
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if ((offset == 1) && (mem_mask == 0xff)) // 4 smbus address
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{
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smbusst.address = data >> 1;
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smbusst.rw = data & 1;
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}
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if ((offset == 1) && (mem_mask == 0xff0000)) // 6 smbus data
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{
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data=data>>16;
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smbusst.data = data;
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}
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if ((offset == 2) && (mem_mask == 0xff)) // 8 smbus command
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smbusst.command = data;
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}
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static ADDRESS_MAP_START( xbox_map, ADDRESS_SPACE_PROGRAM, 32 )
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AM_RANGE(0x00000000, 0x004fffff) AM_RAM
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AM_RANGE(0x07fd0000, 0x07feffff) AM_RAM // a table of some sort?
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AM_RANGE(0x00000000, 0x07ffffff) AM_RAM
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AM_RANGE(0xff000000, 0xffffffff) AM_ROM AM_REGION("bios", 0) AM_MIRROR(0x00f80000)
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ADDRESS_MAP_END
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|
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AM_RANGE(0xff000080, 0xff000083) AM_READ( chihiro_jamtable )
|
||||
AM_RANGE(0xfff00000, 0xfff7ffff) AM_ROM AM_SHARE("biosflash")
|
||||
AM_RANGE(0xfff80000, 0xffffffff) AM_ROM AM_REGION("bios", 0) AM_SHARE("biosflash")
|
||||
static ADDRESS_MAP_START(xbox_map_io, ADDRESS_SPACE_IO, 32)
|
||||
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_32le_r, pci_32le_w)
|
||||
AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
|
||||
AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static INPUT_PORTS_START( chihiro )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static MACHINE_START( chihiro )
|
||||
{
|
||||
smbus_register_device(0x45,smbus_cx25871);
|
||||
debug_console_register_command(machine,"jamdis",CMDFLAG_NONE,0,2,3,jamtable_disasm_command);
|
||||
}
|
||||
|
||||
static MACHINE_DRIVER_START( chihiro_base )
|
||||
|
||||
/* basic machine hardware */
|
||||
MDRV_CPU_ADD("maincpu", PENTIUM, 733333333) /* Wrong! */
|
||||
MDRV_CPU_PROGRAM_MAP(xbox_map)
|
||||
MDRV_CPU_IO_MAP(xbox_map_io)
|
||||
|
||||
MDRV_QUANTUM_TIME(HZ(6000))
|
||||
|
||||
MDRV_PCI_BUS_ADD("pcibus", 0)
|
||||
MDRV_PCI_BUS_DEVICE(0, "PCI Bridge Device - Host Bridge", dummy_pci_r, dummy_pci_w)
|
||||
MDRV_PCI_BUS_DEVICE(1, "HUB Interface - ISA Bridge", dummy_pci_r, dummy_pci_w)
|
||||
MDRV_PCI_BUS_DEVICE(2, "OHCI USB Controller 1", dummy_pci_r, dummy_pci_w)
|
||||
MDRV_PCI_BUS_DEVICE(3, "OHCI USB Controller 2", dummy_pci_r, dummy_pci_w)
|
||||
MDRV_PCI_BUS_DEVICE(30, "AGP Host to PCI Bridge", dummy_pci_r, dummy_pci_w)
|
||||
MDRV_PCI_BUS_ADD("agpbus", 1)
|
||||
MDRV_PCI_BUS_SIBLING("pcibus")
|
||||
MDRV_PCI_BUS_DEVICE(0, "NV2A GeForce 3MX Integrated GPU/Northbridge", dummy_pci_r, dummy_pci_w)
|
||||
|
||||
/* video hardware */
|
||||
MDRV_SCREEN_ADD("screen", RASTER)
|
||||
MDRV_SCREEN_REFRESH_RATE(60)
|
||||
@ -98,10 +320,9 @@ static MACHINE_DRIVER_START( chihiro_base )
|
||||
MDRV_SCREEN_SIZE(640, 480)
|
||||
MDRV_SCREEN_VISIBLE_AREA(0, 639, 0, 479)
|
||||
|
||||
MDRV_PALETTE_LENGTH(65536)
|
||||
MDRV_MACHINE_START(chihiro)
|
||||
|
||||
MDRV_VIDEO_START(chihiro)
|
||||
MDRV_VIDEO_UPDATE(chihiro)
|
||||
MDRV_PALETTE_LENGTH(65536)
|
||||
MACHINE_DRIVER_END
|
||||
|
||||
static MACHINE_DRIVER_START( chihirogd )
|
||||
@ -116,7 +337,7 @@ MACHINE_DRIVER_END
|
||||
ROMX_LOAD(name, offset, length, hash, ROM_BIOS(bios+1)) /* Note '+1' */
|
||||
|
||||
#define CHIHIRO_BIOS \
|
||||
ROM_REGION( 0x200000, "bios", 0) \
|
||||
ROM_REGION( 0x1000000, "bios", 0) \
|
||||
ROM_SYSTEM_BIOS( 0, "bios0", "Chihiro Bios" ) \
|
||||
ROM_LOAD_BIOS( 0, "chihiro_xbox_bios.bin", 0x000000, 0x80000, CRC(66232714) SHA1(b700b0041af8f84835e45d1d1250247bf7077188) ) \
|
||||
ROM_REGION( 0x200000, "others", 0) \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user