mirror of
https://github.com/holub/mame
synced 2025-05-21 21:29:15 +03:00
Various fixes to California Chase, it currently completes the POST [Grull Osgo]
This commit is contained in:
Angelo Salese
parent
cc7de68060
commit
9c7cd89eda
@ -82,6 +82,36 @@ be easily copied. Tested with another HDD.... formatted with DOS, copied
|
||||
all files across to new HDD, boots up fine.
|
||||
|
||||
************************************************************************************/
|
||||
/*
|
||||
Grull Osgo - Improvements
|
||||
|
||||
-Changes about BIOS memory management so ROM Shadow now works properly.
|
||||
The changes are:
|
||||
Rom Memory Map remmapped to 128K size AM_RANGE(0xfffe0000, 0xffffffff) AM_ROM AM_REGION("bios", 0)
|
||||
|
||||
-Changes in mtxc write handler and bios_ram write handler. Now The internal register access are
|
||||
compatible with chipset VIA.
|
||||
(this motherboard has VIA Apollo VXPro chipset. It is not compatible with Intel i430).
|
||||
With this changes now BIOS Shadow ram works fine, BIOS can relocate and decompress the full code
|
||||
necesary to run the Extended Bios, POST and Boot). No more BIOS Checksum error.
|
||||
|
||||
- Suppressed all video related items wich will be replaced with VGA driver.
|
||||
|
||||
- Temporarily added a VGA driver that is working based on original IBM VGA BIOS.(From MESS)
|
||||
(This VGA driver doesn't work yet with TRIDENT VGA BIOS as I can see).
|
||||
|
||||
- Added the flag READONLY to the calchase imagen rom load function, to avoid
|
||||
"DIFF CHD ERROR".
|
||||
|
||||
- Minor changes and NOPS into address maps for debugging purposes.
|
||||
|
||||
- Now Bios is looking for the disk (BIOS Auto detection). It seems all works fine but must be there
|
||||
something wrong in the disk geometry reported by calchase.chd (20,255,63) since BIOS does not accept
|
||||
255 heads as parameter. Perhaps a bad dump?
|
||||
|
||||
TODO: A lot of work to do yet!!!
|
||||
*/
|
||||
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/i386/i386.h"
|
||||
@ -96,7 +126,8 @@ all files across to new HDD, boots up fine.
|
||||
#include "machine/8042kbdc.h"
|
||||
#include "machine/pckeybrd.h"
|
||||
#include "machine/idectrl.h"
|
||||
#include "video/pc_vga.h"
|
||||
#include "video/pc_vga.h" //GRULL-ADDVGA
|
||||
|
||||
|
||||
|
||||
class calchase_state : public driver_device
|
||||
@ -106,6 +137,7 @@ public:
|
||||
: driver_device(mconfig, type, tag) { }
|
||||
|
||||
UINT32 *m_bios_ram;
|
||||
//UINT32 *m_vga_vram; //GRULL-ADDVGA
|
||||
int m_dma_channel;
|
||||
UINT8 m_dma_offset[2][4];
|
||||
UINT8 m_at_pages[0x10];
|
||||
@ -122,6 +154,46 @@ public:
|
||||
|
||||
static void ide_interrupt(device_t *device, int state);
|
||||
|
||||
/*GRULL-ADDVGA
|
||||
static VIDEO_START(calchase)
|
||||
{
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
/*GRULL-ADDVGA
|
||||
static SCREEN_UPDATE(calchase)
|
||||
{
|
||||
calchase_state *state = screen->machine().driver_data<calchase_state>();
|
||||
int x,y,count,i;
|
||||
|
||||
bitmap_fill(bitmap,cliprect,get_black_pen(screen->machine()));
|
||||
|
||||
count = (0);
|
||||
|
||||
for(y=0;y<256;y++)
|
||||
{
|
||||
for(x=0;x<320;x+=32)
|
||||
{
|
||||
for (i=0;i<32;i++)
|
||||
{
|
||||
UINT32 color;
|
||||
|
||||
color = (state->m_vga_vram[count])>>(32-i) & 0x1;
|
||||
|
||||
if((x+i)<screen->visible_area().max_x && ((y)+0)<screen->visible_area().max_y)
|
||||
*BITMAP_ADDR32(bitmap, y, x+(32-i)) = screen->machine().pens[color];
|
||||
|
||||
}
|
||||
|
||||
count++;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
*/
|
||||
|
||||
static READ8_DEVICE_HANDLER(at_dma8237_2_r)
|
||||
{
|
||||
return i8237_r(device, offset / 2);
|
||||
@ -271,6 +343,10 @@ static WRITE32_DEVICE_HANDLER( ide_w )
|
||||
ide_controller32_w(device, 0x1f0/4 + offset, data, mem_mask);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static READ32_DEVICE_HANDLER( fdc_r )
|
||||
{
|
||||
return ide_controller32_r(device, 0x3f0/4 + offset, mem_mask);
|
||||
@ -282,7 +358,9 @@ static WRITE32_DEVICE_HANDLER( fdc_w )
|
||||
ide_controller32_w(device, 0x3f0/4 + offset, data, mem_mask);
|
||||
}
|
||||
|
||||
|
||||
// Intel 82439TX System Controller (MXTC)
|
||||
//GRULL VIA82C585VPX (North Bridge - APOLLO Chipset)
|
||||
|
||||
static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
|
||||
{
|
||||
@ -299,15 +377,18 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
|
||||
|
||||
switch(reg)
|
||||
{
|
||||
case 0x59: // PAM0
|
||||
//GRULLcase 0x59:
|
||||
case 0x63: // PAM0
|
||||
{
|
||||
if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
|
||||
//GRULLif (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
|
||||
if ((data & 0x50) | (data & 0xA0))
|
||||
{
|
||||
memory_set_bankptr(busdevice->machine(), "bank1", state->m_bios_ram);
|
||||
}
|
||||
else // disable RAM access (reads go to BIOS ROM)
|
||||
else // disable RAM access (reads go to BIOS ROM)
|
||||
{
|
||||
memory_set_bankptr(busdevice->machine(), "bank1", busdevice->machine().region("bios")->base() + 0x10000);
|
||||
//GRULLmemory_set_bankptr(busdevice->machine(), "bank1", busdevice->machine().region("bios")->base() + 0x10000);
|
||||
memory_set_bankptr(busdevice->machine(), "bank1", busdevice->machine().region("bios")->base());
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -370,6 +451,7 @@ static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int functi
|
||||
}
|
||||
|
||||
// Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
|
||||
//GRULL Cambiar por VIA82C586B (South Bridge - APOLLO Chipset)
|
||||
|
||||
static UINT8 piix4_config_r(device_t *busdevice, device_t *device, int function, int reg)
|
||||
{
|
||||
@ -430,7 +512,8 @@ static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int functi
|
||||
static WRITE32_HANDLER(bios_ram_w)
|
||||
{
|
||||
calchase_state *state = space->machine().driver_data<calchase_state>();
|
||||
if (state->m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
|
||||
//GRULLif (state->m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
|
||||
if (state->m_mxtc_config_reg[0x63] & 0x50)
|
||||
{
|
||||
COMBINE_DATA(state->m_bios_ram + offset);
|
||||
}
|
||||
@ -438,20 +521,25 @@ static WRITE32_HANDLER(bios_ram_w)
|
||||
|
||||
static ADDRESS_MAP_START( calchase_map, AS_PROGRAM, 32 )
|
||||
AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
|
||||
AM_RANGE(0x000a0000, 0x000bffff) AM_RAM // VGA vram
|
||||
//AM_RANGE(0x000a0000, 0x000bffff) AM_RAM AM_BASE_MEMBER(calchase_state, m_vga_vram) //GRULL-ADDVGA
|
||||
AM_RANGE(0x000a0000, 0x000bffff) AM_NOP
|
||||
AM_RANGE(0x000c0000, 0x000c7fff) AM_RAM AM_REGION("video_bios", 0)
|
||||
AM_RANGE(0x000e0000, 0x000effff) AM_RAM
|
||||
AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bank1")
|
||||
AM_RANGE(0x000f0000, 0x000fffff) AM_WRITE(bios_ram_w)
|
||||
AM_RANGE(0x000c8000, 0x000dffff) AM_NOP
|
||||
//GRULL AM_RANGE(0x000e0000, 0x000effff) AM_RAM
|
||||
//GRULL-AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bank1")
|
||||
//GRULL AM_RANGE(0x000f0000, 0x000fffff) AM_WRITE(bios_ram_w)
|
||||
AM_RANGE(0x000e0000, 0x000fffff) AM_ROMBANK("bank1")
|
||||
AM_RANGE(0x000e0000, 0x000fffff) AM_WRITE(bios_ram_w)
|
||||
AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
|
||||
AM_RANGE(0x04000000, 0x040001ff) AM_RAM
|
||||
AM_RANGE(0x08000000, 0x080001ff) AM_RAM
|
||||
AM_RANGE(0x0c000000, 0x0c0001ff) AM_RAM
|
||||
AM_RANGE(0x10000000, 0x100001ff) AM_RAM
|
||||
AM_RANGE(0x14000000, 0x140001ff) AM_RAM
|
||||
AM_RANGE(0x18000000, 0x180001ff) AM_RAM
|
||||
AM_RANGE(0x20000000, 0x200001ff) AM_RAM
|
||||
AM_RANGE(0x28000000, 0x280001ff) AM_RAM
|
||||
AM_RANGE(0x02000000, 0x28ffffff) AM_NOP
|
||||
//AM_RANGE(0x04000000, 0x040001ff) AM_RAM
|
||||
//AM_RANGE(0x08000000, 0x080001ff) AM_RAM
|
||||
//AM_RANGE(0x0c000000, 0x0c0001ff) AM_RAM
|
||||
//AM_RANGE(0x10000000, 0x100001ff) AM_RAM
|
||||
//AM_RANGE(0x14000000, 0x140001ff) AM_RAM
|
||||
//AM_RANGE(0x18000000, 0x180001ff) AM_RAM
|
||||
//AM_RANGE(0x20000000, 0x200001ff) AM_RAM
|
||||
//AM_RANGE(0x28000000, 0x280001ff) AM_RAM
|
||||
AM_RANGE(0xfffe0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -460,20 +548,43 @@ static ADDRESS_MAP_START( calchase_io, AS_IO, 32)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8_MODERN("rtc", mc146818_device, read, write, 0xffffffff)
|
||||
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8_MODERN("rtc", mc146818_device, read, write, 0xffffffff) /* todo: nvram (CMOS Setup Save)*/
|
||||
AM_RANGE(0x0080, 0x009f) AM_READWRITE(at_page32_r, at_page32_w)
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE("dma8237_2", at32_dma8237_2_r, at32_dma8237_2_w)
|
||||
//AM_RANGE(0x00e8, 0x00eb) AM_NOP
|
||||
AM_RANGE(0x00e8, 0x00ef) AM_NOP //GRULL AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
|
||||
AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
|
||||
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_r, ide_w)
|
||||
AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
|
||||
AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
|
||||
AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
|
||||
AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE("ide", fdc_r, fdc_w)
|
||||
AM_RANGE(0x0280, 0x0287) AM_NOP //To debug
|
||||
AM_RANGE(0x02a0, 0x02a7) AM_NOP //To debug
|
||||
AM_RANGE(0x02c0, 0x02c7) AM_NOP //To debug
|
||||
AM_RANGE(0x02e0, 0x02ef) AM_NOP //To debug
|
||||
AM_RANGE(0x0278, 0x02ff) AM_NOP //To debug
|
||||
AM_RANGE(0x02f8, 0x02ff) AM_NOP //To debug
|
||||
AM_RANGE(0x0320, 0x038f) AM_NOP //To debug
|
||||
AM_RANGE(0x03a0, 0x03a7) AM_NOP //To debug
|
||||
AM_RANGE(0x03e0, 0x03ef) AM_NOP //To debug
|
||||
AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
|
||||
//GRULL-ADDVGA AM_RANGE(0x0300, 0x03af) AM_NOP
|
||||
//GRULL-ADDVGA AM_RANGE(0x03b0, 0x03df) AM_NOP
|
||||
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", fdc_r, fdc_w)
|
||||
AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
|
||||
AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
|
||||
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_32le_r, pci_32le_w)
|
||||
// AM_RANGE(0x43c0, 0x43cf) AM_RAM AM_SHARE("share1")
|
||||
// AM_RANGE(0x83c0, 0x83cf) AM_RAM AM_SHARE("share1")
|
||||
AM_RANGE(0x42e8, 0x43ef) AM_NOP //To debug
|
||||
AM_RANGE(0x43c0, 0x43cf) AM_RAM AM_SHARE("share1")
|
||||
AM_RANGE(0x46e8, 0x46ef) AM_NOP //To debug
|
||||
AM_RANGE(0x4ae8, 0x4aef) AM_NOP //To debug
|
||||
AM_RANGE(0x83c0, 0x83cf) AM_RAM AM_SHARE("share1")
|
||||
AM_RANGE(0x92e8, 0x92ef) AM_NOP //To debug
|
||||
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
/*GRULL-ADDVGA
|
||||
static const gfx_layout CGA_charlayout =
|
||||
{
|
||||
8,8,
|
||||
@ -484,11 +595,14 @@ static const gfx_layout CGA_charlayout =
|
||||
{ 0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8 },
|
||||
8*8
|
||||
};
|
||||
*/
|
||||
|
||||
/*GRULL-ADDVGA
|
||||
static GFXDECODE_START( CGA )
|
||||
GFXDECODE_ENTRY( "video_bios", 0x5182, CGA_charlayout, 0, 256 )
|
||||
//there's also a 8x16 entry (just after the 8x8)
|
||||
GFXDECODE_END
|
||||
*/
|
||||
|
||||
#define AT_KEYB_HELPER(bit, text, key1) \
|
||||
PORT_BIT( bit, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_NAME(text) PORT_CODE(key1)
|
||||
@ -530,6 +644,21 @@ static IRQ_CALLBACK(irq_callback)
|
||||
return pic8259_acknowledge( state->m_pic8259_1);
|
||||
}
|
||||
|
||||
static READ8_HANDLER( vga_setting ) { return 0xff; } // hard-code to color
|
||||
|
||||
static const struct pc_vga_interface vga_interface =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
vga_setting,
|
||||
AS_PROGRAM,
|
||||
0xa0000,
|
||||
AS_IO,
|
||||
0x0000
|
||||
};
|
||||
|
||||
|
||||
|
||||
static MACHINE_START(calchase)
|
||||
{
|
||||
calchase_state *state = machine.driver_data<calchase_state>();
|
||||
@ -550,6 +679,7 @@ static MACHINE_START(calchase)
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( calchase_pic8259_1_set_int_line )
|
||||
{
|
||||
|
||||
cputag_set_input_line(device->machine(), "maincpu", 0, state ? HOLD_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
@ -557,6 +687,7 @@ static READ8_DEVICE_HANDLER( get_slave_ack )
|
||||
{
|
||||
calchase_state *state = device->machine().driver_data<calchase_state>();
|
||||
if (offset==2) { // IRQ = 2
|
||||
logerror("pic8259_slave_ACK!\n");
|
||||
return pic8259_acknowledge(state->m_pic8259_2);
|
||||
}
|
||||
return 0x00;
|
||||
@ -577,6 +708,8 @@ static const struct pic8259_interface calchase_pic8259_2_config =
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
/*************************************************************
|
||||
*
|
||||
* pit8254 configuration
|
||||
@ -604,7 +737,8 @@ static const struct pit8253_config calchase_pit8254_config =
|
||||
|
||||
static MACHINE_RESET(calchase)
|
||||
{
|
||||
memory_set_bankptr(machine, "bank1", machine.region("bios")->base() + 0x10000);
|
||||
//GRULLmemory_set_bankptr(machine, "bank1", machine.region("bios")->base() + 0x10000);
|
||||
memory_set_bankptr(machine, "bank1", machine.region("bios")->base());
|
||||
}
|
||||
|
||||
static void set_gate_a20(running_machine &machine, int a20)
|
||||
@ -643,7 +777,7 @@ static void calchase_set_keyb_int(running_machine &machine, int state)
|
||||
|
||||
|
||||
static MACHINE_CONFIG_START( calchase, calchase_state )
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 200000000) // Cyrix 686MX-PR200 CPU
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 133000000) // Cyrix 686MX-PR200 CPU
|
||||
MCFG_CPU_PROGRAM_MAP(calchase_map)
|
||||
MCFG_CPU_IO_MAP(calchase_io)
|
||||
|
||||
@ -656,45 +790,42 @@ static MACHINE_CONFIG_START( calchase, calchase_state )
|
||||
MCFG_PIC8259_ADD( "pic8259_1", calchase_pic8259_1_config )
|
||||
MCFG_PIC8259_ADD( "pic8259_2", calchase_pic8259_2_config )
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_interrupt)
|
||||
|
||||
MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
|
||||
MCFG_PCI_BUS_ADD("pcibus", 0)
|
||||
MCFG_PCI_BUS_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
|
||||
MCFG_PCI_BUS_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
|
||||
|
||||
MCFG_PALETTE_LENGTH(0x200)
|
||||
MCFG_GFXDECODE( CGA )
|
||||
//GRULL-ADDVGA MCFG_PALETTE_LENGTH(0x200)
|
||||
//GRULL-ADDVGA MCFG_GFXDECODE( CGA )
|
||||
|
||||
MCFG_FRAGMENT_ADD( pcvideo_vga )
|
||||
|
||||
/* video hardware */
|
||||
MCFG_FRAGMENT_ADD( pcvideo_vga ) //GRULL-ADDVGA
|
||||
//GRULL-ADDVGA MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_MODIFY("screen")
|
||||
MCFG_SCREEN_REFRESH_RATE(60)
|
||||
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
|
||||
//PROBAR QUITANDO MCFG_SCREEN_REFRESH_RATE(60)
|
||||
//PROBAR QUITANDO MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) //GRULL-ADDVGA Before 0
|
||||
//GRULL-ADDVGA MCFG_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
|
||||
//GRULL-ADDVGA MCFG_SCREEN_SIZE(64*8, 32*8) // 80*8, 25*8
|
||||
//GRULL-ADDVGA MCFG_SCREEN_VISIBLE_AREA(0*8, 64*8-1, 0*8, 32*8-1) //
|
||||
//GRULL-ADDVGA MCFG_SCREEN_UPDATE(calchase)
|
||||
|
||||
//GRULL-ADDVGA MCFG_VIDEO_START(calchase)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static READ8_HANDLER( vga_setting ) { return 0xff; } // hard-code to color
|
||||
|
||||
static const struct pc_vga_interface vga_interface =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
vga_setting,
|
||||
AS_PROGRAM,
|
||||
0xa0000,
|
||||
AS_IO,
|
||||
0x0000
|
||||
};
|
||||
|
||||
static DRIVER_INIT( calchase )
|
||||
{
|
||||
calchase_state *state = machine.driver_data<calchase_state>();
|
||||
state->m_bios_ram = auto_alloc_array(machine, UINT32, 0x10000/4);
|
||||
//GRULLstate->m_bios_ram = auto_alloc_array(machine, UINT32, 0x10000/4);
|
||||
state->m_bios_ram = auto_alloc_array(machine, UINT32, 0x20000/4);
|
||||
|
||||
pc_vga_init(machine, &vga_interface, NULL); //GRULL_ADDVGA
|
||||
init_pc_common(machine, PCCOMMON_KEYBOARD_AT, calchase_set_keyb_int);
|
||||
|
||||
intel82439tx_init(machine);
|
||||
|
||||
kbdc8042_init(machine, &at8042);
|
||||
pc_vga_init(machine, &vga_interface, NULL);
|
||||
}
|
||||
|
||||
|
||||
@ -702,15 +833,20 @@ ROM_START( calchase )
|
||||
ROM_REGION( 0x40000, "bios", 0 )
|
||||
ROM_LOAD( "mb_bios.bin", 0x00000, 0x20000, CRC(dea7a51b) SHA1(e2028c00bfa6d12959fc88866baca8b06a1eab68) )
|
||||
|
||||
ROM_REGION( 0x8000, "video_bios", 0 )
|
||||
ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
|
||||
ROM_CONTINUE( 0x0001, 0x4000 )
|
||||
ROM_REGION(0x8000,"video_bios", 0)
|
||||
ROM_LOAD("et4000.bin", 0x0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
|
||||
|
||||
|
||||
//GRULL-ADDVGA ROM_REGION( 0x8000, "video_bios", 0 )
|
||||
//GRULL-ADDVGA ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
|
||||
//GRULL-ADDVGA ROM_CONTINUE( 0x0001, 0x4000 )
|
||||
|
||||
ROM_REGION( 0x800, "nvram", 0 )
|
||||
ROM_LOAD( "ds1220y_nv.bin", 0x000, 0x800, CRC(7912c070) SHA1(b4c55c7ca76bcd8dad1c4b50297233349ae02ed3) )
|
||||
|
||||
DISK_REGION( "ide" )
|
||||
DISK_IMAGE( "calchase", 0,SHA1(487e304ffeed23ca618fa936258136605ce9d1a1) )
|
||||
//GRULL DISK_IMAGE( "calchase", 0,SHA1(487e304ffeed23ca618fa936258136605ce9d1a1) )
|
||||
DISK_IMAGE_READONLY( "calchase", 0,SHA1(487e304ffeed23ca618fa936258136605ce9d1a1) )
|
||||
ROM_END
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user