Cleanup devcpu.h (nw)

This commit is contained in:
Miodrag Milanovic 2015-11-06 15:01:46 +01:00
parent 920f0ad7b5
commit 9c96282b3b
7 changed files with 0 additions and 125 deletions

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@ -31,22 +31,6 @@
#define ARM7_MAX_FASTRAM 4
#define ARM7_MAX_HOTSPOTS 16
enum
{
CPUINFO_INT_ARM7_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
CPUINFO_INT_ARM7_FASTRAM_SELECT,
CPUINFO_INT_ARM7_FASTRAM_START,
CPUINFO_INT_ARM7_FASTRAM_END,
CPUINFO_INT_ARM7_FASTRAM_READONLY,
CPUINFO_INT_ARM7_HOTSPOT_SELECT,
CPUINFO_INT_ARM7_HOTSPOT_PC,
CPUINFO_INT_ARM7_HOTSPOT_OPCODE,
CPUINFO_INT_ARM7_HOTSPOT_CYCLES,
CPUINFO_PTR_ARM7_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
};
/***************************************************************************
COMPILER-SPECIFIC OPTIONS

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@ -526,4 +526,3 @@ offs_t i4004_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
return CPU_DISASSEMBLE_NAME(i4004)(this, buffer, pc, oprom, opram, options);
}
// case CPUINFO_IS_OCTAL: info->i = true; break;

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@ -2157,39 +2157,6 @@ void m68000_base_device::init_cpu_coldfire(void)
define_state();
}
/*
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; // there is no level 0
case CPUINFO_INT_INPUT_STATE + 1: info->i = (m68k->virq_state >> 1) & 1; break;
case CPUINFO_INT_INPUT_STATE + 2: info->i = (m68k->virq_state >> 2) & 1; break;
case CPUINFO_INT_INPUT_STATE + 3: info->i = (m68k->virq_state >> 3) & 1; break;
case CPUINFO_INT_INPUT_STATE + 4: info->i = (m68k->virq_state >> 4) & 1; break;
case CPUINFO_INT_INPUT_STATE + 5: info->i = (m68k->virq_state >> 5) & 1; break;
case CPUINFO_INT_INPUT_STATE + 6: info->i = (m68k->virq_state >> 6) & 1; break;
case CPUINFO_INT_INPUT_STATE + 7: info->i = (m68k->virq_state >> 7) & 1; break;
case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "4.95"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO+OG)"); break;
*/
CPU_DISASSEMBLE( dasm_m68000 )
{
return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68000);

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@ -197,25 +197,6 @@ enum
#define MIPS3_MAX_FASTRAM 3
#define MIPS3_MAX_HOTSPOTS 16
enum
{
CPUINFO_INT_MIPS3_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
CPUINFO_INT_MIPS3_FASTRAM_SELECT,
CPUINFO_INT_MIPS3_FASTRAM_START,
CPUINFO_INT_MIPS3_FASTRAM_END,
CPUINFO_INT_MIPS3_FASTRAM_READONLY,
CPUINFO_INT_MIPS3_HOTSPOT_SELECT,
CPUINFO_INT_MIPS3_HOTSPOT_PC,
CPUINFO_INT_MIPS3_HOTSPOT_OPCODE,
CPUINFO_INT_MIPS3_HOTSPOT_CYCLES,
CPUINFO_PTR_MIPS3_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
};
/***************************************************************************
INTERRUPT CONSTANTS
***************************************************************************/

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@ -82,18 +82,6 @@ typedef device_delegate<void (UINT32 data)> sh2_ftcsr_read_delegate;
#define SH2DRC_COMPATIBLE_OPTIONS (SH2DRC_STRICT_VERIFY | SH2DRC_FLUSH_PC | SH2DRC_STRICT_PCREL)
#define SH2DRC_FASTEST_OPTIONS (0)
enum
{
CPUINFO_INT_SH2_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
CPUINFO_INT_SH2_FASTRAM_SELECT,
CPUINFO_INT_SH2_FASTRAM_START,
CPUINFO_INT_SH2_FASTRAM_END,
CPUINFO_INT_SH2_FASTRAM_READONLY,
CPUINFO_PTR_SH2_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
};
#define SH2_MAX_FASTRAM 4
class sh2_frontend;

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@ -120,13 +120,6 @@ enum
Z180_TABLE_ex /* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */
};
enum
{
CPUINFO_PTR_Z180_CYCLE_TABLE = CPUINFO_PTR_CPU_SPECIFIC,
CPUINFO_PTR_Z180_CYCLE_TABLE_LAST = CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_ex
};
#define Z180_IRQ0 0 /* Execute IRQ1 */
#define Z180_IRQ1 1 /* Execute IRQ1 */
#define Z180_IRQ2 2 /* Execute IRQ2 */

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@ -17,43 +17,6 @@
#ifndef __DEVCPU_H__
#define __DEVCPU_H__
#include "emuopts.h"
//**************************************************************************
// CONSTANTS
//**************************************************************************
// CPU information constants
const int MAX_REGS = 256;
enum
{
// --- the following bits of info are returned as 64-bit signed integers ---
CPUINFO_INT_FIRST = 0x00000,
CPUINFO_INT_CPU_SPECIFIC = 0x08000, // R/W: CPU-specific values start here
// --- the following bits of info are returned as pointers to data or functions ---
CPUINFO_PTR_FIRST = 0x10000,
// CPU-specific additions
CPUINFO_PTR_INSTRUCTION_COUNTER = 0x14000,
// R/O: int *icount
CPUINFO_PTR_CPU_SPECIFIC = 0x18000, // R/W: CPU-specific values start here
// --- the following bits of info are returned as pointers to functions ---
CPUINFO_FCT_FIRST = 0x20000,
CPUINFO_FCT_CPU_SPECIFIC = 0x28000, // R/W: CPU-specific values start here
// --- the following bits of info are returned as NULL-terminated strings ---
CPUINFO_STR_FIRST = 0x30000,
CPUINFO_STR_CPU_SPECIFIC = 0x38000 // R/W: CPU-specific values start here
};
//**************************************************************************
// CPU DEVICE CONFIGURATION MACROS
//**************************************************************************