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stratos: prev lcd fix didnt work for corona (nw)

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This commit is contained in:
hap 2019-07-26 02:34:40 +02:00
parent 5b7a630d04
commit 9d357af2d2
2 changed files with 9 additions and 3 deletions
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9
src/mame/drivers/saitek_corona.cpp
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@ -70,6 +70,7 @@ private:
DECLARE_READ8_MEMBER(control1_r);
DECLARE_READ8_MEMBER(control2_r);
DECLARE_READ8_MEMBER(chessboard_r);
DECLARE_WRITE8_MEMBER(lcd_reset_w);
u8 m_control1;
u8 m_control2;
@ -214,6 +215,12 @@ READ8_MEMBER(corona_state::chessboard_r)
return ~m_board->read_file(m_select2 & 0xf);
}
WRITE8_MEMBER(corona_state::lcd_reset_w)
{
// reset lcd?
m_lcd_ready = true;
}
/******************************************************************************
@ -227,7 +234,7 @@ void corona_state::main_map(address_map &map)
map(0x2400, 0x2400).rw(FUNC(corona_state::chessboard_r), FUNC(corona_state::leds1_w));
map(0x2600, 0x2600).rw(FUNC(corona_state::control1_r), FUNC(corona_state::control1_w));
map(0x6000, 0x6000).w(FUNC(corona_state::select2_w));
map(0x6200, 0x6200).unmapw(); // ?
map(0x6200, 0x6200).w(FUNC(corona_state::lcd_reset_w));
map(0x6400, 0x6400).w(FUNC(corona_state::leds2_w));
map(0x6600, 0x6600).rw(FUNC(corona_state::control2_r), FUNC(corona_state::control2_w));
map(0x8000, 0xffff).m(m_rombank, FUNC(address_map_bank_device::amap8));

3
src/mame/drivers/saitek_stratos.cpp
View File

@ -43,8 +43,7 @@ very few bytes difference between revisions. The first Corona is engine version
TODO:
- emulate LCD at lower level, probably an MCU with embedded LCDC
- LCD status bit handling is guessed. stratos expects it to be high after lcd command 0xf,
but tking(D) won't work if it's done that way
- fix LCD 7*7 DMD, it's in m_lcd_data[0x30 to 0x3b] but scrambled
but tking2 won't work if it's done that way, and corona is different too
- tking different internal artwork
- irq timing is derived from the main XTAL, but result should be similar with 5MHz and 5.67MHz,
there are a couple of "FREQ. SEL" nodes on the PCB, maybe related (not the ones in input ports)