mirror of
https://github.com/holub/mame
synced 2025-04-20 23:42:22 +03:00
video/atirage.cpp: Extremely preliminary emulation of PCI ATI 3D Rage family SVGA chips. [R. Belmont]
apple/powermacg3.cpp: Hooked up ATI Rage II video, you can now enter and interact with Open Firmware. [R. Belmont]
This commit is contained in:
arbee
parent
915cf99f06
commit
9de67ba595
@ -55,6 +55,18 @@ if (VIDEOS["AM8052"]~=null) then
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/atirage.h,VIDEOS["ATIRAGE"] = true
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--------------------------------------------------
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if (VIDEOS["ATIRAGE"]~=null) then
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files {
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MAME_DIR .. "src/devices/video/atirage.cpp",
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MAME_DIR .. "src/devices/video/atirage.h",
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}
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end
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--------------------------------------------------
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--
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--@src/devices/video/bufsprite.h,VIDEOS["BUFSPRITE"] = true
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@ -169,7 +169,14 @@ uint16_t mach32_device::offset()
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uint32_t mach32_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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ati_vga_device::screen_update(screen,bitmap,cliprect);
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ati_vga_device::screen_update(screen, bitmap, cliprect);
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draw_hw_cursor(screen, bitmap, cliprect);
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return 0;
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}
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uint32_t mach32_device::draw_hw_cursor(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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uint8_t depth = get_video_depth();
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if(!m_cursor_enable)
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@ -356,3 +363,33 @@ void mach64_device::device_reset()
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{
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mach32_device::device_reset();
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}
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void mach64_device::set_color(u8 index, u32 color)
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{
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// update the palette device so we can see in the F4 viewer what the Rage is doing
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set_pen_color(index, (color>>16) & 0xff, (color>>8) & 0xff, color & 0xff);
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}
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u32 mach64_device::framebuffer_r(offs_t offset, u32 mem_mask)
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{
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const u32 *target = (u32 *)&vga.memory[offset<<2];
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return *target;
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}
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void mach64_device::framebuffer_w(offs_t offset, u32 data, u32 mem_mask)
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{
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COMBINE_DATA((u32*)&vga.memory[offset<<2]);
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}
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u32 mach64_device::framebuffer_be_r(offs_t offset, u32 mem_mask)
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{
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const u32 *target = (u32 *)&vga.memory[offset<<2];
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return swapendian_int32(*target);
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}
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void mach64_device::framebuffer_be_w(offs_t offset, u32 data, u32 mem_mask)
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{
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data = swapendian_int32(data);
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mem_mask = swapendian_int32(mem_mask);
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COMBINE_DATA((u32*)&vga.memory[offset<<2]);
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}
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@ -53,6 +53,7 @@ public:
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// construction/destruction
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mach32_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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virtual uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) override;
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uint32_t draw_hw_cursor(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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required_device<mach32_8514a_device> m_8514a; // provides accelerated 2D drawing, derived from the Mach8 device
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@ -213,6 +214,13 @@ public:
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void mach64_config1_w(uint16_t data) { } // why does the mach64 BIOS write to these, they are read only on the mach32 and earlier
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void mach64_config2_w(uint16_t data) { }
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void set_color(u8 index, u32 color);
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u32 framebuffer_r(offs_t offset, u32 mem_mask);
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void framebuffer_w(offs_t offset, u32 data, u32 mem_mask);
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u32 framebuffer_be_r(offs_t offset, u32 mem_mask);
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void framebuffer_be_w(offs_t offset, u32 data, u32 mem_mask);
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u8 *get_framebuffer_addr() { return &vga.memory[0]; }
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protected:
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mach64_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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@ -222,6 +230,8 @@ protected:
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virtual void device_add_mconfig(machine_config &config) override;
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required_device<mach64_8514a_device> m_8514a; // provides accelerated 2D drawing, derived from the Mach8 device
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private:
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};
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// device type definition
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524
src/devices/video/atirage.cpp
Normal file
524
src/devices/video/atirage.cpp
Normal file
@ -0,0 +1,524 @@
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// license:BSD-3-Clause
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// copyright-holders: R. Belmont
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/*
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ATI Rage PCI/AGP SVGA
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This implementation targets the mach64 VT and 3D Rage chips. Rage 128 has similar registers
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but they're mapped differently.
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mach64 VT = mach64 with video decoding. Uses a Rage-compatible register layout, as opposed to earlier mach64.
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mach64 GT = Rage I (mach64 acceleration and VGA with 3D polygons and MPEG-1 decode)
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mach64 GT-B = Rage II (Rage I with faster 2D & 3D and MPEG-2 decode)
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Rage II+ = Rage II with full DVD acceleration
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Rage IIc = Rage II+ with optional AGP support
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Rage Pro = new triangle setup engine, improved perspective correction, fog + specular lighting,
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and improved video decode
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Rage Pro Turbo = Rage Pro with AGP 2X support and improved performance drivers for Win9X
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Rage LT = lower-power Rage II with DVD support
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Rage Mobility C, EC, L, and M2 = lower-power Rage Pro with DVD motion compensation
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Rage Mobility P, M, and M1 = lower-power Rage Pro with DVD motion compensation and IDCT accleration
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Rage XL = cost-reduced Rage Pro with improved 3D image quality, used in many servers until 2006
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Most PCI IDs are a 2-letter ATI product code in ASCII. For instance, Rage I & II aka mach64 GT are 0x4754 'GT'.
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Reference: rrg-g02700_mach64_register_reference_guide_jul96.pdf, aka "mach64 Register Reference Guide: ATI VT-264 and 3D RAGE"
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http://hackipedia.org/browse.cgi/Computer/Platform/PC%2C%20IBM%20compatible/Video/VGA/SVGA/ATI%2C%20Array%20Technology%20Inc
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*/
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#include "emu.h"
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#include "screen.h"
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#include "atirage.h"
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#define LOG_GENERAL (1U << 0)
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#define LOG_REGISTERS (1U << 1)
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#define LOG_CRTC (1U << 2)
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#define LOG_DAC (1U << 3)
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#define VERBOSE (0)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(ATI_RAGEII, atirageii_device, "rageii", "ATI Rage II PCI")
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DEFINE_DEVICE_TYPE(ATI_RAGEIIC, atirageiic_device, "rageiic", "ATI Rage IIC PCI")
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DEFINE_DEVICE_TYPE(ATI_RAGEPRO, atiragepro_device, "ragepro", "ATI Rage Pro PCI")
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// register offsets
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static constexpr u32 CRTC_H_TOTAL_DISP = 0x00;
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static constexpr u32 CRTC_V_TOTAL_DISP = 0x08;
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static constexpr u32 CRTC_OFF_PITCH = 0x14;
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static constexpr u32 CRTC_GEN_CNTL = 0x1c;
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static constexpr u32 GP_IO = 0x78;
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static constexpr u32 CLOCK_CNTL = 0x90;
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static constexpr u32 CRTC_DAC_BASE = 0xc0;
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static constexpr u32 CONFIG_CHIP_ID = 0xe0;
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// PLL register offsets
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static constexpr u32 PLL_MACRO_CNTL = 1;
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static constexpr u32 PLL_REF_DIV = 2;
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static constexpr u32 PLL_GEN_CNTL = 3;
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static constexpr u32 MCLK_FB_DIV = 4;
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static constexpr u32 PLL_VCLK_CNTL = 5;
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static constexpr u32 VCLK_POST_DIV = 6;
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static constexpr u32 VCLK0_FB_DIV = 7;
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static constexpr u32 VCLK1_FB_DIV = 8;
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static constexpr u32 VCLK2_FB_DIV = 9;
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static constexpr u32 VCLK3_FB_DIV = 10;
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static constexpr u32 PLL_XCLK_CNTL = 11;
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static constexpr u32 PLL_FCP_CNTL = 12;
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// mach64 & 3D Rage post-dividers for PLL
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static const int pll_post_dividers[8] =
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{
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1, 2, 4, 8, 3, 5, 6, 12
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};
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void atirage_device::device_add_mconfig(machine_config &config)
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{
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screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
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screen.set_raw(XTAL(25'174'800), 900, 0, 640, 526, 0, 480);
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screen.set_screen_update(FUNC(atirage_device::screen_update));
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ATIMACH64(config, m_mach64, 0);
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m_mach64->set_screen("screen");
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m_mach64->set_vram_size(0x600000);
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}
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atirage_device::atirage_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
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: pci_device(mconfig, type, tag, owner, clock),
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m_mach64(*this, "vga"),
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m_screen(*this, "screen"),
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read_gpio(*this),
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write_gpio(*this)
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{
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m_hres = m_vres = m_htotal = m_vtotal = m_format = 0;
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m_dac_windex = m_dac_rindex = m_dac_state = 0;
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m_dac_mask = 0xff;
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}
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atirageii_device::atirageii_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: atirage_device(mconfig, ATI_RAGEII, tag, owner, clock)
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{
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}
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atirageiic_device::atirageiic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: atirage_device(mconfig, ATI_RAGEIIC, tag, owner, clock)
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{
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}
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atiragepro_device::atiragepro_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: atirage_device(mconfig, ATI_RAGEPRO, tag, owner, clock)
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{
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}
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void atirage_device::io_map(address_map& map)
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{
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map(0x00000000, 0x000003ff).rw(FUNC(atirage_device::regs_0_read), FUNC(atirage_device::regs_0_write));
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}
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void atirage_device::mem_map(address_map& map)
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{
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map(0x00000000, 0x005fffff).rw(m_mach64, FUNC(mach64_device::framebuffer_r), FUNC(mach64_device::framebuffer_w));
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map(0x007ff800, 0x007ffbff).rw(FUNC(atirage_device::regs_1_read), FUNC(atirage_device::regs_1_write));
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map(0x007ffc00, 0x007fffff).rw(FUNC(atirage_device::regs_0_read), FUNC(atirage_device::regs_0_write));
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map(0x00800000, 0x00dfffff).rw(m_mach64, FUNC(mach64_device::framebuffer_be_r), FUNC(mach64_device::framebuffer_be_w));
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}
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void atirage_device::reg_map(address_map& map)
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{
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}
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void atirage_device::config_map(address_map &map)
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{
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pci_device::config_map(map);
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map(0x0040, 0x0043).rw(FUNC(atirage_device::user_cfg_r), FUNC(atirage_device::user_cfg_w));
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}
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void atirage_device::device_start()
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{
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read_gpio.resolve_safe(0);
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write_gpio.resolve_safe();
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pci_device::device_start();
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add_map(0x1000000, M_MEM, FUNC(atirage_device::mem_map)); // 16 MB memory map
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add_map(0x100, M_IO, FUNC(atirage_device::io_map)); // 256 byte I/O map
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add_map(0x01000, M_MEM, FUNC(atirage_device::reg_map)); // 4K register map
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command = 3;
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intr_pin = 1;
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intr_line = 0;
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// clear the registers
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std::fill(std::begin(m_regs0), std::end(m_regs0), 0);
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std::fill(std::begin(m_regs1), std::end(m_regs1), 0);
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std::fill(std::begin(m_pll_regs), std::end(m_pll_regs), 0);
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std::fill(std::begin(m_dac_colors), std::end(m_dac_colors), 0);
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// set PLL defaults from the manual
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m_pll_regs[PLL_MACRO_CNTL] = 0xd4;
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m_pll_regs[PLL_REF_DIV] = 0x36;
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m_pll_regs[PLL_GEN_CNTL] = 0x4f;
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m_pll_regs[MCLK_FB_DIV] = 0x97;
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m_pll_regs[PLL_VCLK_CNTL] = 0x04;
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m_pll_regs[VCLK_POST_DIV] = 0x6a;
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m_pll_regs[VCLK0_FB_DIV] = 0xbe;
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m_pll_regs[VCLK1_FB_DIV] = 0xd6;
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m_pll_regs[VCLK2_FB_DIV] = 0xee;
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m_pll_regs[VCLK3_FB_DIV] = 0x88;
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m_pll_regs[PLL_XCLK_CNTL] = 0x00;
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m_pll_regs[PLL_FCP_CNTL] = 0x41;
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m_user_cfg = 8;
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save_item(NAME(m_user_cfg));
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save_item(NAME(m_regs0));
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save_item(NAME(m_regs1));
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save_item(NAME(m_pll_regs));
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save_item(NAME(m_hres));
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save_item(NAME(m_vres));
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save_item(NAME(m_htotal));
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save_item(NAME(m_vtotal));
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save_item(NAME(m_format));
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save_item(NAME(m_pixel_clock));
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save_item(NAME(m_dac_windex));
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save_item(NAME(m_dac_rindex));
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save_item(NAME(m_dac_state));
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save_item(NAME(m_dac_mask));
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save_item(NAME(m_dac_colors));
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}
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void atirageii_device::device_start()
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{
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// mach64 GT-B / 3D Rage II (ATI documentation uses both names)
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set_ids(0x10024754, 0x00, 0x030000, 0x10026987);
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atirage_device::device_start();
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revision = 0x9a;
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m_regs0[CONFIG_CHIP_ID] = 0x54;
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m_regs0[CONFIG_CHIP_ID+1] = 0x47;
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m_regs0[CONFIG_CHIP_ID+3] = 0x9a;
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}
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void atirageiic_device::device_start()
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{
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// Rage IIc PCI
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set_ids(0x10024756, 0x00, 0x030000, 0x10026987);
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atirage_device::device_start();
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revision = 0x3a;
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m_regs0[CONFIG_CHIP_ID] = 0x56;
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m_regs0[CONFIG_CHIP_ID+1] = 0x47;
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m_regs0[CONFIG_CHIP_ID+3] = 0x3a;
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}
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void atiragepro_device::device_start()
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{
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// Rage Pro PCI
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set_ids(0x10024750, 0x00, 0x030000, 0x10026987);
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atirage_device::device_start();
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revision = 0x5c;
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m_regs0[CONFIG_CHIP_ID] = 0x50;
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m_regs0[CONFIG_CHIP_ID+1] = 0x47;
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m_regs0[CONFIG_CHIP_ID+3] = 0x5c;
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}
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void atirage_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
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{
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}
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u8 atirage_device::regs_0_read(offs_t offset)
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{
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switch (offset)
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{
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case CRTC_DAC_BASE: // DAC write index
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return m_dac_windex;
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case CRTC_DAC_BASE + 1:
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{
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u8 result;
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switch (m_dac_state)
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{
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case 0: // red
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result = ((m_dac_colors[m_dac_rindex] >> 16) & 0xff);
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break;
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case 1: // blue
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result = ((m_dac_colors[m_dac_rindex] >> 8) & 0xff);
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break;
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case 2: // green
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result = (m_dac_colors[m_dac_rindex] & 0xff);
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break;
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}
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m_dac_state++;
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if (m_dac_state >= 3)
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{
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m_dac_state = 0;
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m_dac_rindex++;
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}
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return result;
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}
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break;
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case CRTC_DAC_BASE + 2:
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return m_dac_mask;
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case CRTC_DAC_BASE + 3:
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return m_dac_rindex;
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case CLOCK_CNTL + 2:
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return m_pll_regs[(m_regs0[CLOCK_CNTL+1] >> 2) & 0xf] << 16;
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case GP_IO: // monitor sense - either 3-line Apple or EDID
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return read_gpio() & 0xff;
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case GP_IO + 1:
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return (read_gpio() & 0xff00) >> 8;
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case GP_IO + 2:
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return (read_gpio() & 0xff0000) >> 16;
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case GP_IO + 3:
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return read_gpio() >> 24;
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}
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return m_regs0[offset];
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}
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void atirage_device::regs_0_write(offs_t offset, u8 data)
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{
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// the FCode drivers try to write to the chip ID, no idea why
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if ((offset >= CONFIG_CHIP_ID) && (offset <= (CONFIG_CHIP_ID + 3)))
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{
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return;
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}
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LOGMASKED(LOG_REGISTERS, "regs_0_write: %02x to %x\n", data, offset);
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m_regs0[offset] = data;
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switch (offset)
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{
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case CRTC_DAC_BASE: // DAC write index
|
||||
m_dac_state = 0;
|
||||
m_dac_windex = data;
|
||||
break;
|
||||
|
||||
case CRTC_DAC_BASE + 1:
|
||||
switch (m_dac_state)
|
||||
{
|
||||
case 0: // red
|
||||
m_dac_colors[m_dac_windex] &= 0x00ffff;
|
||||
m_dac_colors[m_dac_windex] |= ((data & 0xff) << 16);
|
||||
break;
|
||||
|
||||
case 1: // green
|
||||
m_dac_colors[m_dac_windex] &= 0xff00ff;
|
||||
m_dac_colors[m_dac_windex] |= ((data & 0xff) << 8);
|
||||
break;
|
||||
|
||||
case 2: // blue
|
||||
m_dac_colors[m_dac_windex] &= 0xffff00;
|
||||
m_dac_colors[m_dac_windex] |= (data & 0xff);
|
||||
break;
|
||||
}
|
||||
|
||||
m_dac_state++;
|
||||
if (m_dac_state == 3)
|
||||
{
|
||||
m_dac_state = 0;
|
||||
m_mach64->set_color(m_dac_windex, m_dac_colors[m_dac_windex]);
|
||||
m_dac_windex++;
|
||||
}
|
||||
break;
|
||||
|
||||
case CRTC_DAC_BASE + 2:
|
||||
m_dac_mask = data;
|
||||
break;
|
||||
|
||||
case CRTC_DAC_BASE + 3:
|
||||
m_dac_state = 0;
|
||||
m_dac_rindex = data >> 24;
|
||||
break;
|
||||
|
||||
case CRTC_OFF_PITCH:
|
||||
case CRTC_GEN_CNTL:
|
||||
update_mode();
|
||||
break;
|
||||
|
||||
case CLOCK_CNTL + 2:
|
||||
if (BIT(m_regs0[CLOCK_CNTL+1], 1))
|
||||
{
|
||||
u8 regnum = (m_regs0[CLOCK_CNTL+1] >> 2) & 0xf;
|
||||
m_pll_regs[regnum] = data & 0xff;
|
||||
}
|
||||
break;
|
||||
|
||||
case GP_IO:
|
||||
case GP_IO + 1:
|
||||
case GP_IO + 2:
|
||||
case GP_IO + 3:
|
||||
write_gpio(*(u32 *)&m_regs0[GP_IO]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
u8 atirage_device::regs_1_read(offs_t offset)
|
||||
{
|
||||
LOGMASKED(LOG_REGISTERS, "regs 1 read @ %x\n", offset);
|
||||
return m_regs1[offset];
|
||||
}
|
||||
|
||||
void atirage_device::regs_1_write(offs_t offset, u8 data)
|
||||
{
|
||||
m_regs1[offset] = data;
|
||||
}
|
||||
|
||||
u32 atirage_device::user_cfg_r()
|
||||
{
|
||||
return m_user_cfg;
|
||||
}
|
||||
|
||||
void atirage_device::user_cfg_w(u32 data)
|
||||
{
|
||||
m_user_cfg = data;
|
||||
}
|
||||
|
||||
void atirage_device::update_mode()
|
||||
{
|
||||
// first prereq: must be in native mode and the CRTC must be enabled
|
||||
if (!(m_regs0[CRTC_GEN_CNTL+3] & 3))
|
||||
{
|
||||
LOGMASKED(LOG_CRTC, "VGA mode must be OFF and CRTC must be ON\n");
|
||||
return;
|
||||
}
|
||||
|
||||
m_htotal = (m_regs0[CRTC_H_TOTAL_DISP] | (m_regs0[CRTC_H_TOTAL_DISP+1] & 1) << 8) + 1;
|
||||
m_htotal <<= 3; // in units of 8 pixels
|
||||
m_hres = m_regs0[CRTC_H_TOTAL_DISP+2] + 1;
|
||||
m_hres <<= 3;
|
||||
m_vres = (m_regs0[CRTC_V_TOTAL_DISP+2] | (m_regs0[CRTC_V_TOTAL_DISP+3] & 7) << 8) + 1;
|
||||
m_vtotal = (m_regs0[CRTC_V_TOTAL_DISP] | (m_regs0[CRTC_V_TOTAL_DISP+1] & 7) << 8) + 1;
|
||||
m_format = m_regs0[CRTC_GEN_CNTL+1] & 7;
|
||||
LOGMASKED(LOG_CRTC, "Setting mode (%d x %d), total (%d x %d) format %d\n", m_hres, m_vres, m_htotal, m_vtotal, m_format);
|
||||
|
||||
int vclk_source = (m_pll_regs[PLL_VCLK_CNTL] & 3);
|
||||
if ((vclk_source != 0) && (vclk_source != 3))
|
||||
{
|
||||
LOGMASKED(LOG_CRTC, "VCLK source (%d) is not VPLL, can't calculate dot clock\n", m_pll_regs[PLL_VCLK_CNTL] & 3);
|
||||
return;
|
||||
}
|
||||
|
||||
double vpll_frequency;
|
||||
int clk_source = m_regs0[CLOCK_CNTL] & 3;
|
||||
|
||||
switch (vclk_source)
|
||||
{
|
||||
case 0: // CPUCLK (the PCI bus clock, not to exceed 33 MHz)
|
||||
vpll_frequency = (33000000.0 * m_pll_regs[VCLK0_FB_DIV + clk_source]) / m_pll_regs[PLL_REF_DIV];
|
||||
break;
|
||||
|
||||
case 3: // PLLVCLK
|
||||
vpll_frequency = ((clock() * 2.0) * m_pll_regs[VCLK0_FB_DIV + clk_source]) / m_pll_regs[PLL_REF_DIV];
|
||||
break;
|
||||
}
|
||||
LOGMASKED(LOG_CRTC, "VPLL freq %f\n", vpll_frequency);
|
||||
|
||||
int vpll_post_divider = (m_pll_regs[VCLK_POST_DIV] >> (clk_source << 1)) & 3;
|
||||
// Rage Pro adds one more bit to the divider from bits 4/5/6/7 of XCLK_CNTL depending on the clock source.
|
||||
// This should always be zero on mach64/Rage/Rage II.
|
||||
vpll_post_divider |= ((m_pll_regs[PLL_XCLK_CNTL] >> (clk_source + 2)) & 4);
|
||||
|
||||
m_pixel_clock = u32(vpll_frequency / pll_post_dividers[vpll_post_divider]);
|
||||
LOGMASKED(LOG_CRTC, "Pixel clock = %d, refresh = %f\n", m_pixel_clock, (double)m_pixel_clock / (double)m_htotal / (double)m_vtotal);
|
||||
|
||||
rectangle visarea(0, m_hres - 1, 0, m_vres - 1);
|
||||
m_screen->configure(m_htotal, m_vtotal, visarea, attotime::from_ticks(m_htotal * m_vtotal, m_pixel_clock).as_attoseconds());
|
||||
}
|
||||
|
||||
u32 atirage_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
// are we in VGA mode rather than native? if so, let the legacy VGA stuff draw.
|
||||
if (!(m_regs0[CRTC_GEN_CNTL+3] & 1))
|
||||
{
|
||||
return m_mach64->screen_update(screen, bitmap, cliprect);
|
||||
}
|
||||
|
||||
// is the CRTC not enabled or the display disable bit set?
|
||||
if ((!(m_regs0[CRTC_GEN_CNTL+3] & 2)) || (m_regs0[CRTC_GEN_CNTL] & 0x40))
|
||||
{
|
||||
bitmap.fill(0, cliprect);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const int offset = ((m_regs0[CRTC_OFF_PITCH+2] & 0xf) << 16) | (m_regs0[CRTC_OFF_PITCH+1] << 8) | (m_regs0[CRTC_OFF_PITCH]);
|
||||
u8 *vram = m_mach64->get_framebuffer_addr() + (offset * 8);
|
||||
int stride = (m_regs0[CRTC_OFF_PITCH+2] >> 6) | (m_regs0[CRTC_OFF_PITCH+3] << 2);
|
||||
stride *= 4;
|
||||
|
||||
switch (m_format)
|
||||
{
|
||||
case 2: // 8 bpp (also can be a weird 2/2/3 direct color mode)
|
||||
for (u32 y = 0; y < m_vres; y++)
|
||||
{
|
||||
const u8 *src = &vram[stride*y];
|
||||
u32 *dst = &bitmap.pix(y, 0);
|
||||
for (u32 x = 0; x < m_hres; x++)
|
||||
{
|
||||
*dst++ = m_dac_colors[src[x]];
|
||||
}
|
||||
vram += stride;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
LOGMASKED(LOG_GENERAL, "Unknown pixel format %d\n", m_format);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
02 to CLOCK_CTNL + 1
|
||||
PLL: cd to 0
|
||||
06 to CLOCK_CTNL + 1
|
||||
PLL: d5 to 1
|
||||
2a to CLOCK_CTNL + 1
|
||||
PLL: 17 to 10
|
||||
1a to CLOCK_CTNL + 1
|
||||
PLL: c0 to 6
|
||||
0a to CLOCK_CTNL + 1
|
||||
PLL: 21 to 2
|
||||
16 to CLOCK_CTNL + 1
|
||||
PLL: 03 to 5
|
||||
12 to CLOCK_CTNL + 1
|
||||
PLL: 91 to 4
|
||||
0e to CLOCK_CTNL + 1
|
||||
PLL: 14 to 3
|
||||
2e to CLOCK_CTNL + 1
|
||||
PLL: 01 to 11
|
||||
32 to CLOCK_CTNL + 1
|
||||
PLL: a6 to 12
|
||||
32 to CLOCK_CTNL + 1
|
||||
PLL: e6 to 12
|
||||
32 to CLOCK_CTNL + 1
|
||||
PLL: a6 to 12
|
||||
2a to CLOCK_CTNL + 1
|
||||
PLL: 98 to 10
|
||||
2e to CLOCK_CTNL + 1
|
||||
PLL: 01 to 11
|
||||
18 to CLOCK_CTNL + 1
|
||||
Read PLL 6
|
||||
1a to CLOCK_CTNL + 1
|
||||
PLL: 80 to 6
|
||||
0a to CLOCK_CTNL + 1
|
||||
PLL: 24 to 2
|
||||
12 to CLOCK_CTNL + 1
|
||||
PLL: 9e to 4
|
||||
32 to CLOCK_CTNL + 1
|
||||
PLL: a6 to 12
|
||||
32 to CLOCK_CTNL + 1
|
||||
PLL: e6 to 12
|
||||
32 to CLOCK_CTNL + 1
|
||||
PLL: a6 to 12
|
||||
|
||||
*/
|
||||
92
src/devices/video/atirage.h
Normal file
92
src/devices/video/atirage.h
Normal file
@ -0,0 +1,92 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders: R. Belmont
|
||||
|
||||
#ifndef MAME_VIDEO_ATIRAGE_H
|
||||
#define MAME_VIDEO_ATIRAGE_H
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "machine/pci.h"
|
||||
#include "bus/isa/mach32.h"
|
||||
|
||||
class atirage_device : public pci_device
|
||||
{
|
||||
public:
|
||||
atirage_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
void mem_map(address_map &map);
|
||||
void io_map(address_map &map);
|
||||
void reg_map(address_map &map);
|
||||
|
||||
auto gpio_get_cb() { return read_gpio.bind(); }
|
||||
auto gpio_set_cb() { return write_gpio.bind(); }
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
|
||||
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
|
||||
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
|
||||
virtual void config_map(address_map &map) override;
|
||||
|
||||
required_device<mach64_device> m_mach64;
|
||||
required_device<screen_device> m_screen;
|
||||
|
||||
u8 m_regs0[0x400];
|
||||
u8 m_regs1[0x400];
|
||||
|
||||
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
private:
|
||||
devcb_read32 read_gpio;
|
||||
devcb_write32 write_gpio;
|
||||
|
||||
u32 m_user_cfg;
|
||||
u32 m_hres, m_vres, m_htotal, m_vtotal, m_format, m_pixel_clock;
|
||||
u8 m_dac_windex, m_dac_rindex, m_dac_state, m_dac_mask;
|
||||
u32 m_dac_colors[256];
|
||||
u8 m_pll_regs[16];
|
||||
|
||||
u8 regs_0_read(offs_t offset);
|
||||
void regs_0_write(offs_t offset, u8 data);
|
||||
u8 regs_1_read(offs_t offset);
|
||||
void regs_1_write(offs_t offset, u8 data);
|
||||
|
||||
u32 user_cfg_r();
|
||||
void user_cfg_w(u32 data);
|
||||
|
||||
void update_mode();
|
||||
};
|
||||
|
||||
class atirageii_device : public atirage_device
|
||||
{
|
||||
public:
|
||||
atirageii_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
};
|
||||
|
||||
class atirageiic_device : public atirage_device
|
||||
{
|
||||
public:
|
||||
atirageiic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
};
|
||||
|
||||
class atiragepro_device : public atirage_device
|
||||
{
|
||||
public:
|
||||
atiragepro_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(ATI_RAGEII, atirageii_device)
|
||||
DECLARE_DEVICE_TYPE(ATI_RAGEIIC, atirageiic_device)
|
||||
DECLARE_DEVICE_TYPE(ATI_RAGEPRO, atiragepro_device)
|
||||
|
||||
#endif
|
||||
@ -11,7 +11,7 @@
|
||||
|
||||
CPU: PowerPC 750 "G3" @ 233 MHz
|
||||
Memory controller/PCI bridge: Motorola MPC106 "Grackle"
|
||||
Video: ATI Rage II+, ATI Rage Pro on rev. B, ATI Rage Pro Turbo on rev. C
|
||||
Video: ATI Rage II, ATI Rage Pro on rev. B, ATI Rage Pro Turbo on rev. C
|
||||
I/O: Heathrow PCI I/O ASIC (see heathrow.cpp for details)
|
||||
|
||||
****************************************************************************/
|
||||
@ -24,6 +24,7 @@
|
||||
#include "machine/pci.h"
|
||||
#include "machine/pci-ide.h"
|
||||
#include "machine/ram.h"
|
||||
#include "video/atirage.h"
|
||||
#include "awacs_macrisc.h"
|
||||
#include "cuda.h"
|
||||
#include "heathrow.h"
|
||||
@ -42,13 +43,19 @@ public:
|
||||
required_device<macadb_device> m_macadb;
|
||||
required_device<dimm_spd_device> m_dimm0, m_dimm1, m_dimm2;
|
||||
required_device<ram_device> m_ram;
|
||||
required_device<atirage_device> m_atirage;
|
||||
|
||||
private:
|
||||
u32 m_sense;
|
||||
|
||||
void pwrmacg3_map(address_map &map);
|
||||
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
||||
u32 read_sense();
|
||||
void write_sense(u32 data);
|
||||
|
||||
WRITE_LINE_MEMBER(cuda_reset_w)
|
||||
{
|
||||
m_maincpu->set_input_line(INPUT_LINE_HALT, state);
|
||||
@ -70,12 +77,15 @@ pwrmacg3_state::pwrmacg3_state(const machine_config &mconfig, device_type type,
|
||||
m_dimm0(*this, "dimm0"),
|
||||
m_dimm1(*this, "dimm1"),
|
||||
m_dimm2(*this, "dimm2"),
|
||||
m_ram(*this, RAM_TAG)
|
||||
m_ram(*this, RAM_TAG),
|
||||
m_atirage(*this, "pci:12.0")
|
||||
{
|
||||
}
|
||||
|
||||
void pwrmacg3_state::machine_start()
|
||||
{
|
||||
m_sense = 0;
|
||||
|
||||
m_mpc106->set_ram_info((u8 *)m_ram->pointer(), m_ram->size());
|
||||
|
||||
// start off disabling all of the DIMMs
|
||||
@ -85,10 +95,6 @@ void pwrmacg3_state::machine_start()
|
||||
|
||||
switch (m_ram->size())
|
||||
{
|
||||
case 32*1024*1024:
|
||||
m_dimm0->set_dimm_size(dimm_spd_device::SIZE_32_MIB);
|
||||
break;
|
||||
|
||||
case 64*1024*1024:
|
||||
m_dimm0->set_dimm_size(dimm_spd_device::SIZE_64_MIB);
|
||||
break;
|
||||
@ -106,6 +112,8 @@ void pwrmacg3_state::machine_start()
|
||||
m_dimm0->set_dimm_size(dimm_spd_device::SIZE_256_MIB);
|
||||
break;
|
||||
}
|
||||
|
||||
save_item(NAME(m_sense));
|
||||
}
|
||||
|
||||
void pwrmacg3_state::machine_reset()
|
||||
@ -119,9 +127,20 @@ void pwrmacg3_state::pwrmacg3_map(address_map &map)
|
||||
map.unmap_value_high();
|
||||
}
|
||||
|
||||
u32 pwrmacg3_state::read_sense()
|
||||
{
|
||||
// ID as a 640x480 13" for now
|
||||
return (m_sense & 0xffff00ff) | (6 << 8);
|
||||
}
|
||||
|
||||
void pwrmacg3_state::write_sense(u32 data)
|
||||
{
|
||||
m_sense = data;
|
||||
}
|
||||
|
||||
void pwrmacg3_state::pwrmacg3(machine_config &config)
|
||||
{
|
||||
PPC740(config, m_maincpu, 66000000); // actually 233 MHz
|
||||
PPC750(config, m_maincpu, 66000000); // actually 233 MHz
|
||||
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &pwrmacg3_state::pwrmacg3_map);
|
||||
|
||||
@ -132,6 +151,12 @@ void pwrmacg3_state::pwrmacg3(machine_config &config)
|
||||
heathrow.set_maincpu_tag("maincpu");
|
||||
heathrow.set_pci_root_tag(":pci:00.0", AS_DATA);
|
||||
|
||||
// Apple's documentation says systems with the 4.0f2 ROM use a Rage II+, but
|
||||
// the 4.0f2 ROM won't init the Rage if the PCI ID is 4755 (II+), only 4754 (Rage II).
|
||||
atirage_device &ati(ATI_RAGEII(config, m_atirage, 14.318181_MHz_XTAL));
|
||||
ati.gpio_get_cb().set(FUNC(pwrmacg3_state::read_sense));
|
||||
ati.gpio_set_cb().set(FUNC(pwrmacg3_state::write_sense));
|
||||
|
||||
MACADB(config, m_macadb, 15.6672_MHz_XTAL);
|
||||
|
||||
CUDA(config, m_cuda, CUDA_341S0060);
|
||||
@ -170,8 +195,8 @@ void pwrmacg3_state::pwrmacg3(machine_config &config)
|
||||
m_dimm2->sda_callback().set(sda_merger, FUNC(input_merger_device::in_w<3>));
|
||||
|
||||
RAM(config, m_ram);
|
||||
m_ram->set_default_size("32M");
|
||||
m_ram->set_extra_options("32M,64M,96M,128M,256M");
|
||||
m_ram->set_default_size("64M");
|
||||
m_ram->set_extra_options("64M,96M,128M,256M");
|
||||
|
||||
screamer_device &screamer(SCREAMER(config, "codec", 45.1584_MHz_XTAL / 2));
|
||||
screamer.dma_output().set(heathrow, FUNC(heathrow_device::codec_dma_read));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user