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Removing old and duplicate code for genesis/megadrive from MAME (part 1)

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Also, moved some megaplay/megatech constant to a struct and refactored some code (work in progress)
This commit is contained in:
Fabio Priuli 2009-10-08 23:37:03 +00:00
parent 1801f68df1
commit 9debc2c5d0
8 changed files with 551 additions and 699 deletions
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168
src/mame/drivers/genesis.c
View File

@ -172,73 +172,6 @@ MACHINE_RESET( genesis )
timer_adjust_oneshot(scan_timer, video_screen_get_time_until_pos(machine->primary_screen, 0, 320), 0); timer_adjust_oneshot(scan_timer, video_screen_get_time_until_pos(machine->primary_screen, 0, 320), 0);
} }
/* from MESS */
READ16_HANDLER(genesis_ctrl_r)
{
/* int returnval; */
/* logerror("genesis_ctrl_r %x\n", offset); */
switch (offset)
{
case 0: /* DRAM mode is write only */
return 0xffff;
case 0x80: /* return Z80 CPU Function Stop Accessible or not */
/* logerror("Returning z80 state\n"); */
return (z80running ? 0x0100 : 0x0);
case 0x100: /* Z80 CPU Reset - write only */
return 0xffff;
}
return 0x00;
}
/* from MESS */
WRITE16_HANDLER(genesis_ctrl_w)
{
data &= mem_mask;
/* logerror("genesis_ctrl_w %x, %x\n", offset, data); */
switch (offset)
{
case 0: /* set DRAM mode... we have to ignore this for production cartridges */
return;
case 0x80: /* Z80 BusReq */
if (data == 0x100)
{
z80running = 0;
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE); /* halt Z80 */
/* logerror("z80 stopped by 68k BusReq\n"); */
}
else
{
z80running = 1;
// memory_set_bankptr(space->machine, 1, &genesis_z80_ram[0]);
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, CLEAR_LINE);
/* logerror("z80 started, BusReq ends\n"); */
}
return;
case 0x100: /* Z80 CPU Reset */
if (data == 0x00)
{
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE);
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_RESET, PULSE_LINE);
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE);
/* logerror("z80 reset, ram is %p\n", &genesis_z80_ram[0]); */
z80running = 0;
return;
}
else
{
/* logerror("z80 out of reset\n"); */
}
return;
}
}
READ16_HANDLER ( genesis_68k_to_z80_r ) READ16_HANDLER ( genesis_68k_to_z80_r )
{ {
offset *= 2; offset *= 2;
@ -282,58 +215,6 @@ READ16_HANDLER ( genesis_68k_to_z80_r )
return 0x0000; return 0x0000;
} }
READ16_HANDLER ( megaplay_68k_to_z80_r )
{
offset *= 2;
offset &= 0x7fff;
/* Shared Ram */
if ((offset >= 0x0000) && (offset <= 0x1fff))
{
offset &=0x1fff;
// logerror("soundram_r returning %x\n",(gen_z80_shared[offset] << 8) + gen_z80_shared[offset+1]);
return (genesis_z80_ram[offset] << 8) + genesis_z80_ram[offset+1];
}
if ((offset >= 0x2000) && (offset <= 0x3fff))
{
offset &=0x1fff;
// if(offset == 0) /* this read handler was used around MAME0.82 to read DSWB. Now it's (DSW0 & 0xff) */
// return (input_port_read(space->machine, "DSW0") << 8) ^ 0xff00;
return (ic36_ram[offset] << 8) + ic36_ram[offset+1];
}
/* YM2610 */
if ((offset >= 0x4000) && (offset <= 0x5fff))
{
if (ACCESSING_BITS_0_7)
offset += 1;
return ym3438_r(devtag_get_device(space->machine, "ym"), offset);
}
/* Bank Register */
if ((offset >= 0x6000) && (offset <= 0x60ff))
{
}
/* Unused / Illegal */
if ((offset >= 0x6100) && (offset <= 0x7eff))
{
/* nothing */
}
/* VDP */
if ((offset >= 0x7f00) && (offset <= 0x7fff))
{
}
return 0x0000;
}
WRITE16_HANDLER ( genesis_68k_to_z80_w ) WRITE16_HANDLER ( genesis_68k_to_z80_w )
{ {
offset *= 2; offset *= 2;
@ -417,55 +298,6 @@ $A1001F Port C serial control
*/ */
UINT16 *genesis_io_ram;
/* This handler is still used in hshavoc.c & topshoot.c ; */
/* megaplay.c uses a local copy 'OLD_megaplay_genesis_io_w' */
WRITE16_HANDLER ( genesis_io_w )
{
// logerror ("write io offset :%02x data %04x PC: 0x%06x\n",offset,data,cpu_get_previouspc(space->cpu));
switch (offset)
{
case 0x00:
/*??*/
break;
case 0x01:/* port A data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x04])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x04]));
break;
case 0x02: /* port B data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x05])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x05]));
break;
case 0x03: /* port C data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x06])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x06]));
bios_6204 = data & 0x07;
break;
case 0x04: /* port A control */
genesis_io_ram[offset] = data;
break;
case 0x05: /* port B control */
genesis_io_ram[offset] = data;
break;
case 0x06: /* port C control */
genesis_io_ram[offset] = data;
break;
case 0x07: /* port A TxData */
genesis_io_ram[offset] = data;
break;
default:
genesis_io_ram[offset] = data;
}
}
#if 0 #if 0
static ADDRESS_MAP_START( genesis_map, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( genesis_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x3fffff) AM_ROM /* Cartridge Program Rom */ AM_RANGE(0x000000, 0x3fffff) AM_ROM /* Cartridge Program Rom */

75
src/mame/drivers/hshavoc.c
View File

@ -45,6 +45,81 @@ Unfortunately it's read protected.
#define MASTER_CLOCK 53693100 #define MASTER_CLOCK 53693100
/* This should be replaced by the implementation in megadriv.c or by specific input code */
static UINT16 *genesis_io_ram;
static int z80running;
static WRITE16_HANDLER( genesis_io_w )
{
// logerror ("write io offset :%02x data %04x PC: 0x%06x\n",offset,data,cpu_get_previouspc(space->cpu));
switch (offset)
{
case 0x00:
/*??*/
break;
case 0x01:/* port A data */
case 0x02: /* port B data */
case 0x03: /* port C data */
genesis_io_ram[offset] = (data & (genesis_io_ram[offset + 3])) | (genesis_io_ram[offset] & ~(genesis_io_ram[offset + 3]));
break;
case 0x04: /* port A control */
case 0x05: /* port B control */
case 0x06: /* port C control */
case 0x07: /* port A TxData */
genesis_io_ram[offset] = data;
break;
default:
genesis_io_ram[offset] = data;
}
}
static WRITE16_HANDLER( genesis_ctrl_w )
{
data &= mem_mask;
/* logerror("genesis_ctrl_w %x, %x\n", offset, data); */
switch (offset)
{
case 0: /* set DRAM mode... we have to ignore this for production cartridges */
return;
case 0x80: /* Z80 BusReq */
if (data == 0x100)
{
z80running = 0;
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE); /* halt Z80 */
/* logerror("z80 stopped by 68k BusReq\n"); */
}
else
{
z80running = 1;
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, CLEAR_LINE);
/* logerror("z80 started, BusReq ends\n"); */
}
return;
case 0x100: /* Z80 CPU Reset */
if (data == 0x00)
{
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE);
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_RESET, PULSE_LINE);
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE);
/* logerror("z80 reset, ram is %p\n", &genesis_z80_ram[0]); */
z80running = 0;
return;
}
else
{
/* logerror("z80 out of reset\n"); */
}
return;
}
}
static INPUT_PORTS_START( hshavoc ) static INPUT_PORTS_START( hshavoc )
PORT_START("IN0") /* 16bit */ PORT_START("IN0") /* 16bit */
PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Unknown ) ) PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Unknown ) )

54
src/mame/drivers/megadriv.c
View File

@ -1484,7 +1484,7 @@ void (*megadrive_io_write_data_port_ptr)(running_machine *machine, int offset, U
*/ */
static INPUT_PORTS_START( md_common ) INPUT_PORTS_START( md_common )
PORT_START("PAD1") /* Joypad 1 (3 button + start) NOT READ DIRECTLY */ PORT_START("PAD1") /* Joypad 1 (3 button + start) NOT READ DIRECTLY */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1) PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1) PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
@ -1920,7 +1920,6 @@ static void megadrive_io_write_sctrl_port(running_machine *machine, int portnum,
} }
static WRITE16_HANDLER( megadriv_68k_io_write ) static WRITE16_HANDLER( megadriv_68k_io_write )
{ {
// mame_printf_debug("IO Write #%02x data %04x mem_mask %04x\n",offset,data,mem_mask); // mame_printf_debug("IO Write #%02x data %04x mem_mask %04x\n",offset,data,mem_mask);
@ -2327,6 +2326,51 @@ static ADDRESS_MAP_START( megadriv_z80_io_map, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x0000 , 0xff) AM_NOP AM_RANGE(0x0000 , 0xff) AM_NOP
ADDRESS_MAP_END ADDRESS_MAP_END
/***************************** Megaplay *****************************/
/* Megaplay BIOS handles regs[2] at start in a different way. */
/* other io data/ctrl regs are dealt with exactly like in megadrive */
READ8_HANDLER( megaplay_bios_6402_r )
{
return megadrive_io_data_regs[2];// & 0xfe;
}
WRITE8_HANDLER( megaplay_bios_6402_w )
{
megadrive_io_data_regs[2] = (megadrive_io_data_regs[2] & 0x07) | ((data & 0x70) >> 1);
// logerror("BIOS: 0x6402 write: 0x%02x\n", data);
}
READ8_HANDLER( megaplay_bios_6204_r )
{
return (megadrive_io_data_regs[2]);
// return (mplay_bios.bios_width & 0xf8) + (mplay_bios.bios_6204 & 0x07);
}
WRITE8_HANDLER( megaplay_bios_width_w )
{
mplay_bios.bios_width = data;
megadrive_io_data_regs[2] = (megadrive_io_data_regs[2] & 0x07) | ((data & 0xf8));
// logerror("BIOS: 0x6204 - Width write: %02x\n", data);
}
WRITE16_HANDLER( megaplay_io_write )
{
if (offset == 0x03)
megadrive_io_data_regs[2] = (data & megadrive_io_ctrl_regs[2]) | (megadrive_io_data_regs[2] & ~megadrive_io_ctrl_regs[2]);
else
megadriv_68k_io_write(space, offset & 0x1f, data, 0xffff);
}
READ16_HANDLER( megaplay_io_read )
{
if (offset == 0x03)
return megadrive_io_data_regs[2];
else
return megadriv_68k_io_read(space, offset & 0x1f, 0xffff);
}
/****************************************** 32X related ******************************************/ /****************************************** 32X related ******************************************/
/**********************************************************************************************/ /**********************************************************************************************/
@ -6344,6 +6388,12 @@ DRIVER_INIT( megadrie )
hazemdchoice_megadriv_framerate = 50; hazemdchoice_megadriv_framerate = 50;
} }
DRIVER_INIT( mpnew )
{
DRIVER_INIT_CALL(megadrij);
megadrive_io_read_data_port_ptr = megadrive_io_read_data_port_3button;
megadrive_io_write_data_port_ptr = megadrive_io_write_data_port_3button;
}
/* used by megatech */ /* used by megatech */
static READ8_HANDLER( z80_unmapped_port_r ) static READ8_HANDLER( z80_unmapped_port_r )

49
src/mame/drivers/megadriv.h
View File

@ -3,7 +3,9 @@ extern DRIVER_INIT( megadrie );
extern DRIVER_INIT( megadriv ); extern DRIVER_INIT( megadriv );
extern DRIVER_INIT( megadrij ); extern DRIVER_INIT( megadrij );
extern DRIVER_INIT( _32x ); extern DRIVER_INIT( _32x );
extern DRIVER_INIT( mpnew );
INPUT_PORTS_EXTERN( md_common );
INPUT_PORTS_EXTERN( megadriv ); INPUT_PORTS_EXTERN( megadriv );
INPUT_PORTS_EXTERN( aladbl ); INPUT_PORTS_EXTERN( aladbl );
INPUT_PORTS_EXTERN( megadri6 ); INPUT_PORTS_EXTERN( megadri6 );
@ -33,6 +35,7 @@ extern READ8_HANDLER (megatech_sms_ioport_dd_r);
extern READ16_HANDLER( megadriv_vdp_r ); extern READ16_HANDLER( megadriv_vdp_r );
extern WRITE16_HANDLER( megadriv_vdp_w ); extern WRITE16_HANDLER( megadriv_vdp_w );
MACHINE_RESET( megadriv ); MACHINE_RESET( megadriv );
VIDEO_START( megadriv ); VIDEO_START( megadriv );
VIDEO_UPDATE( megadriv ); VIDEO_UPDATE( megadriv );
@ -56,3 +59,49 @@ extern int segac2_sp_pal_lookup[4];
extern int genvdp_use_cram; extern int genvdp_use_cram;
extern int genesis_always_irq6; extern int genesis_always_irq6;
extern int genesis_other_hacks; extern int genesis_other_hacks;
// megaplay & megatech
READ8_HANDLER( megaplay_bios_6402_r );
WRITE8_HANDLER( megaplay_bios_6402_w );
READ8_HANDLER( megaplay_bios_6204_r );
WRITE8_HANDLER( megaplay_bios_width_w );
WRITE16_HANDLER( megaplay_io_write );
READ16_HANDLER( megaplay_io_read );
/* Megaplay BIOS specific */
#define MP_ROM 0x10
#define MP_GAME 0
struct _mplay_bios /* once all the regs are saved in this structure, it would be better to reorganize it a bit... */
{
UINT32 bios_mode; // determines whether ROM banks or Game data
// is to read from 0x8000-0xffff
UINT32 bios_bank; // ROM bank selection
UINT16 game_banksel; // Game bank selection
UINT32 readpos; // serial bank selection position (9-bit)
UINT32 mp_bios_bank_addr;
UINT32 bios_width; // determines the way the game info ROM is read
UINT8 bios_ctrl[6];
UINT8 bios_6600;
UINT8 bios_6403;
UINT8 bios_6404;
};
extern struct _mplay_bios mplay_bios; // defined in megaplay.c
struct _mtech_bios /* once all the regs are saved in this structure, it would be better to reorganize it a bit... */
{
UINT8 mt_cart_select_reg;
UINT32 bios_port_ctrl;
int current_game_is_sms; // is the current game SMS based (running on genesis z80, in VDP compatibility mode)
UINT32 bios_ctrl_inputs;
UINT8 bios_ctrl[6];
int mt_bank_bank_pos;
int mt_bank_partial;
int mt_bank_addr;
};

303
src/mame/drivers/megaplay.c
View File

@ -54,28 +54,15 @@ Bugs:
#include "sound/sn76496.h" #include "sound/sn76496.h"
#include "deprecat.h" #include "deprecat.h"
#include "genesis.h"
#include "megadriv.h" #include "megadriv.h"
#include "segamsys.h" #include "segamsys.h"
#define MASTER_CLOCK 53693100 #define MASTER_CLOCK 53693100
/* Megaplay BIOS specific */
#define MP_ROM 0x10
#define MP_GAME 0
static UINT32 bios_bank; // ROM bank selection struct _mplay_bios mplay_bios;
static UINT16 game_banksel; // Game bank selection static UINT16 *genesis_io_ram;
static UINT32 bios_mode = MP_ROM; // determines whether ROM banks or Game data
// is to read from 0x8000-0xffff
static UINT32 mp_bios_bank_addr;
static UINT32 bios_width; // determines the way the game info ROM is read
UINT8 bios_ctrl[6];
static UINT8 bios_6600;
UINT8 bios_6204;
static UINT8 bios_6403;
static UINT8 bios_6404;
static UINT8* ic3_ram; static UINT8* ic3_ram;
static UINT8* ic37_ram; static UINT8* ic37_ram;
@ -132,48 +119,8 @@ static INTERRUPT_GEN (megaplay_bios_irq)
} }
#endif #endif
static UINT32 readpos = 1; // serial bank selection position (9-bit)
static INPUT_PORTS_START ( megaplay ) static INPUT_PORTS_START ( megaplay )
PORT_START("P1_1") /* Player 1 Controls - part 1 */ PORT_INCLUDE( md_common )
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("P1_2") /* Player 1 Controls - part 2 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("P2_1") /* Player 2 Controls - part 1 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("P2_2") /* Player 2 Controls - part 2 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("TEST") PORT_START("TEST")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Select") PORT_CODE(KEYCODE_0) PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Select") PORT_CODE(KEYCODE_0)
@ -442,7 +389,7 @@ INPUT_PORTS_END
static READ8_HANDLER( megaplay_bios_banksel_r ) static READ8_HANDLER( megaplay_bios_banksel_r )
{ {
return bios_bank; return mplay_bios.bios_bank;
} }
static WRITE8_HANDLER( megaplay_bios_banksel_w ) static WRITE8_HANDLER( megaplay_bios_banksel_w )
@ -452,155 +399,50 @@ static WRITE8_HANDLER( megaplay_bios_banksel_w )
It should be possible to multiplex different game ROMs at It should be possible to multiplex different game ROMs at
0x000000-0x3fffff based on these bits. 0x000000-0x3fffff based on these bits.
*/ */
bios_bank = data; mplay_bios.bios_bank = data;
bios_mode = MP_ROM; mplay_bios.bios_mode = MP_ROM;
// logerror("BIOS: ROM bank %i selected [0x%02x]\n",bios_bank >> 6, data); // logerror("BIOS: ROM bank %i selected [0x%02x]\n",bios_bank >> 6, data);
} }
static READ8_HANDLER( megaplay_bios_gamesel_r ) static READ8_HANDLER( megaplay_bios_gamesel_r )
{ {
return bios_6403; return mplay_bios.bios_6403;
} }
static WRITE8_HANDLER( megaplay_bios_gamesel_w ) static WRITE8_HANDLER( megaplay_bios_gamesel_w )
{ {
bios_6403 = data; mplay_bios.bios_6403 = data;
// logerror("BIOS: 0x6403 write: 0x%02x\n",data); // logerror("BIOS: 0x6403 write: 0x%02x\n",data);
bios_mode = data & 0x10; mplay_bios.bios_mode = data & 0x10;
} }
/* Old code, todo, update the new code instead */
static READ16_HANDLER ( OLD_megaplay_genesis_io_r )
{
/* 8-bit only, data is mirrored in both halves */
UINT8 return_value = 0;
switch (offset)
{
case 0:
/* Charles MacDonald ( http://cgfm2.emuviews.com/ )
D7 : Console is 1= Export (USA, Europe, etc.) 0= Domestic (Japan)
D6 : Video type is 1= PAL, 0= NTSC
D5 : Sega CD unit is 1= not present, 0= connected.
D4 : Unused (always returns zero)
D3 : Bit 3 of version number
D2 : Bit 2 of version number
D1 : Bit 1 of version number
D0 : Bit 0 of version number
*/
return_value = 0x80; /* ? megatech is usa? */
break;
case 1: /* port A data (joypad 1) */
if (genesis_io_ram[offset] & 0x40)
return_value = input_port_read(space->machine, "P1_1") & (genesis_io_ram[4]^0xff);
else
{
return_value = input_port_read(space->machine, "P1_2") & (genesis_io_ram[4]^0xff);
return_value |= input_port_read(space->machine, "P1_1") & 0x03;
}
return_value = (genesis_io_ram[offset] & 0x80) | return_value;
// logerror ("reading joypad 1 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
break;
case 2: /* port B data (joypad 2) */
if (genesis_io_ram[offset] & 0x40)
return_value = input_port_read(space->machine, "P2_1") & (genesis_io_ram[5]^0xff);
else
{
return_value = input_port_read(space->machine, "P2_2") & (genesis_io_ram[5]^0xff);
return_value |= input_port_read(space->machine, "P2_1") & 0x03;
}
return_value = (genesis_io_ram[offset] & 0x80) | return_value;
// logerror ("reading joypad 2 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
break;
// case 3: /* port C data */
// return_value = bios_6402 << 3;
// break;
default:
return_value = genesis_io_ram[offset];
}
return return_value | return_value << 8;
}
static WRITE16_HANDLER ( OLD_megaplay_genesis_io_w )
{
// logerror ("write io offset :%02x data %04x PC: 0x%06x\n",offset,data,cpu_get_previouspc(space->cpu));
switch (offset)
{
case 0x00:
/*??*/
break;
case 0x01:/* port A data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x04])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x04]));
break;
case 0x02: /* port B data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x05])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x05]));
break;
case 0x03: /* port C data */
genesis_io_ram[offset] = (data & (genesis_io_ram[0x06])) | (genesis_io_ram[offset] & ~(genesis_io_ram[0x06]));
bios_6204 = data & 0x07;
break;
case 0x04: /* port A control */
genesis_io_ram[offset] = data;
break;
case 0x05: /* port B control */
genesis_io_ram[offset] = data;
break;
case 0x06: /* port C control */
genesis_io_ram[offset] = data;
break;
case 0x07: /* port A TxData */
genesis_io_ram[offset] = data;
break;
default:
genesis_io_ram[offset] = data;
}
}
static READ8_HANDLER( bank_r ) static READ8_HANDLER( bank_r )
{ {
UINT32 fulladdress; UINT32 fulladdress;
UINT8* bank = memory_region(space->machine, "mtbios"); UINT8* bank = memory_region(space->machine, "mtbios");
fulladdress = mp_bios_bank_addr + offset; fulladdress = mplay_bios.mp_bios_bank_addr + offset;
if ((fulladdress >= 0x000000) && (fulladdress <= 0x3fffff)) // ROM Addresses if ((fulladdress >= 0x000000) && (fulladdress <= 0x3fffff)) // ROM Addresses
{ {
if(bios_mode & MP_ROM) if (mplay_bios.bios_mode & MP_ROM)
{ {
int sel = (bios_bank >> 6) & 0x03; int sel = (mplay_bios.bios_bank >> 6) & 0x03;
if (sel == 0) if (sel == 0)
return 0xff; return 0xff;
else else
return bank[0x10000 + (sel - 1) * 0x8000 + offset]; return bank[0x10000 + (sel - 1) * 0x8000 + offset];
} }
else if(bios_width & 0x08) else if (mplay_bios.bios_width & 0x08)
{ {
if(offset >= 0x2000) if(offset >= 0x2000)
return ic36_ram[offset - 0x2000]; return ic36_ram[offset - 0x2000];
else else
return ic37_ram[(0x2000 * (bios_bank & 0x03)) + offset]; return ic37_ram[(0x2000 * (mplay_bios.bios_bank & 0x03)) + offset];
} }
else else
{ {
@ -609,7 +451,7 @@ static READ8_HANDLER( bank_r )
} }
else if (fulladdress >= 0xa10000 && fulladdress <= 0xa1001f) // IO Acess else if (fulladdress >= 0xa10000 && fulladdress <= 0xa1001f) // IO Acess
{ {
return OLD_megaplay_genesis_io_r(space, (offset & 0x1f) / 2, 0xffff); return megaplay_io_read(space, (offset & 0x1f) / 2, 0xffff);
} }
else else
{ {
@ -622,16 +464,16 @@ static READ8_HANDLER( bank_r )
static WRITE8_HANDLER( bank_w ) static WRITE8_HANDLER( bank_w )
{ {
UINT32 fulladdress; UINT32 fulladdress;
fulladdress = mp_bios_bank_addr + offset; fulladdress = mplay_bios.mp_bios_bank_addr + offset;
if ((fulladdress >= 0x000000) && (fulladdress <= 0x3fffff)) // ROM / Megaplay Custom Addresses if ((fulladdress >= 0x000000) && (fulladdress <= 0x3fffff)) // ROM / Megaplay Custom Addresses
{ {
if(offset <= 0x1fff && (bios_width & 0x08)) if (offset <= 0x1fff && (mplay_bios.bios_width & 0x08))
{ {
ic37_ram[(0x2000 * (bios_bank & 0x03)) + offset] = data; ic37_ram[(0x2000 * (mplay_bios.bios_bank & 0x03)) + offset] = data;
} }
if(offset >= 0x2000 && (bios_width & 0x08)) if(offset >= 0x2000 && (mplay_bios.bios_width & 0x08))
{ {
// ic36_ram[offset] = data; // ic36_ram[offset] = data;
ic36_ram[offset - 0x2000] = data; ic36_ram[offset - 0x2000] = data;
@ -639,7 +481,7 @@ static WRITE8_HANDLER ( bank_w )
} }
else if (fulladdress >= 0xa10000 && fulladdress <=0xa1001f) // IO Access else if (fulladdress >= 0xa10000 && fulladdress <=0xa1001f) // IO Access
{ {
OLD_megaplay_genesis_io_w(space, (offset & 0x1f) / 2, data, 0xffff); megaplay_io_write(space, (offset & 0x1f) / 2, data, 0xffff);
} }
else else
{ {
@ -648,84 +490,56 @@ static WRITE8_HANDLER ( bank_w )
} }
static READ8_HANDLER( megaplay_bios_6402_r )
{
return genesis_io_ram[3];// & 0xfe;
// return bios_6402;// & 0xfe;
}
static WRITE8_HANDLER( megaplay_bios_6402_w )
{
genesis_io_ram[3] = (genesis_io_ram[3] & 0x07) | ((data & 0x70) >> 1);
// bios_6402 = (data >> 4) & 0x07;
// logerror("BIOS: 0x6402 write: 0x%02x\n",data);
}
static READ8_HANDLER( megaplay_bios_6404_r ) static READ8_HANDLER( megaplay_bios_6404_r )
{ {
// logerror("BIOS: 0x6404 read: returned 0x%02x\n",bios_6404 | (bios_6403 & 0x10) >> 4); // logerror("BIOS: 0x6404 read: returned 0x%02x\n",bios_6404 | (bios_6403 & 0x10) >> 4);
return (bios_6404 & 0xfe) | ((bios_6403 & 0x10) >> 4); return (mplay_bios.bios_6404 & 0xfe) | ((mplay_bios.bios_6403 & 0x10) >> 4);
// return bios_6404 | (bios_6403 & 0x10) >> 4; // return mplay_bios.bios_6404 | (mplay_bios.bios_6403 & 0x10) >> 4;
} }
static WRITE8_HANDLER( megaplay_bios_6404_w ) static WRITE8_HANDLER( megaplay_bios_6404_w )
{ {
if(((bios_6404 & 0x0c) == 0x00) && ((data & 0x0c) == 0x0c)) if(((mplay_bios.bios_6404 & 0x0c) == 0x00) && ((data & 0x0c) == 0x0c))
cputag_set_input_line(space->machine, "maincpu", INPUT_LINE_RESET, PULSE_LINE); cputag_set_input_line(space->machine, "maincpu", INPUT_LINE_RESET, PULSE_LINE);
bios_6404 = data; mplay_bios.bios_6404 = data;
// logerror("BIOS: 0x6404 write: 0x%02x\n", data); // logerror("BIOS: 0x6404 write: 0x%02x\n", data);
} }
static READ8_HANDLER( megaplay_bios_6204_r )
{
return (genesis_io_ram[3]);
// return (bios_width & 0xf8) + (bios_6204 & 0x07);
}
static WRITE8_HANDLER( megaplay_bios_width_w )
{
bios_width = data;
genesis_io_ram[3] = (genesis_io_ram[3] & 0x07) | ((data & 0xf8));
// logerror("BIOS: 0x6204 - Width write: %02x\n",data);
}
static READ8_HANDLER( megaplay_bios_6600_r ) static READ8_HANDLER( megaplay_bios_6600_r )
{ {
/* Multi-slot note: /* Multi-slot note:
0x6600 appears to be used to check for extra slots being used. 0x6600 appears to be used to check for extra slots being used.
Enter the following line in place of the return statement in this Enter the following line in place of the return statement in this
function to make the BIOS check all 4 slots (3 and 4 will be "not used") function to make the BIOS check all 4 slots (3 and 4 will be "not used")
return (bios_6600 & 0xfe) | (bios_bank & 0x01); return (mplay_bios.bios_6600 & 0xfe) | (mplay_bios.bios_bank & 0x01);
*/ */
return bios_6600;// & 0xfe; return mplay_bios.bios_6600;// & 0xfe;
} }
static WRITE8_HANDLER( megaplay_bios_6600_w ) static WRITE8_HANDLER( megaplay_bios_6600_w )
{ {
bios_6600 = data; mplay_bios.bios_6600 = data;
// logerror("BIOS: 0x6600 write: 0x%02x\n",data); // logerror("BIOS: 0x6600 write: 0x%02x\n",data);
} }
static WRITE8_HANDLER( megaplay_game_w ) static WRITE8_HANDLER( megaplay_game_w )
{ {
if(readpos == 1) if (mplay_bios.readpos == 1)
game_banksel = 0; mplay_bios.game_banksel = 0;
game_banksel |= (1 << (readpos-1)) * (data & 0x01); mplay_bios.game_banksel |= (1 << (mplay_bios.readpos - 1)) * (data & 0x01);
readpos++; mplay_bios.readpos++;
if(readpos > 9)
if (mplay_bios.readpos > 9)
{ {
bios_mode = MP_GAME; mplay_bios.bios_mode = MP_GAME;
readpos = 1; mplay_bios.readpos = 1;
// popmessage("Game bank selected: 0x%03x",game_banksel); // popmessage("Game bank selected: 0x%03x", mplay_bios.game_banksel);
logerror("BIOS [0x%04x]: 68K address space bank selected: 0x%03x\n",cpu_get_previouspc(space->cpu),game_banksel); logerror("BIOS [0x%04x]: 68K address space bank selected: 0x%03x\n", cpu_get_previouspc(space->cpu), mplay_bios.game_banksel);
} }
mp_bios_bank_addr = ( ( mp_bios_bank_addr >> 1 ) | ( data << 23 ) ) & 0xff8000; mplay_bios.mp_bios_bank_addr = ((mplay_bios.mp_bios_bank_addr >> 1) | (data << 23)) & 0xff8000;
} }
static ADDRESS_MAP_START( megaplay_bios_map, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( megaplay_bios_map, ADDRESS_SPACE_PROGRAM, 8 )
@ -754,33 +568,6 @@ UINT8 segae_vdp_data_r ( UINT8 chip );
void segae_vdp_ctrl_w ( UINT8 chip, UINT8 data ); void segae_vdp_ctrl_w ( UINT8 chip, UINT8 data );
void segae_vdp_data_w ( running_machine *machine, UINT8 chip, UINT8 data ); void segae_vdp_data_w ( running_machine *machine, UINT8 chip, UINT8 data );
#if 0
static READ8_HANDLER (megaplay_bios_port_be_bf_r)
{
UINT8 temp = 0;
switch (offset)
{
case 0: /* port 0xbe, VDP 1 DATA Read */
temp = segae_vdp_data_r(0); break ;
case 1: /* port 0xbf, VDP 1 CTRL Read */
temp = segae_vdp_ctrl_r(0); break ;
}
return temp;
}
static WRITE8_HANDLER (megaplay_bios_port_be_bf_w)
{
switch (offset)
{
case 0: /* port 0xbe, VDP 1 DATA Write */
segae_vdp_data_w(space->machine, 0, data); break;
case 1: /* port 0xbf, VDP 1 CTRL Write */
segae_vdp_ctrl_w(0, data); break;
}
}
#endif
static ADDRESS_MAP_START( megaplay_bios_io_map, ADDRESS_SPACE_IO, 8 ) static ADDRESS_MAP_START( megaplay_bios_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff) ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x7f, 0x7f) AM_DEVWRITE("sn2", sn76496_w) /* SN76489 */ AM_RANGE(0x7f, 0x7f) AM_DEVWRITE("sn2", sn76496_w) /* SN76489 */
@ -811,7 +598,9 @@ static VIDEO_UPDATE(megplay)
//extern VIDEO_EOF(megadriv); //extern VIDEO_EOF(megadriv);
static MACHINE_RESET( mpnew ) static MACHINE_RESET( mpnew )
{ {
mp_bios_bank_addr = 0; mplay_bios.bios_mode = MP_ROM;
mplay_bios.mp_bios_bank_addr = 0;
mplay_bios.readpos = 1;
MACHINE_RESET_CALL(megadriv); MACHINE_RESET_CALL(megadriv);
MACHINE_RESET_CALL(megatech_bios); MACHINE_RESET_CALL(megatech_bios);
} }
@ -1005,7 +794,7 @@ ROM_START( mp_shnb3 ) /* Shinobi 3 */
ROM_END ROM_END
static void megplay_stat(running_machine *machine) static void mplay_start(running_machine *machine)
{ {
UINT8 *src = memory_region(machine, "mtbios"); UINT8 *src = memory_region(machine, "mtbios");
UINT8 *instruction_rom = memory_region(machine, "user1"); UINT8 *instruction_rom = memory_region(machine, "user1");
@ -1058,11 +847,12 @@ static DRIVER_INIT (megaplay)
ic37_ram = auto_alloc_array(machine, UINT8, 0x10000); ic37_ram = auto_alloc_array(machine, UINT8, 0x10000);
genesis_io_ram = auto_alloc_array(machine, UINT16, 0x20 / 2); genesis_io_ram = auto_alloc_array(machine, UINT16, 0x20 / 2);
DRIVER_INIT_CALL(megadrij); DRIVER_INIT_CALL(mpnew);
megplay_stat(machine);
mplay_start(machine);
/* for now ... */ /* for now ... */
memory_install_readwrite16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa10000, 0xa1001f, 0, 0, OLD_megaplay_genesis_io_r, OLD_megaplay_genesis_io_w); memory_install_readwrite16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa10000, 0xa1001f, 0, 0, megaplay_io_read, megaplay_io_write);
/* megaplay has ram shared with the bios cpu here */ /* megaplay has ram shared with the bios cpu here */
memory_install_readwrite8_handler(cputag_get_address_space(machine, "genesis_snd_z80", ADDRESS_SPACE_PROGRAM), 0x2000, 0x3fff, 0, 0, (read8_space_func)SMH_BANK(7), (write8_space_func)SMH_BANK(7)); memory_install_readwrite8_handler(cputag_get_address_space(machine, "genesis_snd_z80", ADDRESS_SPACE_PROGRAM), 0x2000, 0x3fff, 0, 0, (read8_space_func)SMH_BANK(7), (write8_space_func)SMH_BANK(7));
@ -1126,4 +916,3 @@ system16.com lists 'Streets of Rage' but this seems unlikely, there are no gaps
the numbering prior to 'Streets of Rage 2' the numbering prior to 'Streets of Rage 2'
*/ */

68
src/mame/drivers/megatech.c
View File

@ -92,14 +92,12 @@ Sonic Hedgehog 2 171-6215A 837-6963-62 610-0239-62 MPR
#include "rendlay.h" #include "rendlay.h"
#include "segamsys.h" #include "segamsys.h"
#include "genesis.h"
#include "megadriv.h" #include "megadriv.h"
static struct _mtech_bios mtech_bios;
/* Megatech BIOS specific */ /* Megatech BIOS specific */
static UINT32 bios_port_ctrl;
static UINT8* megatech_banked_ram; static UINT8* megatech_banked_ram;
static int current_game_is_sms; // is the current game SMS based (running on genesis z80, in VDP compatibility mode)
UINT32 bios_ctrl_inputs;
#define MASTER_CLOCK 53693100 #define MASTER_CLOCK 53693100
@ -232,8 +230,6 @@ INPUT_PORTS_END
/* MEGATECH specific */ /* MEGATECH specific */
static UINT8 mt_cart_select_reg;
static READ8_HANDLER( megatech_instr_r ) static READ8_HANDLER( megatech_instr_r )
{ {
UINT8* instr = memory_region(space->machine, "mtbios") + 0x8000; UINT8* instr = memory_region(space->machine, "mtbios") + 0x8000;
@ -245,7 +241,7 @@ static READ8_HANDLER( megatech_instr_r )
static READ8_HANDLER( megatech_cart_select_r ) static READ8_HANDLER( megatech_cart_select_r )
{ {
return (mt_cart_select_reg); return mtech_bios.mt_cart_select_reg;
} }
#ifdef UNUSED_FUNCTION #ifdef UNUSED_FUNCTION
@ -298,7 +294,7 @@ static void megatech_select_game(running_machine *machine, int gameno)
if (bios_region[0x8000]==2) if (bios_region[0x8000]==2)
{ {
printf("SMS cart!!, CPU not running\n"); printf("SMS cart!!, CPU not running\n");
current_game_is_sms = 1; mtech_bios.current_game_is_sms = 1;
megatech_set_genz80_as_sms_standard_map(machine, "genesis_snd_z80", MAPPER_STANDARD); megatech_set_genz80_as_sms_standard_map(machine, "genesis_snd_z80", MAPPER_STANDARD);
cputag_set_input_line(machine, "genesis_snd_z80", INPUT_LINE_HALT, CLEAR_LINE); cputag_set_input_line(machine, "genesis_snd_z80", INPUT_LINE_HALT, CLEAR_LINE);
cputag_set_input_line(machine, "genesis_snd_z80", INPUT_LINE_RESET, CLEAR_LINE); cputag_set_input_line(machine, "genesis_snd_z80", INPUT_LINE_RESET, CLEAR_LINE);
@ -308,7 +304,7 @@ static void megatech_select_game(running_machine *machine, int gameno)
else if (bios_region[0x8000]==1) else if (bios_region[0x8000]==1)
{ {
printf("Genesis Cart, CPU0 running\n"); printf("Genesis Cart, CPU0 running\n");
current_game_is_sms = 0; mtech_bios.current_game_is_sms = 0;
megatech_set_megadrive_z80_as_megadrive_z80(machine, "genesis_snd_z80"); megatech_set_megadrive_z80_as_megadrive_z80(machine, "genesis_snd_z80");
cputag_set_input_line(machine, "maincpu", INPUT_LINE_RESET, CLEAR_LINE); cputag_set_input_line(machine, "maincpu", INPUT_LINE_RESET, CLEAR_LINE);
cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, CLEAR_LINE); cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, CLEAR_LINE);
@ -342,23 +338,23 @@ static WRITE8_HANDLER( megatech_cart_select_w )
// printf("megatech_instr_w %02x\n",data); // printf("megatech_instr_w %02x\n",data);
mt_cart_select_reg = data; mtech_bios.mt_cart_select_reg = data;
megatech_select_game(space->machine, mt_cart_select_reg); megatech_select_game(space->machine, mtech_bios.mt_cart_select_reg);
/* /*
if (mt_cart_select_reg==2) if (mtech_bios.mtech_bios.mt_cart_select_reg == 2)
{ {
printf("game 2 selected\n"); printf("game 2 selected\n");
memcpy(memory_region(space->machine, "mtbios") + 0x8000, memory_region(space->machine, "inst0"), 0x8000); memcpy(memory_region(space->machine, "mtbios") + 0x8000, memory_region(space->machine, "inst0"), 0x8000);
} }
// else if (mt_cart_select_reg==0) // else if (mtech_bios.mt_cart_select_reg == 0)
// { // {
// printf("game 0 selected\n"); // printf("game 0 selected\n");
// memcpy(memory_region(space->machine, "mtbios") + 0x8000, memory_region(space->machine, "inst2"), 0x8000); // memcpy(memory_region(space->machine, "mtbios") + 0x8000, memory_region(space->machine, "inst2"), 0x8000);
// } // }
else if (mt_cart_select_reg==6) else if (mtech_bios.mt_cart_select_reg == 6)
{ {
printf("game 6 selected\n"); printf("game 6 selected\n");
memcpy(memory_region(space->machine, "mtbios") + 0x8000, memory_region(space->machine, "user6"), 0x8000); memcpy(memory_region(space->machine, "mtbios") + 0x8000, memory_region(space->machine, "user6"), 0x8000);
@ -378,54 +374,50 @@ static READ8_HANDLER( bios_ctrl_r )
if(offset == 0) if(offset == 0)
return 0; return 0;
if(offset == 2) if(offset == 2)
return bios_ctrl[offset] & 0xfe; return mtech_bios.bios_ctrl[offset] & 0xfe;
return bios_ctrl[offset]; return mtech_bios.bios_ctrl[offset];
} }
static WRITE8_HANDLER( bios_ctrl_w ) static WRITE8_HANDLER( bios_ctrl_w )
{ {
if(offset == 1) if(offset == 1)
{ {
bios_ctrl_inputs = data & 0x04; // Genesis/SMS input ports disable bit mtech_bios.bios_ctrl_inputs = data & 0x04; // Genesis/SMS input ports disable bit
} }
bios_ctrl[offset] = data; mtech_bios.bios_ctrl[offset] = data;
} }
static int mt_bank_bank_pos = 0;
static int mt_bank_partial = 0;
static int mt_bank_addr = 0;
/* this sets 0x300000 which may indicate that the 68k can see the instruction rom /* this sets 0x300000 which may indicate that the 68k can see the instruction rom
there, this limiting the max game rom capacity to 3meg. */ there, this limiting the max game rom capacity to 3meg. */
static WRITE8_HANDLER (mt_z80_bank_w) static WRITE8_HANDLER (mt_z80_bank_w)
{ {
mt_bank_partial |= (data & 0x01)<<23; // add new bit to partial address mtech_bios.mt_bank_partial |= (data & 0x01) << 23; // add new bit to partial address
mt_bank_bank_pos++; mtech_bios.mt_bank_bank_pos++;
if (mt_bank_bank_pos<9) if (mtech_bios.mt_bank_bank_pos < 9)
{ {
mt_bank_partial >>= 1; mtech_bios.mt_bank_partial >>= 1;
} }
else else
{ {
mt_bank_bank_pos = 0; mtech_bios.mt_bank_bank_pos = 0;
mt_bank_addr = mt_bank_partial; mtech_bios.mt_bank_addr = mtech_bios.mt_bank_partial;
mt_bank_partial = 0; mtech_bios.mt_bank_partial = 0;
printf("MT z80 bank set to %08x\n",mt_bank_addr); printf("MT z80 bank set to %08x\n", mtech_bios.mt_bank_addr);
} }
} }
static READ8_HANDLER( megatech_banked_ram_r ) static READ8_HANDLER( megatech_banked_ram_r )
{ {
return megatech_banked_ram[offset + 0x1000 * (mt_cart_select_reg&0x7) ]; return megatech_banked_ram[offset + 0x1000 * (mtech_bios.mt_cart_select_reg & 0x07)];
} }
static WRITE8_HANDLER( megatech_banked_ram_w ) static WRITE8_HANDLER( megatech_banked_ram_w )
{ {
megatech_banked_ram[offset + 0x1000 * (mt_cart_select_reg&0x7) ] = data; megatech_banked_ram[offset + 0x1000 * (mtech_bios.mt_cart_select_reg & 0x07)] = data;
} }
@ -450,12 +442,12 @@ ADDRESS_MAP_END
static WRITE8_HANDLER (megatech_bios_port_ctrl_w) static WRITE8_HANDLER (megatech_bios_port_ctrl_w)
{ {
bios_port_ctrl = data; mtech_bios.bios_port_ctrl = data;
} }
static READ8_HANDLER (megatech_bios_joypad_r) static READ8_HANDLER (megatech_bios_joypad_r)
{ {
return megatech_bios_port_cc_dc_r(space->machine,offset,bios_port_ctrl); return megatech_bios_port_cc_dc_r(space->machine, offset, mtech_bios.bios_port_ctrl);
} }
@ -501,7 +493,7 @@ static VIDEO_UPDATE(mtnew)
if (screen == megadriv_screen) if (screen == megadriv_screen)
{ {
/* if we're running an sms game then use the SMS update.. maybe this should be moved to the megadrive emulation core as compatibility mode is a feature of the chip */ /* if we're running an sms game then use the SMS update.. maybe this should be moved to the megadrive emulation core as compatibility mode is a feature of the chip */
if (!current_game_is_sms) VIDEO_UPDATE_CALL(megadriv); if (!mtech_bios.current_game_is_sms) VIDEO_UPDATE_CALL(megadriv);
else VIDEO_UPDATE_CALL(megatech_md_sms); else VIDEO_UPDATE_CALL(megatech_md_sms);
} }
else if (screen == menu_screen) VIDEO_UPDATE_CALL(megatech_bios); else if (screen == menu_screen) VIDEO_UPDATE_CALL(megatech_bios);
@ -510,13 +502,17 @@ static VIDEO_UPDATE(mtnew)
static VIDEO_EOF(mtnew) static VIDEO_EOF(mtnew)
{ {
if (!current_game_is_sms) VIDEO_EOF_CALL(megadriv); if (!mtech_bios.current_game_is_sms) VIDEO_EOF_CALL(megadriv);
else VIDEO_EOF_CALL(megatech_md_sms); else VIDEO_EOF_CALL(megatech_md_sms);
VIDEO_EOF_CALL(megatech_bios); VIDEO_EOF_CALL(megatech_bios);
} }
static MACHINE_RESET(mtnew) static MACHINE_RESET(mtnew)
{ {
mtech_bios.mt_bank_bank_pos = 0;
mtech_bios.mt_bank_partial = 0;
mtech_bios.mt_bank_addr = 0;
MACHINE_RESET_CALL(megadriv); MACHINE_RESET_CALL(megadriv);
MACHINE_RESET_CALL(megatech_bios); MACHINE_RESET_CALL(megatech_bios);
MACHINE_RESET_CALL(megatech_md_sms); MACHINE_RESET_CALL(megatech_md_sms);

76
src/mame/drivers/topshoot.c
View File

@ -142,6 +142,82 @@ connector, but of course, I can be wrong.
#include "genesis.h" #include "genesis.h"
/* This should be replaced by the implementation in megadriv.c or by specific input code */
static UINT16 *genesis_io_ram;
static int z80running;
static WRITE16_HANDLER( genesis_io_w )
{
// logerror ("write io offset :%02x data %04x PC: 0x%06x\n",offset,data,cpu_get_previouspc(space->cpu));
switch (offset)
{
case 0x00:
/*??*/
break;
case 0x01:/* port A data */
case 0x02: /* port B data */
case 0x03: /* port C data */
genesis_io_ram[offset] = (data & (genesis_io_ram[offset + 3])) | (genesis_io_ram[offset] & ~(genesis_io_ram[offset + 3]));
break;
case 0x04: /* port A control */
case 0x05: /* port B control */
case 0x06: /* port C control */
case 0x07: /* port A TxData */
genesis_io_ram[offset] = data;
break;
default:
genesis_io_ram[offset] = data;
}
}
static WRITE16_HANDLER( genesis_ctrl_w )
{
data &= mem_mask;
/* logerror("genesis_ctrl_w %x, %x\n", offset, data); */
switch (offset)
{
case 0: /* set DRAM mode... we have to ignore this for production cartridges */
return;
case 0x80: /* Z80 BusReq */
if (data == 0x100)
{
z80running = 0;
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE); /* halt Z80 */
/* logerror("z80 stopped by 68k BusReq\n"); */
}
else
{
z80running = 1;
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, CLEAR_LINE);
/* logerror("z80 started, BusReq ends\n"); */
}
return;
case 0x100: /* Z80 CPU Reset */
if (data == 0x00)
{
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE);
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_RESET, PULSE_LINE);
cputag_set_input_line(space->machine, "genesis_snd_z80", INPUT_LINE_HALT, ASSERT_LINE);
/* logerror("z80 reset, ram is %p\n", &genesis_z80_ram[0]); */
z80running = 0;
return;
}
else
{
/* logerror("z80 out of reset\n"); */
}
return;
}
}
static INPUT_PORTS_START( topshoot ) /* Top Shooter Input Ports */ static INPUT_PORTS_START( topshoot ) /* Top Shooter Input Ports */
PORT_START("IN0") /* 16bit */ PORT_START("IN0") /* 16bit */
PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Unknown ) ) PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Unknown ) )

15
src/mame/includes/genesis.h
View File

@ -1,29 +1,14 @@
/* Todo, reorganise, cleanup etc.*/ /* Todo, reorganise, cleanup etc.*/
/*----------- defined in drivers/megaplay.c -----------*/
extern UINT16 *ic36_ram;
extern UINT8 bios_6204;
extern UINT8 bios_ctrl[6];
/*----------- defined in drivers/megatech.c -----------*/
extern UINT32 bios_ctrl_inputs;
/*----------- defined in drivers/genesis.c -----------*/ /*----------- defined in drivers/genesis.c -----------*/
extern UINT8 *genesis_z80_ram; extern UINT8 *genesis_z80_ram;
extern UINT16 *genesis_68k_ram; extern UINT16 *genesis_68k_ram;
extern MACHINE_START( genesis ); extern MACHINE_START( genesis );
extern MACHINE_RESET( genesis ); extern MACHINE_RESET( genesis );
extern WRITE16_HANDLER ( genesis_io_w );
extern UINT16 *genesis_io_ram;
extern READ16_HANDLER(genesis_ctrl_r);
extern READ16_HANDLER ( megaplay_68k_to_z80_r );
extern READ8_HANDLER ( genesis_z80_r ); extern READ8_HANDLER ( genesis_z80_r );
extern READ8_HANDLER ( genesis_z80_bank_r ); extern READ8_HANDLER ( genesis_z80_bank_r );
extern WRITE8_HANDLER ( genesis_z80_w ); extern WRITE8_HANDLER ( genesis_z80_w );
extern WRITE16_HANDLER(genesis_ctrl_w);
extern WRITE16_HANDLER ( genesis_68k_to_z80_w ); extern WRITE16_HANDLER ( genesis_68k_to_z80_w );
extern READ16_HANDLER ( genesis_68k_to_z80_r ); extern READ16_HANDLER ( genesis_68k_to_z80_r );
extern INTERRUPT_GEN( genesis_vblank_interrupt ); extern INTERRUPT_GEN( genesis_vblank_interrupt );