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r2dtank: Correct CPU type; better guesses at CPU and PSG clocks (nw)

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This commit is contained in:
AJR 2019-02-04 21:36:52 -05:00
parent 6a7c3a8079
commit 9e8ca4c016
1 changed files with 9 additions and 6 deletions
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15
src/mame/drivers/r2dtank.cpp
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@ -30,6 +30,9 @@ other = M5L8226 (x2)
RAM = 4116 (x11)
----------------------------------------------------
XTAL values appear to be 3579.545 (X1) and 11.200 (X2).
********************************************************************/
#include "emu.h"
@ -49,7 +52,7 @@ RAM = 4116 (x11)
#define LOG_AUDIO_COMM (0)
#define MAIN_CPU_MASTER_CLOCK (11200000)
#define MAIN_CPU_MASTER_CLOCK (11.2_MHz_XTAL)
#define PIXEL_CLOCK (MAIN_CPU_MASTER_CLOCK / 2)
#define CRTC_CLOCK (MAIN_CPU_MASTER_CLOCK / 16)
@ -443,17 +446,17 @@ INPUT_PORTS_END
*************************************/
MACHINE_CONFIG_START(r2dtank_state::r2dtank)
MCFG_DEVICE_ADD("maincpu", M6809,3000000) /* ?? too fast ? */
MCFG_DEVICE_ADD("maincpu", MC6809, MAIN_CPU_MASTER_CLOCK / 4) // divider guessed
MCFG_DEVICE_PROGRAM_MAP(r2dtank_main_map)
MCFG_DEVICE_ADD("audiocpu", M6802,3000000) /* ?? */
MCFG_DEVICE_ADD("audiocpu", M6802, 3.579545_MHz_XTAL)
MCFG_DEVICE_PROGRAM_MAP(r2dtank_audio_map)
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, 256, 0, 256, 256, 0, 256) /* temporary, CRTC will configure screen */
MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, 360, 0, 256, 276, 0, 224)
MCFG_SCREEN_UPDATE_DEVICE("crtc", mc6845_device, screen_update)
PALETTE(config, m_palette, palette_device::BGR_3BIT);
@ -496,11 +499,11 @@ MACHINE_CONFIG_START(r2dtank_state::r2dtank)
GENERIC_LATCH_8(config, m_soundlatch);
GENERIC_LATCH_8(config, m_soundlatch2);
AY8910(config, m_ay1, (4000000 / 4));
AY8910(config, m_ay1, 3.579545_MHz_XTAL / 4); // probably E clock from MC6802
m_ay1->port_a_read_callback().set_ioport("DSWB");
m_ay1->add_route(ALL_OUTPUTS, "mono", 0.25);
AY8910(config, m_ay2, (4000000 / 4));
AY8910(config, m_ay2, 3.579545_MHz_XTAL / 4);
m_ay2->port_a_read_callback().set_ioport("IN1");
m_ay2->port_b_read_callback().set_ioport("DSWA");
m_ay2->add_route(ALL_OUTPUTS, "mono", 0.25);