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luckybal: More notes; another handler (nw)
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@ -217,11 +217,15 @@
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Dev notes:
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Not just the ROM, but all external read/write accesses may have
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even and odd data lines swapped. The program includes subroutines
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to perform this swapping, and the PPI needs it for initialization
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(otherwise the invalid control word $44 gets written and the
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program keeps resetting since the outputs can't be read back).
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Not just the ROM, but most external read/write accesses may have
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even and odd data lines swapped. The frequently-called subroutine
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at $4A0D performs this swapping, and the PPI needs it for
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initialization (otherwise the invalid control word $44 gets
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written and the program keeps resetting when it can't read the
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outputs back).
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Currently the machine gets stuck polling the control register for
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the Z180's unemulated clocked serial I/O.
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*********************************************************************/
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@ -254,6 +258,7 @@ public:
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, m_dac(*this, "dac")
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{ }
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DECLARE_WRITE8_MEMBER(port90_bitswap_w);
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DECLARE_READ8_MEMBER(ppi_bitswap_r);
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DECLARE_WRITE8_MEMBER(ppi_bitswap_w);
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DECLARE_WRITE8_MEMBER(output_port_a_w);
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@ -281,6 +286,7 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( main_io, AS_IO, 8, luckybal_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x90, 0x90) AM_WRITE(port90_bitswap_w)
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AM_RANGE(0xc0, 0xc3) AM_READWRITE(ppi_bitswap_r, ppi_bitswap_w)
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AM_RANGE(0xe0, 0xe3) AM_DEVREADWRITE("v9938", v9938_device, read, write)
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ADDRESS_MAP_END
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@ -334,6 +340,12 @@ M_MAP EQU 90H ; [A]= Bank to select (BIT6=MEM, BIT7=EN_NMI)
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* R/W handlers *
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**************************************/
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WRITE8_MEMBER(luckybal_state::port90_bitswap_w)
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{
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data = bitswap<8>(data, 6, 7, 4, 5, 2, 3, 0, 1);
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logerror("%s: Write to port 90: %02X\n", machine().describe_context(), data);
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}
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READ8_MEMBER(luckybal_state::ppi_bitswap_r)
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{
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return bitswap<8>(m_ppi->read(space, offset), 6, 7, 4, 5, 2, 3, 0, 1);
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