mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
hd6305: move common peripherals to base class
This commit is contained in:
hap
parent
656f6f5a96
commit
9ee1e66496
@ -1,14 +1,18 @@
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// license:BSD-3-Clause
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// copyright-holders:Aaron Giles, Vas Crabb, Olivier Galibert
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/*
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Hitachi HD6305 series
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TODO:
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- add HD6305Y2 peripherals (nothing to test it with?)
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- add HD63705Z0 peripherals
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*/
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#include "emu.h"
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#include "hd6305.h"
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#include "m6805defs.h"
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/****************************************************************************
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* HD6305 section
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****************************************************************************/
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hd6305_device::hd6305_device(
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machine_config const &mconfig,
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char const *tag,
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@ -16,44 +20,20 @@ hd6305_device::hd6305_device(
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uint32_t clock,
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device_type const type,
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configuration_params const ¶ms,
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address_map_constructor internal_map)
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: m6805_base_device(mconfig, tag, owner, clock, type, params, internal_map)
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address_map_constructor internal_map) :
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m6805_base_device(mconfig, tag, owner, clock, type, params, internal_map),
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m_sci_clk(*this),
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m_sci_tx(*this),
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m_read_port(*this, 0xff),
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m_write_port(*this)
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{
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}
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hd6305v0_device::hd6305v0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hd6305_device(
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mconfig,
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tag,
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owner,
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clock,
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HD6305V0,
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{ s_hmos_s_ops, s_hmos_cycles, 14, 0x00ff, 0x00c0, 0x1fff, 0x1ffc },
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address_map_constructor(FUNC(hd6305v0_device::internal_map), this)),
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m_read_port(*this, 0xff),
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m_write_port(*this),
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m_sci_clk(*this),
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m_sci_tx(*this)
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{
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}
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// common peripherals
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void hd6305v0_device::internal_map(address_map &map)
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void hd6305_device::device_start()
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{
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map(0x0000, 0x0003).rw(FUNC(hd6305v0_device::port_r), FUNC(hd6305v0_device::port_w));
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map(0x0004, 0x0007).rw(FUNC(hd6305v0_device::port_ddr_r), FUNC(hd6305v0_device::port_ddr_w));
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map(0x0008, 0x0008).rw(FUNC(hd6305v0_device::timer_data_r), FUNC(hd6305v0_device::timer_data_w));
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map(0x0009, 0x0009).rw(FUNC(hd6305v0_device::timer_ctrl_r), FUNC(hd6305v0_device::timer_ctrl_w));
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map(0x000a, 0x000a).rw(FUNC(hd6305v0_device::misc_r), FUNC(hd6305v0_device::misc_w));
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map(0x0010, 0x0010).rw(FUNC(hd6305v0_device::sci_ctrl_r), FUNC(hd6305v0_device::sci_ctrl_w));
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map(0x0011, 0x0011).rw(FUNC(hd6305v0_device::sci_ssr_r), FUNC(hd6305v0_device::sci_ssr_w));
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map(0x0012, 0x0012).rw(FUNC(hd6305v0_device::sci_data_r), FUNC(hd6305v0_device::sci_data_w));
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map(0x0040, 0x00ff).ram();
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map(0x1000, 0x1fff).rom().region(DEVICE_SELF, 0);
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}
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void hd6305v0_device::device_start()
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{
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hd6305_device::device_start();
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m6805_base_device::device_start();
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save_item(NAME(m_port_data));
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save_item(NAME(m_port_ddr));
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@ -69,13 +49,13 @@ void hd6305v0_device::device_start()
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save_item(NAME(m_sci_tx_byte));
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save_item(NAME(m_sci_tx_step));
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m_timer_timer = timer_alloc(FUNC(hd6305v0_device::timer_cb), this);
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m_timer_sci = timer_alloc(FUNC(hd6305v0_device::sci_cb), this);
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m_timer_timer = timer_alloc(FUNC(hd6305_device::timer_cb), this);
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m_timer_sci = timer_alloc(FUNC(hd6305_device::sci_cb), this);
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}
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void hd6305v0_device::device_reset()
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void hd6305_device::device_reset()
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{
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hd6305_device::device_reset();
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m6805_base_device::device_reset();
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std::fill(m_port_data.begin(), m_port_data.end(), 0x00);
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std::fill(m_port_ddr.begin(), m_port_ddr.end(), 0x00);
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@ -99,7 +79,7 @@ void hd6305v0_device::device_reset()
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m_sci_tx(1);
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}
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u8 hd6305v0_device::port_r(offs_t port)
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u8 hd6305_device::port_r(offs_t port)
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{
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if(m_port_ddr[port] == 0xff)
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return m_port_data[port];
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@ -107,7 +87,7 @@ u8 hd6305v0_device::port_r(offs_t port)
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return (m_port_ddr[port] & m_port_data[port]) | (m_read_port[port]() & ~m_port_ddr[port]);
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}
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void hd6305v0_device::port_w(offs_t port, u8 data)
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void hd6305_device::port_w(offs_t port, u8 data)
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{
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if(data != m_port_data[port]) {
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m_port_data[port] = data;
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@ -115,12 +95,12 @@ void hd6305v0_device::port_w(offs_t port, u8 data)
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}
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}
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u8 hd6305v0_device::port_ddr_r(offs_t port)
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u8 hd6305_device::port_ddr_r(offs_t port)
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{
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return m_port_ddr[port];
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}
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void hd6305v0_device::port_ddr_w(offs_t port, u8 data)
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void hd6305_device::port_ddr_w(offs_t port, u8 data)
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{
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if(data != m_port_ddr[port]) {
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logerror("port %d ddr %c%c%c%c%c%c%c%c\n",
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@ -139,7 +119,7 @@ void hd6305v0_device::port_ddr_w(offs_t port, u8 data)
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}
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}
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void hd6305v0_device::timer_update_regs()
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void hd6305_device::timer_update_regs()
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{
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u32 counter = m_prescaler;
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u64 tc = machine().time().as_ticks(clock())/4;
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@ -147,7 +127,7 @@ void hd6305v0_device::timer_update_regs()
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u32 next_counter = counter + cycles;
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u32 shift = BIT(m_tcr, 0, 3);
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u32 steps = shift ? (((next_counter >> (shift-1)) + 1) >> 1) - (((counter >> (shift-1)) + 1) >> 1): cycles;
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u32 steps = shift ? (((next_counter >> (shift-1)) + 1) >> 1) - (((counter >> (shift-1)) + 1) >> 1) : cycles;
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m_tdr -= steps;
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m_prescaler = next_counter & 0x7f;
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@ -155,11 +135,11 @@ void hd6305v0_device::timer_update_regs()
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if(!m_tdr && steps) {
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m_tcr |= 0x80;
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if(!BIT(m_tcr, 6))
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m_pending_interrupts |= 1 << M6805V0_INT_TIMER1;
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m_pending_interrupts |= 1 << HD6305_INT_TIMER1;
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}
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}
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void hd6305v0_device::timer_wait_next_timeout()
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void hd6305_device::timer_wait_next_timeout()
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{
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u32 shift = BIT(m_tcr, 0, 3);
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u32 cycles;
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@ -177,26 +157,26 @@ void hd6305v0_device::timer_wait_next_timeout()
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m_timer_timer->adjust(attotime::from_ticks(cycles*4, clock()));
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}
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u8 hd6305v0_device::timer_data_r()
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u8 hd6305_device::timer_data_r()
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{
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timer_update_regs();
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return m_tdr;
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}
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void hd6305v0_device::timer_data_w(u8 data)
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void hd6305_device::timer_data_w(u8 data)
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{
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timer_update_regs();
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m_tdr = data;
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timer_wait_next_timeout();
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}
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u8 hd6305v0_device::timer_ctrl_r()
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u8 hd6305_device::timer_ctrl_r()
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{
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timer_update_regs();
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return m_tcr;
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}
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void hd6305v0_device::timer_ctrl_w(u8 data)
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void hd6305_device::timer_ctrl_w(u8 data)
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{
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timer_update_regs();
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u8 old = m_tcr;
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@ -213,9 +193,9 @@ void hd6305v0_device::timer_ctrl_w(u8 data)
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logerror("WARNING: timer mode not implemented\n");
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}
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if((m_tcr & 0xc0) == 0x80)
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m_pending_interrupts |= 1 << M6805V0_INT_TIMER1;
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m_pending_interrupts |= 1 << HD6305_INT_TIMER1;
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else
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m_pending_interrupts &= ~(1 << M6805V0_INT_TIMER1);
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m_pending_interrupts &= ~(1 << HD6305_INT_TIMER1);
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if(BIT(m_tcr, 3)) {
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m_prescaler = 0x7f;
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m_tcr &= ~0x08;
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@ -225,18 +205,18 @@ void hd6305v0_device::timer_ctrl_w(u8 data)
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}
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TIMER_CALLBACK_MEMBER(hd6305v0_device::timer_cb)
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TIMER_CALLBACK_MEMBER(hd6305_device::timer_cb)
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{
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timer_update_regs();
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timer_wait_next_timeout();
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}
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u8 hd6305v0_device::misc_r()
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u8 hd6305_device::misc_r()
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{
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return m_mr;
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}
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void hd6305v0_device::misc_w(u8 data)
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void hd6305_device::misc_w(u8 data)
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{
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m_mr = (m_mr & data & 0x80) | (data & 0x60) | 0x1f;
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logerror("misc %02x int2=%s, %s int=%s\n", data,
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@ -245,17 +225,17 @@ void hd6305v0_device::misc_w(u8 data)
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BIT(m_mr, 5) ? "edge" : "level");
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}
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void hd6305v0_device::sci_timer_step()
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void hd6305_device::sci_timer_step()
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{
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m_timer_sci->adjust(attotime::from_ticks(1 << (BIT(m_scr, 0, 4) + 2), clock()));
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}
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TIMER_CALLBACK_MEMBER(hd6305v0_device::sci_cb)
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TIMER_CALLBACK_MEMBER(hd6305_device::sci_cb)
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{
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if(m_sci_tx_step == 16) {
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m_ssr |= 0x80;
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if(!BIT(m_ssr, 5))
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m_pending_interrupts |= 1 << M6805V0_INT_SCI;
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m_pending_interrupts |= 1 << HD6305_INT_SCI;
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if(m_sci_tx_filled) {
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m_sci_tx_filled = false;
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@ -281,12 +261,12 @@ TIMER_CALLBACK_MEMBER(hd6305v0_device::sci_cb)
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sci_timer_step();
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}
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u8 hd6305v0_device::sci_ctrl_r()
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u8 hd6305_device::sci_ctrl_r()
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{
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return m_scr;
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}
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void hd6305v0_device::sci_ctrl_w(u8 data)
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void hd6305_device::sci_ctrl_w(u8 data)
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{
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m_scr = data;
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logerror("sci ctrl %02x d3=%s d4=%s d5=%s rate=%d\n", data,
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@ -296,12 +276,12 @@ void hd6305v0_device::sci_ctrl_w(u8 data)
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clock()/(1 << (BIT(data, 0, 4) + 3)));
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}
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u8 hd6305v0_device::sci_ssr_r()
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u8 hd6305_device::sci_ssr_r()
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{
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return m_ssr;
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}
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void hd6305v0_device::sci_ssr_w(u8 data)
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void hd6305_device::sci_ssr_w(u8 data)
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{
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m_ssr = ((m_ssr & data) & 0xc0) | (data & 0x38) | 7;
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logerror("sci ssr w %02x sci irq=%s, %s timer2 irq=%s, %s%s\n", data,
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@ -312,18 +292,18 @@ void hd6305v0_device::sci_ssr_w(u8 data)
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BIT(m_ssr, 3) ? "reset sci prescaler" : "");
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if((m_ssr & 0xa0) == 0x80)
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m_pending_interrupts |= 1 << M6805V0_INT_SCI;
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m_pending_interrupts |= 1 << HD6305_INT_SCI;
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else
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m_pending_interrupts &= ~(1 << M6805V0_INT_SCI);
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m_pending_interrupts &= ~(1 << HD6305_INT_SCI);
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}
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u8 hd6305v0_device::sci_data_r()
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u8 hd6305_device::sci_data_r()
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{
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logerror("sci data r\n");
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return 0x00;
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}
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void hd6305v0_device::sci_data_w(u8 data)
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void hd6305_device::sci_data_w(u8 data)
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{
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m_sci_tx_data = data;
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if(m_sci_tx_step == 0) {
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@ -338,10 +318,10 @@ void hd6305v0_device::sci_data_w(u8 data)
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m_sci_tx_filled = true;
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}
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void hd6305v0_device::execute_set_input(int inputnum, int state)
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void hd6305_device::execute_set_input(int inputnum, int state)
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{
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// TODO: edge vs. level on int1
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if(inputnum == M6805V0_INT_IRQ1 || inputnum == M6805V0_INT_IRQ2) {
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if(inputnum == HD6305_INT_IRQ1 || inputnum == HD6305_INT_IRQ2) {
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if(m_irq_state[inputnum] != state) {
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m_irq_state[inputnum] = state;
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@ -351,34 +331,69 @@ void hd6305v0_device::execute_set_input(int inputnum, int state)
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}
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}
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void hd6305v0_device::interrupt_vector()
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void hd6305_device::interrupt_vector()
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{
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if((m_pending_interrupts & (1 << M6805V0_INT_IRQ1)) != 0) {
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m_pending_interrupts &= ~(1 << M6805V0_INT_IRQ1);
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if((m_pending_interrupts & (1 << HD6305_INT_IRQ1)) != 0) {
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m_pending_interrupts &= ~(1 << HD6305_INT_IRQ1);
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rm16<false>(0x1ffa, m_pc);
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}
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else if((m_pending_interrupts & (1 << M6805V0_INT_IRQ2)) != 0) {
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m_pending_interrupts &= ~(1 << M6805V0_INT_IRQ2);
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else if((m_pending_interrupts & (1 << HD6305_INT_IRQ2)) != 0) {
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m_pending_interrupts &= ~(1 << HD6305_INT_IRQ2);
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rm16<false>(0x1ff8, m_pc);
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}
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else if((m_pending_interrupts & (1 << M6805V0_INT_TIMER1)) != 0) {
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else if((m_pending_interrupts & (1 << HD6305_INT_TIMER1)) != 0) {
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// TODO: 1ff6 when in wait...
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m_pending_interrupts &= ~(1 << M6805V0_INT_TIMER1);
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m_pending_interrupts &= ~(1 << HD6305_INT_TIMER1);
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rm16<false>(0x1ff8, m_pc);
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}
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else if((m_pending_interrupts & (1 << M6805V0_INT_TIMER2)) != 0) {
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m_pending_interrupts &= ~(1 << M6805V0_INT_TIMER2);
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else if((m_pending_interrupts & (1 << HD6305_INT_TIMER2)) != 0) {
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m_pending_interrupts &= ~(1 << HD6305_INT_TIMER2);
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rm16<false>(0x1ff4, m_pc);
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}
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else if((m_pending_interrupts & (1 << M6805V0_INT_SCI)) != 0) {
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m_pending_interrupts &= ~(1 << M6805V0_INT_SCI);
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else if((m_pending_interrupts & (1 << HD6305_INT_SCI)) != 0) {
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m_pending_interrupts &= ~(1 << HD6305_INT_SCI);
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rm16<false>(0x1ff4, m_pc);
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}
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}
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hd6305y2_device::hd6305y2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: hd6305_device(
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/****************************************************************************
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* HD6305V0 section
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****************************************************************************/
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hd6305v0_device::hd6305v0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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hd6305_device(
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mconfig,
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tag,
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owner,
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clock,
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HD6305V0,
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{ s_hmos_s_ops, s_hmos_cycles, 14, 0x00ff, 0x00c0, 0x1fff, 0x1ffc },
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address_map_constructor(FUNC(hd6305v0_device::internal_map), this))
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{
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}
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void hd6305v0_device::internal_map(address_map &map)
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{
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map(0x0000, 0x0003).rw(FUNC(hd6305v0_device::port_r), FUNC(hd6305v0_device::port_w));
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map(0x0004, 0x0007).rw(FUNC(hd6305v0_device::port_ddr_r), FUNC(hd6305v0_device::port_ddr_w));
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map(0x0008, 0x0008).rw(FUNC(hd6305v0_device::timer_data_r), FUNC(hd6305v0_device::timer_data_w));
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map(0x0009, 0x0009).rw(FUNC(hd6305v0_device::timer_ctrl_r), FUNC(hd6305v0_device::timer_ctrl_w));
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map(0x000a, 0x000a).rw(FUNC(hd6305v0_device::misc_r), FUNC(hd6305v0_device::misc_w));
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map(0x0010, 0x0010).rw(FUNC(hd6305v0_device::sci_ctrl_r), FUNC(hd6305v0_device::sci_ctrl_w));
|
||||
map(0x0011, 0x0011).rw(FUNC(hd6305v0_device::sci_ssr_r), FUNC(hd6305v0_device::sci_ssr_w));
|
||||
map(0x0012, 0x0012).rw(FUNC(hd6305v0_device::sci_data_r), FUNC(hd6305v0_device::sci_data_w));
|
||||
map(0x0040, 0x00ff).ram();
|
||||
map(0x1000, 0x1fff).rom().region(DEVICE_SELF, 0);
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* HD6305Y2 section
|
||||
****************************************************************************/
|
||||
|
||||
hd6305y2_device::hd6305y2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
|
||||
hd6305_device(
|
||||
mconfig,
|
||||
tag,
|
||||
owner,
|
||||
@ -395,8 +410,13 @@ void hd6305y2_device::internal_map(address_map &map)
|
||||
map(0x0040, 0x013f).ram();
|
||||
}
|
||||
|
||||
hd63705z0_device::hd63705z0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
|
||||
: hd6305_device(
|
||||
|
||||
/****************************************************************************
|
||||
* HD63705Z0 section
|
||||
****************************************************************************/
|
||||
|
||||
hd63705z0_device::hd63705z0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
|
||||
hd6305_device(
|
||||
mconfig,
|
||||
tag,
|
||||
owner,
|
||||
|
||||
@ -23,6 +23,10 @@ DECLARE_DEVICE_TYPE(HD63705Z0, hd63705z0_device)
|
||||
|
||||
class hd6305_device : public m6805_base_device
|
||||
{
|
||||
public:
|
||||
auto write_sci_tx() { return m_sci_tx.bind(); }
|
||||
auto write_sci_clk() { return m_sci_clk.bind(); }
|
||||
|
||||
protected:
|
||||
// construction/destruction
|
||||
hd6305_device(
|
||||
@ -34,64 +38,13 @@ protected:
|
||||
configuration_params const ¶ms,
|
||||
address_map_constructor internal_map);
|
||||
|
||||
virtual bool execute_input_edge_triggered(int inputnum) const noexcept override { return inputnum == INPUT_LINE_NMI; }
|
||||
|
||||
virtual bool test_il() override { return m_nmi_state != CLEAR_LINE; }
|
||||
};
|
||||
|
||||
// ======================> hd6305v0_device
|
||||
|
||||
class hd6305v0_device : public hd6305_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
hd6305v0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
auto write_sci_tx() { return m_sci_tx.bind(); }
|
||||
auto write_sci_clk() { return m_sci_clk.bind(); }
|
||||
|
||||
auto read_porta() { return m_read_port [0].bind(); }
|
||||
auto write_porta() { return m_write_port[0].bind(); }
|
||||
auto read_portb() { return m_read_port [1].bind(); }
|
||||
auto write_portb() { return m_write_port[1].bind(); }
|
||||
auto read_portc() { return m_read_port [2].bind(); }
|
||||
auto write_portc() { return m_write_port[2].bind(); }
|
||||
auto read_portd() { return m_read_port [3].bind(); }
|
||||
auto write_portd() { return m_write_port[3].bind(); }
|
||||
|
||||
protected:
|
||||
virtual void device_start() override ATTR_COLD;
|
||||
virtual void device_reset() override ATTR_COLD;
|
||||
virtual void execute_set_input(int inputnum, int state) override;
|
||||
virtual bool execute_input_edge_triggered(int inputnum) const noexcept override { return inputnum == INPUT_LINE_NMI; }
|
||||
virtual void interrupt_vector() override;
|
||||
|
||||
private:
|
||||
devcb_read8::array<4> m_read_port;
|
||||
devcb_write8::array<4> m_write_port;
|
||||
devcb_write_line m_sci_clk;
|
||||
devcb_write_line m_sci_tx;
|
||||
|
||||
emu_timer *m_timer_timer;
|
||||
emu_timer *m_timer_sci;
|
||||
|
||||
std::array<u8, 4> m_port_data;
|
||||
std::array<u8, 4> m_port_ddr;
|
||||
|
||||
u64 m_timer_last_update;
|
||||
|
||||
u8 m_tdr;
|
||||
u8 m_prescaler;
|
||||
u8 m_tcr;
|
||||
u8 m_ssr;
|
||||
u8 m_scr;
|
||||
u8 m_mr;
|
||||
u8 m_sci_tx_data;
|
||||
|
||||
bool m_sci_tx_filled;
|
||||
u8 m_sci_tx_byte;
|
||||
u8 m_sci_tx_step;
|
||||
|
||||
void internal_map(address_map &map) ATTR_COLD;
|
||||
virtual bool test_il() override { return m_nmi_state != CLEAR_LINE; }
|
||||
|
||||
u8 port_r(offs_t port);
|
||||
void port_w(offs_t port, u8 data);
|
||||
@ -119,6 +72,53 @@ private:
|
||||
|
||||
TIMER_CALLBACK_MEMBER(timer_cb);
|
||||
TIMER_CALLBACK_MEMBER(sci_cb);
|
||||
|
||||
devcb_write_line m_sci_clk;
|
||||
devcb_write_line m_sci_tx;
|
||||
|
||||
// maximum 9 I/O ports
|
||||
devcb_read8::array<9> m_read_port;
|
||||
devcb_write8::array<9> m_write_port;
|
||||
std::array<u8, 9> m_port_data;
|
||||
std::array<u8, 9> m_port_ddr;
|
||||
|
||||
emu_timer *m_timer_timer;
|
||||
emu_timer *m_timer_sci;
|
||||
|
||||
u64 m_timer_last_update;
|
||||
|
||||
u8 m_tdr;
|
||||
u8 m_prescaler;
|
||||
u8 m_tcr;
|
||||
u8 m_ssr;
|
||||
u8 m_scr;
|
||||
u8 m_mr;
|
||||
u8 m_sci_tx_data;
|
||||
|
||||
bool m_sci_tx_filled;
|
||||
u8 m_sci_tx_byte;
|
||||
u8 m_sci_tx_step;
|
||||
};
|
||||
|
||||
// ======================> hd6305v0_device
|
||||
|
||||
class hd6305v0_device : public hd6305_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
hd6305v0_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
auto read_porta() { return m_read_port [0].bind(); }
|
||||
auto write_porta() { return m_write_port[0].bind(); }
|
||||
auto read_portb() { return m_read_port [1].bind(); }
|
||||
auto write_portb() { return m_write_port[1].bind(); }
|
||||
auto read_portc() { return m_read_port [2].bind(); }
|
||||
auto write_portc() { return m_write_port[2].bind(); }
|
||||
auto read_portd() { return m_read_port [3].bind(); }
|
||||
auto write_portd() { return m_write_port[3].bind(); }
|
||||
|
||||
private:
|
||||
void internal_map(address_map &map) ATTR_COLD;
|
||||
};
|
||||
|
||||
// ======================> hd6305y2_device
|
||||
@ -151,14 +151,14 @@ private:
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* 6805V0 section
|
||||
* HD6305 section
|
||||
****************************************************************************/
|
||||
|
||||
#define M6805V0_INT_IRQ1 0x00
|
||||
#define M6805V0_INT_IRQ2 0x01
|
||||
#define M6805V0_INT_TIMER1 0x02
|
||||
#define M6805V0_INT_TIMER2 0x03
|
||||
#define M6805V0_INT_SCI 0x04
|
||||
#define HD6305_INT_IRQ1 0x00
|
||||
#define HD6305_INT_IRQ2 0x01
|
||||
#define HD6305_INT_TIMER1 0x02
|
||||
#define HD6305_INT_TIMER2 0x03
|
||||
#define HD6305_INT_SCI 0x04
|
||||
|
||||
/****************************************************************************
|
||||
* HD63705 section
|
||||
|
||||
@ -2225,7 +2225,8 @@ void system1_state::sys1ppi(machine_config &config)
|
||||
|
||||
GENERIC_LATCH_8(config, m_soundlatch);
|
||||
|
||||
// 1st SN audio output actually goes to 2nd SN audio input (pin 9)
|
||||
// 1st SN audio output actually goes to 2nd SN audio input (pin 9),
|
||||
// with a resistor in between, so the volume is lowered a bit.
|
||||
SN76489A(config, m_sn[0], SOUND_CLOCK/4).add_route(ALL_OUTPUTS, "mono", 0.40);
|
||||
|
||||
// 2nd SN's clock is selectable via jumper
|
||||
|
||||
@ -296,6 +296,6 @@ void mks3_device::req_w(int state)
|
||||
return;
|
||||
|
||||
m_req = state;
|
||||
m_cpu->set_input_line(M6805V0_INT_IRQ1, m_req);
|
||||
m_cpu->set_input_line(HD6305_INT_IRQ1, m_req);
|
||||
logerror("req %d\n", m_req);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user