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Converted a bunch of CPU cores over to the new memory functions.

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This commit is contained in:
Aaron Giles 2008-11-22 18:38:41 +00:00
parent 7173ebcdba
commit 9ee2f770aa
38 changed files with 1376 additions and 1359 deletions
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7
src/emu/cpu/alph8201/alph8201.c
View File

@ -147,6 +147,7 @@ Timming
****************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "alph8201.h"
@ -195,6 +196,9 @@ typedef struct
#if HANDLE_HALT_LINE
UINT8 halt; /* halt input line */
#endif
const device_config *device;
const address_space *program;
} ALPHA8201_Regs;
/* The opcode table now is a combination of cycle counts and function pointers */
@ -664,6 +668,9 @@ static const s_opcode opcode_8301[256]=
****************************************************************************/
static CPU_INIT( ALPHA8201 )
{
R.device = device;
R.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
state_save_register_item_array("ALPHA8201", device->tag, 0, R.RAM);
state_save_register_item("ALPHA8201", device->tag, 0, R.PREVPC);
state_save_register_item("ALPHA8201", device->tag, 0, PC);

8
src/emu/cpu/alph8201/alph8201.h
View File

@ -47,26 +47,26 @@ extern CPU_GET_INFO( alpha8301 );
/*
* Read a UINT8 from given memory location
*/
#define ALPHA8201_RDMEM(A) ((unsigned)program_read_byte_8le(A))
#define ALPHA8201_RDMEM(A) ((unsigned)memory_read_byte_8le(R.program, A))
/*
* Write a UINT8 to given memory location
*/
#define ALPHA8201_WRMEM(A,V) (program_write_byte_8le(A,V))
#define ALPHA8201_WRMEM(A,V) (memory_write_byte_8le(R.program, A,V))
/*
* ALPHA8201_RDOP() is identical to ALPHA8201_RDMEM() except it is used for reading
* opcodes. In case of system with memory mapped I/O, this function can be
* used to greatly speed up emulation
*/
#define ALPHA8201_RDOP(A) ((unsigned)program_decrypted_read_byte(A))
#define ALPHA8201_RDOP(A) ((unsigned)memory_decrypted_read_byte(R.program, A))
/*
* ALPHA8201_RDOP_ARG() is identical to ALPHA8201_RDOP() except it is used for reading
* opcode arguments. This difference can be used to support systems that
* use different encoding mechanisms for opcodes and opcode arguments
*/
#define ALPHA8201_RDOP_ARG(A) ((unsigned)program_raw_read_byte(A))
#define ALPHA8201_RDOP_ARG(A) ((unsigned)memory_raw_read_byte(R.program, A))
CPU_DISASSEMBLE( ALPHA8201 );

12
src/emu/cpu/apexc/apexc.c
View File

@ -323,6 +323,7 @@ field: X address D Function Y address D (part 2)
another track.
*/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "cpuintrf.h"
#include "debugger.h"
#include "apexc.h"
@ -339,6 +340,10 @@ typedef struct
int running; /* 1 flag: */
/* running: flag implied by the existence of the stop instruction */
const device_config *device;
const address_space *program;
const address_space *io;
} apexc_regs;
static apexc_regs apexc;
@ -447,12 +452,12 @@ static void word_write(int address, UINT32 data, UINT32 mask)
static int papertape_read(void)
{
return io_read_byte_8be(0) & 0x1f;
return memory_read_byte_8be(apexc.io, 0) & 0x1f;
}
static void papertape_punch(int data)
{
io_write_byte_8be(0, data);
memory_write_byte_8be(apexc.io, 0, data);
}
/*
@ -769,6 +774,9 @@ special_fetch:
static CPU_INIT( apexc )
{
apexc.device = device;
apexc.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
apexc.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
}
static CPU_RESET( apexc )

4
src/emu/cpu/apexc/apexc.h
View File

@ -21,8 +21,8 @@ enum
CPU_GET_INFO( apexc );
#ifndef SUPPORT_ODD_WORD_SIZES
#define apexc_readmem(address) program_read_dword_32be((address)<<2)
#define apexc_writemem(address, data) program_write_dword_32be((address)<<2, (data))
#define apexc_readmem(address) memory_read_dword_32be(apexc.program, (address)<<2)
#define apexc_writemem(address, data) memory_write_dword_32be(apexc.program, (address)<<2, (data))
/* eewww ! - Fortunately, there is no memory mapped I/O, so we can simulate masked write
without danger */
#define apexc_writemem_masked(address, data, mask) \

14
src/emu/cpu/arm/arm.c
View File

@ -15,6 +15,7 @@
*/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "arm.h"
#include "debugger.h"
@ -231,6 +232,7 @@ typedef struct
UINT8 pendingFiq;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
} ARM_REGS;
static ARM_REGS arm;
@ -252,18 +254,18 @@ static void arm_check_irq_state(void);
INLINE void cpu_write32( int addr, UINT32 data )
{
/* Unaligned writes are treated as normal writes */
program_write_dword_32le(addr&ADDRESS_MASK,data);
memory_write_dword_32le(arm.program, addr&ADDRESS_MASK,data);
if (ARM_DEBUG_CORE && addr&3) logerror("%08x: Unaligned write %08x\n",R15,addr);
}
INLINE void cpu_write8( int addr, UINT8 data )
{
program_write_byte_32le(addr,data);
memory_write_byte_32le(arm.program,addr,data);
}
INLINE UINT32 cpu_read32( int addr )
{
UINT32 result = program_read_dword_32le(addr&ADDRESS_MASK);
UINT32 result = memory_read_dword_32le(arm.program,addr&ADDRESS_MASK);
/* Unaligned reads rotate the word, they never combine words */
if (addr&3) {
@ -283,7 +285,7 @@ INLINE UINT32 cpu_read32( int addr )
INLINE UINT8 cpu_read8( int addr )
{
return program_read_byte_32le(addr);
return memory_read_byte_32le(arm.program, addr);
}
INLINE UINT32 GetRegister( int rIndex )
@ -306,6 +308,7 @@ static CPU_RESET( arm )
memset(&arm, 0, sizeof(arm));
arm.irq_callback = save_irqcallback;
arm.device = device;
arm.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* start up in SVC mode with interrupts disabled. */
R15 = eARM_MODE_SVC|I_MASK|F_MASK;
@ -329,7 +332,7 @@ static CPU_EXECUTE( arm )
/* load instruction */
pc = R15;
insn = program_decrypted_read_dword( pc & ADDRESS_MASK );
insn = memory_decrypted_read_dword( arm.program, pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
@ -514,6 +517,7 @@ static CPU_INIT( arm )
{
arm.irq_callback = irqcallback;
arm.device = device;
arm.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
state_save_register_item_array("arm", device->tag, 0, arm.sArmRegister);
state_save_register_item_array("arm", device->tag, 0, arm.coproRegister);

16
src/emu/cpu/arm7/arm7core.c
View File

@ -77,6 +77,7 @@
By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino
*****************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include <stdarg.h>
#include "deprecat.h"
@ -139,19 +140,19 @@ char *(*arm7_dasm_cop_do_callback)(char *pBuf, UINT32 opcode, char *pConditionCo
INLINE void arm7_cpu_write32(UINT32 addr, UINT32 data)
{
addr &= ~3;
program_write_dword_32le(addr, data);
memory_write_dword_32le(ARM7.program, addr, data);
}
INLINE void arm7_cpu_write16(UINT32 addr, UINT16 data)
{
addr &= ~1;
program_write_word_32le(addr, data);
memory_write_word_32le(ARM7.program, addr, data);
}
INLINE void arm7_cpu_write8(UINT32 addr, UINT8 data)
{
program_write_byte_32le(addr, data);
memory_write_byte_32le(ARM7.program, addr, data);
}
INLINE UINT32 arm7_cpu_read32(offs_t addr)
@ -160,12 +161,12 @@ INLINE UINT32 arm7_cpu_read32(offs_t addr)
if (addr & 3)
{
result = program_read_dword_32le(addr & ~3);
result = memory_read_dword_32le(ARM7.program, addr & ~3);
result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
}
else
{
result = program_read_dword_32le(addr);
result = memory_read_dword_32le(ARM7.program, addr);
}
return result;
@ -175,7 +176,7 @@ INLINE UINT16 arm7_cpu_read16(offs_t addr)
{
UINT16 result;
result = program_read_word_32le(addr & ~1);
result = memory_read_word_32le(ARM7.program, addr & ~1);
if (addr & 1)
{
@ -188,7 +189,7 @@ INLINE UINT16 arm7_cpu_read16(offs_t addr)
INLINE UINT8 arm7_cpu_read8(offs_t addr)
{
// Handle through normal 8 bit handler (for 32 bit cpu)
return program_read_byte_32le(addr);
return memory_read_byte_32le(ARM7.program, addr);
}
/***************
@ -527,6 +528,7 @@ static void arm7_core_reset(const device_config *device)
memset(&ARM7, 0, sizeof(ARM7));
ARM7.irq_callback = save_irqcallback;
ARM7.device = device;
ARM7.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* start up in SVC mode with interrupts disabled. */
SwitchMode(eARM7_MODE_SVC);

4
src/emu/cpu/arm7/arm7exec.c
View File

@ -58,7 +58,7 @@
INT32 offs;
pc = R15;
insn = program_decrypted_read_word(pc & (~1));
insn = memory_decrypted_read_word(ARM7.program, pc & (~1));
ARM7_ICOUNT -= (3 - thumbCycles[insn >> 8]);
switch ((insn & THUMB_INSN_TYPE) >> THUMB_INSN_TYPE_SHIFT)
{
@ -1168,7 +1168,7 @@
/* load 32 bit instruction */
pc = R15;
insn = program_decrypted_read_dword(pc);
insn = memory_decrypted_read_dword(ARM7.program, pc);
/* process condition codes for this instruction */
switch (insn >> INSN_COND_SHIFT)

7
src/emu/cpu/asap/asapdasm.c
View File

@ -28,13 +28,6 @@ static const char *const condition[16] =
};
/***************************************************************************
MEMORY ACCESSORS
***************************************************************************/
#define ROPCODE(pc) program_decrypted_read_dword(pc)
/***************************************************************************
CODE CODE
***************************************************************************/

20
src/emu/cpu/ccpu/ccpu.c
View File

@ -8,6 +8,7 @@
***************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "ccpu.h"
@ -38,6 +39,11 @@ typedef struct
UINT8 waiting;
UINT8 watchdog;
const device_config *device;
const address_space *program;
const address_space *data;
const address_space *io;
} ccpuRegs;
@ -55,13 +61,13 @@ static int ccpu_icount;
MACROS
***************************************************************************/
#define READOP(a) (program_decrypted_read_byte(a))
#define READOP(a) (memory_decrypted_read_byte(ccpu.program, a))
#define RDMEM(a) (data_read_word_16be((a) * 2) & 0xfff)
#define WRMEM(a,v) (data_write_word_16be((a) * 2, (v)))
#define RDMEM(a) (memory_read_word_16be(ccpu.data, (a) * 2) & 0xfff)
#define WRMEM(a,v) (memory_write_word_16be(ccpu.data, (a) * 2, (v)))
#define READPORT(a) (io_read_byte_8be(a))
#define WRITEPORT(a,v) (io_write_byte_8be((a), (v)))
#define READPORT(a) (memory_read_byte_8be(ccpu.io, a))
#define WRITEPORT(a,v) (memory_write_byte_8be(ccpu.io, (a), (v)))
#define SET_A0() do { ccpu.a0flag = ccpu.A; } while (0)
#define SET_CMP_VAL(x) do { ccpu.cmpacc = *ccpu.acc; ccpu.cmpval = (x) & 0xfff; } while (0)
@ -140,6 +146,10 @@ static CPU_INIT( ccpu )
/* copy input params */
ccpu.external_input = configdata->external_input ? configdata->external_input : read_jmi;
ccpu.vector_callback = configdata->vector_callback;
ccpu.device = device;
ccpu.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
ccpu.data = memory_find_address_space(device, ADDRESS_SPACE_DATA);
ccpu.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
state_save_register_item("ccpu", device->tag, 0, ccpu.PC);
state_save_register_item("ccpu", device->tag, 0, ccpu.A);

7
src/emu/cpu/cp1610/cp1610.c
View File

@ -21,6 +21,7 @@
*
*****************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "cpuexec.h"
#include "debugger.h"
#include "cp1610.h"
@ -36,7 +37,6 @@ typedef struct {
int intr_enabled;
//int (*reset_callback)(void);
cpu_irq_callback irq_callback;
const device_config *device;
UINT16 intr_vector;
int reset_state;
int intr_state;
@ -45,6 +45,8 @@ typedef struct {
int intr_pending;
int intrm_pending;
int mask_interrupts;
const device_config *device;
const address_space *program;
} cp1610_Regs;
static int cp1610_icount;
@ -1550,7 +1552,7 @@ static void cp1610_xori(int d)
static CPU_RESET( cp1610 )
{
/* This is how we set the reset vector */
cpu_set_input_line(device->machine->activecpu, CP1610_RESET, PULSE_LINE);
cpu_set_input_line(device, CP1610_RESET, PULSE_LINE);
}
/***************************************************
@ -3392,6 +3394,7 @@ static CPU_INIT( cp1610 )
cp1610.intrm_pending = 0;
cp1610.irq_callback = irqcallback;
cp1610.device = device;
cp1610.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
}
static void cp1610_set_irq_line(UINT32 irqline, int state)

6
src/emu/cpu/cp1610/cp1610.h
View File

@ -41,8 +41,8 @@ CPU_GET_INFO( cp1610 );
CPU_DISASSEMBLE( cp1610 );
// Temporary
#define cp1610_readop(A) program_read_word_16be((A)<<1)
#define cp1610_readmem16(A) program_read_word_16be((A)<<1)
#define cp1610_writemem16(A,B) program_write_word_16be((A)<<1,B)
#define cp1610_readop(A) memory_read_word_16be(cp1610.program, (A)<<1)
#define cp1610_readmem16(A) memory_read_word_16be(cp1610.program, (A)<<1)
#define cp1610_writemem16(A,B) memory_write_word_16be(cp1610.program, (A)<<1,B)
#endif /* __CP1610_H__ */

25
src/emu/cpu/cubeqcpu/cubeqcpu.c
View File

@ -10,6 +10,7 @@
***************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "cubeqcpu.h"
@ -127,6 +128,9 @@ typedef struct
void (*dac_w)(UINT16 data);
UINT16 *sound_data;
const device_config *device;
const address_space *program;
} cquestsnd_state;
@ -163,6 +167,9 @@ typedef struct
UINT8 wc;
UINT8 rc;
UINT8 clkcnt;
const device_config *device;
const address_space *program;
} cquestrot_state;
@ -204,6 +211,9 @@ typedef struct
UINT8 *ptr_ram;
UINT32 *e_stack;
UINT32 *o_stack;
const device_config *device;
const address_space *program;
} cquestlin_state;
@ -343,6 +353,9 @@ static CPU_INIT( cquestsnd )
cquestsnd.dac_w = _config->dac_w;
cquestsnd.sound_data = (UINT16*)memory_region(device->machine, _config->sound_data_region);
cquestsnd.device = device;
cquestsnd.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* Allocate RAM shared with 68000 */
cquestsnd.sram = malloc(4096);
@ -411,6 +424,9 @@ static CPU_INIT( cquestrot )
cquestrot.dram = malloc(16384 * sizeof(UINT16)); /* Shared with 68000 */
cquestrot.sram = malloc(2048 * sizeof(UINT16)); /* Private */
cquestrot.device = device;
cquestrot.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
cquestrot_state_register(device, "cquestrot");
}
@ -489,6 +505,9 @@ static CPU_INIT( cquestlin )
cquestlin.e_stack = malloc(32768 * sizeof(UINT32)); /* Stack DRAM: 32kx20 */
cquestlin.o_stack = malloc(32768 * sizeof(UINT32)); /* Stack DRAM: 32kx20 */
cquestlin.device = device;
cquestlin.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
cquestlin_state_register(device, "cquestlin");
}
@ -549,7 +568,7 @@ static CPU_EXECUTE( cquestsnd )
do
{
/* Decode the instruction */
UINT64 inst = program_decrypted_read_qword(SND_PC << 3);
UINT64 inst = memory_decrypted_read_qword(cquestsnd.program, SND_PC << 3);
UINT32 inslow = inst & 0xffffffff;
UINT32 inshig = inst >> 32;
@ -883,7 +902,7 @@ static CPU_EXECUTE( cquestrot )
do
{
/* Decode the instruction */
UINT64 inst = program_decrypted_read_qword(ROT_PC << 3);
UINT64 inst = memory_decrypted_read_qword(cquestrot.program, ROT_PC << 3);
UINT32 inslow = inst & 0xffffffff;
UINT32 inshig = inst >> 32;
@ -1405,7 +1424,7 @@ static CPU_EXECUTE( cquestlin )
/* Are we executing the foreground or backgroud program? */
int prog = (cquestlin.clkcnt & 3) ? BACKGROUND : FOREGROUND;
UINT64 inst = program_decrypted_read_qword(LINE_PC << 3);
UINT64 inst = memory_decrypted_read_qword(cquestlin.program, LINE_PC << 3);
UINT32 inslow = inst & 0xffffffff;
UINT32 inshig = inst >> 32;

5
src/emu/cpu/drcfe.c
View File

@ -17,6 +17,7 @@
***************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include <stddef.h>
#include "cpuintrf.h"
#include "mame.h"
@ -145,7 +146,7 @@ drcfe_state *drcfe_init(const device_config *cpu, const drcfe_config *config, vo
/* initialize the state */
drcfe->device = cpu;
drcfe->program = cpu_get_address_space(cpu, ADDRESS_SPACE_PROGRAM);
drcfe->program = memory_find_address_space(cpu, ADDRESS_SPACE_PROGRAM);
drcfe->pageshift = cpu_get_page_shift(cpu, ADDRESS_SPACE_PROGRAM);
drcfe->translate = (cpu_translate_func)cpu_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
#ifdef LSB_FIRST
@ -302,7 +303,7 @@ static opcode_desc *describe_one(drcfe_state *drcfe, offs_t curpc, const opcode_
/* get a pointer to the physical address */
change_pc(desc->physpc);
desc->opptr.v = program_decrypted_read_ptr(desc->physpc ^ drcfe->codexor);
desc->opptr.v = memory_decrypted_read_ptr(drcfe->program, desc->physpc ^ drcfe->codexor);
assert(desc->opptr.v != NULL);
if (desc->opptr.v == NULL)
{

25
src/emu/cpu/dsp32/dsp32.c
View File

@ -27,6 +27,7 @@
***************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "dsp32.h"
@ -212,17 +213,17 @@ static int dsp32_icount;
MEMORY ACCESSORS
***************************************************************************/
#define ROPCODE(pc) program_decrypted_read_dword(pc)
#define ROPCODE(pc) memory_decrypted_read_dword(dsp32.program, pc)
#define RBYTE(addr) program_read_byte_32le(addr)
#define WBYTE(addr,data) program_write_byte_32le((addr), data)
#define RBYTE(addr) memory_read_byte_32le(dsp32.program, addr)
#define WBYTE(addr,data) memory_write_byte_32le(dsp32.program, (addr), data)
#if (!DETECT_MISALIGNED_MEMORY)
#define RWORD(addr) program_read_word_32le(addr)
#define WWORD(addr,data) program_write_word_32le((addr), data)
#define RLONG(addr) program_read_dword_32le(addr)
#define WLONG(addr,data) program_write_dword_32le((addr), data)
#define RWORD(addr) memory_read_word_32le(dsp32.program, addr)
#define WWORD(addr,data) memory_write_word_32le(dsp32.program, (addr), data)
#define RLONG(addr) memory_read_dword_32le(dsp32.program, addr)
#define WLONG(addr,data) memory_write_dword_32le(dsp32.program, (addr), data)
#else
@ -230,7 +231,7 @@ INLINE UINT16 RWORD(offs_t addr)
{
UINT16 data;
if (addr & 1) fprintf(stderr, "Unaligned word read @ %06X, PC=%06X\n", addr, dsp32.PC);
data = program_read_word_32le(addr);
data = memory_read_word_32le(dsp32.program, addr);
return data;
}
@ -238,20 +239,20 @@ INLINE UINT32 RLONG(offs_t addr)
{
UINT32 data;
if (addr & 3) fprintf(stderr, "Unaligned long read @ %06X, PC=%06X\n", addr, dsp32.PC);
data = program_write_word_32le(addr);
data = memory_write_word_32le(dsp32.program, addr);
return data;
}
INLINE void WWORD(offs_t addr, UINT16 data)
{
if (addr & 1) fprintf(stderr, "Unaligned word write @ %06X, PC=%06X\n", addr, dsp32.PC);
program_read_dword_32le((addr), data);
memory_read_dword_32le(dsp32.program, (addr), data);
}
INLINE void WLONG(offs_t addr, UINT32 data)
{
if (addr & 3) fprintf(stderr, "Unaligned long write @ %06X, PC=%06X\n", addr, dsp32.PC);
program_write_dword_32le((addr), data);
memory_write_dword_32le(dsp32.program, (addr), data);
}
#endif
@ -357,7 +358,7 @@ static CPU_INIT( dsp32c )
dsp32.output_pins_changed = configdata->output_pins_changed;
dsp32.device = device;
dsp32.program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
dsp32.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
}

2
src/emu/cpu/dsp32/dsp32dis.c
View File

@ -13,8 +13,6 @@
MEMORY ACCESSORS
***************************************************************************/
#define ROPCODE(pc) program_decrypted_read_dword(pc)
#define ABS(x) (((x) >= 0) ? (x) : -(x))

9
src/emu/cpu/dsp56k/dsp56k.c
View File

@ -29,6 +29,7 @@
- 1-21 Vectored exception requests on the Host Interface!
***************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "dsp56k.h"
@ -209,6 +210,8 @@ typedef struct
int interrupt_cycles;
void (*output_pins_changed)(UINT32 pins);
const device_config *device;
const address_space *program;
const address_space *data;
} dsp56k_core;
@ -249,7 +252,7 @@ static int dsp56k_icount;
/***************************************************************************
MEMORY ACCESSORS
***************************************************************************/
#define ROPCODE(pc) program_decrypted_read_word(pc)
#define ROPCODE(pc) memory_decrypted_read_word(core.program, pc)
/***************************************************************************
@ -401,6 +404,8 @@ static CPU_INIT( dsp56k )
//core.config = device->static_config;
//core.irq_callback = irqcallback;
core.device = device;
core.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
core.data = memory_find_address_space(device, ADDRESS_SPACE_DATA);
}
static void agu_reset(void)
@ -449,7 +454,7 @@ static CPU_RESET( dsp56k )
alu_reset();
/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU put in MAME */
program_write_word_16le(0x0000, 0x0124);
memory_write_word_16le(core.program, 0x0000, 0x0124);
}

46
src/emu/cpu/dsp56k/dsp56ops.c
View File

@ -2188,7 +2188,7 @@ static size_t dsp56k_op_bfop(const UINT16 op, const UINT16 op2, UINT8* cycles)
decode_BBB_bitmask(BITS(op2,0xe000), &iVal);
workAddr = assemble_address_from_Pppppp_table(BITS(OP,0x0020), BITS(OP,0x001f));
previousValue = data_read_word_16le(WORD(workAddr));
previousValue = memory_read_word_16le(core.data, WORD(workAddr));
workingWord = previousValue;
switch(BITS(op2, 0x1f00))
@ -2254,7 +2254,7 @@ static size_t dsp56k_op_bfop_1(const UINT16 op, const UINT16 op2, UINT8* cycles)
decode_RR_table(BITS(op,0x0003), &R);
workAddr = *((UINT16*)R.addr);
previousValue = data_read_word_16le(WORD(workAddr));
previousValue = memory_read_word_16le(core.data, WORD(workAddr));
workingWord = previousValue;
switch(BITS(op2, 0x1f00))
@ -3030,7 +3030,7 @@ static size_t dsp56k_op_movec(const UINT16 op, UINT8* cycles)
if (W)
{
/* Write D */
UINT16 value = data_read_word_16le(WORD(*((UINT16*)R.addr))) ;
UINT16 value = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr))) ;
typed_pointer temp_src = { &value, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@ -3072,7 +3072,7 @@ static size_t dsp56k_op_movec_1(const UINT16 op, UINT8* cycles)
if (W)
{
/* Write D */
UINT16 tempData = data_read_word_16le(WORD(memOffset));
UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@ -3116,7 +3116,7 @@ static size_t dsp56k_op_movec_2(const UINT16 op, UINT8* cycles)
if (W)
{
/* Write D */
UINT16 tempData = data_read_word_16le(WORD(memOffset));
UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@ -3167,7 +3167,7 @@ static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles
else
{
/* 16-bit long address */
UINT16 tempD = data_read_word_16le(WORD(op2));
UINT16 tempD = memory_read_word_16le(core.data, WORD(op2));
typed_pointer tempTP = {&tempD, DT_WORD};
SetDestinationValue(tempTP, SD);
}
@ -3245,7 +3245,7 @@ static size_t dsp56k_op_movec_5(const UINT16 op, const UINT16 op2, UINT8* cycles
if (W)
{
/* Write D */
UINT16 tempData = data_read_word_16le(WORD(memOffset));
UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@ -3308,7 +3308,7 @@ static size_t dsp56k_op_movem(const UINT16 op, UINT8* cycles)
{
/* Read from Program Memory */
typed_pointer data;
UINT16 ldata = program_read_word_16le(WORD(*((UINT16*)R.addr)));
UINT16 ldata = memory_read_word_16le(core.program, WORD(*((UINT16*)R.addr)));
data.addr = &ldata;
data.data_type = DT_WORD;
@ -3362,7 +3362,7 @@ static size_t dsp56k_op_movep(const UINT16 op, UINT8* cycles)
if (W)
{
UINT16 data = data_read_word_16le(WORD(pp));
UINT16 data = memory_read_word_16le(core.data, WORD(pp));
typed_pointer tempTP;
tempTP.addr = &data;
@ -3401,7 +3401,7 @@ static size_t dsp56k_op_movep_1(const UINT16 op, UINT8* cycles)
/* A little different than most W if's - opposite read and write */
if (W)
{
UINT16 data = data_read_word_16le(WORD(*((UINT16*)SD.addr)));
UINT16 data = memory_read_word_16le(core.data, WORD(*((UINT16*)SD.addr)));
typed_pointer tempTP;
tempTP.addr = &data;
@ -4352,7 +4352,7 @@ static void execute_x_memory_data_move(const UINT16 op, typed_pointer* d_registe
if (W)
{
/* From X:<ea> to SD */
UINT16 data = data_read_word_16le(WORD(*((UINT16*)R.addr)));
UINT16 data = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr)));
typed_pointer tempTP;
tempTP.addr = &data;
@ -4400,7 +4400,7 @@ static void execute_x_memory_data_move2(const UINT16 op, typed_pointer* d_regist
if (W)
{
/* Write D */
UINT16 value = data_read_word_16le(WORD(*mem_offset));
UINT16 value = memory_read_word_16le(core.data, WORD(*mem_offset));
typed_pointer tempV = {&value, DT_WORD};
SetDestinationValue(tempV, SD);
}
@ -4428,7 +4428,7 @@ static void execute_x_memory_data_move_with_short_displacement(const UINT16 op,
if (W)
{
/* Write D */
UINT16 tempData = data_read_word_16le(WORD(memOffset));
UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@ -4464,13 +4464,13 @@ static void execute_dual_x_memory_data_read(const UINT16 op, typed_pointer* d_re
fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.");
/* First memmove */
srcVal1 = data_read_word_16le(WORD(*((UINT16*)R.addr)));
srcVal1 = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr)));
tempV.addr = &srcVal1;
tempV.data_type = DT_WORD;
SetDestinationValue(tempV, D1);
/* Second memmove */
srcVal2 = data_read_word_16le(WORD(R3));
srcVal2 = memory_read_word_16le(core.data, WORD(R3));
tempV.addr = &srcVal2;
tempV.data_type = DT_WORD;
SetDestinationValue(tempV, D2);
@ -4565,13 +4565,13 @@ static void SetDataMemoryValue(typed_pointer source, UINT32 destinationAddr)
{
switch(source.data_type)
{
case DT_BYTE: data_write_word_16le(destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
case DT_WORD: data_write_word_16le(destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
case DT_DOUBLE_WORD: data_write_word_16le(destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
case DT_BYTE: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
case DT_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
case DT_DOUBLE_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
// !!! Is this universal ???
// !!! Forget not, yon shift-limiter !!!
case DT_LONG_WORD: data_write_word_16le(destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
case DT_LONG_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
}
}
@ -4580,13 +4580,13 @@ static void SetProgramMemoryValue(typed_pointer source, UINT32 destinationAddr)
{
switch(source.data_type)
{
case DT_BYTE: program_write_word_16le(destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
case DT_WORD: program_write_word_16le(destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
case DT_DOUBLE_WORD: program_write_word_16le(destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
case DT_BYTE: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
case DT_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
case DT_DOUBLE_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
// !!! Is this universal ???
// !!! Forget not, yon shift-limiter !!!
case DT_LONG_WORD: program_write_word_16le(destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
case DT_LONG_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
}
}

6
src/emu/cpu/dsp56k/dsp56pcu.c
View File

@ -150,8 +150,8 @@ static void pcu_reset(void)
// ...
// P:$cffe -> Internal P:$07ff low byte
// P:$cfff -> Internal P:$07ff high byte
UINT8 mem_value_low = program_read_byte_16le(mem_offset); /* TODO: IS THIS READING RIGHT? */
UINT8 mem_value_high = program_read_byte_16be(mem_offset);
UINT8 mem_value_low = memory_read_byte_16le(core.program, mem_offset); /* TODO: IS THIS READING RIGHT? */
UINT8 mem_value_high = memory_read_byte_16be(core.program, mem_offset);
dsp56k_program_ram[i] = (mem_value_high << 8) || mem_value_low;
}
@ -172,7 +172,7 @@ static void pcu_reset(void)
// they need. Once they've had their fill, they turn bootstrap mode off
// and the CPU begins execution at 0x0000;
// HACK - Read bit 15 at 0xc000 to see if we're working with the SSIO or host interface.
if (program_read_word_16le(0xc000<<1) & 0x8000)
if (memory_read_word_16le(core.program, 0xc000<<1) & 0x8000)
{
core.bootstrap_mode = BOOTSTRAP_SSIX;
logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from SSIx.\n");

72
src/emu/cpu/e132xs/e132xs.c
View File

@ -211,6 +211,7 @@
*********************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "cpuexec.h"
@ -224,16 +225,6 @@
#define DEBUG_PRINTF(x) do { } while (0)
#endif
static UINT8 (*hyp_cpu_read_byte)(offs_t address);
static UINT16 (*hyp_cpu_read_half_word)(offs_t address);
static UINT32 (*hyp_cpu_read_word)(offs_t address);
static UINT32 (*hyp_cpu_read_io_word)(offs_t address);
static void (*hyp_cpu_write_byte)(offs_t address, UINT8 data);
static void (*hyp_cpu_write_half_word)(offs_t address, UINT16 data);
static void (*hyp_cpu_write_word)(offs_t address, UINT32 data);
static void (*hyp_cpu_write_io_word)(offs_t address, UINT32 data);
int hyp_type_16bit;
// set C in adds/addsi/subs/sums
#define SETCARRYS 0
#define MISSIONCRAFT_FLAGS 1
@ -334,6 +325,9 @@ typedef struct
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
UINT32 opcodexor;
INT32 instruction_length;
INT32 intblock;
@ -386,31 +380,6 @@ static void check_interrupts(void);
#define SAME_SRC_DSTF (decode)->same_src_dstf
#define SAME_SRCF_DST (decode)->same_srcf_dst
#if (HAS_E116T || HAS_E116XT || HAS_E116XS || HAS_E116XSR || HAS_GMS30C2116 || HAS_GMS30C2216)
static UINT32 internal_program_read_dword_16be(offs_t address)
{
return (program_read_word_16be(address & ~1) << 16) | program_read_word_16be((address & ~1) + 2);
}
static void internal_program_write_dword_16be(offs_t address, UINT32 data)
{
program_write_word_16be(address & ~1, (data & 0xffff0000)>>16);
program_write_word_16be((address & ~1)+2, data & 0xffff);
}
static UINT32 internal_io_read_dword_16be(offs_t address)
{
return (io_read_word_16be(address & ~1)<< 16) | io_read_word_16be((address & ~1) + 2);
}
static void internal_io_write_dword_16be(offs_t address, UINT32 data)
{
io_write_word_16be(address & ~1, (data & 0xffff0000)>>16);
io_write_word_16be((address & ~1)+2, data & 0xffff);
}
#endif
// 4Kb IRAM (On-Chip Memory)
#if (HAS_E116T || HAS_GMS30C2116)
@ -1580,6 +1549,8 @@ static void hyperstone_init(const device_config *device, int index, int clock, c
hyperstone.irq_callback = irqcallback;
hyperstone.device = device;
hyperstone.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
hyperstone.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
hyperstone.timer = timer_alloc(e132xs_timer_callback, NULL);
hyperstone.clock_scale_mask = scale_mask;
}
@ -1587,19 +1558,8 @@ static void hyperstone_init(const device_config *device, int index, int clock, c
#if (HAS_E116T || HAS_E116XT || HAS_E116XS || HAS_E116XSR || HAS_GMS30C2116 || HAS_GMS30C2216)
static void e116_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int scale_mask)
{
hyp_cpu_read_byte = program_read_byte_16be;
hyp_cpu_read_half_word = program_read_word_16be;
hyp_cpu_read_word = internal_program_read_dword_16be;
hyp_cpu_read_io_word = internal_io_read_dword_16be;
hyp_cpu_write_byte = program_write_byte_16be;
hyp_cpu_write_half_word = program_write_word_16be;
hyp_cpu_write_word = internal_program_write_dword_16be;
hyp_cpu_write_io_word = internal_io_write_dword_16be;
hyp_type_16bit = 1;
hyperstone_init(device, index, clock, irqcallback, scale_mask);
hyperstone.opcodexor = 0;
}
#endif
@ -1648,19 +1608,8 @@ static CPU_INIT( gms30c2216 )
#if (HAS_E132N || HAS_E132T || HAS_E132XN || HAS_E132XT || HAS_E132XS || HAS_E132XSR || HAS_GMS30C2132 || HAS_GMS30C2232)
static void e132_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int scale_mask)
{
hyp_cpu_read_byte = program_read_byte_32be;
hyp_cpu_read_half_word = program_read_word_32be;
hyp_cpu_read_word = program_read_dword_32be;
hyp_cpu_read_io_word = io_read_dword_32be;
hyp_cpu_write_byte = program_write_byte_32be;
hyp_cpu_write_half_word = program_write_word_32be;
hyp_cpu_write_word = program_write_dword_32be;
hyp_cpu_write_io_word = io_write_dword_32be;
hyp_type_16bit = 0;
hyperstone_init(device, index, clock, irqcallback, scale_mask);
hyperstone.opcodexor = WORD_XOR_BE(0);
}
#endif
@ -1726,12 +1675,17 @@ static CPU_RESET( hyperstone )
emu_timer *save_timer;
cpu_irq_callback save_irqcallback;
UINT32 save_opcodexor;
save_timer = hyperstone.timer;
save_irqcallback = hyperstone.irq_callback;
save_opcodexor = hyperstone.opcodexor;
memset(&hyperstone, 0, sizeof(hyperstone_regs));
hyperstone.irq_callback = save_irqcallback;
hyperstone.opcodexor = save_opcodexor;
hyperstone.device = device;
hyperstone.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
hyperstone.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
hyperstone.timer = save_timer;
hyperstone.tr_clocks_per_tick = 2;

20
src/emu/cpu/e132xs/e132xs.h
View File

@ -81,32 +81,30 @@ CPU_GET_INFO( gms30c2232 );
extern unsigned dasm_hyperstone(char *buffer, unsigned pc, const UINT8 *oprom, unsigned h_flag, int private_fp);
extern int hyp_type_16bit;
/* Memory access */
/* read byte */
#define READ_B(addr) ((*hyp_cpu_read_byte)(addr))
#define READ_B(addr) memory_read_byte(hyperstone.program, (addr))
/* read half-word */
#define READ_HW(addr) ((*hyp_cpu_read_half_word)((addr) & ~1))
#define READ_HW(addr) memory_read_word(hyperstone.program, (addr) & ~1)
/* read word */
#define READ_W(addr) ((*hyp_cpu_read_word)((addr) & ~3))
#define READ_W(addr) memory_read_dword(hyperstone.program, (addr) & ~3)
/* write byte */
#define WRITE_B(addr, data) ((*hyp_cpu_write_byte)(addr, data))
#define WRITE_B(addr, data) memory_write_byte(hyperstone.program, addr, data)
/* write half-word */
#define WRITE_HW(addr, data) ((*hyp_cpu_write_half_word)((addr) & ~1, data))
#define WRITE_HW(addr, data) memory_write_word(hyperstone.program, (addr) & ~1, data)
/* write word */
#define WRITE_W(addr, data) ((*hyp_cpu_write_word)((addr) & ~3, data))
#define WRITE_W(addr, data) memory_write_dword(hyperstone.program, (addr) & ~3, data)
/* I/O access */
/* read word */
#define IO_READ_W(addr) ((*hyp_cpu_read_io_word)(((addr) >> 11) & 0x7ffc))
#define IO_READ_W(addr) memory_read_dword(hyperstone.io, ((addr) >> 11) & 0x7ffc)
/* write word */
#define IO_WRITE_W(addr, data) ((*hyp_cpu_write_io_word)(((addr) >> 11) & 0x7ffc, data))
#define IO_WRITE_W(addr, data) memory_write_dword(hyperstone.io, ((addr) >> 11) & 0x7ffc, data)
#define READ_OP(addr) (program_decrypted_read_word(hyp_type_16bit ? addr: WORD_XOR_BE(addr)))
#define READ_OP(addr) memory_decrypted_read_word(hyperstone.program, (addr) ^ hyperstone.opcodexor)
/* Registers Number */

35
src/emu/cpu/f8/f8.c
View File

@ -26,6 +26,7 @@
added interrupt functionality
*/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "f8.h"
@ -51,6 +52,8 @@ typedef struct {
UINT16 irq_vector;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *iospace;
UINT8 r[64]; /* scratchpad RAM */
int irq_request;
} f8_Regs;
@ -109,7 +112,7 @@ static void ROMC_00(int insttim) /* SKR - added parameter to tell if */
* of PC0.
*/
f8.dbus = program_decrypted_read_byte(f8.pc0);
f8.dbus = memory_decrypted_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
f8_icount -= insttim; /* SKR - ROMC00 is usually short, not short+long, */
/* but DS is long */
@ -123,7 +126,7 @@ static void ROMC_01(void)
* location addressed by PC0; then all devices add the 8-bit value
* on the data bus as signed binary number to PC0.
*/
f8.dbus = program_raw_read_byte(f8.pc0);
f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.pc0 += (INT8)f8.dbus;
f8_icount -= cL;
}
@ -136,7 +139,7 @@ static void ROMC_02(void)
* the memory location addressed by DC0; then all devices increment
* DC0.
*/
f8.dbus = program_read_byte_8be(f8.dc0);
f8.dbus = memory_read_byte_8be(f8.program, f8.dc0);
f8.dc0 += 1;
f8_icount -= cL;
}
@ -147,7 +150,7 @@ static void ROMC_03(int insttim) /* SKR - added parameter to tell if */
* Similiar to 0x00, except that it is used for immediate operands
* fetches (using PC0) instead of instruction fetches.
*/
f8.dbus = f8.io = program_raw_read_byte(f8.pc0);
f8.dbus = f8.io = memory_raw_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
f8_icount -= insttim;
}
@ -167,7 +170,7 @@ static void ROMC_05(void)
* Store the data bus contents into the memory location pointed
* to by DC0; increment DC0.
*/
program_write_byte_8be(f8.dc0, f8.dbus);
memory_write_byte_8be(f8.program, f8.dc0, f8.dbus);
f8.dc0 += 1;
f8_icount -= cL;
}
@ -241,7 +244,7 @@ static void ROMC_0C(void)
* by PC0 into the data bus; then all devices move the value that
* has just been placed on the data bus into the low order byte of PC0.
*/
f8.dbus = program_raw_read_byte(f8.pc0);
f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.pc0 = (f8.pc0 & 0xff00) | f8.dbus;
f8_icount -= cL;
}
@ -264,7 +267,7 @@ static void ROMC_0E(void)
* The value on the data bus is then moved to the low order byte
* of DC0 by all devices.
*/
f8.dbus = program_raw_read_byte(f8.pc0);
f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.dc0 = (f8.dc0 & 0xff00) | f8.dbus;
f8_icount -= cL;
}
@ -304,7 +307,7 @@ static void ROMC_11(void)
* data bus. All devices must then move the contents of the
* data bus to the upper byte of DC0.
*/
f8.dbus = program_raw_read_byte(f8.pc0);
f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.dc0 = (f8.dc0 & 0x00ff) | (f8.dbus << 8);
f8_icount -= cL;
}
@ -403,7 +406,7 @@ static void ROMC_1A(void)
* register was addressed; the device containing the addressed port
* must place the contents of the data bus into the address port.
*/
io_write_byte_8be(f8.io, f8.dbus);
memory_write_byte_8be(f8.iospace, f8.io, f8.dbus);
f8_icount -= cL;
}
@ -416,7 +419,7 @@ static void ROMC_1B(void)
* contents of timer and interrupt control registers cannot be read
* back onto the data bus).
*/
f8.dbus = io_read_byte_8be(f8.io);
f8.dbus = memory_read_byte_8be(f8.iospace, f8.io);
f8_icount -= cL;
}
@ -1258,7 +1261,7 @@ static void f8_ins_0(int n)
{
ROMC_1C(cS);
CLR_OZCS;
f8.a = io_read_byte_8be(n);
f8.a = memory_read_byte_8be(f8.iospace, n);
SET_SZ(f8.a);
}
@ -1283,7 +1286,7 @@ static void f8_ins_1(int n)
static void f8_outs_0(int n)
{
ROMC_1C(cS);
io_write_byte_8be(n, f8.a);
memory_write_byte_8be(f8.iospace, n, f8.a);
}
/***************************************************
@ -1540,6 +1543,8 @@ static CPU_RESET( f8 )
memset(&f8, 0, sizeof(f8_Regs));
f8.irq_callback = save_callback;
f8.device = device;
f8.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
f8.iospace = memory_find_address_space(device, ADDRESS_SPACE_IO);
f8.w&=~I;
/* save PC0 to PC1 and reset PC0 */
@ -1898,6 +1903,8 @@ static CPU_INIT( f8 )
{
f8.irq_callback = irqcallback;
f8.device = device;
f8.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
f8.iospace = memory_find_address_space(device, ADDRESS_SPACE_IO);
}
static CPU_SET_INFO( f8 )
@ -1908,14 +1915,14 @@ static CPU_SET_INFO( f8 )
case CPUINFO_INT_SP: f8.pc1 = info->i; break;
case CPUINFO_INT_PC:
f8.pc0 = info->i;
f8.dbus = program_decrypted_read_byte(f8.pc0);
f8.dbus = memory_decrypted_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
break;
case CPUINFO_INT_PREVIOUSPC: break; /* TODO? */
case CPUINFO_INT_INPUT_STATE: f8.irq_request = info->i; break;
case CPUINFO_INT_REGISTER + F8_PC0:
f8.pc0 = info->i;
f8.dbus = program_decrypted_read_byte(f8.pc0);
f8.dbus = memory_decrypted_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
break;
case CPUINFO_INT_REGISTER + F8_PC1: f8.pc1 = info->i; break;

2
src/emu/cpu/g65816/g65816.c
View File

@ -84,6 +84,7 @@ TODO general:
/* ================================= DATA ================================= */
/* ======================================================================== */
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "g65816cm.h"
/* Our CPU structure */
@ -330,6 +331,7 @@ static CPU_INIT( g65816 )
{
g65816_set_irq_callback(irqcallback);
g65816i_cpu.device = device;
g65816i_cpu.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
state_save_register_item("G65816", device->tag, 0, g65816i_cpu.a);
state_save_register_item("G65816", device->tag, 0, g65816i_cpu.b);

6
src/emu/cpu/g65816/g65816.h
View File

@ -94,9 +94,9 @@ CPU_GET_INFO( g65816 );
#undef G65816_CALL_DEBUGGER
#define G65816_CALL_DEBUGGER(x) debugger_instruction_hook(g65816i_cpu.device, x)
#define g65816_read_8(addr) program_read_byte_8be(addr)
#define g65816_write_8(addr,data) program_write_byte_8be(addr,data)
#define g65816_read_8_immediate(A) program_read_byte_8be(A)
#define g65816_read_8(addr) memory_read_byte_8be(g65816i_cpu.program, addr)
#define g65816_write_8(addr,data) memory_write_byte_8be(g65816i_cpu.program, addr,data)
#define g65816_read_8_immediate(A) memory_read_byte_8be(g65816i_cpu.program, A)
#define g65816_jumping(A) change_pc(A)
#define g65816_branching(A)

1
src/emu/cpu/g65816/g65816cm.h
View File

@ -90,6 +90,7 @@ struct _g65816i_cpu_struct
uint irq_delay; /* delay 1 instruction before checking irq */
cpu_irq_callback int_ack; /* Interrupt Acknowledge */
const device_config *device;
const address_space *program;
read8_space_func read_vector; /* Read vector override */
uint stopped; /* Sets how the CPU is stopped */
void (*const *opcodes)(void);

6
src/emu/cpu/h6280/h6280.c
View File

@ -107,6 +107,7 @@
- Improvements to the handling of taking of delayed interrupts.
******************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "h6280.h"
@ -139,6 +140,8 @@ typedef struct
UINT8 irq_pending;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
#if LAZY_FLAGS
INT32 NZ; /* last value (lazy N and Z flag) */
@ -188,6 +191,8 @@ static CPU_INIT( h6280 )
h6280.irq_callback = irqcallback;
h6280.device = device;
h6280.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
h6280.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
}
static CPU_RESET( h6280 )
@ -200,6 +205,7 @@ static CPU_RESET( h6280 )
memset(&h6280, 0, sizeof(h6280_Regs));
h6280.irq_callback = save_irqcallback;
h6280.device = device;
h6280.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* set I and B flags */
P = _fI | _fB;

34
src/emu/cpu/h6280/h6280ops.h
View File

@ -128,7 +128,7 @@
***************************************************************/
INLINE UINT8 RDMEM(offs_t addr) {
CHECK_VDC_VCE_PENALTY(addr);
return program_read_byte_8le(TRANSLATED(addr));
return memory_read_byte_8le(h6280.program, TRANSLATED(addr));
}
/***************************************************************
@ -136,60 +136,60 @@ INLINE UINT8 RDMEM(offs_t addr) {
***************************************************************/
INLINE void WRMEM(offs_t addr, UINT8 data) {
CHECK_VDC_VCE_PENALTY(addr);
program_write_byte_8le(TRANSLATED(addr),data);
memory_write_byte_8le(h6280.program, TRANSLATED(addr),data);
}
/***************************************************************
* RDMEMZ read memory - zero page
***************************************************************/
#define RDMEMZ(addr) \
program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff));
memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff));
/***************************************************************
* WRMEMZ write memory - zero page
***************************************************************/
#define WRMEMZ(addr,data) \
program_write_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff),data);
memory_write_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff),data);
/***************************************************************
* RDMEMW read word from memory
***************************************************************/
#define RDMEMW(addr) \
program_read_byte_8le(TRANSLATED(addr)) \
| ( program_read_byte_8le(TRANSLATED(addr+1)) << 8 )
memory_read_byte_8le(h6280.program, TRANSLATED(addr)) \
| ( memory_read_byte_8le(h6280.program, TRANSLATED(addr+1)) << 8 )
/***************************************************************
* RDZPWORD read a word from a zero page address
***************************************************************/
#define RDZPWORD(addr) \
((addr&0xff)==0xff) ? \
program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
+(program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr-0xff)&0x1fff))<<8) : \
program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
+(program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr+1)&0x1fff))<<8)
memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
+(memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr-0xff)&0x1fff))<<8) : \
memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
+(memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr+1)&0x1fff))<<8)
/***************************************************************
* push a register onto the stack
***************************************************************/
#define PUSH(Rg) program_write_byte_8le( (h6280.mmr[1] << 13) | h6280.sp.d,Rg); S--
#define PUSH(Rg) memory_write_byte_8le(h6280.program, (h6280.mmr[1] << 13) | h6280.sp.d,Rg); S--
/***************************************************************
* pull a register from the stack
***************************************************************/
#define PULL(Rg) S++; Rg = program_read_byte_8le( (h6280.mmr[1] << 13) | h6280.sp.d)
#define PULL(Rg) S++; Rg = memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | h6280.sp.d)
/***************************************************************
* RDOP read an opcode
***************************************************************/
#define RDOP() \
program_decrypted_read_byte(TRANSLATED(PCW))
memory_decrypted_read_byte(h6280.program, TRANSLATED(PCW))
/***************************************************************
* RDOPARG read an opcode argument
***************************************************************/
#define RDOPARG() \
program_raw_read_byte(TRANSLATED(PCW))
memory_raw_read_byte(h6280.program, TRANSLATED(PCW))
/***************************************************************
* BRA branch relative
@ -1121,21 +1121,21 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
***************************************************************/
#define ST0 \
CLEAR_T; \
io_write_byte_8le(0x0000,tmp)
memory_write_byte_8le(h6280.io,0x0000,tmp)
/* 6280 ********************************************************
* ST1 Store at hardware address 2
***************************************************************/
#define ST1 \
CLEAR_T; \
io_write_byte_8le(0x0002,tmp)
memory_write_byte_8le(h6280.io,0x0002,tmp)
/* 6280 ********************************************************
* ST2 Store at hardware address 3
***************************************************************/
#define ST2 \
CLEAR_T; \
io_write_byte_8le(0x0003,tmp)
memory_write_byte_8le(h6280.io,0x0003,tmp)
/* 6280 ********************************************************
* STA Store accumulator

8
src/emu/cpu/i386/i386.c
View File

@ -443,7 +443,7 @@ static void I386OP(decode_two_byte)(void)
/*************************************************************************/
static UINT64 i386_debug_segbase(void *ref, UINT32 params, const UINT64 *param)
static UINT64 i386_debug_segbase(void *globalref, void *ref, UINT32 params, const UINT64 *param)
{
UINT32 result;
I386_SREG seg;
@ -462,7 +462,7 @@ static UINT64 i386_debug_segbase(void *ref, UINT32 params, const UINT64 *param)
return result;
}
static UINT64 i386_debug_seglimit(void *ref, UINT32 params, const UINT64 *param)
static UINT64 i386_debug_seglimit(void *globalref, void *ref, UINT32 params, const UINT64 *param)
{
UINT32 result = 0;
I386_SREG seg;
@ -524,6 +524,8 @@ static CPU_INIT( i386 )
I.irq_callback = irqcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
state_save_register_item_array(state_type, device->tag, 0, I.reg.d);
state_save_register_item(state_type, device->tag, 0, I.sreg[ES].selector);
@ -620,6 +622,8 @@ static CPU_RESET( i386 )
memset( &I, 0, sizeof(I386_REGS) );
I.irq_callback = save_irqcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
I.sreg[CS].selector = 0xf000;
I.sreg[CS].base = 0xffff0000;

113
src/emu/cpu/i386/i386.h
View File

@ -3,6 +3,7 @@
#ifndef __I386_H__
#define __I386_H__
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "cpuintrf.h"
#define I386OP(XX) i386_##XX
@ -251,6 +252,8 @@ typedef struct {
UINT8 irq_state;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
UINT32 a20_mask;
int cpuid_max_input_value_eax;
@ -361,8 +364,8 @@ INLINE int translate_address(UINT32 *address)
UINT32 offset = a & 0xfff;
// TODO: 4MB pages
UINT32 page_dir = program_read_dword_32le(pdbr + directory * 4);
UINT32 page_entry = program_read_dword_32le((page_dir & 0xfffff000) + (table * 4));
UINT32 page_dir = memory_read_dword_32le(I.program, pdbr + directory * 4);
UINT32 page_entry = memory_read_dword_32le(I.program, (page_dir & 0xfffff000) + (table * 4));
*address = (page_entry & 0xfffff000) | offset;
return 1;
@ -410,7 +413,7 @@ INLINE UINT8 FETCH(void)
translate_address(&address);
}
value = program_decrypted_read_byte(address & I.a20_mask);
value = memory_decrypted_read_byte(I.program, address & I.a20_mask);
I.eip++;
I.pc++;
return value;
@ -427,11 +430,11 @@ INLINE UINT16 FETCH16(void)
if( address & 0x1 ) { /* Unaligned read */
address &= I.a20_mask;
value = (program_decrypted_read_byte(address+0) << 0) |
(program_decrypted_read_byte(address+1) << 8);
value = (memory_decrypted_read_byte(I.program, address+0) << 0) |
(memory_decrypted_read_byte(I.program, address+1) << 8);
} else {
address &= I.a20_mask;
value = program_decrypted_read_word(address);
value = memory_decrypted_read_word(I.program, address);
}
I.eip += 2;
I.pc += 2;
@ -449,13 +452,13 @@ INLINE UINT32 FETCH32(void)
if( I.pc & 0x3 ) { /* Unaligned read */
address &= I.a20_mask;
value = (program_decrypted_read_byte(address+0) << 0) |
(program_decrypted_read_byte(address+1) << 8) |
(program_decrypted_read_byte(address+2) << 16) |
(program_decrypted_read_byte(address+3) << 24);
value = (memory_decrypted_read_byte(I.program, address+0) << 0) |
(memory_decrypted_read_byte(I.program, address+1) << 8) |
(memory_decrypted_read_byte(I.program, address+2) << 16) |
(memory_decrypted_read_byte(I.program, address+3) << 24);
} else {
address &= I.a20_mask;
value = program_decrypted_read_dword(address);
value = memory_decrypted_read_dword(I.program, address);
}
I.eip += 4;
I.pc += 4;
@ -472,7 +475,7 @@ INLINE UINT8 READ8(UINT32 ea)
}
address &= I.a20_mask;
return program_read_byte_32le(address);
return memory_read_byte_32le(I.program, address);
}
INLINE UINT16 READ16(UINT32 ea)
{
@ -486,10 +489,10 @@ INLINE UINT16 READ16(UINT32 ea)
address &= I.a20_mask;
if( ea & 0x1 ) { /* Unaligned read */
value = (program_read_byte_32le( address+0 ) << 0) |
(program_read_byte_32le( address+1 ) << 8);
value = (memory_read_byte_32le( I.program, address+0 ) << 0) |
(memory_read_byte_32le( I.program, address+1 ) << 8);
} else {
value = program_read_word_32le( address );
value = memory_read_word_32le( I.program, address );
}
return value;
}
@ -505,12 +508,12 @@ INLINE UINT32 READ32(UINT32 ea)
address &= I.a20_mask;
if( ea & 0x3 ) { /* Unaligned read */
value = (program_read_byte_32le( address+0 ) << 0) |
(program_read_byte_32le( address+1 ) << 8) |
(program_read_byte_32le( address+2 ) << 16) |
(program_read_byte_32le( address+3 ) << 24);
value = (memory_read_byte_32le( I.program, address+0 ) << 0) |
(memory_read_byte_32le( I.program, address+1 ) << 8) |
(memory_read_byte_32le( I.program, address+2 ) << 16) |
(memory_read_byte_32le( I.program, address+3 ) << 24);
} else {
value = program_read_dword_32le( address );
value = memory_read_dword_32le( I.program, address );
}
return value;
}
@ -527,17 +530,17 @@ INLINE UINT64 READ64(UINT32 ea)
address &= I.a20_mask;
if( ea & 0x7 ) { /* Unaligned read */
value = (((UINT64) program_read_byte_32le( address+0 )) << 0) |
(((UINT64) program_read_byte_32le( address+1 )) << 8) |
(((UINT64) program_read_byte_32le( address+2 )) << 16) |
(((UINT64) program_read_byte_32le( address+3 )) << 24) |
(((UINT64) program_read_byte_32le( address+4 )) << 32) |
(((UINT64) program_read_byte_32le( address+5 )) << 40) |
(((UINT64) program_read_byte_32le( address+6 )) << 48) |
(((UINT64) program_read_byte_32le( address+7 )) << 56);
value = (((UINT64) memory_read_byte_32le( I.program, address+0 )) << 0) |
(((UINT64) memory_read_byte_32le( I.program, address+1 )) << 8) |
(((UINT64) memory_read_byte_32le( I.program, address+2 )) << 16) |
(((UINT64) memory_read_byte_32le( I.program, address+3 )) << 24) |
(((UINT64) memory_read_byte_32le( I.program, address+4 )) << 32) |
(((UINT64) memory_read_byte_32le( I.program, address+5 )) << 40) |
(((UINT64) memory_read_byte_32le( I.program, address+6 )) << 48) |
(((UINT64) memory_read_byte_32le( I.program, address+7 )) << 56);
} else {
value = (((UINT64) program_read_dword_32le( address+0 )) << 0) |
(((UINT64) program_read_dword_32le( address+4 )) << 32);
value = (((UINT64) memory_read_dword_32le( I.program, address+0 )) << 0) |
(((UINT64) memory_read_dword_32le( I.program, address+4 )) << 32);
}
return value;
}
@ -552,7 +555,7 @@ INLINE void WRITE8(UINT32 ea, UINT8 value)
}
address &= I.a20_mask;
program_write_byte_32le(address, value);
memory_write_byte_32le(I.program, address, value);
}
INLINE void WRITE16(UINT32 ea, UINT16 value)
{
@ -565,10 +568,10 @@ INLINE void WRITE16(UINT32 ea, UINT16 value)
address &= I.a20_mask;
if( ea & 0x1 ) { /* Unaligned write */
program_write_byte_32le( address+0, value & 0xff );
program_write_byte_32le( address+1, (value >> 8) & 0xff );
memory_write_byte_32le( I.program, address+0, value & 0xff );
memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff );
} else {
program_write_word_32le(address, value);
memory_write_word_32le(I.program, address, value);
}
}
INLINE void WRITE32(UINT32 ea, UINT32 value)
@ -582,12 +585,12 @@ INLINE void WRITE32(UINT32 ea, UINT32 value)
ea &= I.a20_mask;
if( ea & 0x3 ) { /* Unaligned write */
program_write_byte_32le( address+0, value & 0xff );
program_write_byte_32le( address+1, (value >> 8) & 0xff );
program_write_byte_32le( address+2, (value >> 16) & 0xff );
program_write_byte_32le( address+3, (value >> 24) & 0xff );
memory_write_byte_32le( I.program, address+0, value & 0xff );
memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff );
memory_write_byte_32le( I.program, address+2, (value >> 16) & 0xff );
memory_write_byte_32le( I.program, address+3, (value >> 24) & 0xff );
} else {
program_write_dword_32le(address, value);
memory_write_dword_32le(I.program, address, value);
}
}
@ -602,17 +605,17 @@ INLINE void WRITE64(UINT32 ea, UINT64 value)
ea &= I.a20_mask;
if( ea & 0x7 ) { /* Unaligned write */
program_write_byte_32le( address+0, value & 0xff );
program_write_byte_32le( address+1, (value >> 8) & 0xff );
program_write_byte_32le( address+2, (value >> 16) & 0xff );
program_write_byte_32le( address+3, (value >> 24) & 0xff );
program_write_byte_32le( address+4, (value >> 32) & 0xff );
program_write_byte_32le( address+5, (value >> 40) & 0xff );
program_write_byte_32le( address+6, (value >> 48) & 0xff );
program_write_byte_32le( address+7, (value >> 56) & 0xff );
memory_write_byte_32le( I.program, address+0, value & 0xff );
memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff );
memory_write_byte_32le( I.program, address+2, (value >> 16) & 0xff );
memory_write_byte_32le( I.program, address+3, (value >> 24) & 0xff );
memory_write_byte_32le( I.program, address+4, (value >> 32) & 0xff );
memory_write_byte_32le( I.program, address+5, (value >> 40) & 0xff );
memory_write_byte_32le( I.program, address+6, (value >> 48) & 0xff );
memory_write_byte_32le( I.program, address+7, (value >> 56) & 0xff );
} else {
program_write_dword_32le(address+0, value & 0xffffffff);
program_write_dword_32le(address+4, (value >> 32) & 0xffffffff);
memory_write_dword_32le(I.program, address+0, value & 0xffffffff);
memory_write_dword_32le(I.program, address+4, (value >> 32) & 0xffffffff);
}
}
@ -893,11 +896,11 @@ INLINE void BUMP_DI(int adjustment)
/***********************************************************************************/
#define READPORT8(port) (io_read_byte_32le(port))
#define READPORT16(port) (io_read_word_32le(port))
#define READPORT32(port) (io_read_dword_32le(port))
#define WRITEPORT8(port, value) (io_write_byte_32le(port, value))
#define WRITEPORT16(port, value) (io_write_word_32le(port, value))
#define WRITEPORT32(port, value) (io_write_dword_32le(port, value))
#define READPORT8(port) (memory_read_byte_32le(I.io, port))
#define READPORT16(port) (memory_read_word_32le(I.io, port))
#define READPORT32(port) (memory_read_dword_32le(I.io, port))
#define WRITEPORT8(port, value) (memory_write_byte_32le(I.io, port, value))
#define WRITEPORT16(port, value) (memory_write_word_32le(I.io, port, value))
#define WRITEPORT32(port, value) (memory_write_dword_32le(I.io, port, value))
#endif /* __I386_H__ */

18
src/emu/cpu/i8085/i8085.c
View File

@ -124,6 +124,7 @@
/*int survival_prot = 0; */
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "i8085.h"
#include "i8085cpu.h"
@ -149,6 +150,8 @@ typedef struct {
INT8 irq_state[4];
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
void (*sod_callback)(int state);
int (*sid_callback)(void);
} i8085_Regs;
@ -162,20 +165,20 @@ static UINT8 RIM_IEN = 0; //AT: IEN status latch used by the RIM instruction
static UINT8 ROP(void)
{
I.STATUS = 0xa2; // instruction fetch
return program_decrypted_read_byte(I.PC.w.l++);
return memory_decrypted_read_byte(I.program, I.PC.w.l++);
}
static UINT8 ARG(void)
{
return program_raw_read_byte(I.PC.w.l++);
return memory_raw_read_byte(I.program, I.PC.w.l++);
}
static UINT16 ARG16(void)
{
UINT16 w;
w = program_raw_read_byte(I.PC.d);
w = memory_raw_read_byte(I.program, I.PC.d);
I.PC.w.l++;
w += program_raw_read_byte(I.PC.d) << 8;
w += memory_raw_read_byte(I.program, I.PC.d) << 8;
I.PC.w.l++;
return w;
}
@ -183,13 +186,13 @@ static UINT16 ARG16(void)
static UINT8 RM(UINT32 a)
{
I.STATUS = 0x82; // memory read
return program_read_byte_8le(a);
return memory_read_byte_8le(I.program, a);
}
static void WM(UINT32 a, UINT8 v)
{
I.STATUS = 0x00; // memory write
program_write_byte_8le(a, v);
memory_write_byte_8le(I.program, a, v);
}
INLINE void execute_one(int opcode)
@ -1362,6 +1365,8 @@ static CPU_INIT( i8085 )
I.cputype = 1;
I.irq_callback = irqcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
state_save_register_item("i8085", device->tag, 0, I.AF.w.l);
state_save_register_item("i8085", device->tag, 0, I.BC.w.l);
@ -1399,6 +1404,7 @@ static CPU_RESET( i8085 )
I.sod_callback = save_sodcallback;
I.sid_callback = save_sidcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
change_pc(I.PC.d);
I.cputype = cputype_bak;

12
src/emu/cpu/i8085/i8085cpu.h
View File

@ -109,12 +109,12 @@ int q = I.AF.b.h+R; \
#define M_IN \
I.STATUS = 0x42; \
I.XX.d=ARG(); \
I.AF.b.h=io_read_byte_8le(I.XX.d);
I.AF.b.h=memory_read_byte_8le(I.io, I.XX.d);
#define M_OUT \
I.STATUS = 0x10; \
I.XX.d=ARG(); \
io_write_byte_8le(I.XX.d,I.AF.b.h)
memory_write_byte_8le(I.io, I.XX.d,I.AF.b.h)
#define M_DAD(R) { \
int q = I.HL.d + I.R.d; \
@ -126,14 +126,14 @@ int q = I.AF.b.h+R; \
#define M_PUSH(R) { \
I.STATUS = 0x04; \
program_write_byte_8le(--I.SP.w.l, I.R.b.h); \
program_write_byte_8le(--I.SP.w.l, I.R.b.l); \
memory_write_byte_8le(I.program, --I.SP.w.l, I.R.b.h); \
memory_write_byte_8le(I.program, --I.SP.w.l, I.R.b.l); \
}
#define M_POP(R) { \
I.STATUS = 0x86; \
I.R.b.l = program_read_byte_8le(I.SP.w.l++); \
I.R.b.h = program_read_byte_8le(I.SP.w.l++); \
I.R.b.l = memory_read_byte_8le(I.program, I.SP.w.l++); \
I.R.b.h = memory_read_byte_8le(I.program, I.SP.w.l++); \
}
#define M_RET(cc) \

5
src/emu/cpu/i86/i286.c
View File

@ -3,6 +3,7 @@
* (initial work based on David Hedley's pcemu) *
****************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "host.h"
@ -59,6 +60,8 @@ typedef struct
} ldtr, tr;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
INT32 AuxVal, OverVal, SignVal, ZeroVal, CarryVal, DirVal; /* 0 or non-0 valued flags */
UINT8 ParityVal;
UINT8 TF, IF; /* 0 or 1 valued flags */
@ -288,6 +291,8 @@ static CPU_INIT( i80286 )
I.irq_callback = irqcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
/* If a reset parameter is given, take it as pointer to an address mask */
if( device->static_config )

7
src/emu/cpu/i86/i86.c
View File

@ -4,6 +4,7 @@
****************************************************************************/
/* 26.March 2000 PeT changed set_irq_line */
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "cpuintrf.h"
@ -41,6 +42,8 @@ typedef struct
UINT16 flags;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
INT32 AuxVal, OverVal, SignVal, ZeroVal, CarryVal, DirVal; /* 0 or non-0 valued flags */
UINT8 ParityVal;
UINT8 TF, IF; /* 0 or 1 valued flags */
@ -143,6 +146,8 @@ static CPU_INIT( i8086 )
I.irq_callback = irqcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
i8086_state_register(device);
configure_memory_16bit();
@ -167,6 +172,8 @@ static CPU_RESET( i8086 )
I.irq_callback = save_irqcallback;
I.mem = save_mem;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
I.sregs[CS] = 0xf000;
I.base[CS] = SegBase(CS);

24
src/emu/cpu/i86/i86.h
View File

@ -71,15 +71,15 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
/************************************************************************/
#define read_byte(a) (*I.mem.rbyte)(a)
#define read_word(a) (*I.mem.rword)(a)
#define write_byte(a,d) (*I.mem.wbyte)((a),(d))
#define write_word(a,d) (*I.mem.wword)((a),(d))
#define read_byte(a) (*I.mem.rbyte)(I.program, a)
#define read_word(a) (*I.mem.rword)(I.program, a)
#define write_byte(a,d) (*I.mem.wbyte)(I.program, (a),(d))
#define write_word(a,d) (*I.mem.wword)(I.program, (a),(d))
#define read_port_byte(a) (*I.mem.rbyte_port)(a)
#define read_port_word(a) (*I.mem.rword_port)(a)
#define write_port_byte(a,d) (*I.mem.wbyte_port)((a),(d))
#define write_port_word(a,d) (*I.mem.wword_port)((a),(d))
#define read_port_byte(a) (*I.mem.rbyte)(I.io, a)
#define read_port_word(a) (*I.mem.rword)(I.io, a)
#define write_port_byte(a,d) (*I.mem.wbyte)(I.io, (a),(d))
#define write_port_word(a,d) (*I.mem.wword)(I.io, (a),(d))
/************************************************************************/
@ -99,10 +99,10 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
#define WriteWord(ea,val) write_word((ea) & AMASK, val);
#define FETCH_XOR(a) ((a) ^ I.mem.fetch_xor)
#define FETCH (program_raw_read_byte(FETCH_XOR(I.pc++)))
#define FETCHOP (program_decrypted_read_byte(FETCH_XOR(I.pc++)))
#define PEEKOP(addr) (program_decrypted_read_byte(FETCH_XOR(addr)))
#define FETCHWORD(var) { var = program_raw_read_byte(FETCH_XOR(I.pc)); var += (program_raw_read_byte(FETCH_XOR(I.pc + 1)) << 8); I.pc += 2; }
#define FETCH (memory_raw_read_byte(I.program, FETCH_XOR(I.pc++)))
#define FETCHOP (memory_decrypted_read_byte(I.program, FETCH_XOR(I.pc++)))
#define PEEKOP(addr) (memory_decrypted_read_byte(I.program, FETCH_XOR(addr)))
#define FETCHWORD(var) { var = memory_raw_read_byte(I.program, FETCH_XOR(I.pc)); var += (memory_raw_read_byte(I.program, FETCH_XOR(I.pc + 1)) << 8); I.pc += 2; }
#define CHANGE_PC(addr) change_pc(addr)
#define PUSH(val) { I.regs.w[SP] -= 2; WriteWord(((I.base[SS] + I.regs.w[SP]) & AMASK), val); }
#define POP(var) { var = ReadWord(((I.base[SS] + I.regs.w[SP]) & AMASK)); I.regs.w[SP] += 2; }

60
src/emu/cpu/i86/i86mem.c
View File

@ -8,15 +8,10 @@ static void configure_memory_8bit(void)
{
I.mem.fetch_xor = 0;
I.mem.rbyte = program_read_byte_8le;
I.mem.rword = program_read_word_8le;
I.mem.wbyte = program_write_byte_8le;
I.mem.wword = program_write_word_8le;
I.mem.rbyte_port = io_read_byte_8le;
I.mem.rword_port = io_read_word_8le;
I.mem.wbyte_port = io_write_byte_8le;
I.mem.wword_port = io_write_word_8le;
I.mem.rbyte = memory_read_byte_8le;
I.mem.rword = memory_read_word_8le;
I.mem.wbyte = memory_write_byte_8le;
I.mem.wword = memory_write_word_8le;
}
#endif
#endif
@ -26,47 +21,25 @@ static void configure_memory_8bit(void)
16-bit memory accessors
*****************************************************************************/
static UINT16 read_word_16le(offs_t addr)
static UINT16 read_word_16le(const address_space *space, offs_t addr)
{
if (!(addr & 1))
return program_read_word_16le(addr);
return memory_read_word_16le(space, addr);
else
{
UINT16 result = program_read_byte_16le(addr);
return result | (program_read_byte_16le(addr + 1) << 8);
UINT16 result = memory_read_byte_16le(space, addr);
return result | (memory_read_byte_16le(space, addr + 1) << 8);
}
}
static void write_word_16le(offs_t addr, UINT16 data)
static void write_word_16le(const address_space *space, offs_t addr, UINT16 data)
{
if (!(addr & 1))
program_write_word_16le(addr, data);
memory_write_word_16le(space, addr, data);
else
{
program_write_byte_16le(addr, data);
program_write_byte_16le(addr + 1, data >> 8);
}
}
static UINT16 read_port_word_16le(offs_t addr)
{
if (!(addr & 1))
return io_read_word_16le(addr);
else
{
UINT16 result = io_read_byte_16le(addr);
return result | (io_read_byte_16le(addr + 1) << 8);
}
}
static void write_port_word_16le(offs_t addr, UINT16 data)
{
if (!(addr & 1))
io_write_word_16le(addr, data);
else
{
io_write_byte_16le(addr, data);
io_write_byte_16le(addr + 1, data >> 8);
memory_write_byte_16le(space, addr, data);
memory_write_byte_16le(space, addr + 1, data >> 8);
}
}
@ -74,13 +47,8 @@ static void configure_memory_16bit(void)
{
I.mem.fetch_xor = BYTE_XOR_LE(0);
I.mem.rbyte = program_read_byte_16le;
I.mem.rbyte = memory_read_byte_16le;
I.mem.rword = read_word_16le;
I.mem.wbyte = program_write_byte_16le;
I.mem.wbyte = memory_write_byte_16le;
I.mem.wword = write_word_16le;
I.mem.rbyte_port = io_read_byte_16le;
I.mem.rword_port = read_port_word_16le;
I.mem.wbyte_port = io_write_byte_16le;
I.mem.wword_port = write_port_word_16le;
}

13
src/emu/cpu/i86/i86mem.h
View File

@ -3,13 +3,8 @@ struct _memory_interface
{
offs_t fetch_xor;
UINT8 (*rbyte)(offs_t);
UINT16 (*rword)(offs_t);
void (*wbyte)(offs_t, UINT8);
void (*wword)(offs_t, UINT16);
UINT8 (*rbyte_port)(offs_t);
UINT16 (*rword_port)(offs_t);
void (*wbyte_port)(offs_t, UINT8);
void (*wword_port)(offs_t, UINT16);
UINT8 (*rbyte)(const address_space *, offs_t);
UINT16 (*rword)(const address_space *, offs_t);
void (*wbyte)(const address_space *, offs_t, UINT8);
void (*wword)(const address_space *, offs_t, UINT16);
};

89
src/emu/cpu/i8x41/i8x41.c
View File

@ -114,6 +114,7 @@
*/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "i8x41.h"
@ -137,19 +138,22 @@ struct _upi41_state_t {
UINT8 ram_mask;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *data;
const address_space *io;
int icount;
};
#define RM(a) program_read_byte_8le(a)
#define RM(s,a) memory_read_byte_8le((s)->program, a)
#define IRAM_R(a) data_read_byte_8le((a) & upi41_state->ram_mask)
#define IRAM_W(a,v) data_write_byte_8le((a) & upi41_state->ram_mask, v)
#define IRAM_R(s,a) memory_read_byte_8le((s)->data, (a) & upi41_state->ram_mask)
#define IRAM_W(s,a,v) memory_write_byte_8le((s)->data, (a) & upi41_state->ram_mask, v)
#define RP(a) io_read_byte_8le(a)
#define WP(a,v) io_write_byte_8le(a,v)
#define RP(s,a) memory_read_byte_8le((s)->io, a)
#define WP(s,a,v) memory_write_byte_8le((s)->io, a,v)
#define ROP(pc) program_decrypted_read_byte(pc)
#define ROP_ARG(pc) program_raw_read_byte(pc)
#define ROP(s,pc) memory_decrypted_read_byte((s)->program, pc)
#define ROP_ARG(s,pc) memory_raw_read_byte((s)->program, pc)
/* PC vectors */
#define V_RESET 0x000 /* power on address */
@ -218,8 +222,8 @@ struct _upi41_state_t {
#define CONTROL upi41_state->control
#define GETR(n) (IRAM_R(((PSW & BS) ? M_BANK1:M_BANK0)+(n)))
#define SETR(n,v) (IRAM_W(((PSW & BS) ? M_BANK1:M_BANK0)+(n), (v)))
#define GETR(s,n) (IRAM_R((s), ((PSW & BS) ? M_BANK1:M_BANK0)+(n)))
#define SETR(s,n,v) (IRAM_W((s), ((PSW & BS) ? M_BANK1:M_BANK0)+(n), (v)))
static void set_irq_line(upi41_state_t *upi41_state, int irqline, int state);
@ -229,8 +233,8 @@ static void set_irq_line(upi41_state_t *upi41_state, int irqline, int state);
INLINE void push_pc_to_stack(upi41_state_t *upi41_state)
{
IRAM_W( M_STACK + (PSW&SP) * 2 + 0, PC & 0xff);
IRAM_W( M_STACK + (PSW&SP) * 2 + 1, ((PC >> 8) & 0x0f) | (PSW & 0xf0) );
IRAM_W( upi41_state, M_STACK + (PSW&SP) * 2 + 0, PC & 0xff);
IRAM_W( upi41_state, M_STACK + (PSW&SP) * 2 + 1, ((PC >> 8) & 0x0f) | (PSW & 0xf0) );
PSW = (PSW & ~SP) | ((PSW + 1) & SP);
}
@ -839,6 +843,9 @@ static CPU_INIT( i8x41 )
upi41_state->irq_callback = irqcallback;
upi41_state->device = device;
upi41_state->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
upi41_state->data = memory_find_address_space(device, ADDRESS_SPACE_DATA);
upi41_state->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
upi41_state->subtype = 8041;
upi41_state->ram_mask = I8X41_intRAM_MASK;
@ -919,7 +926,7 @@ static CPU_EXECUTE( i8x41 )
do
{
UINT8 op = program_decrypted_read_byte(PC);
UINT8 op = memory_decrypted_read_byte(upi41_state->program, PC);
PPC = PC;
@ -935,7 +942,7 @@ static CPU_EXECUTE( i8x41 )
inst_cycles = i8x41_cycles[op];
for ( ; inst_cycles > 0; inst_cycles-- )
{
T1_level = RP(I8X41_t1);
T1_level = RP(upi41_state, I8X41_t1);
if( (CONTROL & TEST1) && (T1_level == 0) ) /* Negative Edge */
{
upi41_state->timer++;
@ -1112,15 +1119,15 @@ static CPU_SET_INFO( i8x41 )
case CPUINFO_INT_REGISTER + I8X41_PSW: PSW = info->i; break;
case CPUINFO_INT_REGISTER + I8X41_A: A = info->i; break;
case CPUINFO_INT_REGISTER + I8X41_T: upi41_state->timer = info->i & 0x1fff; break;
case CPUINFO_INT_REGISTER + I8X41_R0: SETR(0, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R1: SETR(1, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R2: SETR(2, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R3: SETR(3, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R4: SETR(4, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R5: SETR(5, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R6: SETR(6, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R7: SETR(7, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_T: upi41_state->timer = info->i & 0x1fff; break;
case CPUINFO_INT_REGISTER + I8X41_R0: SETR(upi41_state, 0, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R1: SETR(upi41_state, 1, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R2: SETR(upi41_state, 2, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R3: SETR(upi41_state, 3, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R4: SETR(upi41_state, 4, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R5: SETR(upi41_state, 5, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R6: SETR(upi41_state, 6, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_R7: SETR(upi41_state, 7, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_DATA:
DBBI = info->i;
@ -1135,7 +1142,7 @@ static CPU_SET_INFO( i8x41 )
P2_HS |= 0x20;
if( 0 == (STATE & OBF) ) P2_HS |= 0x10;
else P2_HS &= 0xef;
WP(0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
}
break;
@ -1160,7 +1167,7 @@ static CPU_SET_INFO( i8x41 )
P2_HS |= 0x20;
if( 0 == (STATE & OBF) ) P2_HS |= 0x10;
else P2_HS &= 0xef;
WP(0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
}
break;
@ -1231,14 +1238,14 @@ CPU_GET_INFO( i8041 )
case CPUINFO_INT_REGISTER + I8X41_PSW: info->i = PSW; break;
case CPUINFO_INT_REGISTER + I8X41_A: info->i = A; break;
case CPUINFO_INT_REGISTER + I8X41_T: info->i = upi41_state->timer; break;
case CPUINFO_INT_REGISTER + I8X41_R0: info->i = GETR(0); break;
case CPUINFO_INT_REGISTER + I8X41_R1: info->i = GETR(1); break;
case CPUINFO_INT_REGISTER + I8X41_R2: info->i = GETR(2); break;
case CPUINFO_INT_REGISTER + I8X41_R3: info->i = GETR(3); break;
case CPUINFO_INT_REGISTER + I8X41_R4: info->i = GETR(4); break;
case CPUINFO_INT_REGISTER + I8X41_R5: info->i = GETR(5); break;
case CPUINFO_INT_REGISTER + I8X41_R6: info->i = GETR(6); break;
case CPUINFO_INT_REGISTER + I8X41_R7: info->i = GETR(7); break;
case CPUINFO_INT_REGISTER + I8X41_R0: info->i = GETR(upi41_state, 0); break;
case CPUINFO_INT_REGISTER + I8X41_R1: info->i = GETR(upi41_state, 1); break;
case CPUINFO_INT_REGISTER + I8X41_R2: info->i = GETR(upi41_state, 2); break;
case CPUINFO_INT_REGISTER + I8X41_R3: info->i = GETR(upi41_state, 3); break;
case CPUINFO_INT_REGISTER + I8X41_R4: info->i = GETR(upi41_state, 4); break;
case CPUINFO_INT_REGISTER + I8X41_R5: info->i = GETR(upi41_state, 5); break;
case CPUINFO_INT_REGISTER + I8X41_R6: info->i = GETR(upi41_state, 6); break;
case CPUINFO_INT_REGISTER + I8X41_R7: info->i = GETR(upi41_state, 7); break;
case CPUINFO_INT_REGISTER + I8X41_DATA:
STATE &= ~OBF; /* reset the output buffer full flag */
@ -1247,7 +1254,7 @@ CPU_GET_INFO( i8041 )
P2_HS &= 0xef;
if( STATE & IBF ) P2_HS |= 0x20;
else P2_HS &= 0xdf;
WP(0x02, (P2 & P2_HS) ); /* Clear the DBBO IRQ out on P24 */
WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Clear the DBBO IRQ out on P24 */
}
info->i = DBBO;
break;
@ -1299,14 +1306,14 @@ CPU_GET_INFO( i8041 )
case CPUINFO_STR_REGISTER + I8X41_PSW: sprintf(info->s, "PSW:%02X", upi41_state->psw); break;
case CPUINFO_STR_REGISTER + I8X41_A: sprintf(info->s, "A:%02X", upi41_state->a); break;
case CPUINFO_STR_REGISTER + I8X41_T: sprintf(info->s, "T:%02X.%02X", upi41_state->timer, (upi41_state->prescaler & 0x1f) ); break;
case CPUINFO_STR_REGISTER + I8X41_R0: sprintf(info->s, "R0:%02X", GETR(0)); break;
case CPUINFO_STR_REGISTER + I8X41_R1: sprintf(info->s, "R1:%02X", GETR(1)); break;
case CPUINFO_STR_REGISTER + I8X41_R2: sprintf(info->s, "R2:%02X", GETR(2)); break;
case CPUINFO_STR_REGISTER + I8X41_R3: sprintf(info->s, "R3:%02X", GETR(3)); break;
case CPUINFO_STR_REGISTER + I8X41_R4: sprintf(info->s, "R4:%02X", GETR(4)); break;
case CPUINFO_STR_REGISTER + I8X41_R5: sprintf(info->s, "R5:%02X", GETR(5)); break;
case CPUINFO_STR_REGISTER + I8X41_R6: sprintf(info->s, "R6:%02X", GETR(6)); break;
case CPUINFO_STR_REGISTER + I8X41_R7: sprintf(info->s, "R7:%02X", GETR(7)); break;
case CPUINFO_STR_REGISTER + I8X41_R0: sprintf(info->s, "R0:%02X", GETR(upi41_state, 0));break;
case CPUINFO_STR_REGISTER + I8X41_R1: sprintf(info->s, "R1:%02X", GETR(upi41_state, 1));break;
case CPUINFO_STR_REGISTER + I8X41_R2: sprintf(info->s, "R2:%02X", GETR(upi41_state, 2));break;
case CPUINFO_STR_REGISTER + I8X41_R3: sprintf(info->s, "R3:%02X", GETR(upi41_state, 3));break;
case CPUINFO_STR_REGISTER + I8X41_R4: sprintf(info->s, "R4:%02X", GETR(upi41_state, 4));break;
case CPUINFO_STR_REGISTER + I8X41_R5: sprintf(info->s, "R5:%02X", GETR(upi41_state, 5));break;
case CPUINFO_STR_REGISTER + I8X41_R6: sprintf(info->s, "R6:%02X", GETR(upi41_state, 6));break;
case CPUINFO_STR_REGISTER + I8X41_R7: sprintf(info->s, "R7:%02X", GETR(upi41_state, 7));break;
case CPUINFO_STR_REGISTER + I8X41_P1: sprintf(info->s, "P1:%02X", upi41_state->p1); break;
case CPUINFO_STR_REGISTER + I8X41_P2: sprintf(info->s, "P2:%02X", upi41_state->p2); break;
case CPUINFO_STR_REGISTER + I8X41_DATA_DASM: sprintf(info->s, "DBBI:%02X", upi41_state->dbbi); break;

194
src/emu/cpu/i8x41/i8x41ops.c
View File

@ -10,7 +10,7 @@
***********************************/
OP_HANDLER( illegal )
{
logerror("i8x41 #%d: illegal opcode at 0x%03x: %02x\n", cpunum_get_active(), PC, ROP(PC));
logerror("i8x41 #%d: illegal opcode at 0x%03x: %02x\n", cpunum_get_active(), PC, ROP(upi41_state, PC));
}
/***********************************
@ -18,7 +18,7 @@ OP_HANDLER( illegal )
***********************************/
OP_HANDLER( add_r )
{
UINT8 res = A + GETR(r);
UINT8 res = A + GETR(upi41_state, r);
if( res < A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
A = res;
@ -30,7 +30,7 @@ OP_HANDLER( add_r )
***********************************/
OP_HANDLER( add_rm )
{
UINT8 res = A + IRAM_R(GETR(r));
UINT8 res = A + IRAM_R(upi41_state, GETR(upi41_state, r));
if( res < A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
A = res;
@ -42,7 +42,7 @@ OP_HANDLER( add_rm )
***********************************/
OP_HANDLER( add_i )
{
UINT8 res = A + ROP_ARG(PC);
UINT8 res = A + ROP_ARG(upi41_state, PC);
PC++;
if( res < A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
@ -55,7 +55,7 @@ OP_HANDLER( add_i )
***********************************/
OP_HANDLER( addc_r )
{
UINT8 res = A + GETR(r) + (PSW >> 7);
UINT8 res = A + GETR(upi41_state, r) + (PSW >> 7);
if( res <= A ) PSW |= FC;
if( (res & 0x0f) <= (A & 0x0f) ) PSW |= FA;
A = res;
@ -67,7 +67,7 @@ OP_HANDLER( addc_r )
***********************************/
OP_HANDLER( addc_rm )
{
UINT8 res = A + IRAM_R(GETR(r)) + (PSW >> 7);
UINT8 res = A + IRAM_R(upi41_state, GETR(upi41_state, r)) + (PSW >> 7);
if( res <= A ) PSW |= FC;
if( (res & 0x0f) <= (A & 0x0f) ) PSW |= FA;
A = res;
@ -79,7 +79,7 @@ OP_HANDLER( addc_rm )
***********************************/
OP_HANDLER( addc_i )
{
UINT8 res = A + ROP_ARG(PC) + (PSW >> 7);
UINT8 res = A + ROP_ARG(upi41_state, PC) + (PSW >> 7);
PC++;
if( res <= A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
@ -92,7 +92,7 @@ OP_HANDLER( addc_i )
***********************************/
OP_HANDLER( anl_r )
{
A = A & GETR(r);
A = A & GETR(upi41_state, r);
}
/***********************************
@ -101,7 +101,7 @@ OP_HANDLER( anl_r )
***********************************/
OP_HANDLER( anl_rm )
{
A = A & IRAM_R(GETR(r));
A = A & IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@ -110,7 +110,7 @@ OP_HANDLER( anl_rm )
***********************************/
OP_HANDLER( anl_i )
{
A = A & ROP_ARG(PC);
A = A & ROP_ARG(upi41_state, PC);
PC++;
}
@ -121,14 +121,14 @@ OP_HANDLER( anl_i )
OP_HANDLER( anl_p_i )
{
UINT8 p = r;
UINT8 val = ROP_ARG(PC);
UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
/* changed to latched port scheme */
switch (p)
{
case 00: break; /* invalid port */
case 01: P1 &= val; WP(p, P1); break;
case 02: P2 &= val; WP(p, (P2 & P2_HS) ); break;
case 01: P1 &= val; WP(upi41_state, p, P1); break;
case 02: P2 &= val; WP(upi41_state, p, (P2 & P2_HS) ); break;
case 03: break; /* invalid port */
default: break;
}
@ -142,10 +142,10 @@ OP_HANDLER( anld_p_a )
{
UINT8 p = r;
/* added proper expanded port setup */
WP(2, (P2 & 0xf0) | 0x0c | p); /* AND mode */
WP(I8X41_ps, 0); /* activate command strobe */
WP(2, (A & 0x0f)); /* Expander to take care of AND function */
WP(I8X41_ps, 1); /* release command strobe */
WP(upi41_state, 2, (P2 & 0xf0) | 0x0c | p); /* AND mode */
WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
WP(upi41_state, 2, (A & 0x0f)); /* Expander to take care of AND function */
WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@ -155,7 +155,7 @@ OP_HANDLER( anld_p_a )
OP_HANDLER( call_i )
{
UINT16 page = (r & 0xe0) << 3;
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC++;
PUSH_PC_TO_STACK();
PC = page | adr;
@ -266,7 +266,7 @@ OP_HANDLER( dec_a )
***********************************/
OP_HANDLER( dec_r )
{
SETR(r, GETR(r) - 1);
SETR(upi41_state, r, GETR(upi41_state, r) - 1);
}
/***********************************
@ -293,10 +293,10 @@ OP_HANDLER( dis_tcnti )
***********************************/
OP_HANDLER( djnz_r_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC++;
SETR(r, GETR(r) - 1);
if( GETR(r) )
SETR(upi41_state, r, GETR(upi41_state, r) - 1);
if( GETR(upi41_state, r) )
PC = (PC & 0x700) | adr;
}
@ -308,7 +308,7 @@ OP_HANDLER( en_dma )
{
ENABLE |= DMA; /* enable DMA handshake lines */
P2_HS &= 0xbf;
WP(0x02, (P2 & P2_HS) );
WP(upi41_state, 0x02, (P2 & P2_HS) );
}
/***********************************
@ -326,7 +326,7 @@ OP_HANDLER( en_flags )
else P2_HS &= 0xef;
if( STATE & IBF ) P2_HS |= 0x20;
else P2_HS &= 0xdf;
WP(0x02, (P2 & P2_HS) );
WP(upi41_state, 0x02, (P2 & P2_HS) );
}
}
@ -370,7 +370,7 @@ OP_HANDLER( in_a_dbb )
P2_HS &= 0xdf;
if( STATE & OBF ) P2_HS |= 0x10;
else P2_HS &= 0xef;
WP(0x02, (P2 & P2_HS) ); /* Clear the DBBI IRQ out on P25 */
WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Clear the DBBI IRQ out on P25 */
}
A = DBBI;
}
@ -386,8 +386,8 @@ OP_HANDLER( in_a_p )
switch( p )
{
case 00: break; /* invalid port */
case 01: A = (RP(p) & P1); break;
case 02: A = (RP(p) & P2); break;
case 01: A = (RP(upi41_state, p) & P1); break;
case 02: A = (RP(upi41_state, p) & P2); break;
case 03: break; /* invalid port */
default: break;
}
@ -408,7 +408,7 @@ OP_HANDLER( inc_a )
***********************************/
OP_HANDLER( inc_r )
{
SETR(r, GETR(r) + 1);
SETR(upi41_state, r, GETR(upi41_state, r) + 1);
}
/***********************************
@ -417,8 +417,8 @@ OP_HANDLER( inc_r )
***********************************/
OP_HANDLER( inc_rm )
{
UINT16 addr = GETR(r);
IRAM_W( addr, IRAM_R(addr) + 1 );
UINT16 addr = GETR(upi41_state, r);
IRAM_W(upi41_state, addr, IRAM_R(upi41_state, addr) + 1 );
}
/***********************************
@ -428,7 +428,7 @@ OP_HANDLER( inc_rm )
OP_HANDLER( jbb_i )
{
UINT8 bit = r;
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( A & (1 << bit) )
PC = (PC & 0x700) | adr;
@ -440,7 +440,7 @@ OP_HANDLER( jbb_i )
***********************************/
OP_HANDLER( jc_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( PSW & FC )
PC = (PC & 0x700) | adr;
@ -452,7 +452,7 @@ OP_HANDLER( jc_i )
***********************************/
OP_HANDLER( jf0_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( STATE & F0 )
PC = (PC & 0x700) | adr;
@ -464,7 +464,7 @@ OP_HANDLER( jf0_i )
***********************************/
OP_HANDLER( jf1_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( STATE & F1 )
PC = (PC & 0x700) | adr;
@ -481,7 +481,7 @@ OP_HANDLER( jmp_i )
* JMP is said to use aaa0 (8 pages)
*/
UINT16 page = ((r & 0xe0) << 3);
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC = page | adr;
}
@ -492,7 +492,7 @@ OP_HANDLER( jmp_i )
OP_HANDLER( jmpp_a )
{
UINT16 adr = (PC & 0x700) | A;
PC = (PC & 0x700) | RM(adr);
PC = (PC & 0x700) | RM(upi41_state, adr);
}
/***********************************
@ -501,7 +501,7 @@ OP_HANDLER( jmpp_a )
***********************************/
OP_HANDLER( jnc_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !(PSW & FC) )
PC = (PC & 0x700) | adr;
@ -513,7 +513,7 @@ OP_HANDLER( jnc_i )
***********************************/
OP_HANDLER( jnibf_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( 0 == (STATE & IBF) )
PC = (PC & 0x700) | adr;
@ -525,9 +525,9 @@ OP_HANDLER( jnibf_i )
***********************************/
OP_HANDLER( jnt0_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( 0 == RP(I8X41_t0) )
if( 0 == RP(upi41_state, I8X41_t0) )
PC = (PC & 0x700) | adr;
}
@ -537,11 +537,11 @@ OP_HANDLER( jnt0_i )
***********************************/
OP_HANDLER( jnt1_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !(ENABLE & CNT) )
{
UINT8 level = RP(I8X41_t1);
UINT8 level = RP(upi41_state, I8X41_t1);
if( level ) CONTROL |= TEST1;
else CONTROL &= ~TEST1;
}
@ -555,7 +555,7 @@ OP_HANDLER( jnt1_i )
***********************************/
OP_HANDLER( jnz_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( A )
PC = (PC & 0x700) | adr;
@ -567,7 +567,7 @@ OP_HANDLER( jnz_i )
***********************************/
OP_HANDLER( jobf_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( STATE & OBF )
PC = (PC & 0x700) | adr;
@ -579,7 +579,7 @@ OP_HANDLER( jobf_i )
***********************************/
OP_HANDLER( jtf_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( CONTROL & TOVF )
PC = (PC & 0x700) | adr;
@ -592,9 +592,9 @@ OP_HANDLER( jtf_i )
***********************************/
OP_HANDLER( jt0_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( RP(I8X41_t0) )
if( RP(upi41_state, I8X41_t0) )
PC = (PC & 0x700) | adr;
}
@ -604,11 +604,11 @@ OP_HANDLER( jt0_i )
***********************************/
OP_HANDLER( jt1_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !(ENABLE & CNT) )
{
UINT8 level = RP(I8X41_t1);
UINT8 level = RP(upi41_state, I8X41_t1);
if( level ) CONTROL |= TEST1;
else CONTROL &= ~TEST1;
}
@ -622,7 +622,7 @@ OP_HANDLER( jt1_i )
***********************************/
OP_HANDLER( jz_i )
{
UINT8 adr = ROP_ARG(PC);
UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !A )
PC = (PC & 0x700) | adr;
@ -634,7 +634,7 @@ OP_HANDLER( jz_i )
***********************************/
OP_HANDLER( mov_a_i )
{
A = ROP(PC);
A = ROP(upi41_state, PC);
PC += 1;
}
@ -653,7 +653,7 @@ OP_HANDLER( mov_a_psw )
***********************************/
OP_HANDLER( mov_a_r )
{
A = GETR(r);
A = GETR(upi41_state, r);
}
/***********************************
@ -662,7 +662,7 @@ OP_HANDLER( mov_a_r )
***********************************/
OP_HANDLER( mov_a_rm )
{
A = IRAM_R(GETR(r));
A = IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@ -689,7 +689,7 @@ OP_HANDLER( mov_psw_a )
***********************************/
OP_HANDLER( mov_r_a )
{
SETR(r, A);
SETR(upi41_state, r, A);
}
/***********************************
@ -698,9 +698,9 @@ OP_HANDLER( mov_r_a )
***********************************/
OP_HANDLER( mov_r_i )
{
UINT8 val = ROP_ARG(PC);
UINT8 val = ROP_ARG(upi41_state, PC);
PC += 1;
SETR(r, val);
SETR(upi41_state, r, val);
}
/***********************************
@ -709,7 +709,7 @@ OP_HANDLER( mov_r_i )
***********************************/
OP_HANDLER( mov_rm_a )
{
IRAM_W(GETR(r), A );
IRAM_W(upi41_state, GETR(upi41_state, r), A );
}
/***********************************
@ -718,9 +718,9 @@ OP_HANDLER( mov_rm_a )
***********************************/
OP_HANDLER( mov_rm_i )
{
UINT8 val = ROP_ARG(PC);
UINT8 val = ROP_ARG(upi41_state, PC);
PC += 1;
IRAM_W(GETR(r), val );
IRAM_W(upi41_state, GETR(upi41_state, r), val );
}
/***********************************
@ -749,10 +749,10 @@ OP_HANDLER( movd_a_p )
{
UINT8 p = r;
/* added proper expanded port setup */
WP(2, (P2 & 0xf0) | 0x00 | p); /* READ mode */
WP(I8X41_ps, 0); /* activate command strobe */
A = RP(2) & 0xf;
WP(I8X41_ps, 1); /* release command strobe */
WP(upi41_state, 2, (P2 & 0xf0) | 0x00 | p); /* READ mode */
WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
A = RP(upi41_state, 2) & 0xf;
WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@ -763,10 +763,10 @@ OP_HANDLER( movd_p_a )
{
UINT8 p = r;
/* added proper expanded port setup */
WP(2, (P2 & 0xf0) | 0x04 | p); /* WRITE mode */
WP(I8X41_ps, 0); /* activate command strobe */
WP(2, A & 0x0f);
WP(I8X41_ps, 1); /* release command strobe */
WP(upi41_state, 2, (P2 & 0xf0) | 0x04 | p); /* WRITE mode */
WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
WP(upi41_state, 2, A & 0x0f);
WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@ -776,7 +776,7 @@ OP_HANDLER( movd_p_a )
OP_HANDLER( movp_a_am )
{
UINT16 addr = (PC & 0x700) | A;
A = RM(addr);
A = RM(upi41_state, addr);
}
/***********************************
@ -786,7 +786,7 @@ OP_HANDLER( movp_a_am )
OP_HANDLER( movp3_a_am )
{
UINT16 addr = 0x300 | A;
A = RM(addr);
A = RM(upi41_state, addr);
}
/***********************************
@ -803,7 +803,7 @@ OP_HANDLER( nop )
***********************************/
OP_HANDLER( orl_r )
{
A = A | GETR(r);
A = A | GETR(upi41_state, r);
}
/***********************************
@ -812,7 +812,7 @@ OP_HANDLER( orl_r )
***********************************/
OP_HANDLER( orl_rm )
{
A = A | IRAM_R(GETR(r));
A = A | IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@ -821,7 +821,7 @@ OP_HANDLER( orl_rm )
***********************************/
OP_HANDLER( orl_i )
{
UINT8 val = ROP_ARG(PC);
UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
A = A | val;
}
@ -833,14 +833,14 @@ OP_HANDLER( orl_i )
OP_HANDLER( orl_p_i )
{
UINT8 p = r;
UINT8 val = ROP_ARG(PC);
UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
/* changed to latched port scheme */
switch (p)
{
case 00: break; /* invalid port */
case 01: P1 |= val; WP(p, P1); break;
case 02: P2 |= val; WP(p, P2); break;
case 01: P1 |= val; WP(upi41_state, p, P1); break;
case 02: P2 |= val; WP(upi41_state, p, P2); break;
case 03: break; /* invalid port */
default: break;
}
@ -854,10 +854,10 @@ OP_HANDLER( orld_p_a )
{
UINT8 p = r;
/* added proper expanded port setup */
WP(2, (P2 & 0xf0) | 0x08 | p); /* OR mode */
WP(I8X41_ps, 0); /* activate command strobe */
WP(2, A & 0x0f); /* Expander to take care of OR function */
WP(I8X41_ps, 1); /* release command strobe */
WP(upi41_state, 2, (P2 & 0xf0) | 0x08 | p); /* OR mode */
WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
WP(upi41_state, 2, A & 0x0f); /* Expander to take care of OR function */
WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@ -873,7 +873,7 @@ OP_HANDLER( out_dbb_a )
P2_HS |= 0x10;
if( STATE & IBF ) P2_HS |= 0x20;
else P2_HS &= 0xdf;
WP(0x02, (P2 & P2_HS) ); /* Assert the DBBO IRQ out on P24 */
WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Assert the DBBO IRQ out on P24 */
}
}
@ -888,8 +888,8 @@ OP_HANDLER( out_p_a )
switch (p)
{
case 00: break; /* invalid port */
case 01: WP(p, A); P1 = A; break;
case 02: WP(p, A); P2 = A; break;
case 01: WP(upi41_state, p, A); P1 = A; break;
case 02: WP(upi41_state, p, A); P2 = A; break;
case 03: break; /* invalid port */
default: break;
}
@ -903,8 +903,8 @@ OP_HANDLER( ret )
{
UINT8 msb;
PSW = (PSW & ~SP) | ((PSW - 1) & SP);
msb = IRAM_R(M_STACK + (PSW&SP) * 2 + 1);
PC = IRAM_R(M_STACK + (PSW&SP) * 2 + 0);
msb = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 1);
PC = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 0);
PC |= (msb << 8) & 0x700;
}
@ -916,8 +916,8 @@ OP_HANDLER( retr )
{
UINT8 msb;
PSW = (PSW & ~SP) | ((PSW - 1) & SP);
msb = IRAM_R(M_STACK + (PSW&SP) * 2 + 1);
PC = IRAM_R(M_STACK + (PSW&SP) * 2 + 0);
msb = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 1);
PC = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 0);
PC |= (msb << 8) & 0x700;
PSW = (PSW & 0x0f) | (msb & 0xf0);
CONTROL &= ~IRQ_IGNR;
@ -1025,8 +1025,8 @@ OP_HANDLER( swap_a )
***********************************/
OP_HANDLER( xch_a_r )
{
UINT8 tmp = GETR(r);
SETR(r, A);
UINT8 tmp = GETR(upi41_state, r);
SETR(upi41_state, r, A);
A = tmp;
}
@ -1036,9 +1036,9 @@ OP_HANDLER( xch_a_r )
***********************************/
OP_HANDLER( xch_a_rm )
{
UINT16 addr = GETR(r);
UINT8 tmp = IRAM_R(addr);
IRAM_W( addr, A );
UINT16 addr = GETR(upi41_state, r);
UINT8 tmp = IRAM_R(upi41_state, addr);
IRAM_W(upi41_state, addr, A );
A = tmp;
}
@ -1048,9 +1048,9 @@ OP_HANDLER( xch_a_rm )
***********************************/
OP_HANDLER( xchd_a_rm )
{
UINT16 addr = GETR(r);
UINT8 tmp = IRAM_R(addr);
IRAM_W( addr, (tmp & 0xf0) | (A & 0x0f) );
UINT16 addr = GETR(upi41_state, r);
UINT8 tmp = IRAM_R(upi41_state, addr);
IRAM_W(upi41_state, addr, (tmp & 0xf0) | (A & 0x0f) );
A = (A & 0xf0) | (tmp & 0x0f);
}
@ -1060,7 +1060,7 @@ OP_HANDLER( xchd_a_rm )
***********************************/
OP_HANDLER( xrl_r )
{
A = A ^ GETR(r);
A = A ^ GETR(upi41_state, r);
}
/***********************************
@ -1069,7 +1069,7 @@ OP_HANDLER( xrl_r )
***********************************/
OP_HANDLER( xrl_rm )
{
A = A ^ IRAM_R(GETR(r));
A = A ^ IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@ -1078,7 +1078,7 @@ OP_HANDLER( xrl_rm )
***********************************/
OP_HANDLER( xrl_i )
{
UINT8 val = ROP_ARG(PC);
UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
A = A ^ val;
}

1793
src/emu/cpu/i960/i960.c
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