From 9ef51b6bcd251f2adedcace54024ecffe5a0ed09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Oliver=20St=C3=B6neberg?= Date: Fri, 7 Sep 2012 19:46:27 +0000 Subject: [PATCH] added missing \n to some fatalerror() calls (no whatsnew) --- src/emu/cpu/am29000/am29000.c | 4 +- src/emu/cpu/arm7/arm7.c | 8 +- src/emu/cpu/arm7/arm7core.c | 8 +- src/emu/cpu/cosmac/cosmac.c | 2 +- src/emu/cpu/drcbec.c | 6 +- src/emu/cpu/drcbeut.c | 2 +- src/emu/cpu/drcbex64.c | 6 +- src/emu/cpu/drcbex86.c | 6 +- src/emu/cpu/drcuml.c | 8 +- src/emu/cpu/dsp32/dsp32ops.c | 8 +- src/emu/cpu/dsp56k/dsp56ops.c | 10 +- src/emu/cpu/e132xs/e132xs.c | 2 +- src/emu/cpu/h83002/h8_16.c | 4 +- src/emu/cpu/h83002/h8_8.c | 2 +- src/emu/cpu/h83002/h8ops.h | 2 +- src/emu/cpu/i386/i386.c | 4 +- src/emu/cpu/i386/i386op16.c | 14 +-- src/emu/cpu/i386/i386op32.c | 14 +-- src/emu/cpu/i386/i386ops.c | 8 +- src/emu/cpu/i386/i486ops.c | 4 +- src/emu/cpu/i386/pentops.c | 6 +- src/emu/cpu/i386/x87ops.c | 2 +- src/emu/cpu/i960/i960.c | 66 ++++++------ src/emu/cpu/jaguar/jaguar.c | 4 +- src/emu/cpu/mc68hc11/hc11ops.c | 2 +- src/emu/cpu/mcs48/mcs48.c | 8 +- src/emu/cpu/mips/mips3.c | 2 +- src/emu/cpu/mips/mips3com.c | 2 +- src/emu/cpu/mips/mips3drc.c | 6 +- src/emu/cpu/pic16c5x/16c5xdsm.c | 8 +- src/emu/cpu/pic16c62x/16c62xdsm.c | 8 +- src/emu/cpu/powerpc/drc_ops.c | 2 +- src/emu/cpu/powerpc/ppc.c | 12 +-- src/emu/cpu/powerpc/ppc403.c | 34 +++---- src/emu/cpu/powerpc/ppc602.c | 2 +- src/emu/cpu/powerpc/ppc603.c | 2 +- src/emu/cpu/powerpc/ppc_mem.c | 2 +- src/emu/cpu/powerpc/ppc_ops.c | 6 +- src/emu/cpu/powerpc/ppccom.c | 10 +- src/emu/cpu/powerpc/ppcdrc.c | 4 +- src/emu/cpu/rsp/rspdrc.c | 8 +- src/emu/cpu/sh2/sh2comn.c | 2 +- src/emu/cpu/sh2/sh2drc.c | 4 +- src/emu/cpu/sharc/compute.c | 20 ++-- src/emu/cpu/sharc/sharc.c | 14 +-- src/emu/cpu/sharc/sharcdma.c | 8 +- src/emu/cpu/sharc/sharcmem.c | 8 +- src/emu/cpu/sharc/sharcops.c | 64 ++++++------ src/emu/cpu/tms32010/32010dsm.c | 8 +- src/emu/cpu/tms32025/32025dsm.c | 8 +- src/emu/cpu/tms32031/32031ops.c | 4 +- src/emu/cpu/tms32051/32051ops.c | 160 +++++++++++++++--------------- src/emu/cpu/tms34010/tms34010.c | 2 +- src/emu/cpu/tms57002/tms57002.c | 2 +- src/emu/cpu/uml.c | 2 +- src/emu/cpu/upd7810/upd7810.c | 2 +- src/emu/cpu/v60/am1.c | 26 ++--- src/emu/cpu/v60/am2.c | 24 ++--- src/emu/cpu/v60/am3.c | 14 +-- src/emu/cpu/v60/op12.c | 6 +- src/emu/cpu/v60/op2.c | 4 +- src/emu/cpu/v60/op5.c | 2 +- src/emu/cpu/v60/op7a.c | 10 +- src/emu/cpu/v60/v60.c | 2 +- src/emu/cpu/v810/v810.c | 2 +- src/emu/cpu/z80/z80daisy.c | 4 +- src/osd/sdl/draw13.c | 2 +- 67 files changed, 361 insertions(+), 361 deletions(-) diff --git a/src/emu/cpu/am29000/am29000.c b/src/emu/cpu/am29000/am29000.c index 70a0b5d4dbc..4c117d9500a 100644 --- a/src/emu/cpu/am29000/am29000.c +++ b/src/emu/cpu/am29000/am29000.c @@ -274,7 +274,7 @@ static UINT32 read_program_word(am29000_state *state, UINT32 address) return state->direct->read_decrypted_dword(address); else { - fatalerror("Am29000 instruction MMU translation enabled!"); + fatalerror("Am29000 instruction MMU translation enabled!\n"); } return 0; } @@ -425,7 +425,7 @@ static CPU_EXECUTE( am29000 ) } else { - fatalerror("Am29000: Non vectored interrupt fetch!"); + fatalerror("Am29000: Non vectored interrupt fetch!\n"); } am29000->exceptions = 0; diff --git a/src/emu/cpu/arm7/arm7.c b/src/emu/cpu/arm7/arm7.c index cee5a5b715b..a56cc24cb55 100644 --- a/src/emu/cpu/arm7/arm7.c +++ b/src/emu/cpu/arm7/arm7.c @@ -288,7 +288,7 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags) } else { - fatalerror("ARM7: Not Yet Implemented: Coarse Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x", vaddr, domain, R15); + fatalerror("ARM7: Not Yet Implemented: Coarse Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x\n", vaddr, domain, R15); } break; case COPRO_TLB_SECTION_TABLE: @@ -323,7 +323,7 @@ int arm7_tlb_translate(arm_state *cpustate, UINT32 *addr, int flags) break; case COPRO_TLB_FINE_TABLE: // Entry is the physical address of a fine second-level table - fatalerror("ARM7: Not Yet Implemented: fine second-level TLB lookup, PC = %08x, vaddr = %08x", R15, vaddr); + fatalerror("ARM7: Not Yet Implemented: fine second-level TLB lookup, PC = %08x, vaddr = %08x\n", R15, vaddr); break; default: // Entry is the physical address of a three-legged termite-eaten table @@ -577,7 +577,7 @@ static CPU_EXECUTE( arm7 ) UINT32 temp1, temp2; temp1 = GET_CPSR & 0xF00000C3; temp2 = (R15 & 0xF0000000) | ((R15 & 0x0C000000) >> (26 - 6)) | (R15 & 0x00000003); - if (temp1 != temp2) fatalerror( "%08X: 32-bit and 26-bit modes are out of sync (%08X %08X)", pc, temp1, temp2); + if (temp1 != temp2) fatalerror( "%08X: 32-bit and 26-bit modes are out of sync (%08X %08X)\n", pc, temp1, temp2); } #endif @@ -1250,7 +1250,7 @@ static WRITE32_DEVICE_HANDLER( arm7_rt_w_callback ) { if (!arm7_tlb_translate( cpustate, &R15, 0)) { - fatalerror("ARM7_MMU_ENABLE_HACK translate failed"); + fatalerror("ARM7_MMU_ENABLE_HACK translate failed\n"); } } #endif diff --git a/src/emu/cpu/arm7/arm7core.c b/src/emu/cpu/arm7/arm7core.c index 7bb484cda03..b15fb7217a7 100644 --- a/src/emu/cpu/arm7/arm7core.c +++ b/src/emu/cpu/arm7/arm7core.c @@ -170,7 +170,7 @@ void arm7_check_irq_state(arm_state *cpustate) // Data Abort if (cpustate->pendingAbtD) { - if (MODE26) fatalerror( "pendingAbtD (todo)"); + if (MODE26) fatalerror( "pendingAbtD (todo)\n"); SwitchMode(cpustate, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */ SET_REGISTER(cpustate, 14, pc - 8 + 8); /* save PC to R14 */ SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */ @@ -184,7 +184,7 @@ void arm7_check_irq_state(arm_state *cpustate) // FIQ if (cpustate->pendingFiq && (cpsr & F_MASK) == 0) { - if (MODE26) fatalerror( "pendingFiq (todo)"); + if (MODE26) fatalerror( "pendingFiq (todo)\n"); SwitchMode(cpustate, eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */ SET_REGISTER(cpustate, 14, pc - 4 + 4); /* save PC to R14 */ SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */ @@ -219,7 +219,7 @@ void arm7_check_irq_state(arm_state *cpustate) // Prefetch Abort if (cpustate->pendingAbtP) { - if (MODE26) fatalerror( "pendingAbtP (todo)"); + if (MODE26) fatalerror( "pendingAbtP (todo)\n"); SwitchMode(cpustate, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */ SET_REGISTER(cpustate, 14, pc - 4 + 4); /* save PC to R14 */ SET_REGISTER(cpustate, SPSR, cpsr); /* Save current CPSR */ @@ -233,7 +233,7 @@ void arm7_check_irq_state(arm_state *cpustate) // Undefined instruction if (cpustate->pendingUnd) { - if (MODE26) fatalerror( "pendingUnd (todo)"); + if (MODE26) fatalerror( "pendingUnd (todo)\n"); SwitchMode(cpustate, eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */ // compensate for prefetch (should this also be done for normal IRQ?) if (T_IS_SET(GET_CPSR)) diff --git a/src/emu/cpu/cosmac/cosmac.c b/src/emu/cpu/cosmac/cosmac.c index 89bc3423ce3..5149be749c9 100644 --- a/src/emu/cpu/cosmac/cosmac.c +++ b/src/emu/cpu/cosmac/cosmac.c @@ -219,7 +219,7 @@ void cosmac_device::device_config_complete() // or error out if none provided else { - fatalerror("COSMAC_INTERFACE for cpu '%s' not defined!", tag()); + fatalerror("COSMAC_INTERFACE for cpu '%s' not defined!\n", tag()); } } diff --git a/src/emu/cpu/drcbec.c b/src/emu/cpu/drcbec.c index 37bd406104d..906ed3c5781 100644 --- a/src/emu/cpu/drcbec.c +++ b/src/emu/cpu/drcbec.c @@ -548,7 +548,7 @@ int drcbe_c::execute(code_handle &entry) case MAKE_OPCODE_SHORT(OP_MAPVAR, 4, 0): // MAPVAR mapvar,value // these opcodes should be processed at compile-time only - fatalerror("Unexpected opcode"); + fatalerror("Unexpected opcode\n"); break; case MAKE_OPCODE_SHORT(OP_DEBUG, 4, 0): // DEBUG pc @@ -2102,7 +2102,7 @@ int drcbe_c::execute(code_handle &entry) break; default: - fatalerror("Unexpected opcode!"); + fatalerror("Unexpected opcode!\n"); break; } @@ -2193,7 +2193,7 @@ void drcbe_c::output_parameter(drcbec_instruction **dstptr, void **immedptr, int break; default: - fatalerror("Unexpected param->type"); + fatalerror("Unexpected param->type\n"); break; } diff --git a/src/emu/cpu/drcbeut.c b/src/emu/cpu/drcbeut.c index 30f2861b78f..9d656fc77a1 100644 --- a/src/emu/cpu/drcbeut.c +++ b/src/emu/cpu/drcbeut.c @@ -561,7 +561,7 @@ void drc_label_list::reset(bool fatal_on_leftovers) { // fatal if we were a leftover if (fatal_on_leftovers && curlabel->m_codeptr == NULL) - fatalerror("Label %08X never defined!", curlabel->m_label.label()); + fatalerror("Label %08X never defined!\n", curlabel->m_label.label()); // free the label m_cache.dealloc(curlabel, sizeof(*curlabel)); diff --git a/src/emu/cpu/drcbex64.c b/src/emu/cpu/drcbex64.c index 88f8c8ffc8d..1ec54a30d4c 100644 --- a/src/emu/cpu/drcbex64.c +++ b/src/emu/cpu/drcbex64.c @@ -470,7 +470,7 @@ drcbe_x64::be_parameter::be_parameter(drcbe_x64 &drcbe, const parameter ¶m, // everything else is unexpected default: - fatalerror("Unexpected parameter type"); + fatalerror("Unexpected parameter type\n"); break; } } @@ -709,7 +709,7 @@ void drcbe_x64::reset() // generate a little bit of glue code to set up the environment drccodeptr *cachetop = m_cache.begin_codegen(500); if (cachetop == NULL) - fatalerror("Out of cache space after a reset!"); + fatalerror("Out of cache space after a reset!\n"); x86code *dst = (x86code *)*cachetop; @@ -2595,7 +2595,7 @@ void drcbe_x64::fixup_label(void *parameter, drccodeptr labelcodeptr) ((UINT32 *)src)[-1] = labelcodeptr - src; } else - fatalerror("fixup_label called with invalid jmp source!"); + fatalerror("fixup_label called with invalid jmp source!\n"); } diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c index 7d0687c7a86..b8961d02315 100644 --- a/src/emu/cpu/drcbex86.c +++ b/src/emu/cpu/drcbex86.c @@ -350,7 +350,7 @@ drcbe_x86::be_parameter::be_parameter(drcbe_x86 &drcbe, const parameter ¶m, // everything else is unexpected default: - fatalerror("Unexpected parameter type"); + fatalerror("Unexpected parameter type\n"); break; } } @@ -625,7 +625,7 @@ void drcbe_x86::reset() // generate a little bit of glue code to set up the environment drccodeptr *cachetop = m_cache.begin_codegen(500); if (cachetop == NULL) - fatalerror("Out of cache space after a reset!"); + fatalerror("Out of cache space after a reset!\n"); x86code *dst = (x86code *)*cachetop; @@ -2834,7 +2834,7 @@ void drcbe_x86::fixup_label(void *parameter, drccodeptr labelcodeptr) ((UINT32 *)src)[-1] = labelcodeptr - src; } else - fatalerror("fixup_label called with invalid jmp source!"); + fatalerror("fixup_label called with invalid jmp source!\n"); } diff --git a/src/emu/cpu/drcuml.c b/src/emu/cpu/drcuml.c index b19ff71f555..4e671565815 100644 --- a/src/emu/cpu/drcuml.c +++ b/src/emu/cpu/drcuml.c @@ -211,7 +211,7 @@ void drcuml_state::reset() } catch (drcuml_block::abort_compilation &) { - fatalerror("Out of cache space in drcuml_state::reset"); + fatalerror("Out of cache space in drcuml_state::reset\n"); } } @@ -401,7 +401,7 @@ uml::instruction &drcuml_block::append() // get a pointer to the next instruction instruction &curinst = m_inst[m_nextinst++]; if (m_nextinst > m_maxinst) - fatalerror("Overran maxinst in drcuml_block_append"); + fatalerror("Overran maxinst in drcuml_block_append\n"); return curinst; } @@ -771,7 +771,7 @@ static void validate_backend(drcuml_state *drcuml) bevalidate_iterate_over_params(drcuml, handles, test, param, 0); printf("\n"); } - fatalerror("All tests passed!"); + fatalerror("All tests passed!\n"); } @@ -1161,7 +1161,7 @@ static int bevalidate_verify_state(drcuml_state *drcuml, const drcuml_machine_st printf("\n"); printf("Errors:\n"); printf("%s\n", errorbuf); - fatalerror("Error during validation"); + fatalerror("Error during validation\n"); } return errend != errorbuf; } diff --git a/src/emu/cpu/dsp32/dsp32ops.c b/src/emu/cpu/dsp32/dsp32ops.c index a4733c883c4..644a1473904 100644 --- a/src/emu/cpu/dsp32/dsp32ops.c +++ b/src/emu/cpu/dsp32/dsp32ops.c @@ -145,7 +145,7 @@ void dsp32c_device::illegal(UINT32 op) void dsp32c_device::unimplemented(UINT32 op) { - fatalerror("Unimplemented op @ %06X: %08X (dis=%02X, tbl=%03X)", PC - 4, op, op >> 25, op >> 21); + fatalerror("Unimplemented op @ %06X: %08X (dis=%02X, tbl=%03X)\n", PC - 4, op, op >> 25, op >> 21); } @@ -449,14 +449,14 @@ inline UINT32 dsp32c_device::double_to_dsp(double val) double dsp32c_device::dau_read_pi_special(int i) { - fatalerror("Unimplemented dau_read_pi_special(%d)", i); + fatalerror("Unimplemented dau_read_pi_special(%d)\n", i); return 0; } void dsp32c_device::dau_write_pi_special(int i, double val) { - fatalerror("Unimplemented dau_write_pi_special(%d)", i); + fatalerror("Unimplemented dau_write_pi_special(%d)\n", i); } @@ -696,7 +696,7 @@ int dsp32c_device::condition(int cond) case 46: // !ireq2 case 47: // ireq2 default: - fatalerror("Unimplemented condition: %X", cond); + fatalerror("Unimplemented condition: %X\n", cond); } } #endif diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c index a57966ec3b2..56b7460a684 100644 --- a/src/emu/cpu/dsp56k/dsp56ops.c +++ b/src/emu/cpu/dsp56k/dsp56ops.c @@ -2192,7 +2192,7 @@ static size_t dsp56k_op_andi(dsp56k_core* cpustate, const UINT16 op, UINT8* cycl break; default: - fatalerror("DSP56k - BAD EE value in andi operation") ; + fatalerror("DSP56k - BAD EE value in andi operation\n") ; } /* S L E U N Z V C */ @@ -4467,7 +4467,7 @@ static void execute_mm_table(dsp56k_core* cpustate, UINT16 rnum, UINT16 mm) case 0x0: rX = &R0; nX = &N0; break; case 0x1: rX = &R1; nX = &N1; break; case 0x2: rX = &R2; nX = &N2; break; - case 0x3: fatalerror("Dsp56k: Error. execute_mm_table specified R3 as its first source!"); break; + case 0x3: fatalerror("Dsp56k: Error. execute_mm_table specified R3 as its first source!\n"); break; } switch(mm) @@ -4522,7 +4522,7 @@ static UINT16 execute_q_table(dsp56k_core* cpustate, int RR, UINT16 q) } /* Should not get here */ - fatalerror("dsp56k: execute_q_table did something impossible!"); + fatalerror("dsp56k: execute_q_table did something impossible!\n"); return 0; } @@ -4785,12 +4785,12 @@ static void execute_dual_x_memory_data_read(dsp56k_core* cpustate, const UINT16 /* Can't do an R3 for S1 */ if (R.addr == &R3) - fatalerror("Dsp56k: Error. Dual x memory data read specified R3 as its first source!"); + fatalerror("Dsp56k: Error. Dual x memory data read specified R3 as its first source!\n"); /* The note on A-142 is very interesting. You can effectively access external memory in the last 64 bytes of X data memory! */ if (*((UINT16*)D2.addr) >= 0xffc0) - fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read."); + fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.\n"); /* First memmove */ srcVal1 = cpustate->data->read_word(ADDRESS(*((UINT16*)R.addr))); diff --git a/src/emu/cpu/e132xs/e132xs.c b/src/emu/cpu/e132xs/e132xs.c index 46907b40a9e..0537e98156f 100644 --- a/src/emu/cpu/e132xs/e132xs.c +++ b/src/emu/cpu/e132xs/e132xs.c @@ -4194,7 +4194,7 @@ INLINE void hyperstone_extend(hyperstone_state *cpustate, struct regs_decode *de INLINE void hyperstone_do(hyperstone_state *cpustate, struct regs_decode *decode) { - fatalerror("Executed hyperstone_do instruction. PC = %08X", PPC); + fatalerror("Executed hyperstone_do instruction. PC = %08X\n", PPC); } INLINE void hyperstone_ldwr(hyperstone_state *cpustate, struct regs_decode *decode) diff --git a/src/emu/cpu/h83002/h8_16.c b/src/emu/cpu/h83002/h8_16.c index 36889e312cf..2fcce22ce83 100644 --- a/src/emu/cpu/h83002/h8_16.c +++ b/src/emu/cpu/h83002/h8_16.c @@ -492,7 +492,7 @@ static CPU_SET_INFO( h8 ) case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_3002_InterruptRequest(h8, 57, info->i); break; default: - fatalerror("h8_set_info unknown request %x", state); + fatalerror("h8_set_info unknown request %x\n", state); break; } } @@ -529,7 +529,7 @@ static CPU_SET_INFO( h8s_2394 ) case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_3002_InterruptRequest(h8, 85, info->i); break; default: - fatalerror("h8_set_info unknown request %x", state); + fatalerror("h8_set_info unknown request %x\n", state); break; } } diff --git a/src/emu/cpu/h83002/h8_8.c b/src/emu/cpu/h83002/h8_8.c index d442454a01e..73f3273d5c7 100644 --- a/src/emu/cpu/h83002/h8_8.c +++ b/src/emu/cpu/h83002/h8_8.c @@ -504,7 +504,7 @@ static CPU_SET_INFO( h8 ) case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX: h8_300_InterruptRequest(h8, 32, info->i); break; default: - fatalerror("h8_set_info unknown request %x", state); + fatalerror("h8_set_info unknown request %x\n", state); break; } } diff --git a/src/emu/cpu/h83002/h8ops.h b/src/emu/cpu/h83002/h8ops.h index 707d6abdb93..f6592587011 100644 --- a/src/emu/cpu/h83002/h8ops.h +++ b/src/emu/cpu/h83002/h8ops.h @@ -247,7 +247,7 @@ static CPU_EXECUTE(h8) if (h8->h8err) { - fatalerror("H8/3xx: Unknown opcode (PC=%x) %x", h8->ppc, opcode); + fatalerror("H8/3xx: Unknown opcode (PC=%x) %x\n", h8->ppc, opcode); } } diff --git a/src/emu/cpu/i386/i386.c b/src/emu/cpu/i386/i386.c index cefd7540d58..f9f0a00d5cf 100644 --- a/src/emu/cpu/i386/i386.c +++ b/src/emu/cpu/i386/i386.c @@ -289,7 +289,7 @@ static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8 UINT8 segment; if( mod_rm >= 0xc0 ) - fatalerror("i386: Called modrm_to_EA with modrm value %02X !",mod_rm); + fatalerror("i386: Called modrm_to_EA with modrm value %02X!\n",mod_rm); if( cpustate->address_size ) { switch( rm ) @@ -2719,7 +2719,7 @@ static void report_invalid_opcode(i386_state *cpustate) static void report_unimplemented_opcode(i386_state *cpustate) { #ifndef DEBUG_MISSING_OPCODE - fatalerror("i386: Unimplemented opcode %02X at %08X", cpustate->opcode, cpustate->pc - 1 ); + fatalerror("i386: Unimplemented opcode %02X at %08X\n", cpustate->opcode, cpustate->pc - 1 ); #else astring errmsg; errmsg.cat("i386: Unimplemented opcode "); diff --git a/src/emu/cpu/i386/i386op16.c b/src/emu/cpu/i386/i386op16.c index 4543c7afcb6..46a9ec58f74 100644 --- a/src/emu/cpu/i386/i386op16.c +++ b/src/emu/cpu/i386/i386op16.c @@ -2965,7 +2965,7 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff UINT16 address, selector; if( modrm >= 0xc0 ) { - fatalerror("i386: groupFF_16 /%d NYI", (modrm >> 3) & 0x7); + fatalerror("i386: groupFF_16 /%d NYI\n", (modrm >> 3) & 0x7); } else { @@ -3012,7 +3012,7 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff if( modrm >= 0xc0 ) { - fatalerror("i386: groupFF_16 /%d NYI", (modrm >> 3) & 0x7); + fatalerror("i386: groupFF_16 /%d NYI\n", (modrm >> 3) & 0x7); } else { @@ -3052,7 +3052,7 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff I386OP(invalid)(cpustate); break; default: - fatalerror("i386: groupFF_16 /%d unimplemented", (modrm >> 3) & 0x7); + fatalerror("i386: groupFF_16 /%d unimplemented\n", (modrm >> 3) & 0x7); break; } } @@ -3246,7 +3246,7 @@ static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 00 break; default: - fatalerror("i386: group0F00_16 /%d unimplemented", (modrm >> 3) & 0x7); + fatalerror("i386: group0F00_16 /%d unimplemented\n", (modrm >> 3) & 0x7); break; } } @@ -3350,7 +3350,7 @@ static void I386OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01 break; } default: - fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); + fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } @@ -3470,7 +3470,7 @@ static void I386OP(group0FBA_16)(i386_state *cpustate) // Opcode 0x0f ba } break; default: - fatalerror("i386: group0FBA_16 /%d unknown", (modrm >> 3) & 0x7); + fatalerror("i386: group0FBA_16 /%d unknown\n", (modrm >> 3) & 0x7); break; } } @@ -3676,7 +3676,7 @@ static void I386OP(load_far_pointer16)(i386_state *cpustate, int s) UINT16 selector; if( modrm >= 0xc0 ) { - fatalerror("i386: load_far_pointer16 NYI"); + fatalerror("i386: load_far_pointer16 NYI\n"); } else { UINT32 ea = GetEA(cpustate,modrm,0); STORE_REG16(modrm, READ16(cpustate,ea + 0)); diff --git a/src/emu/cpu/i386/i386op32.c b/src/emu/cpu/i386/i386op32.c index a34703326e0..1ae5e221a64 100644 --- a/src/emu/cpu/i386/i386op32.c +++ b/src/emu/cpu/i386/i386op32.c @@ -2768,7 +2768,7 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff if( modrm >= 0xc0 ) { - fatalerror("i386: groupFF_32 /%d: NYI", (modrm >> 3) & 0x7); + fatalerror("i386: groupFF_32 /%d: NYI\n", (modrm >> 3) & 0x7); } else { @@ -2815,7 +2815,7 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff if( modrm >= 0xc0 ) { - fatalerror("i386: groupFF_32 /%d: NYI", (modrm >> 3) & 0x7); + fatalerror("i386: groupFF_32 /%d: NYI\n", (modrm >> 3) & 0x7); } else { @@ -2852,7 +2852,7 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff } break; default: - fatalerror("i386: groupFF_32 /%d unimplemented at %08X", (modrm >> 3) & 0x7, cpustate->pc-2); + fatalerror("i386: groupFF_32 /%d unimplemented at %08X\n", (modrm >> 3) & 0x7, cpustate->pc-2); break; } } @@ -3044,7 +3044,7 @@ static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 00 break; default: - fatalerror("i386: group0F00_32 /%d unimplemented", (modrm >> 3) & 0x7); + fatalerror("i386: group0F00_32 /%d unimplemented\n", (modrm >> 3) & 0x7); break; } } @@ -3148,7 +3148,7 @@ static void I386OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01 break; } default: - fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); + fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } @@ -3268,7 +3268,7 @@ static void I386OP(group0FBA_32)(i386_state *cpustate) // Opcode 0x0f ba } break; default: - fatalerror("i386: group0FBA_32 /%d unknown", (modrm >> 3) & 0x7); + fatalerror("i386: group0FBA_32 /%d unknown\n", (modrm >> 3) & 0x7); break; } } @@ -3474,7 +3474,7 @@ static void I386OP(load_far_pointer32)(i386_state *cpustate, int s) UINT16 selector; if( modrm >= 0xc0 ) { - fatalerror("i386: load_far_pointer32 NYI"); + fatalerror("i386: load_far_pointer32 NYI\n"); } else { UINT32 ea = GetEA(cpustate,modrm,0); STORE_REG32(modrm, READ32(cpustate,ea + 0)); diff --git a/src/emu/cpu/i386/i386ops.c b/src/emu/cpu/i386/i386ops.c index e345ebceab5..85a25ee3e25 100644 --- a/src/emu/cpu/i386/i386ops.c +++ b/src/emu/cpu/i386/i386ops.c @@ -694,7 +694,7 @@ static void I386OP(mov_cr_r32)(i386_state *cpustate) // Opcode 0x0f 22 case 3: CYCLES(cpustate,CYCLES_MOV_REG_CR3); break; case 4: CYCLES(cpustate,1); break; // TODO default: - fatalerror("i386: mov_cr_r32 CR%d !", cr); + fatalerror("i386: mov_cr_r32 CR%d!\n", cr); break; } } @@ -718,7 +718,7 @@ static void I386OP(mov_dr_r32)(i386_state *cpustate) // Opcode 0x0f 23 CYCLES(cpustate,CYCLES_MOV_DR6_7_REG); break; default: - fatalerror("i386: mov_dr_r32 DR%d !", dr); + fatalerror("i386: mov_dr_r32 DR%d!\n", dr); break; } } @@ -1201,7 +1201,7 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag) break; default: - fatalerror("i386: Invalid REP/opcode %02X combination",opcode); + fatalerror("i386: Invalid REP/opcode %02X combination\n",opcode); break; } @@ -2204,7 +2204,7 @@ static void I386OP(groupFE_8)(i386_state *cpustate) // Opcode 0xfe } break; default: - fatalerror("i386: groupFE_8 /%d unimplemented", (modrm >> 3) & 0x7); + fatalerror("i386: groupFE_8 /%d unimplemented\n", (modrm >> 3) & 0x7); break; } } diff --git a/src/emu/cpu/i386/i486ops.c b/src/emu/cpu/i386/i486ops.c index 5bc0d610897..54e64964397 100644 --- a/src/emu/cpu/i386/i486ops.c +++ b/src/emu/cpu/i386/i486ops.c @@ -305,7 +305,7 @@ static void I486OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01 break; } default: - fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); + fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } @@ -414,7 +414,7 @@ static void I486OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01 break; } default: - fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); + fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } diff --git a/src/emu/cpu/i386/pentops.c b/src/emu/cpu/i386/pentops.c index 073baa2a073..dc3df7aa9d6 100644 --- a/src/emu/cpu/i386/pentops.c +++ b/src/emu/cpu/i386/pentops.c @@ -75,7 +75,7 @@ static void PENTIUMOP(cmpxchg8b_m64)(i386_state *cpustate) // Opcode 0x0f c7 { UINT8 modm = FETCH(cpustate); if( modm >= 0xc0 ) { - fatalerror("pentium: cmpxchg8b_m64 - invalid modm"); + fatalerror("pentium: cmpxchg8b_m64 - invalid modm\n"); } else { UINT32 ea = GetEA(cpustate, modm, 0); UINT64 value = READ64(cpustate,ea); @@ -132,10 +132,10 @@ static void SSEOP(sse_group0fae)(i386_state *cpustate) // Opcode 0f ae GetNonTranslatedEA(cpustate, modm, NULL); break; default: - fatalerror("pentium: bad/unsupported 0f ae opcode"); + fatalerror("pentium: bad/unsupported 0f ae opcode\n"); } } else { - fatalerror("pentium: bad/unsupported 0f ae opcode"); + fatalerror("pentium: bad/unsupported 0f ae opcode\n"); } } diff --git a/src/emu/cpu/i386/x87ops.c b/src/emu/cpu/i386/x87ops.c index b5597e0dcfd..d133681db4e 100644 --- a/src/emu/cpu/i386/x87ops.c +++ b/src/emu/cpu/i386/x87ops.c @@ -4249,7 +4249,7 @@ void x87_fstsw_m2byte(i386_state *cpustate, UINT8 modrm) void x87_invalid(i386_state *cpustate, UINT8 modrm) { // TODO - fatalerror("x87 invalid instruction (PC:%.4x)", cpustate->pc); + fatalerror("x87 invalid instruction (PC:%.4x)\n", cpustate->pc); } diff --git a/src/emu/cpu/i960/i960.c b/src/emu/cpu/i960/i960.c index 4462756f100..9a9df2fe31b 100644 --- a/src/emu/cpu/i960/i960.c +++ b/src/emu/cpu/i960/i960.c @@ -109,7 +109,7 @@ INLINE void send_iac(i960_state_t *i960, UINT32 adr) i960->IP = iac[3]; break; default: - fatalerror("I960: %x: IAC %08x %08x %08x %08x", i960->PIP, iac[0], iac[1], iac[2], iac[3]); + fatalerror("I960: %x: IAC %08x %08x %08x %08x\n", i960->PIP, iac[0], iac[1], iac[2], iac[3]); break; } } @@ -157,7 +157,7 @@ INLINE UINT32 get_ea(i960_state_t *i960, UINT32 opcode) return ret; default: - fatalerror("I960: %x: unhandled MEMB mode %x", i960->PIP, mode); + fatalerror("I960: %x: unhandled MEMB mode %x\n", i960->PIP, mode); return 0; } } @@ -192,7 +192,7 @@ INLINE void set_ri(i960_state_t *i960, UINT32 opcode, UINT32 val) if(!(opcode & 0x00002000)) i960->r[(opcode>>19) & 0x1f] = val; else { - fatalerror("I960: %x: set_ri on literal?", i960->PIP); + fatalerror("I960: %x: set_ri on literal?\n", i960->PIP); } } @@ -204,7 +204,7 @@ INLINE void set_ri2(i960_state_t *i960, UINT32 opcode, UINT32 val, UINT32 val2) i960->r[((opcode>>19) & 0x1f)+1] = val2; } else { - fatalerror("I960: %x: set_ri2 on literal?", i960->PIP); + fatalerror("I960: %x: set_ri2 on literal?\n", i960->PIP); } } @@ -214,7 +214,7 @@ INLINE void set_ri64(i960_state_t *i960, UINT32 opcode, UINT64 val) i960->r[(opcode>>19) & 0x1f] = val; i960->r[((opcode>>19) & 0x1f)+1] = val >> 32; } else - fatalerror("I960: %x: set_ri64 on literal?", i960->PIP); + fatalerror("I960: %x: set_ri64 on literal?\n", i960->PIP); } INLINE double get_1_rif(i960_state_t *i960, UINT32 opcode) @@ -252,7 +252,7 @@ INLINE void set_rif(i960_state_t *i960, UINT32 opcode, double val) else if(!(opcode & 0x00e00000)) i960->fp[(opcode>>19) & 3] = val; else - fatalerror("I960: %x: set_rif on literal?", i960->PIP); + fatalerror("I960: %x: set_rif on literal?\n", i960->PIP); } INLINE double get_1_rifl(i960_state_t *i960, UINT32 opcode) @@ -296,7 +296,7 @@ INLINE void set_rifl(i960_state_t *i960, UINT32 opcode, double val) } else if(!(opcode & 0x00e00000)) i960->fp[(opcode>>19) & 3] = val; else - fatalerror("I960: %x: set_rifl on literal?", i960->PIP); + fatalerror("I960: %x: set_rifl on literal?\n", i960->PIP); } INLINE UINT32 get_1_ci(i960_state_t *i960, UINT32 opcode) @@ -608,7 +608,7 @@ static void do_ret(i960_state_t *i960) break; default: - fatalerror("I960: %x: Unsupported return mode %d", i960->PIP, i960->r[I960_PFP] & 7); + fatalerror("I960: %x: Unsupported return mode %d\n", i960->PIP, i960->r[I960_PFP] & 7); } } @@ -950,7 +950,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 58.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 58.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1036,7 +1036,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 59.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 59.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1117,7 +1117,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 5a.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5a.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1160,7 +1160,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 5b.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5b.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1173,7 +1173,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 5c.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5c.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1190,7 +1190,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 5d.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5d.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1207,7 +1207,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 5e.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5e.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1224,7 +1224,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 5f.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5f.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1258,7 +1258,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 60.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 60.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1321,7 +1321,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 64.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 64.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1336,7 +1336,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 65.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 65.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1360,7 +1360,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 66.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 66.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1407,7 +1407,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 67.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 67.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1480,7 +1480,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 68.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 68.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1551,7 +1551,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 69.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 69.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1592,7 +1592,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 6c.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 6c.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1605,7 +1605,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 6d.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 6d.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1646,7 +1646,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) set_rifl(i960, opcode, -fabs(t1f)); break; default: - fatalerror("I960: %x: Unhandled 6e.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 6e.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1677,7 +1677,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 70.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 70.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1717,7 +1717,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 74.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 74.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1752,7 +1752,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 78.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 78.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1787,7 +1787,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled 79.%x", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 79.%x\n", i960->PIP, (opcode >> 7) & 0xf); } break; @@ -1948,7 +1948,7 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) break; default: - fatalerror("I960: %x: Unhandled %02x", i960->PIP, opcode >> 24); + fatalerror("I960: %x: Unhandled %02x\n", i960->PIP, opcode >> 24); } } @@ -2058,7 +2058,7 @@ static CPU_SET_INFO( i960 ) case CPUINFO_INT_INPUT_STATE + I960_IRQ3: set_irq_line(i960, I960_IRQ3, info->i); break; default: - fatalerror("i960_set_info %x", state); + fatalerror("i960_set_info %x\n", state); } } @@ -2211,7 +2211,7 @@ CPU_GET_INFO( i960 ) case CPUINFO_STR_REGISTER + I960_G15: sprintf(info->s, "fp :%08x", i960->r[31]); break; // default: -// fatalerror("i960_get_info %x ", state); +// fatalerror("i960_get_info %x \n", state); } } diff --git a/src/emu/cpu/jaguar/jaguar.c b/src/emu/cpu/jaguar/jaguar.c index 93003278c1d..0364c183d6d 100644 --- a/src/emu/cpu/jaguar/jaguar.c +++ b/src/emu/cpu/jaguar/jaguar.c @@ -496,7 +496,7 @@ static CPU_EXECUTE( jaguargpu ) UINT32 op; /* debugging */ - //if (jaguar->PC < 0xf03000 || jaguar->PC > 0xf04000) { fatalerror("GPU: jaguar->PC = %06X (ppc = %06X)", jaguar->PC, jaguar->ppc); } + //if (jaguar->PC < 0xf03000 || jaguar->PC > 0xf04000) { fatalerror("GPU: jaguar->PC = %06X (ppc = %06X)\n", jaguar->PC, jaguar->ppc); } jaguar->ppc = jaguar->PC; debugger_instruction_hook(device, jaguar->PC); @@ -535,7 +535,7 @@ static CPU_EXECUTE( jaguardsp ) UINT32 op; /* debugging */ - //if (jaguar->PC < 0xf1b000 || jaguar->PC > 0xf1d000) { fatalerror(stderr, "DSP: jaguar->PC = %06X", jaguar->PC); } + //if (jaguar->PC < 0xf1b000 || jaguar->PC > 0xf1d000) { fatalerror(stderr, "DSP: jaguar->PC = %06X\n", jaguar->PC); } jaguar->ppc = jaguar->PC; debugger_instruction_hook(device, jaguar->PC); diff --git a/src/emu/cpu/mc68hc11/hc11ops.c b/src/emu/cpu/mc68hc11/hc11ops.c index 1d460463fda..55aaab26ce2 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.c +++ b/src/emu/cpu/mc68hc11/hc11ops.c @@ -3538,5 +3538,5 @@ static void HC11OP(page4)(hc11_state *cpustate) static void HC11OP(invalid)(hc11_state *cpustate) { - fatalerror("HC11: Invalid opcode 0x%02X at %04X", READ8(cpustate, cpustate->pc-1), cpustate->pc-1); + fatalerror("HC11: Invalid opcode 0x%02X at %04X\n", READ8(cpustate, cpustate->pc-1), cpustate->pc-1); } diff --git a/src/emu/cpu/mcs48/mcs48.c b/src/emu/cpu/mcs48/mcs48.c index 8b245ded4ee..e5e294d8a33 100644 --- a/src/emu/cpu/mcs48/mcs48.c +++ b/src/emu/cpu/mcs48/mcs48.c @@ -1434,7 +1434,7 @@ static void mcs48_generic_get_info(legacy_cpu_device *device, UINT32 state, cpui else if (ramsize == 256) info->i = 8; else - fatalerror("mcs48_generic_get_info: Invalid RAM size"); + fatalerror("mcs48_generic_get_info: Invalid RAM size\n"); break; /* --- the following bits of info are returned as pointers to functions --- */ @@ -1448,7 +1448,7 @@ static void mcs48_generic_get_info(legacy_cpu_device *device, UINT32 state, cpui else if (romsize == 4096) info->init = CPU_INIT_NAME(mcs48_4k_rom); else - fatalerror("mcs48_generic_get_info: Invalid ROM size"); + fatalerror("mcs48_generic_get_info: Invalid ROM size\n"); break; case CPUINFO_FCT_DISASSEMBLE: @@ -1469,7 +1469,7 @@ static void mcs48_generic_get_info(legacy_cpu_device *device, UINT32 state, cpui else if (romsize == 4096) info->internal_map8 = ADDRESS_MAP_NAME(program_12bit); else - fatalerror("mcs48_generic_get_info: Invalid RAM size"); + fatalerror("mcs48_generic_get_info: Invalid RAM size\n"); break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: @@ -1480,7 +1480,7 @@ static void mcs48_generic_get_info(legacy_cpu_device *device, UINT32 state, cpui else if (ramsize == 256) info->internal_map8 = ADDRESS_MAP_NAME(data_8bit); else - fatalerror("mcs48_generic_get_info: Invalid RAM size"); + fatalerror("mcs48_generic_get_info: Invalid RAM size\n"); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ diff --git a/src/emu/cpu/mips/mips3.c b/src/emu/cpu/mips/mips3.c index 9ab7ae567e7..58f62b3a3dd 100644 --- a/src/emu/cpu/mips/mips3.c +++ b/src/emu/cpu/mips/mips3.c @@ -688,7 +688,7 @@ INLINE void set_cop0_reg(int idx, UINT64 val) /* update interrupts and cycle counting */ UINT32 diff = mips3.core.cpr[0][idx] ^ val; // if (val & 0xe0) -// fatalerror("System set 64-bit addressing mode, SR=%08X", val); +// fatalerror("System set 64-bit addressing mode, SR=%08X\n", val); mips3.core.cpr[0][idx] = val; if (diff & 0x8000) mips3com_update_cycle_counting(&mips3.core); diff --git a/src/emu/cpu/mips/mips3com.c b/src/emu/cpu/mips/mips3com.c index d5cb2f2d651..952fc10e457 100644 --- a/src/emu/cpu/mips/mips3com.c +++ b/src/emu/cpu/mips/mips3com.c @@ -857,7 +857,7 @@ static UINT32 compute_prid_register(const mips3_state *mips) return 0x2700; default: - fatalerror("Unknown MIPS flavor specified"); + fatalerror("Unknown MIPS flavor specified\n"); } return 0x2000; } diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index 3f2d43efa0b..8e64d4dfa5f 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -397,7 +397,7 @@ static void mips3_init(mips3_flavor flavor, int bigendian, legacy_cpu_device *de /* allocate enough space for the cache and the core */ cache = auto_alloc(device->machine(), drc_cache(CACHE_SIZE + sizeof(*mips3))); if (cache == NULL) - fatalerror("Unable to allocate cache of size %d", (UINT32)(CACHE_SIZE + sizeof(*mips3))); + fatalerror("Unable to allocate cache of size %d\n", (UINT32)(CACHE_SIZE + sizeof(*mips3))); /* allocate the core memory */ *(mips3_state **)device->token() = mips3 = (mips3_state *)cache->alloc_near(sizeof(*mips3)); @@ -744,7 +744,7 @@ static void code_flush_cache(mips3_state *mips3) } catch (drcuml_block::abort_compilation &) { - fatalerror("Unrecoverable error generating static code"); + fatalerror("Unrecoverable error generating static code\n"); } } @@ -967,7 +967,7 @@ static void cfunc_unimplemented(void *param) { mips3_state *mips3 = (mips3_state *)param; UINT32 opcode = mips3->impstate->arg0; - fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)", mips3->pc, opcode, opcode >> 26, opcode & 0x3f); + fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", mips3->pc, opcode, opcode >> 26, opcode & 0x3f); } diff --git a/src/emu/cpu/pic16c5x/16c5xdsm.c b/src/emu/cpu/pic16c5x/16c5xdsm.c index 3b2f997f42d..dcaa0d86cd2 100644 --- a/src/emu/cpu/pic16c5x/16c5xdsm.c +++ b/src/emu/cpu/pic16c5x/16c5xdsm.c @@ -124,13 +124,13 @@ static void InitDasm16C5x(void) case 'k': bit --; break; - default: fatalerror("Invalid instruction encoding '%s %s'", + default: fatalerror("Invalid instruction encoding '%s %s'\n", ops[0],ops[1]); } } if (bit != -1 ) { - fatalerror("not enough bits in encoding '%s %s' %d", + fatalerror("not enough bits in encoding '%s %s' %d\n", ops[0],ops[1],bit); } while (isspace((UINT8)*p)) p++; @@ -213,7 +213,7 @@ CPU_DISASSEMBLE( pic16c5x ) case 'k': k <<=1; k |= ((code & (1<> 24); cycles = (INT8)(result >> 16); diff --git a/src/emu/cpu/powerpc/ppc.c b/src/emu/cpu/powerpc/ppc.c index e115fa56371..b65ad717d9a 100644 --- a/src/emu/cpu/powerpc/ppc.c +++ b/src/emu/cpu/powerpc/ppc.c @@ -671,7 +671,7 @@ INLINE void ppc_set_spr(int spr, UINT32 value) } } - fatalerror("ppc: set_spr: unknown spr %d (%03X) !", spr, spr); + fatalerror("ppc: set_spr: unknown spr %d (%03X)!\n", spr, spr); } INLINE UINT32 ppc_get_spr(int spr) @@ -739,11 +739,11 @@ INLINE UINT32 ppc_get_spr(int spr) switch (spr) { case SPR603E_TBL_R: - fatalerror("ppc: get_spr: TBL_R "); + fatalerror("ppc: get_spr: TBL_R\n"); break; case SPR603E_TBU_R: - fatalerror("ppc: get_spr: TBU_R "); + fatalerror("ppc: get_spr: TBU_R\n"); break; case SPR603E_TBL_W: return (UINT32)(ppc_read_timebase()); @@ -782,7 +782,7 @@ INLINE UINT32 ppc_get_spr(int spr) } } - fatalerror("ppc: get_spr: unknown spr %d (%03X) !", spr, spr); + fatalerror("ppc: get_spr: unknown spr %d (%03X)!\n", spr, spr); return 0; } @@ -798,7 +798,7 @@ static void ppc_write64_translated(address_space *space, offs_t address, UINT64 INLINE void ppc_set_msr(UINT32 value) { if( value & (MSR_ILE | MSR_LE) ) - fatalerror("ppc: set_msr: little_endian mode not supported !"); + fatalerror("ppc: set_msr: little_endian mode not supported!\n"); MSR = value; @@ -1152,7 +1152,7 @@ static CPU_INIT( ppc603 ) if (pll_config == -1) { - fatalerror("PPC: Invalid bus/multiplier combination (bus frequency = %d, multiplier = %1.1f)", config->bus_frequency, multiplier); + fatalerror("PPC: Invalid bus/multiplier combination (bus frequency = %d, multiplier = %1.1f)\n", config->bus_frequency, multiplier); } ppc.hid1 = pll_config << 28; diff --git a/src/emu/cpu/powerpc/ppc403.c b/src/emu/cpu/powerpc/ppc403.c index 3ee47476885..fca554c5811 100644 --- a/src/emu/cpu/powerpc/ppc403.c +++ b/src/emu/cpu/powerpc/ppc403.c @@ -69,7 +69,7 @@ INLINE void ppc_set_dcr(int dcr, UINT32 value) case DCR_DMACR3: ppc.dma[3].cr = value; ppc403_dma_exec(3); break; default: - fatalerror("ppc: set_dcr: Unimplemented DCR %X", dcr); + fatalerror("ppc: set_dcr: Unimplemented DCR %X\n", dcr); break; } } @@ -110,7 +110,7 @@ INLINE UINT32 ppc_get_dcr(int dcr) case DCR_DMACR3: return ppc.dma[3].cr; default: - fatalerror("ppc: get_dcr: Unimplemented DCR %X", dcr); + fatalerror("ppc: get_dcr: Unimplemented DCR %X\n", dcr); break; } } @@ -232,7 +232,7 @@ static CPU_EXECUTE( ppc403 ) } break; case 3: - fatalerror("PPC: Watchdog Timer caused reset"); + fatalerror("PPC: Watchdog Timer caused reset\n"); break; } } @@ -395,7 +395,7 @@ void ppc403_exception(int exception) } default: - fatalerror("ppc: Unhandled exception %d", exception); + fatalerror("ppc: Unhandled exception %d\n", exception); break; } } @@ -452,7 +452,7 @@ static void ppc403_set_irq_line(int irqline, int state) } else { - fatalerror("PPC: Unknown IRQ line %d", irqline); + fatalerror("PPC: Unknown IRQ line %d\n", irqline); } } @@ -565,7 +565,7 @@ static UINT8 ppc403_spu_r(UINT32 a) case 0x7: return ppc.spu.sprc; case 0x8: return ppc.spu.sptc; case 0x9: return ppc.spu.sprb; - default: fatalerror("ppc: spu_r: %02X", a & 0xf); + default: fatalerror("ppc: spu_r: %02X\n", a & 0xf); } } @@ -671,7 +671,7 @@ static void ppc403_spu_w(UINT32 a, UINT8 d) break; default: - fatalerror("ppc: spu_w: %02X, %02X", a & 0xf, d); + fatalerror("ppc: spu_w: %02X, %02X\n", a & 0xf, d); break; } //mame_printf_debug("spu_w: %02X, %02X at %08X\n", a & 0xf, d, ppc.pc); @@ -821,14 +821,14 @@ static void ppc403_dma_exec(int ch) #endif } else { - fatalerror("ppc: dma_exec: buffered DMA to unknown peripheral ! (channel %d)", ch); + fatalerror("ppc: dma_exec: buffered DMA to unknown peripheral ! (channel %d)\n", ch); } } break; case 1: /* fly-by DMA */ - fatalerror("ppc: dma_exec: fly-by DMA not implemented"); + fatalerror("ppc: dma_exec: fly-by DMA not implemented\n"); break; case 2: /* software initiated mem-to-mem DMA */ @@ -879,12 +879,12 @@ static void ppc403_dma_exec(int ch) } break; default: - fatalerror("dma: dma_exec: SW mem-to-mem DMA, width = %d", width); + fatalerror("dma: dma_exec: SW mem-to-mem DMA, width = %d\n", width); } break; case 3: /* hardware initiated mem-to-mem DMA */ - fatalerror("ppc: dma_exec: HW mem-to-mem DMA not implemented"); + fatalerror("ppc: dma_exec: HW mem-to-mem DMA not implemented\n"); break; } @@ -892,10 +892,10 @@ static void ppc403_dma_exec(int ch) /* DEBUG: check for not yet supported features */ if( (ppc.dma[ch].cr & DMA_TCE) == 0 ) - fatalerror("ppc: dma_exec: DMA_TCE == 0"); + fatalerror("ppc: dma_exec: DMA_TCE == 0\n"); if( ppc.dma[ch].cr & DMA_CH ) - fatalerror("ppc: dma_exec: DMA chaining not implemented"); + fatalerror("ppc: dma_exec: DMA chaining not implemented\n"); /* generate interrupts */ if( ppc.dma[ch].cr & DMA_CIE ) @@ -931,23 +931,23 @@ static void ppc403_write8(address_space *space, UINT32 a, UINT8 d) static UINT16 ppc403_read16_unaligned(address_space *space, UINT32 a) { - fatalerror("ppc: Unaligned read16 %08X at %08X", a, ppc.pc); + fatalerror("ppc: Unaligned read16 %08X at %08X\n", a, ppc.pc); return 0; } static UINT32 ppc403_read32_unaligned(address_space *space, UINT32 a) { - fatalerror("ppc: Unaligned read32 %08X at %08X", a, ppc.pc); + fatalerror("ppc: Unaligned read32 %08X at %08X\n", a, ppc.pc); return 0; } static void ppc403_write16_unaligned(address_space *space, UINT32 a, UINT16 d) { - fatalerror("ppc: Unaligned write16 %08X, %04X at %08X", a, d, ppc.pc); + fatalerror("ppc: Unaligned write16 %08X, %04X at %08X\n", a, d, ppc.pc); } static void ppc403_write32_unaligned(address_space *space, UINT32 a, UINT32 d) { - fatalerror("ppc: Unaligned write32 %08X, %08X at %08X", a, d, ppc.pc); + fatalerror("ppc: Unaligned write32 %08X, %08X at %08X\n", a, d, ppc.pc); } diff --git a/src/emu/cpu/powerpc/ppc602.c b/src/emu/cpu/powerpc/ppc602.c index 9922b7940e1..1ae7ecdb683 100644 --- a/src/emu/cpu/powerpc/ppc602.c +++ b/src/emu/cpu/powerpc/ppc602.c @@ -157,7 +157,7 @@ void ppc602_exception(int exception) default: - fatalerror("ppc: Unhandled exception %d", exception); + fatalerror("ppc: Unhandled exception %d\n", exception); break; } } diff --git a/src/emu/cpu/powerpc/ppc603.c b/src/emu/cpu/powerpc/ppc603.c index d4dd2ca926c..fec16755344 100644 --- a/src/emu/cpu/powerpc/ppc603.c +++ b/src/emu/cpu/powerpc/ppc603.c @@ -160,7 +160,7 @@ void ppc603_exception(int exception) break; default: - fatalerror("ppc: Unhandled exception %d", exception); + fatalerror("ppc: Unhandled exception %d\n", exception); break; } } diff --git a/src/emu/cpu/powerpc/ppc_mem.c b/src/emu/cpu/powerpc/ppc_mem.c index 38c76a6bba2..2763b383a6b 100644 --- a/src/emu/cpu/powerpc/ppc_mem.c +++ b/src/emu/cpu/powerpc/ppc_mem.c @@ -176,7 +176,7 @@ static int ppc_translate_address(offs_t *addr_ptr, int flags) { /* direct store translation */ if ((flags & PPC_TRANSLATE_NOEXCEPTION) == 0) - fatalerror("ppc: direct store translation not yet implemented"); + fatalerror("ppc: direct store translation not yet implemented\n"); return 0; } else diff --git a/src/emu/cpu/powerpc/ppc_ops.c b/src/emu/cpu/powerpc/ppc_ops.c index 287517fff77..21344198523 100644 --- a/src/emu/cpu/powerpc/ppc_ops.c +++ b/src/emu/cpu/powerpc/ppc_ops.c @@ -6,7 +6,7 @@ #ifndef PPC_DRC static void ppc_unimplemented(UINT32 op) { - fatalerror("ppc: Unimplemented opcode %08X at %08X", op, ppc.pc); + fatalerror("ppc: Unimplemented opcode %08X at %08X\n", op, ppc.pc); } static void ppc_addx(UINT32 op) @@ -1610,7 +1610,7 @@ static void ppc_xoris(UINT32 op) static void ppc_invalid(UINT32 op) { - fatalerror("ppc: Invalid opcode %08X PC : %X", op, ppc.pc); + fatalerror("ppc: Invalid opcode %08X PC : %X\n", op, ppc.pc); } #endif @@ -1951,7 +1951,7 @@ static void ppc_mftb(UINT32 op) { case 268: REG(RT) = (UINT32)(ppc_read_timebase()); break; case 269: REG(RT) = (UINT32)(ppc_read_timebase() >> 32); break; - default: fatalerror("ppc: Invalid timebase register %d at %08X", x, ppc.pc); break; + default: fatalerror("ppc: Invalid timebase register %d at %08X\n", x, ppc.pc); break; } } diff --git a/src/emu/cpu/powerpc/ppccom.c b/src/emu/cpu/powerpc/ppccom.c index 88713d28f3f..7222ab7d55f 100644 --- a/src/emu/cpu/powerpc/ppccom.c +++ b/src/emu/cpu/powerpc/ppccom.c @@ -507,7 +507,7 @@ static UINT32 ppccom_translate_address_internal(powerpc_state *ppc, int intentio { /* we don't support the MMU of the 403GCX */ if (ppc->flavor == PPC_MODEL_403GCX && (ppc->msr & MSROEA_DR)) - fatalerror("MMU enabled but not supported!"); + fatalerror("MMU enabled but not supported!\n"); /* only check if PE is enabled */ if (transtype == TRANSLATE_WRITE && (ppc->msr & MSR4XX_PE)) @@ -2023,7 +2023,7 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan) /* check for unsupported features */ if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_TCE)) - fatalerror("ppc4xx_dma_exec: DMA_TCE == 0"); + fatalerror("ppc4xx_dma_exec: DMA_TCE == 0\n"); /* transfer mode */ switch ((dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_TM_MASK) >> 21) @@ -2058,7 +2058,7 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan) /* fly-by mode DMA */ case 1: - fatalerror("ppc4xx_dma_exec: fly-by DMA not implemented"); + fatalerror("ppc4xx_dma_exec: fly-by DMA not implemented\n"); break; /* software initiated memory-to-memory mode DMA */ @@ -2114,7 +2114,7 @@ static void ppc4xx_dma_exec(powerpc_state *ppc, int dmachan) /* hardware initiated memory-to-memory mode DMA */ case 3: - fatalerror("ppc4xx_dma_exec: HW mem-to-mem DMA not implemented"); + fatalerror("ppc4xx_dma_exec: HW mem-to-mem DMA not implemented\n"); break; } } @@ -2225,7 +2225,7 @@ static void ppc4xx_spu_rx_data(powerpc_state *ppc, UINT8 data) /* fail if we are going to overflow */ new_rxin = (ppc->spu.rxin + 1) % ARRAY_LENGTH(ppc->spu.rxbuffer); if (new_rxin == ppc->spu.rxout) - fatalerror("ppc4xx_spu_rx_data: buffer overrun!"); + fatalerror("ppc4xx_spu_rx_data: buffer overrun!\n"); /* store the data and accept the new in index */ ppc->spu.rxbuffer[ppc->spu.rxin] = data; diff --git a/src/emu/cpu/powerpc/ppcdrc.c b/src/emu/cpu/powerpc/ppcdrc.c index eeceb0b0792..897580a704d 100644 --- a/src/emu/cpu/powerpc/ppcdrc.c +++ b/src/emu/cpu/powerpc/ppcdrc.c @@ -912,7 +912,7 @@ static void code_flush_cache(powerpc_state *ppc) } catch (drcuml_block::abort_compilation &) { - fatalerror("Error generating PPC static handlers"); + fatalerror("Error generating PPC static handlers\n"); } } @@ -1096,7 +1096,7 @@ static void cfunc_unimplemented(void *param) { powerpc_state *ppc = (powerpc_state *)param; UINT32 opcode = ppc->impstate->arg0; - fatalerror("PC=%08X: Unimplemented op %08X", ppc->pc, opcode); + fatalerror("PC=%08X: Unimplemented op %08X\n", ppc->pc, opcode); } diff --git a/src/emu/cpu/rsp/rspdrc.c b/src/emu/cpu/rsp/rspdrc.c index 960026abc27..4745b85f655 100644 --- a/src/emu/cpu/rsp/rspdrc.c +++ b/src/emu/cpu/rsp/rspdrc.c @@ -486,7 +486,7 @@ static void cfunc_get_cop0_reg(void *param) } else { - fatalerror("RSP: cfunc_get_cop0_reg: %d", reg); + fatalerror("RSP: cfunc_get_cop0_reg: %d\n", reg); } } @@ -3457,7 +3457,7 @@ static void code_flush_cache(rsp_state *rsp) } catch (drcuml_block::abort_compilation &) { - fatalerror("Unable to generate static RSP code"); + fatalerror("Unable to generate static RSP code\n"); } } @@ -3579,7 +3579,7 @@ static void cfunc_unimplemented(void *param) { rsp_state *rsp = (rsp_state *)param; UINT32 opcode = rsp->impstate->arg0; - fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)", rsp->pc, opcode, opcode >> 26, opcode & 0x3f); + fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", rsp->pc, opcode, opcode >> 26, opcode & 0x3f); } @@ -3590,7 +3590,7 @@ static void cfunc_unimplemented(void *param) #ifdef UNUSED_CODE static void cfunc_fatalerror(void *param) { - fatalerror("fatalerror"); + fatalerror("fatalerror\n"); } #endif diff --git a/src/emu/cpu/sh2/sh2comn.c b/src/emu/cpu/sh2/sh2comn.c index e390d252123..d67ceace009 100644 --- a/src/emu/cpu/sh2/sh2comn.c +++ b/src/emu/cpu/sh2/sh2comn.c @@ -360,7 +360,7 @@ void sh2_do_dma(sh2_state *sh2, int dma) { //printf("dma stalled\n"); sh2->dma_timer_active[dma]=2;// mark as stalled - fatalerror("SH2 dma_callback_fifo_data_available == 0 in unsupported mode"); + fatalerror("SH2 dma_callback_fifo_data_available == 0 in unsupported mode\n"); } } diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c index 083ce497968..6addac5e835 100644 --- a/src/emu/cpu/sh2/sh2drc.c +++ b/src/emu/cpu/sh2/sh2drc.c @@ -276,7 +276,7 @@ static void cfunc_unimplemented(void *param) { sh2_state *sh2 = (sh2_state *)param; UINT16 opcode = sh2->arg0; - fatalerror("PC=%08X: Unimplemented op %04X", sh2->pc, opcode); + fatalerror("PC=%08X: Unimplemented op %04X\n", sh2->pc, opcode); } /*------------------------------------------------- @@ -863,7 +863,7 @@ static void code_flush_cache(sh2_state *sh2) } catch (drcuml_block::abort_compilation &) { - fatalerror("Unable to generate SH2 static code"); + fatalerror("Unable to generate SH2 static code\n"); } sh2->cache_dirty = FALSE; diff --git a/src/emu/cpu/sharc/compute.c b/src/emu/cpu/sharc/compute.c index d2fa09a167c..e08fe87e9f0 100644 --- a/src/emu/cpu/sharc/compute.c +++ b/src/emu/cpu/sharc/compute.c @@ -114,7 +114,7 @@ INLINE void compute_add(SHARC_REGS *cpustate, int rn, int rx, int ry) UINT32 r = REG(rx) + REG(ry); if (cpustate->mode1 & MODE1_ALUSAT) - fatalerror("SHARC: compute_add: ALU saturation not implemented !"); + fatalerror("SHARC: compute_add: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); SET_FLAG_AN(r); @@ -132,7 +132,7 @@ INLINE void compute_sub(SHARC_REGS *cpustate, int rn, int rx, int ry) UINT32 r = REG(rx) - REG(ry); if (cpustate->mode1 & MODE1_ALUSAT) - fatalerror("SHARC: compute_sub: ALU saturation not implemented !"); + fatalerror("SHARC: compute_sub: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); SET_FLAG_AN(r); @@ -151,7 +151,7 @@ INLINE void compute_add_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) UINT32 r = REG(rx) + REG(ry) + c; if (cpustate->mode1 & MODE1_ALUSAT) - fatalerror("SHARC: compute_add_ci: ALU saturation not implemented !"); + fatalerror("SHARC: compute_add_ci: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); SET_FLAG_AN(r); @@ -170,7 +170,7 @@ INLINE void compute_sub_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) UINT32 r = REG(rx) - REG(ry) + c - 1; if (cpustate->mode1 & MODE1_ALUSAT) - fatalerror("SHARC: compute_sub_ci: ALU saturation not implemented !"); + fatalerror("SHARC: compute_sub_ci: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); SET_FLAG_AN(r); @@ -971,11 +971,11 @@ INLINE void compute_multi_mr_to_reg(SHARC_REGS *cpustate, int ai, int rk) { case 0: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf)); break; case 1: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf >> 32)); break; - case 2: fatalerror("SHARC: tried to load MR2F"); break; + case 2: fatalerror("SHARC: tried to load MR2F\n"); break; case 4: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb)); break; case 5: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb >> 32)); break; - case 6: fatalerror("SHARC: tried to load MR2B"); break; - default: fatalerror("SHARC: unknown ai %d in mr_to_reg", ai); + case 6: fatalerror("SHARC: tried to load MR2B\n"); break; + default: fatalerror("SHARC: unknown ai %d in mr_to_reg\n", ai); } CLEAR_MULTIPLIER_FLAGS(); @@ -987,11 +987,11 @@ INLINE void compute_multi_reg_to_mr(SHARC_REGS *cpustate, int ai, int rk) { case 0: cpustate->mrf &= ~0xffffffff; cpustate->mrf |= GET_UREG(cpustate, rk); break; case 1: cpustate->mrf &= 0xffffffff; cpustate->mrf |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break; - case 2: fatalerror("SHARC: tried to write MR2F"); break; + case 2: fatalerror("SHARC: tried to write MR2F\n"); break; case 4: cpustate->mrb &= ~0xffffffff; cpustate->mrb |= GET_UREG(cpustate, rk); break; case 5: cpustate->mrb &= 0xffffffff; cpustate->mrb |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break; - case 6: fatalerror("SHARC: tried to write MR2B"); break; - default: fatalerror("SHARC: unknown ai %d in reg_to_mr", ai); + case 6: fatalerror("SHARC: tried to write MR2B\n"); break; + default: fatalerror("SHARC: unknown ai %d in reg_to_mr\n", ai); } CLEAR_MULTIPLIER_FLAGS(); diff --git a/src/emu/cpu/sharc/sharc.c b/src/emu/cpu/sharc/sharc.c index 974553a3156..d266cd0f433 100644 --- a/src/emu/cpu/sharc/sharc.c +++ b/src/emu/cpu/sharc/sharc.c @@ -245,7 +245,7 @@ static void iop_write_latency_effect(SHARC_REGS *cpustate) break; } - default: fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X", cpustate->iop_latency_reg); + default: fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X\n", cpustate->iop_latency_reg); } } @@ -267,7 +267,7 @@ static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address) } return r; } - default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X", address, cpustate->pc); + default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X\n", address, cpustate->pc); } return 0; } @@ -324,7 +324,7 @@ static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data) case 0x4e: cpustate->dma[7].ext_modifier = data; return; case 0x4f: cpustate->dma[7].ext_count = data; return; - default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X", address, data, cpustate->pc); + default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X\n", address, data, cpustate->pc); } } @@ -579,7 +579,7 @@ static CPU_RESET( sharc ) break; default: - fatalerror("SHARC: Unimplemented boot mode %d", cpustate->boot_mode); + fatalerror("SHARC: Unimplemented boot mode %d\n", cpustate->boot_mode); } cpustate->pc = 0x20004; @@ -618,7 +618,7 @@ void sharc_set_flag_input(device_t *device, int flag_num, int state) } else { - fatalerror("sharc_set_flag_input: flag %d is set output!", flag_num); + fatalerror("sharc_set_flag_input: flag %d is set output!\n", flag_num); } } } @@ -755,12 +755,12 @@ static CPU_EXECUTE( sharc ) } case 1: // counter-based, length 1 { - //fatalerror("SHARC: counter-based loop, length 1 at %08X", cpustate->pc); + //fatalerror("SHARC: counter-based loop, length 1 at %08X\n", cpustate->pc); //break; } case 2: // counter-based, length 2 { - //fatalerror("SHARC: counter-based loop, length 2 at %08X", cpustate->pc); + //fatalerror("SHARC: counter-based loop, length 2 at %08X\n", cpustate->pc); //break; } case 3: // counter-based, length >2 diff --git a/src/emu/cpu/sharc/sharcdma.c b/src/emu/cpu/sharc/sharcdma.c index 740f68bda14..5def70d801f 100644 --- a/src/emu/cpu/sharc/sharcdma.c +++ b/src/emu/cpu/sharc/sharcdma.c @@ -21,7 +21,7 @@ static void schedule_chained_dma_op(SHARC_REGS *cpustate, int channel, UINT32 dm if (cpustate->dmaop_cycles > 0) { - fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!", cpustate->pc); + fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc); } if (chained_direction) // Transmit to external @@ -54,7 +54,7 @@ static void schedule_dma_op(SHARC_REGS *cpustate, int channel, UINT32 src, UINT3 { if (cpustate->dmaop_cycles > 0) { - fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!", cpustate->pc); + fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc); } cpustate->dmaop_channel = channel; @@ -155,9 +155,9 @@ static void sharc_dma_exec(SHARC_REGS *cpustate, int channel) //flsh = (cpustate->dma[channel].control >> 13) & 0x1; if (ishake) - fatalerror("SHARC: dma_exec: handshake not supported"); + fatalerror("SHARC: dma_exec: handshake not supported\n"); if (intio) - fatalerror("SHARC: dma_exec: single-word interrupt enable not supported"); + fatalerror("SHARC: dma_exec: single-word interrupt enable not supported\n"); diff --git a/src/emu/cpu/sharc/sharcmem.c b/src/emu/cpu/sharc/sharcmem.c index 79d8f3679a1..e4947c98dba 100644 --- a/src/emu/cpu/sharc/sharcmem.c +++ b/src/emu/cpu/sharc/sharcmem.c @@ -18,7 +18,7 @@ static UINT32 pm_read32(SHARC_REGS *cpustate, UINT32 address) (cpustate->internal_ram_block1[addr + 1]); } else { - fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc); + fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, cpustate->pc); } } @@ -42,7 +42,7 @@ static void pm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) return; } else { - fatalerror("SHARC: PM Bus Write %08X, %08X at %08X", address, data, cpustate->pc); + fatalerror("SHARC: PM Bus Write %08X, %08X at %08X\n", address, data, cpustate->pc); } } @@ -66,7 +66,7 @@ static UINT64 pm_read48(SHARC_REGS *cpustate, UINT32 address) ((UINT64)(cpustate->internal_ram_block1[addr + 2]) << 0); } else { - fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc); + fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, cpustate->pc); } return 0; @@ -94,7 +94,7 @@ static void pm_write48(SHARC_REGS *cpustate, UINT32 address, UINT64 data) return; } else { - fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X", address, (UINT16)(data >> 32),(UINT32)data, cpustate->pc); + fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X\n", address, (UINT16)(data >> 32),(UINT32)data, cpustate->pc); } } diff --git a/src/emu/cpu/sharc/sharcops.c b/src/emu/cpu/sharc/sharcops.c index bbe2bc2414a..59d730d06a6 100644 --- a/src/emu/cpu/sharc/sharcops.c +++ b/src/emu/cpu/sharc/sharcops.c @@ -161,15 +161,15 @@ static void systemreg_write_latency_effect(SHARC_REGS *cpustate) if ((data & 0x1) != (oldreg & 0x1)) { - fatalerror("SHARC: systemreg_latency_op: enable I8 bit-reversing"); + fatalerror("SHARC: systemreg_latency_op: enable I8 bit-reversing\n"); } if ((data & 0x2) != (oldreg & 0x2)) { - fatalerror("SHARC: systemreg_latency_op: enable I0 bit-reversing"); + fatalerror("SHARC: systemreg_latency_op: enable I0 bit-reversing\n"); } if ((data & 0x4) != (oldreg & 0x4)) { - fatalerror("SHARC: systemreg_latency_op: enable MR alternate"); + fatalerror("SHARC: systemreg_latency_op: enable MR alternate\n"); } if ((data & 0x8) != (oldreg & 0x8)) /* Switch DAG1 7-4 */ @@ -260,7 +260,7 @@ static void systemreg_write_latency_effect(SHARC_REGS *cpustate) } break; } - default: fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X", cpustate->systemreg_latency_reg, cpustate->pc); + default: fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X\n", cpustate->systemreg_latency_reg, cpustate->pc); } cpustate->systemreg_latency_reg = -1; @@ -332,7 +332,7 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) switch(reg) { case 0x4: return cpustate->pcstack[cpustate->pcstkp]; /* PCSTK */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } break; } @@ -358,7 +358,7 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) } case 0xd: return cpustate->imask; /* IMASK */ case 0xe: return cpustate->stky; /* STKY */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } break; } @@ -371,12 +371,12 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) case 0xb: return (UINT32)(cpustate->px); /* PX */ case 0xc: return (UINT16)(cpustate->px); /* PX1 */ case 0xd: return (UINT32)(cpustate->px >> 16); /* PX2 */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } break; } - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } } @@ -441,7 +441,7 @@ static void SET_UREG(SHARC_REGS *cpustate, int ureg, UINT32 data) { case 0x5: cpustate->pcstkp = data; break; /* PCSTKP */ case 0x8: cpustate->lcntr = data; break; /* LCNTR */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } break; @@ -471,7 +471,7 @@ static void SET_UREG(SHARC_REGS *cpustate, int ureg, UINT32 data) } case 0xe: cpustate->stky = data; break; /* STKY */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } break; @@ -480,11 +480,11 @@ static void SET_UREG(SHARC_REGS *cpustate, int ureg, UINT32 data) { case 0xc: cpustate->px &= U64(0xffffffffffff0000); cpustate->px |= (data & 0xffff); break; /* PX1 */ case 0xd: cpustate->px &= U64(0x000000000000ffff); cpustate->px |= (UINT64)data << 16; break; /* PX2 */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } break; - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc); + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); } } @@ -694,7 +694,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int break; } - default: fatalerror("SHARC: unimplemented shift operation %02X at %08X", shiftop, cpustate->pc); + default: fatalerror("SHARC: unimplemented shift operation %02X at %08X\n", shiftop, cpustate->pc); } } @@ -786,7 +786,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) } default: - fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)", multiop, cpustate->pc, opcode); + fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)\n", multiop, cpustate->pc, opcode); break; } } @@ -853,7 +853,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) break; } - default: fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)", op, cpustate->pc, opcode); + default: fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)\n", op, cpustate->pc, opcode); } break; } @@ -875,7 +875,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) case 0xb2: REG(rn) = compute_mrb_plus_mul_ssin(cpustate, rx, ry); break; default: - fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)", op, cpustate->pc, opcode); + fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)\n", op, cpustate->pc, opcode); break; } break; @@ -1046,13 +1046,13 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) } default: - fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)", op, cpustate->pc, opcode); + fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)\n", op, cpustate->pc, opcode); } break; } default: - fatalerror("SHARC: compute: invalid single-function operation %02X", cu); + fatalerror("SHARC: compute: invalid single-function operation %02X\n", cu); } } } @@ -1062,7 +1062,7 @@ INLINE void PUSH_PC(SHARC_REGS *cpustate, UINT32 pc) cpustate->pcstkp++; if(cpustate->pcstkp >= 32) { - fatalerror("SHARC: PC Stack overflow !"); + fatalerror("SHARC: PC Stack overflow!\n"); } if (cpustate->pcstkp == 0) @@ -1084,7 +1084,7 @@ INLINE UINT32 POP_PC(SHARC_REGS *cpustate) if(cpustate->pcstkp == 0) { - fatalerror("SHARC: PC Stack underflow !"); + fatalerror("SHARC: PC Stack underflow!\n"); } cpustate->pcstkp--; @@ -1111,7 +1111,7 @@ INLINE void PUSH_LOOP(SHARC_REGS *cpustate, UINT32 pc, UINT32 count) cpustate->lstkp++; if(cpustate->lstkp >= 6) { - fatalerror("SHARC: Loop Stack overflow !"); + fatalerror("SHARC: Loop Stack overflow!\n"); } if (cpustate->lstkp == 0) @@ -1133,7 +1133,7 @@ INLINE void POP_LOOP(SHARC_REGS *cpustate) { if(cpustate->lstkp == 0) { - fatalerror("SHARC: Loop Stack underflow !"); + fatalerror("SHARC: Loop Stack underflow!\n"); } cpustate->lstkp--; @@ -1156,7 +1156,7 @@ INLINE void PUSH_STATUS_STACK(SHARC_REGS *cpustate) cpustate->status_stkp++; if (cpustate->status_stkp >= 5) { - fatalerror("SHARC: Status stack overflow !"); + fatalerror("SHARC: Status stack overflow!\n"); } if (cpustate->status_stkp == 0) @@ -1180,7 +1180,7 @@ INLINE void POP_STATUS_STACK(SHARC_REGS *cpustate) cpustate->status_stkp--; if (cpustate->status_stkp < 0) { - fatalerror("SHARC: Status stack underflow !"); + fatalerror("SHARC: Status stack underflow!\n"); } if (cpustate->status_stkp == 0) @@ -2254,7 +2254,7 @@ static void sharcop_rts(SHARC_REGS *cpustate) int compute = cpustate->opcode & 0x7fffff; //if(lr) - // fatalerror("SHARC: rts: loop reentry not implemented !"); + // fatalerror("SHARC: rts: loop reentry not implemented!\n"); if (e) /* IF...ELSE */ { @@ -2646,7 +2646,7 @@ static void sharcop_sysreg_bitop(SHARC_REGS *cpustate) break; } default: - fatalerror("SHARC: sysreg_bitop: invalid bitop %d", bop); + fatalerror("SHARC: sysreg_bitop: invalid bitop %d\n", bop); break; } @@ -2681,7 +2681,7 @@ static void sharcop_modify(SHARC_REGS *cpustate) /* I register bit-reverse */ static void sharcop_bit_reverse(SHARC_REGS *cpustate) { - fatalerror("SHARC: sharcop_bit_reverse unimplemented"); + fatalerror("SHARC: sharcop_bit_reverse unimplemented\n"); } /*****************************************************************************/ @@ -2692,20 +2692,20 @@ static void sharcop_push_pop_stacks(SHARC_REGS *cpustate) { if (cpustate->opcode & U64(0x008000000000)) { - fatalerror("sharcop_push_pop_stacks: push loop not implemented"); + fatalerror("sharcop_push_pop_stacks: push loop not implemented\n"); } if (cpustate->opcode & U64(0x004000000000)) { - fatalerror("sharcop_push_pop_stacks: pop loop not implemented"); + fatalerror("sharcop_push_pop_stacks: pop loop not implemented\n"); } if (cpustate->opcode & U64(0x002000000000)) { - //fatalerror("sharcop_push_pop_stacks: push sts not implemented"); + //fatalerror("sharcop_push_pop_stacks: push sts not implemented\n"); PUSH_STATUS_STACK(cpustate); } if (cpustate->opcode & U64(0x001000000000)) { - //fatalerror("sharcop_push_pop_stacks: pop sts not implemented"); + //fatalerror("sharcop_push_pop_stacks: pop sts not implemented\n"); POP_STATUS_STACK(cpustate); } if (cpustate->opcode & U64(0x000800000000)) @@ -2750,5 +2750,5 @@ static void sharcop_unimplemented(SHARC_REGS *cpustate) char dasm[1000]; CPU_DISASSEMBLE_NAME(sharc)(NULL, dasm, cpustate->pc, NULL, NULL, 0); mame_printf_debug("SHARC: %08X: %s\n", cpustate->pc, dasm); - fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X", (UINT16)(cpustate->opcode >> 32), (UINT32)(cpustate->opcode), cpustate->pc); + fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X\n", (UINT16)(cpustate->opcode >> 32), (UINT32)(cpustate->opcode), cpustate->pc); } diff --git a/src/emu/cpu/tms32010/32010dsm.c b/src/emu/cpu/tms32010/32010dsm.c index 5aea3812eaf..9bc4edcfedf 100644 --- a/src/emu/cpu/tms32010/32010dsm.c +++ b/src/emu/cpu/tms32010/32010dsm.c @@ -199,13 +199,13 @@ static void InitDasm32010(void) case 'w': bit --; break; - default: fatalerror("Invalid instruction encoding '%s %s'", + default: fatalerror("Invalid instruction encoding '%s %s'\n", ops[0],ops[1]); } } if (bit != -1 ) { - fatalerror("not enough bits in encoding '%s %s' %d", + fatalerror("not enough bits in encoding '%s %s' %d\n", ops[0],ops[1],bit); } while (isspace((UINT8)*p)) p++; @@ -289,7 +289,7 @@ CPU_DISASSEMBLE( tms32010 ) case 'w': w <<=1; w |= ((code & (1<> 21); + fatalerror("Unimplemented op @ %06X: %08X (tbl=%03X)\n", m_pc - 1, op, op >> 21); } @@ -855,7 +855,7 @@ void tms3203x_device::mpyf(tmsreg &dst, tmsreg &src1, tmsreg &src2) #if USE_FP void tms3203x_device::norm(tmsreg &dst, tmsreg &src) { - fatalerror("norm not implemented"); + fatalerror("norm not implemented\n"); } #else void tms3203x_device::norm(tmsreg &dst, tmsreg &src) diff --git a/src/emu/cpu/tms32051/32051ops.c b/src/emu/cpu/tms32051/32051ops.c index 6e2f582ac92..fe48f9edaf3 100644 --- a/src/emu/cpu/tms32051/32051ops.c +++ b/src/emu/cpu/tms32051/32051ops.c @@ -269,7 +269,7 @@ INLINE INT32 PREG_PSCALER(tms32051_state *cpustate, INT32 preg) static void op_invalid(tms32051_state *cpustate) { - fatalerror("32051: invalid op at %08X", cpustate->pc-1); + fatalerror("32051: invalid op at %08X\n", cpustate->pc-1); } static void op_group_be(tms32051_state *cpustate); @@ -279,12 +279,12 @@ static void op_group_bf(tms32051_state *cpustate); static void op_abs(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op abs at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op abs at %08X\n", cpustate->pc-1); } static void op_adcb(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op adcb at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op adcb at %08X\n", cpustate->pc-1); } static void op_add_mem(tms32051_state *cpustate) @@ -339,7 +339,7 @@ static void op_add_limm(tms32051_state *cpustate) static void op_add_s16_mem(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op add s16 mem at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op add s16 mem at %08X\n", cpustate->pc-1); } static void op_addb(tms32051_state *cpustate) @@ -351,22 +351,22 @@ static void op_addb(tms32051_state *cpustate) static void op_addc(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op addc at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op addc at %08X\n", cpustate->pc-1); } static void op_adds(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op adds at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op adds at %08X\n", cpustate->pc-1); } static void op_addt(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op addt at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op addt at %08X\n", cpustate->pc-1); } static void op_and_mem(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op and mem at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op and mem at %08X\n", cpustate->pc-1); } static void op_and_limm(tms32051_state *cpustate) @@ -381,12 +381,12 @@ static void op_and_limm(tms32051_state *cpustate) static void op_and_s16_limm(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op and s16 limm at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op and s16 limm at %08X\n", cpustate->pc-1); } static void op_andb(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op andb at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op andb at %08X\n", cpustate->pc-1); } static void op_bsar(tms32051_state *cpustate) @@ -520,7 +520,7 @@ static void op_lacl_mem(tms32051_state *cpustate) static void op_lact(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op lact at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op lact at %08X\n", cpustate->pc-1); } static void op_lamm(tms32051_state *cpustate) @@ -550,7 +550,7 @@ static void op_neg(tms32051_state *cpustate) static void op_norm(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op norm at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op norm at %08X\n", cpustate->pc-1); } static void op_or_mem(tms32051_state *cpustate) @@ -575,7 +575,7 @@ static void op_or_limm(tms32051_state *cpustate) static void op_or_s16_limm(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op or s16 limm at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op or s16 limm at %08X\n", cpustate->pc-1); } static void op_orb(tms32051_state *cpustate) @@ -587,7 +587,7 @@ static void op_orb(tms32051_state *cpustate) static void op_rol(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op rol at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op rol at %08X\n", cpustate->pc-1); } static void op_rolb(tms32051_state *cpustate) @@ -605,12 +605,12 @@ static void op_rolb(tms32051_state *cpustate) static void op_ror(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op ror at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op ror at %08X\n", cpustate->pc-1); } static void op_rorb(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op rorb at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op rorb at %08X\n", cpustate->pc-1); } static void op_sacb(tms32051_state *cpustate) @@ -649,12 +649,12 @@ static void op_samm(tms32051_state *cpustate) static void op_sath(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sath at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sath at %08X\n", cpustate->pc-1); } static void op_satl(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op satl at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op satl at %08X\n", cpustate->pc-1); } static void op_sbb(tms32051_state *cpustate) @@ -666,7 +666,7 @@ static void op_sbb(tms32051_state *cpustate) static void op_sbbb(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sbbb at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sbbb at %08X\n", cpustate->pc-1); } static void op_sfl(tms32051_state *cpustate) @@ -707,7 +707,7 @@ static void op_sfr(tms32051_state *cpustate) static void op_sfrb(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sfrb at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sfrb at %08X\n", cpustate->pc-1); } static void op_sub_mem(tms32051_state *cpustate) @@ -733,7 +733,7 @@ static void op_sub_mem(tms32051_state *cpustate) static void op_sub_s16_mem(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sub s16 mem at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sub s16 mem at %08X\n", cpustate->pc-1); } static void op_sub_simm(tms32051_state *cpustate) @@ -767,22 +767,22 @@ static void op_sub_limm(tms32051_state *cpustate) static void op_subb(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op subb at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op subb at %08X\n", cpustate->pc-1); } static void op_subc(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op subc at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op subc at %08X\n", cpustate->pc-1); } static void op_subs(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op subs at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op subs at %08X\n", cpustate->pc-1); } static void op_subt(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op subt at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op subt at %08X\n", cpustate->pc-1); } static void op_xor_mem(tms32051_state *cpustate) @@ -807,17 +807,17 @@ static void op_xor_limm(tms32051_state *cpustate) static void op_xor_s16_limm(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op xor s16 limm at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op xor s16 limm at %08X\n", cpustate->pc-1); } static void op_xorb(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op xorb at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op xorb at %08X\n", cpustate->pc-1); } static void op_zalr(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op zalr at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op zalr at %08X\n", cpustate->pc-1); } static void op_zap(tms32051_state *cpustate) @@ -911,7 +911,7 @@ static void op_lar_limm(tms32051_state *cpustate) static void op_ldp_mem(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op ldp mem at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op ldp mem at %08X\n", cpustate->pc-1); } static void op_ldp_imm(tms32051_state *cpustate) @@ -995,7 +995,7 @@ static void op_banz(tms32051_state *cpustate) static void op_banzd(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op banzd at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op banzd at %08X\n", cpustate->pc-1); } static void op_bcnd(tms32051_state *cpustate) @@ -1084,7 +1084,7 @@ static void op_calld(tms32051_state *cpustate) static void op_cc(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op cc at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op cc at %08X\n", cpustate->pc-1); } static void op_ccd(tms32051_state *cpustate) @@ -1104,12 +1104,12 @@ static void op_ccd(tms32051_state *cpustate) static void op_intr(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op intr at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op intr at %08X\n", cpustate->pc-1); } static void op_nmi(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op nmi at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op nmi at %08X\n", cpustate->pc-1); } static void op_retc(tms32051_state *cpustate) @@ -1155,12 +1155,12 @@ static void op_rete(tms32051_state *cpustate) static void op_reti(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op reti at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op reti at %08X\n", cpustate->pc-1); } static void op_trap(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op trap at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op trap at %08X\n", cpustate->pc-1); } static void op_xc(tms32051_state *cpustate) @@ -1213,7 +1213,7 @@ static void op_bldd_dlimm(tms32051_state *cpustate) static void op_bldd_sbmar(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op bldd sbmar at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op bldd sbmar at %08X\n", cpustate->pc-1); } static void op_bldd_dbmar(tms32051_state *cpustate) @@ -1250,7 +1250,7 @@ static void op_bldp(tms32051_state *cpustate) static void op_blpd_bmar(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op bpld bmar at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op bpld bmar at %08X\n", cpustate->pc-1); } static void op_blpd_imm(tms32051_state *cpustate) @@ -1273,12 +1273,12 @@ static void op_blpd_imm(tms32051_state *cpustate) static void op_dmov(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op dmov at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op dmov at %08X\n", cpustate->pc-1); } static void op_in(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op in at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op in at %08X\n", cpustate->pc-1); } static void op_lmmr(tms32051_state *cpustate) @@ -1299,7 +1299,7 @@ static void op_lmmr(tms32051_state *cpustate) static void op_out(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op out at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op out at %08X\n", cpustate->pc-1); } static void op_smmr(tms32051_state *cpustate) @@ -1373,7 +1373,7 @@ static void op_apl_imm(tms32051_state *cpustate) static void op_cpl_dbmr(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op cpl dbmr at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op cpl dbmr at %08X\n", cpustate->pc-1); } static void op_cpl_imm(tms32051_state *cpustate) @@ -1418,12 +1418,12 @@ static void op_splk(tms32051_state *cpustate) static void op_xpl_dbmr(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op xpl dbmr at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op xpl dbmr at %08X\n", cpustate->pc-1); } static void op_xpl_imm(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op xpl imm at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op xpl imm at %08X\n", cpustate->pc-1); } static void op_apac(tms32051_state *cpustate) @@ -1436,7 +1436,7 @@ static void op_apac(tms32051_state *cpustate) static void op_lph(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op lph at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op lph at %08X\n", cpustate->pc-1); } static void op_lt(tms32051_state *cpustate) @@ -1474,37 +1474,37 @@ static void op_lta(tms32051_state *cpustate) static void op_ltd(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op ltd at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op ltd at %08X\n", cpustate->pc-1); } static void op_ltp(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op ltp at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op ltp at %08X\n", cpustate->pc-1); } static void op_lts(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op lts at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op lts at %08X\n", cpustate->pc-1); } static void op_mac(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op mac at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op mac at %08X\n", cpustate->pc-1); } static void op_macd(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op macd at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op macd at %08X\n", cpustate->pc-1); } static void op_madd(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op madd at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op madd at %08X\n", cpustate->pc-1); } static void op_mads(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op mads at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op mads at %08X\n", cpustate->pc-1); } static void op_mpy_mem(tms32051_state *cpustate) @@ -1519,37 +1519,37 @@ static void op_mpy_mem(tms32051_state *cpustate) static void op_mpy_simm(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op mpy simm at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op mpy simm at %08X\n", cpustate->pc-1); } static void op_mpy_limm(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op mpy limm at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op mpy limm at %08X\n", cpustate->pc-1); } static void op_mpya(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op mpya at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op mpya at %08X\n", cpustate->pc-1); } static void op_mpys(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op mpys at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op mpys at %08X\n", cpustate->pc-1); } static void op_mpyu(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op mpyu at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op mpyu at %08X\n", cpustate->pc-1); } static void op_pac(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op pac at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op pac at %08X\n", cpustate->pc-1); } static void op_spac(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op spac at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op spac at %08X\n", cpustate->pc-1); } static void op_sph(tms32051_state *cpustate) @@ -1563,7 +1563,7 @@ static void op_sph(tms32051_state *cpustate) static void op_spl(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op spl at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op spl at %08X\n", cpustate->pc-1); } static void op_spm(tms32051_state *cpustate) @@ -1575,17 +1575,17 @@ static void op_spm(tms32051_state *cpustate) static void op_sqra(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sqra at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sqra at %08X\n", cpustate->pc-1); } static void op_sqrs(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sqrs at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sqrs at %08X\n", cpustate->pc-1); } static void op_zpr(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op zpr at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op zpr at %08X\n", cpustate->pc-1); } static void op_bit(tms32051_state *cpustate) @@ -1624,17 +1624,17 @@ static void op_clrc_ext(tms32051_state *cpustate) static void op_clrc_hold(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op clrc hold at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op clrc hold at %08X\n", cpustate->pc-1); } static void op_clrc_tc(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op clrc tc at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op clrc tc at %08X\n", cpustate->pc-1); } static void op_clrc_carry(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op clrc carry at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op clrc carry at %08X\n", cpustate->pc-1); } static void op_clrc_cnf(tms32051_state *cpustate) @@ -1655,27 +1655,27 @@ static void op_clrc_intm(tms32051_state *cpustate) static void op_clrc_xf(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op clrc xf at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op clrc xf at %08X\n", cpustate->pc-1); } static void op_idle(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op idle at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op idle at %08X\n", cpustate->pc-1); } static void op_idle2(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op idle2 at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op idle2 at %08X\n", cpustate->pc-1); } static void op_lst_st0(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op lst st0 at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op lst st0 at %08X\n", cpustate->pc-1); } static void op_lst_st1(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op lst st1 at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op lst st1 at %08X\n", cpustate->pc-1); } static void op_pop(tms32051_state *cpustate) @@ -1687,17 +1687,17 @@ static void op_pop(tms32051_state *cpustate) static void op_popd(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op popd at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op popd at %08X\n", cpustate->pc-1); } static void op_pshd(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op pshd at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op pshd at %08X\n", cpustate->pc-1); } static void op_push(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op push at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op push at %08X\n", cpustate->pc-1); } static void op_rpt_mem(tms32051_state *cpustate) @@ -1741,7 +1741,7 @@ static void op_rptb(tms32051_state *cpustate) static void op_rptz(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op rptz at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op rptz at %08X\n", cpustate->pc-1); } static void op_setc_ov(tms32051_state *cpustate) @@ -1760,22 +1760,22 @@ static void op_setc_ext(tms32051_state *cpustate) static void op_setc_hold(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op setc hold at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op setc hold at %08X\n", cpustate->pc-1); } static void op_setc_tc(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op setc tc at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op setc tc at %08X\n", cpustate->pc-1); } static void op_setc_carry(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op setc carry at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op setc carry at %08X\n", cpustate->pc-1); } static void op_setc_xf(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op setc xf at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op setc xf at %08X\n", cpustate->pc-1); } static void op_setc_cnf(tms32051_state *cpustate) @@ -1796,10 +1796,10 @@ static void op_setc_intm(tms32051_state *cpustate) static void op_sst_st0(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sst st0 at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sst st0 at %08X\n", cpustate->pc-1); } static void op_sst_st1(tms32051_state *cpustate) { - fatalerror("32051: unimplemented op sst st1 at %08X", cpustate->pc-1); + fatalerror("32051: unimplemented op sst st1 at %08X\n", cpustate->pc-1); } diff --git a/src/emu/cpu/tms34010/tms34010.c b/src/emu/cpu/tms34010/tms34010.c index 64cdbf86a3f..5f4eab8e87c 100644 --- a/src/emu/cpu/tms34010/tms34010.c +++ b/src/emu/cpu/tms34010/tms34010.c @@ -997,7 +997,7 @@ static TIMER_CALLBACK( scanline_callback ) /* interlaced timing not supported */ if ((SMART_IOREG(tms, DPYCTL) & 0x4000) == 0) - fatalerror("Interlaced video configured on the TMS34010 (unsupported)"); + fatalerror("Interlaced video configured on the TMS34010 (unsupported)\n"); } } } diff --git a/src/emu/cpu/tms57002/tms57002.c b/src/emu/cpu/tms57002/tms57002.c index c95636b11bd..615169acab5 100644 --- a/src/emu/cpu/tms57002/tms57002.c +++ b/src/emu/cpu/tms57002/tms57002.c @@ -759,7 +759,7 @@ void tms57002_device::execute_run() #undef CINTRP default: - fatalerror("Unhandled opcode in tms57002_execute"); + fatalerror("Unhandled opcode in tms57002_execute\n"); } } inst: diff --git a/src/emu/cpu/uml.c b/src/emu/cpu/uml.c index 7d2ef743a13..ac046c607de 100644 --- a/src/emu/cpu/uml.c +++ b/src/emu/cpu/uml.c @@ -495,7 +495,7 @@ void uml::instruction::simplify() case SIZE_WORD: convert_to_mov_immediate((INT16)m_param[1].immediate()); break; case SIZE_DWORD: convert_to_mov_immediate((INT32)m_param[1].immediate()); break; case SIZE_QWORD: convert_to_mov_immediate((INT64)m_param[1].immediate()); break; - case SIZE_DQWORD: fatalerror("Invalid SEXT target size"); break; + case SIZE_DQWORD: fatalerror("Invalid SEXT target size\n"); break; } break; diff --git a/src/emu/cpu/upd7810/upd7810.c b/src/emu/cpu/upd7810/upd7810.c index 8767697321b..897158a56c0 100644 --- a/src/emu/cpu/upd7810/upd7810.c +++ b/src/emu/cpu/upd7810/upd7810.c @@ -1946,7 +1946,7 @@ static CPU_EXECUTE( upd7810 ) PC += cpustate->op74[OP2].oplen - 2; break; default: - fatalerror("uPD7810 internal error: check cycle counts for main"); + fatalerror("uPD7810 internal error: check cycle counts for main\n"); } } PSW &= ~SK; diff --git a/src/emu/cpu/v60/am1.c b/src/emu/cpu/v60/am1.c index e25f70d1c5d..40548d70835 100644 --- a/src/emu/cpu/v60/am1.c +++ b/src/emu/cpu/v60/am1.c @@ -105,7 +105,7 @@ static UINT32 bam1Autoincrement(v60_state *cpustate) cpustate->reg[cpustate->modval & 0x1F] +=4; break; default: - fatalerror("CPU - BAM1 - 7"); + fatalerror("CPU - BAM1 - 7\n"); break; } return 1; @@ -144,7 +144,7 @@ static UINT32 bam1Autodecrement(v60_state *cpustate) cpustate->reg[cpustate->modval & 0x1F]-=4; break; default: - fatalerror("CPU - BAM1 - 7"); + fatalerror("CPU - BAM1 - 7\n"); break; } cpustate->amout = cpustate->program->read_dword_unaligned(cpustate->reg[cpustate->modval & 0x1F]); @@ -1087,69 +1087,69 @@ static UINT32 am1ImmediateQuick(v60_state *cpustate) static UINT32 am1Error1(v60_state *cpustate) { - fatalerror("CPU - AM1 - 1 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM1 - 1 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam1Error1(v60_state *cpustate) { - fatalerror("CPU - BAM1 - 1 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM1 - 1 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 am1Error2(v60_state *cpustate) { - fatalerror("CPU - AM1 - 2 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM1 - 2 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam1Error2(v60_state *cpustate) { - fatalerror("CPU - BAM1 - 2 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM1 - 2 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #ifdef UNUSED_FUNCTION static UINT32 am1Error3(v60_state *cpustate) { - fatalerror("CPU - AM1 - 3 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM1 - 3 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam1Error3(v60_state *cpustate) { - fatalerror("CPU - BAM1 - 3 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM1 - 3 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #endif static UINT32 am1Error4(v60_state *cpustate) { - fatalerror("CPU - AM1 - 4 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM1 - 4 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam1Error4(v60_state *cpustate) { - fatalerror("CPU - BAM1 - 4 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM1 - 4 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 am1Error5(v60_state *cpustate) { - fatalerror("CPU - AM1 - 5 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM1 - 5 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam1Error5(v60_state *cpustate) { - fatalerror("CPU - BAM1 - 5 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM1 - 5 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam1Error6(v60_state *cpustate) { - fatalerror("CPU - BAM1 - 6 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM1 - 6 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } diff --git a/src/emu/cpu/v60/am2.c b/src/emu/cpu/v60/am2.c index fcfe8034384..3524b559402 100644 --- a/src/emu/cpu/v60/am2.c +++ b/src/emu/cpu/v60/am2.c @@ -94,7 +94,7 @@ static UINT32 bam2Autoincrement(v60_state *cpustate) cpustate->reg[cpustate->modval & 0x1F] +=4; break; default: - fatalerror("CPU - AM2 - 7 (t0 cpustate->PC=%x)", cpustate->PC); + fatalerror("CPU - AM2 - 7 (t0 cpustate->PC=%x)\n", cpustate->PC); break; } @@ -139,7 +139,7 @@ static UINT32 bam2Autodecrement(v60_state *cpustate) cpustate->reg[cpustate->modval & 0x1F]-=4; break; default: - fatalerror("CPU - BAM2 - 7 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM2 - 7 (cpustate->PC=%06x)\n", cpustate->PC); break; } @@ -963,65 +963,65 @@ static UINT32 am2Error1(v60_state *cpustate) static UINT32 am2Error2(v60_state *cpustate) { - fatalerror("CPU - AM2 - 2 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM2 - 2 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #ifdef UNUSED_FUNCTION static UINT32 am2Error3(v60_state *cpustate) { - fatalerror("CPU - AM2 - 3 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM2 - 3 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #endif static UINT32 am2Error4(v60_state *cpustate) { - fatalerror("CPU - AM2 - 4 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM2 - 4 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 am2Error5(v60_state *cpustate) { - fatalerror("CPU - AM2 - 5 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM2 - 5 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam2Error1(v60_state *cpustate) { - fatalerror("CPU - BAM2 - 1 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM2 - 1 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam2Error2(v60_state *cpustate) { - fatalerror("CPU - BAM2 - 2 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM2 - 2 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #ifdef UNUSED_FUNCTION static UINT32 bam2Error3(v60_state *cpustate) { - fatalerror("CPU - BAM2 - 3 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM2 - 3 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #endif static UINT32 bam2Error4(v60_state *cpustate) { - fatalerror("CPU - BAM2 - 4 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM2 - 4 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam2Error5(v60_state *cpustate) { - fatalerror("CPU - BAM2 - 5 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM2 - 5 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 bam2Error6(v60_state *cpustate) { - fatalerror("CPU - BAM2 - 6 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - BAM2 - 6 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } diff --git a/src/emu/cpu/v60/am3.c b/src/emu/cpu/v60/am3.c index ca69f092b62..84c7ec6a958 100644 --- a/src/emu/cpu/v60/am3.c +++ b/src/emu/cpu/v60/am3.c @@ -718,13 +718,13 @@ static UINT32 am3DirectAddressDeferredIndexed(v60_state *cpustate) static UINT32 am3Immediate(v60_state *cpustate) { - fatalerror("CPU - AM3 - IMM (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM3 - IMM (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 am3ImmediateQuick(v60_state *cpustate) { - fatalerror("CPU - AM3 - IMMQ (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM3 - IMMQ (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } @@ -735,33 +735,33 @@ static UINT32 am3ImmediateQuick(v60_state *cpustate) static UINT32 am3Error1(v60_state *cpustate) { - fatalerror("CPU - AM3 - 1 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM3 - 1 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 am3Error2(v60_state *cpustate) { - fatalerror("CPU - AM3 - 2 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM3 - 2 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #ifdef UNUSED_FUNCTION static UINT32 am3Error3(v60_state *cpustate) { - fatalerror("CPU - AM3 - 3 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM3 - 3 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } #endif static UINT32 am3Error4(v60_state *cpustate) { - fatalerror("CPU - AM3 - 4 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM3 - 4 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 am3Error5(v60_state *cpustate) { - fatalerror("CPU - AM3 - 5 (cpustate->PC=%06x)", cpustate->PC); + fatalerror("CPU - AM3 - 5 (cpustate->PC=%06x)\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } diff --git a/src/emu/cpu/v60/op12.c b/src/emu/cpu/v60/op12.c index ef5944cdfda..f8e999cd4e1 100644 --- a/src/emu/cpu/v60/op12.c +++ b/src/emu/cpu/v60/op12.c @@ -456,7 +456,7 @@ static UINT32 opCHLVL(v60_state *cpustate) if (cpustate->op1 > 3) { - fatalerror("Illegal data field on opCHLVL, cpustate->PC=%x", cpustate->PC); + fatalerror("Illegal data field on opCHLVL, cpustate->PC=%x\n", cpustate->PC); } oldPSW = v60_update_psw_for_exception(cpustate, 0, cpustate->op1); @@ -762,7 +762,7 @@ static UINT32 opLDPR(v60_state *cpustate) } else { - fatalerror("Invalid operand on LDPR cpustate->PC=%x", cpustate->PC); + fatalerror("Invalid operand on LDPR cpustate->PC=%x\n", cpustate->PC); } F12END(cpustate); } @@ -2100,7 +2100,7 @@ static UINT32 opSTPR(v60_state *cpustate) cpustate->modwritevalw = cpustate->reg[cpustate->op1 + 36]; else { - fatalerror("Invalid operand on STPR cpustate->PC=%x", cpustate->PC); + fatalerror("Invalid operand on STPR cpustate->PC=%x\n", cpustate->PC); } F12WriteSecondOperand(cpustate, 2); F12END(cpustate); diff --git a/src/emu/cpu/v60/op2.c b/src/emu/cpu/v60/op2.c index d5895775d87..b1c7b58d9c1 100644 --- a/src/emu/cpu/v60/op2.c +++ b/src/emu/cpu/v60/op2.c @@ -255,13 +255,13 @@ static UINT32 opCMPF(v60_state *cpustate) static UINT32 op5FUNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled 5F opcode at %08x", cpustate->PC); + fatalerror("Unhandled 5F opcode at %08x\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 op5CUNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled 5C opcode at %08x", cpustate->PC); + fatalerror("Unhandled 5C opcode at %08x\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } diff --git a/src/emu/cpu/v60/op5.c b/src/emu/cpu/v60/op5.c index 63663ed4c29..8c6808c6285 100644 --- a/src/emu/cpu/v60/op5.c +++ b/src/emu/cpu/v60/op5.c @@ -79,7 +79,7 @@ static UINT32 opTRAPFL(v60_state *cpustate) if ((cpustate->TKCW & 0x1F0) & ((v60ReadPSW(cpustate) & 0x1F00) >> 4)) { // @@@ FPU exception - fatalerror("Hit TRAPFL! cpustate->PC=%x", cpustate->PC); + fatalerror("Hit TRAPFL! cpustate->PC=%x\n", cpustate->PC); } return 1; diff --git a/src/emu/cpu/v60/op7a.c b/src/emu/cpu/v60/op7a.c index e2d062fa14a..08303c3eb8b 100644 --- a/src/emu/cpu/v60/op7a.c +++ b/src/emu/cpu/v60/op7a.c @@ -965,31 +965,31 @@ static UINT32 opCVTDZP(v60_state *cpustate) static UINT32 op58UNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled 58 opcode at cpustate->PC: /%06x", cpustate->PC); + fatalerror("Unhandled 58 opcode at cpustate->PC: /%06x\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 op5AUNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled 5A opcode at cpustate->PC: /%06x", cpustate->PC); + fatalerror("Unhandled 5A opcode at cpustate->PC: /%06x\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 op5BUNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled 5B opcode at cpustate->PC: /%06x", cpustate->PC); + fatalerror("Unhandled 5B opcode at cpustate->PC: /%06x\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 op5DUNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled 5D opcode at cpustate->PC: /%06x", cpustate->PC); + fatalerror("Unhandled 5D opcode at cpustate->PC: /%06x\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } static UINT32 op59UNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled 59 opcode at cpustate->PC: /%06x", cpustate->PC); + fatalerror("Unhandled 59 opcode at cpustate->PC: /%06x\n", cpustate->PC); return 0; /* never reached, fatalerror won't return */ } diff --git a/src/emu/cpu/v60/v60.c b/src/emu/cpu/v60/v60.c index 0d28c2d7cf3..3d1f0638df0 100644 --- a/src/emu/cpu/v60/v60.c +++ b/src/emu/cpu/v60/v60.c @@ -317,7 +317,7 @@ INLINE UINT32 v60_update_psw_for_exception(v60_state *cpustate, int is_interrupt static UINT32 opUNHANDLED(v60_state *cpustate) { - fatalerror("Unhandled OpCode found : %02x at %08x", OpRead16(cpustate, cpustate->PC), cpustate->PC); + fatalerror("Unhandled OpCode found : %02x at %08x\n", OpRead16(cpustate, cpustate->PC), cpustate->PC); return 0; /* never reached, fatalerror won't return */ } diff --git a/src/emu/cpu/v810/v810.c b/src/emu/cpu/v810/v810.c index 8c6c4b7e5f0..e6db6a3f58a 100644 --- a/src/emu/cpu/v810/v810.c +++ b/src/emu/cpu/v810/v810.c @@ -1067,7 +1067,7 @@ static UINT32 opFpoint(v810_state *cpustate,UINT32 op) static UINT32 opBSU(v810_state *cpustate,UINT32 op) { if(!(op & 8)) - fatalerror("V810: unknown BSU opcode %04x",op); + fatalerror("V810: unknown BSU opcode %04x\n",op); { UINT32 srcbit,dstbit,src,dst,size; diff --git a/src/emu/cpu/z80/z80daisy.c b/src/emu/cpu/z80/z80daisy.c index e7d5b20d2cf..9ecc46bcb4e 100644 --- a/src/emu/cpu/z80/z80daisy.c +++ b/src/emu/cpu/z80/z80daisy.c @@ -62,12 +62,12 @@ void z80_daisy_chain::init(device_t *cpudevice, const z80_daisy_config *daisy) // find the device device_t *target = cpudevice->siblingdevice(daisy->devname); if (target == NULL) - fatalerror("Unable to locate device '%s'", daisy->devname); + fatalerror("Unable to locate device '%s'\n", daisy->devname); // make sure it has an interface device_z80daisy_interface *intf; if (!target->interface(intf)) - fatalerror("Device '%s' does not implement the z80daisy interface!", daisy->devname); + fatalerror("Device '%s' does not implement the z80daisy interface!\n", daisy->devname); // append to the end *tailptr = auto_alloc(cpudevice->machine(), daisy_entry(target)); diff --git a/src/osd/sdl/draw13.c b/src/osd/sdl/draw13.c index 4e9ef1afabe..4cf0a6126e0 100644 --- a/src/osd/sdl/draw13.c +++ b/src/osd/sdl/draw13.c @@ -622,7 +622,7 @@ static int draw13_window_create(sdl_window_info *window, int width, int height) if (!sdl->sdl_renderer) { - fatalerror("Error on creating renderer: %s \n", SDL_GetError()); + fatalerror("Error on creating renderer: %s\n", SDL_GetError()); } //SDL_SelectRenderer(window->sdl_window);