mirror of
https://github.com/holub/mame
synced 2025-10-06 09:00:04 +03:00
More clean-ups.
This commit is contained in:
angelosa
parent
179883f35e
commit
9fcb8359e6
@ -257,7 +257,6 @@ public:
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m_dpram(*this, "dpram"),
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m_paletteram(*this, "paletteram"),
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m_spriteram(*this, "spriteram"),
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m_serial_comms_ram(*this, "serialram"),
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m_rozram(*this, "rozram"),
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m_roz_ctrl(*this, "rozctrl"),
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m_c45_road(*this, "c45_road")
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@ -324,10 +323,6 @@ public:
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DECLARE_WRITE16_MEMBER( rozram_word_w );
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DECLARE_READ16_MEMBER( gfx_ctrl_r );
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DECLARE_WRITE16_MEMBER( gfx_ctrl_w );
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DECLARE_READ16_MEMBER( serial_comms_ram_r );
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DECLARE_WRITE16_MEMBER( serial_comms_ram_w );
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DECLARE_READ16_MEMBER( serial_comms_ctrl_r );
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DECLARE_WRITE16_MEMBER( serial_comms_ctrl_w );
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void draw_sprite_init();
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void update_palette();
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@ -343,7 +338,6 @@ public:
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required_shared_ptr<uint8_t> m_dpram; /* 2Kx8 */
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required_shared_ptr<uint16_t> m_paletteram;
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optional_shared_ptr<uint16_t> m_spriteram;
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optional_shared_ptr<uint16_t> m_serial_comms_ram;
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optional_shared_ptr<uint16_t> m_rozram;
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optional_shared_ptr<uint16_t> m_roz_ctrl;
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tilemap_t *m_tilemap_roz;
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@ -1,11 +1,12 @@
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// license:BSD-3-Clause
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// copyright-holders:<author_name>
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// copyright-holders:Angelo Salese
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/***************************************************************************
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Namco C139 - Serial I/F Controller
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TODO:
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- Make this to actually work!
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- Is RAM shared with a specific CPU other than master/slave?
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***************************************************************************/
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@ -33,7 +34,7 @@ ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START( regs_map, 16, namco_c139_device )
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AM_RANGE(0x00, 0x00) AM_READ(status_r) // WRITE clears flags
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// AM_RANGE(0x02, 0x02) // settings?
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AM_RANGE(0x02, 0x02) AM_NOP // settings?
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// AM_RANGE(0x0a, 0x0a) // WRITE tx_w
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// AM_RANGE(0x0c, 0x0c) // READ rx_r
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// AM_RANGE(0x0e, 0x0e) //
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@ -76,23 +76,23 @@ namco_c148_device::namco_c148_device(const machine_config &mconfig, const char *
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// (*) denotes master CPU only
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DEVICE_ADDRESS_MAP_START( map, 16, namco_c148_device )
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ADDRESS_MAP_GLOBAL_MASK(0x3e000)
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AM_RANGE(0x06000, 0x06000) AM_READWRITE8(cpu_irq_level_r,cpu_irq_level_w,0x00ff) // CPUIRQ lv
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AM_RANGE(0x08000, 0x08000) AM_READWRITE8(ex_irq_level_r,ex_irq_level_w,0x00ff) // EXIRQ lv
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AM_RANGE(0x0a000, 0x0a000) AM_READWRITE8(pos_irq_level_r,pos_irq_level_w,0x00ff) // POSIRQ lv
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AM_RANGE(0x0c000, 0x0c000) AM_READWRITE8(sci_irq_level_r,sci_irq_level_w,0x00ff) // SCIRQ lv
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AM_RANGE(0x0e000, 0x0e000) AM_READWRITE8(vblank_irq_level_r,vblank_irq_level_w,0x00ff) // VBlank IRQ lv
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AM_RANGE(0x04000, 0x05fff) AM_READWRITE8(bus_ctrl_r, bus_ctrl_w, 0x00ff)
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AM_RANGE(0x06000, 0x07fff) AM_READWRITE8(cpu_irq_level_r,cpu_irq_level_w,0x00ff) // CPUIRQ lv
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AM_RANGE(0x08000, 0x09fff) AM_READWRITE8(ex_irq_level_r,ex_irq_level_w,0x00ff) // EXIRQ lv
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AM_RANGE(0x0a000, 0x0bfff) AM_READWRITE8(pos_irq_level_r,pos_irq_level_w,0x00ff) // POSIRQ lv
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AM_RANGE(0x0c000, 0x0dfff) AM_READWRITE8(sci_irq_level_r,sci_irq_level_w,0x00ff) // SCIRQ lv
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AM_RANGE(0x0e000, 0x0ffff) AM_READWRITE8(vblank_irq_level_r,vblank_irq_level_w,0x00ff) // VBlank IRQ lv
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AM_RANGE(0x10000, 0x10000) AM_WRITE(cpu_irq_assert_w)
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AM_RANGE(0x16000, 0x16000) AM_READWRITE(cpu_irq_ack_r, cpu_irq_ack_w) // CPUIRQ ack
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AM_RANGE(0x18000, 0x18000) AM_READWRITE(ex_irq_ack_r, ex_irq_ack_w) // EXIRQ ack
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AM_RANGE(0x1a000, 0x1a000) AM_READWRITE(pos_irq_ack_r, pos_irq_ack_w) // POSIRQ ack
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AM_RANGE(0x1c000, 0x1c000) AM_READWRITE(sci_irq_ack_r, sci_irq_ack_w) // SCIRQ ack
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AM_RANGE(0x1e000, 0x1e000) AM_READWRITE(vblank_irq_ack_r, vblank_irq_ack_w) // VBlank IRQ ack
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AM_RANGE(0x20000, 0x20000) AM_READ8(ext_r,0x00ff) // EEPROM ready status (*)
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AM_RANGE(0x22000, 0x22000) AM_WRITE8(ext1_w,0x00ff) // sound CPU reset (*)
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AM_RANGE(0x24000, 0x24000) AM_WRITE8(ext2_w,0x00ff) // slave & i/o reset (*)
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AM_RANGE(0x26000, 0x26000) AM_NOP // watchdog
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AM_RANGE(0x10000, 0x11fff) AM_WRITE(cpu_irq_assert_w)
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AM_RANGE(0x16000, 0x17fff) AM_READWRITE(cpu_irq_ack_r, cpu_irq_ack_w) // CPUIRQ ack
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AM_RANGE(0x18000, 0x19fff) AM_READWRITE(ex_irq_ack_r, ex_irq_ack_w) // EXIRQ ack
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AM_RANGE(0x1a000, 0x1bfff) AM_READWRITE(pos_irq_ack_r, pos_irq_ack_w) // POSIRQ ack
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AM_RANGE(0x1c000, 0x1dfff) AM_READWRITE(sci_irq_ack_r, sci_irq_ack_w) // SCIRQ ack
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AM_RANGE(0x1e000, 0x1ffff) AM_READWRITE(vblank_irq_ack_r, vblank_irq_ack_w) // VBlank IRQ ack
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AM_RANGE(0x20000, 0x21fff) AM_READ8(ext_r,0x00ff) // EEPROM ready status (*)
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AM_RANGE(0x22000, 0x23fff) AM_READNOP AM_WRITE8(ext1_w,0x00ff) // sound CPU reset (*)
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AM_RANGE(0x24000, 0x25fff) AM_WRITE8(ext2_w,0x00ff) // slave & i/o reset (*)
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AM_RANGE(0x26000, 0x27fff) AM_NOP // watchdog
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ADDRESS_MAP_END
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@ -184,6 +184,17 @@ WRITE8_MEMBER( namco_c148_device::ext2_w )
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// TODO: bit 1/2 in Winning Run GPU might be irq enable?
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}
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READ8_MEMBER( namco_c148_device::bus_ctrl_r )
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{
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return m_bus_reg;
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}
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WRITE8_MEMBER( namco_c148_device::bus_ctrl_w )
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{
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m_bus_reg = data & 7;
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}
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WRITE16_MEMBER( namco_c148_device::cpu_irq_assert_w)
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{
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// TODO: Starblade relies on this for showing large polygons, is it the right place?
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@ -91,6 +91,9 @@ public:
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DECLARE_WRITE8_MEMBER( ext_posirq_line_w );
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DECLARE_WRITE16_MEMBER( cpu_irq_assert_w );
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DECLARE_READ8_MEMBER( bus_ctrl_r );
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DECLARE_WRITE8_MEMBER( bus_ctrl_w );
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DECLARE_READ8_MEMBER( ext_r );
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DECLARE_WRITE8_MEMBER( ext1_w );
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DECLARE_WRITE8_MEMBER( ext2_w );
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@ -121,6 +124,7 @@ private:
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}m_irqlevel;
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uint8_t m_posirq_line;
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uint8_t m_bus_reg;
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void flush_irq_acks();
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};
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@ -178,40 +178,6 @@ READ8_MEMBER( namcos2_shared_state::namcos2_68k_eeprom_r )
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return m_eeprom[offset];
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}
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/**************************************************************/
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/* 68000 Shared serial communications processor (CPU5?) */
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/**************************************************************/
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READ16_MEMBER( namcos2_state::serial_comms_ram_r ){
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return m_serial_comms_ram[offset];
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}
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WRITE16_MEMBER( namcos2_state::serial_comms_ram_w ){
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COMBINE_DATA( &m_serial_comms_ram[offset] );
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}
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READ16_MEMBER( namcos2_state::serial_comms_ctrl_r )
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{
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uint16_t retval = m_serial_comms_ctrl[offset];
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switch(offset){
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case 0x00:
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retval |= 0x0004; /* Set READY? status bit */
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break;
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default:
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break;
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}
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return retval;
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}
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WRITE16_MEMBER( namcos2_state::serial_comms_ctrl_w )
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{
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COMBINE_DATA( &m_serial_comms_ctrl[offset] );
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}
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/*************************************************************/
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/* 68000 Shared protection/random key generator */
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/*************************************************************
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