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https://github.com/holub/mame
synced 2025-07-04 17:38:08 +03:00
gigatron: Fix copyrights. (#6211)
* gigatron: Fix copyrights. (nw) * gigatron: make capitalization consistent (nw) * gamedrv: fix a minor spelling mistake (nw) * gigatron: change the ROM names to valid characters * gigatron: cpu device work (nw) * gigatron: cpu work (nw) * gigatron: cpu work (nw) * gigatron: cpu device work (nw) * gigatron: cpu device progress * gigatron: driver + cpu work (nw) * gigatron: some more instructions * gigatron: slight fixes (nw) * gigatron: fixes (nw) * gigatron: whoops (nw) * gigatron: make some fixes thanks hap (nw) * gigatron: temporarily fix error with mem address (nw) * gigatron: do a bit of work (nw)
This commit is contained in:
Sterophonick
ajrhacker
parent
86fb011122
commit
a09672cc2b
@ -1,5 +1,5 @@
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// license:BSD-3-Clause
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// copyright-holders:Sterophonick
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// license:BSD-2-Clause
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// copyright-holders:Sterophonick, Phil Thomas
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/*****************************************************************************
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*
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* Skeleton device for Gigatron CPU Core
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@ -13,7 +13,7 @@
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#include "gigatrondasm.h"
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DEFINE_DEVICE_TYPE(GTRON, gigatron_cpu_device, "gigatron_cpu", "Gigatron CPU Device")
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DEFINE_DEVICE_TYPE(GTRON, gigatron_cpu_device, "gigatron_cpu", "Gigatron")
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/* FLAGS */
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@ -25,9 +25,11 @@ DEFINE_DEVICE_TYPE(GTRON, gigatron_cpu_device, "gigatron_cpu", "Gigatron CPU Dev
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#endif
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#define gigatron_readop(A) m_program->read_dword(A)
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#define gigatron_readop(A) m_program->read_word(A)
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#define gigatron_readmem16(A) m_data->read_dword(A)
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#define gigatron_readmem8(A) m_data->read_byte(A)
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#define gigatron_writemem16(A,B) m_data->write_dword((A),B)
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#define gigatron_writemem8(A,B) m_data->write_byte((A),B)
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/***********************************
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@ -54,7 +56,7 @@ void gigatron_cpu_device::execute_run()
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uint8_t op = (opcode >> 13) & 0x0007;
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uint8_t mode = (opcode >> 10) & 0x0007;
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uint8_t bus = (opcode >> 8) & 0x0003;
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uint8_t d = (opcode >> 0) & 0x00ff;
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uint16_t d = (opcode >> 0) & 0x00ff;
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switch( op)
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{
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@ -76,7 +78,7 @@ void gigatron_cpu_device::execute_run()
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gigatron_illegal();
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break;
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}
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m_icount--;
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} while( m_icount > 0 );
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}
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@ -95,6 +97,8 @@ void gigatron_cpu_device::init()
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m_x = 0;
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m_y = 0;
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m_pc = 0;
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m_npc = (m_pc + 1);
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m_inReg = 0xFF;
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state_add(GTRON_AC, "AC", m_ac);
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state_add(GTRON_X, "X", m_x);
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state_add(GTRON_Y, "Y", m_y);
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@ -102,29 +106,172 @@ void gigatron_cpu_device::init()
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set_icountptr(m_icount);
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}
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void gigatron_cpu_device::branchOp(int op, int mode, int bus, int d)
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void gigatron_cpu_device::branchOp(uint8_t op, uint8_t mode, uint8_t bus, uint8_t d)
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{
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const uint8_t ZERO = 0x80;
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bool c = false;
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uint8_t ac2 = m_ac ^ ZERO;
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uint16_t base = m_pc & 0xff00;
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switch (mode) {
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case 0:
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c = true;
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base = m_y << 8;
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break;
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case 1:
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c = (ac2 > ZERO);
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break;
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case 2:
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c = (ac2 < ZERO);
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break;
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case 3:
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c = (ac2 != ZERO);
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break;
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case 4:
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c = (ac2 == ZERO);
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break;
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case 5:
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c = (ac2 >= ZERO);
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break;
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case 6:
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c = (ac2 <= ZERO);
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break;
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case 7:
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c = true;
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break;
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}
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if (c) {
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uint8_t b = offset(bus, d);
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m_npc = base | b;
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}
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}
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void gigatron_cpu_device::aluOp(int op, int mode, int bus, int d)
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void gigatron_cpu_device::aluOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d)
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{
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int b;
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(void)b;
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uint8_t b = 0;
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//(void)b;
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switch(bus) {
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case 0:
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b = d;
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break;
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case 1:
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b = gigatron_readmem8((uint16_t)(addr(mode, d) & m_ramMask));
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break;
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case 2:
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b = m_ac;
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break;
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case 3:
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b = m_inReg;
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break;
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}
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switch(op) {
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case 1:
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b = (m_ac & b);
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break;
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case 2:
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b = (m_ac | b);
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break;
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case 3:
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b = (m_ac ^ b);
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break;
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case 4:
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b = (m_ac + b);
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break;
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case 5:
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b = (m_ac - b);
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break;
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}
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switch (mode) {
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case 0:
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case 1:
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case 2:
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case 3:
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m_ac = b;
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break;
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case 4:
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m_x = b;
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break;
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case 5:
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m_y = b;
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break;
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case 6:
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case 7:
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uint16_t rising = ~(m_out & b);
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if (rising & 0x40) {
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m_outx = m_ac;
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}
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break;
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}
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}
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void gigatron_cpu_device::storeOp(int op, int mode, int bus, int d)
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uint16_t gigatron_cpu_device::addr(uint8_t mode, uint16_t d)
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{
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switch (mode) {
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case 0:
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case 4:
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case 5:
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case 6:
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return d;
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case 1:
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return m_x;
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case 2:
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return (m_y << 8) | d;
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case 3:
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return (m_y << 8) | m_x;
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case 7:
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uint16_t addr2 = (m_y << 8) | m_x;
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m_x = (m_x + 1) & 0xff;
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return addr2;
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}
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return 0;
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}
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uint8_t gigatron_cpu_device::offset(uint8_t bus, uint16_t d)
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{
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switch (bus) {
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case 0:
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return d;
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case 1:
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return gigatron_readmem8(d);
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case 2:
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return m_ac;
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case 3:
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return m_inReg;
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}
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return 0;
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}
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void gigatron_cpu_device::storeOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d)
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{
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uint8_t b = 0;
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switch (bus) {
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case 0:
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b = d;
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break;
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case 1:
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b = 0;
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logerror("UNDEFINED BEHAVIOR! 0x%04x\n", m_pc);
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break;
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case 2:
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b = m_ac;
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break;
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case 3:
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b = m_inReg;
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break;
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}
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u16 address = addr(mode, d) & m_ramMask;
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gigatron_writemem8(address, b);
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switch (mode) {
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case 4:
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m_x = b;
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break;
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case 5:
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m_y = b;
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break;
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}
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}
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void gigatron_cpu_device::device_reset()
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@ -136,19 +283,7 @@ void gigatron_cpu_device::execute_set_input(int irqline, int state)
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#if 0
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switch(irqline)
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{
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case GTRON_INT_INTRM: // level-sensitive
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m_intrm_pending = ((ASSERT_LINE == state) || (HOLD_LINE == state));
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m_intrm_state = (ASSERT_LINE == state);
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break;
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case GTRON_RESET: // edge-sensitive
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if (CLEAR_LINE != state)
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m_reset_pending = 1;
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m_reset_state = (ASSERT_LINE == state);
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break;
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case GTRON_INT_INTR: // edge-sensitive
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if (CLEAR_LINE != state)
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m_intr_pending = 1;
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m_intr_state = (ASSERT_LINE == state);
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default:
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break;
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}
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#endif
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@ -1,8 +1,8 @@
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// license:BSD-3-Clause
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// copyright-holders:Sterophonick
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// license:BSD-2-Clause
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// copyright-holders:Sterophonick, Phil Thomas
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/*****************************************************************************
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*
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* Skeleton Device for Gigatron CPU Core
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* Skeleton device for Gigatron CPU Core
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*
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*****************************************************************************/
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@ -46,13 +46,20 @@ protected:
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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void branchOp(int op, int mode, int bus, int d);
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void aluOp(int op, int mode, int bus, int d);
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void storeOp(int op, int mode, int bus, int d);
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void branchOp(uint8_t op, uint8_t mode, uint8_t bus, uint8_t d);
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void aluOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d);
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void storeOp(uint8_t op, uint8_t mode, uint8_t bus, uint16_t d);
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uint8_t offset(uint8_t bus, uint16_t d);
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uint16_t addr(uint8_t mode, uint16_t d);
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uint8_t m_ac;
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uint8_t m_x;
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uint8_t m_y;
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uint8_t m_npc;
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uint8_t m_inReg;
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uint16_t m_ramMask;
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uint16_t m_out;
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uint16_t m_outx;
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virtual void init();
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@ -75,7 +75,7 @@ constexpr u64 MACHINE_NO_SOUND_HW = machine_flags::NO_SOUND_HW;
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constexpr u64 MACHINE_MECHANICAL = machine_flags::MECHANICAL;
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constexpr u64 MACHINE_IS_INCOMPLETE = machine_flags::IS_INCOMPLETE;
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// flags taht map to device feature flags
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// flags that map to device feature flags
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constexpr u64 MACHINE_UNEMULATED_PROTECTION = 0x00000001'00000000; // game's protection not fully emulated
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constexpr u64 MACHINE_WRONG_COLORS = 0x00000002'00000000; // colors are totally wrong
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constexpr u64 MACHINE_IMPERFECT_COLORS = 0x00000004'00000000; // colors are not 100% accurate, but close
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@ -38,6 +38,11 @@ private:
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void prog_map(address_map &map);
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void data_map(address_map &map);
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DECLARE_READ8_MEMBER(gigatron_random)
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{
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return machine().rand() & 0xff;
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}
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required_device<cpu_device> m_maincpu;
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};
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@ -54,6 +59,7 @@ void gigatron_state::prog_map(address_map &map)
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void gigatron_state::data_map(address_map &map)
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{
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map(0x4000, 0x7fff).r(FUNC(gigatron_state::gigatron_random));
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}
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void gigatron_state::machine_start()
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@ -75,7 +81,7 @@ void gigatron_state::gigatron(machine_config &config)
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/* video hardware */
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screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
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screen.set_refresh_hz(60);
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screen.set_refresh_hz(59.98);
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screen.set_size(640, 480);
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screen.set_visarea(0, 640-1, 0, 480-1);
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screen.set_screen_update(FUNC(gigatron_state::screen_update));
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@ -88,13 +94,13 @@ void gigatron_state::gigatron(machine_config &config)
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ROM_START( gigatron )
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ROM_REGION( 0x20000, "maincpu", 0 )
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ROM_SYSTEM_BIOS(0, "v4", "Gigatron ROM V4")
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ROMX_LOAD( "romv4.rom", 0x0000, 0x20000, CRC(78995109) SHA1(2395fc48e64099836111f5aeca39ddbf4650ea4e),ROM_BIOS(0))
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ROMX_LOAD( "gigrom4.rom", 0x0000, 0x20000, CRC(78995109) SHA1(2395fc48e64099836111f5aeca39ddbf4650ea4e),ROM_BIOS(0))
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ROM_SYSTEM_BIOS(1, "v3", "Gigatron ROM V3")
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ROMX_LOAD( "romv3.rom", 0x0000, 0x20000, CRC(1536efbe) SHA1(959268069e761a01d620396eedb9abc1ee63c421),ROM_BIOS(1))
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ROMX_LOAD( "gigrom3.rom", 0x0000, 0x20000, CRC(1536efbe) SHA1(959268069e761a01d620396eedb9abc1ee63c421),ROM_BIOS(1))
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ROM_SYSTEM_BIOS(2, "v2", "Gigatron ROM V2")
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ROMX_LOAD( "romv2.rom", 0x0000, 0x20000, CRC(b4a3d936) SHA1(c93f417d589144b912c79f85b9e942d66242c2c3),ROM_BIOS(2))
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ROMX_LOAD( "gigrom2.rom", 0x0000, 0x20000, CRC(b4a3d936) SHA1(c93f417d589144b912c79f85b9e942d66242c2c3),ROM_BIOS(2))
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ROM_SYSTEM_BIOS(3, "v1", "Gigatron ROM V1")
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ROMX_LOAD( "romv1.rom", 0x0000, 0x20000, CRC(8ea5a2af) SHA1(e5758d5cc467c3476bd8f992fd45dfcdf06d0430),ROM_BIOS(3))
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ROMX_LOAD( "gigrom1.rom", 0x0000, 0x20000, CRC(8ea5a2af) SHA1(e5758d5cc467c3476bd8f992fd45dfcdf06d0430),ROM_BIOS(3))
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ROM_END
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COMP(2018, gigatron, 0, 0, gigatron, gigatron, gigatron_state, empty_init, "Marcel van Kervinck", "Gigatron TTL Microcomputer", MACHINE_IS_SKELETON)
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