From a0dfb8c5237ea13236085678d3364655b62cf4dd Mon Sep 17 00:00:00 2001 From: "therealmogminer@gmail.com" Date: Wed, 1 Jul 2015 21:28:40 +0200 Subject: [PATCH] rsp simd: Clamp DMEM fetches to 4kb, nw --- src/emu/cpu/rsp/rspcp2.h | 2 +- src/emu/cpu/rsp/vldst.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/emu/cpu/rsp/rspcp2.h b/src/emu/cpu/rsp/rspcp2.h index 77bbd468233..6f14d110a68 100644 --- a/src/emu/cpu/rsp/rspcp2.h +++ b/src/emu/cpu/rsp/rspcp2.h @@ -251,7 +251,7 @@ protected: rsp_vec_t vec_load_and_shuffle_operand(const UINT16* src, UINT32 element); static inline UINT32 sign_extend_6(INT32 i) { - return (i << (32 - 7)) >> (32 - 7); + return ((i << (32 - 7)) >> (32 - 7)) & 0xfff; } static inline rsp_vec_t vec_load_unshuffled_operand(const UINT16* src) { diff --git a/src/emu/cpu/rsp/vldst.h b/src/emu/cpu/rsp/vldst.h index eaef0ccb512..80e95dd57fc 100644 --- a/src/emu/cpu/rsp/vldst.h +++ b/src/emu/cpu/rsp/vldst.h @@ -4,6 +4,8 @@ // LBV, LDV, LLV, LSV, SBV, SDV, SLV, SSV inline void vec_lbdlsv_sbdlsv(UINT32 iw, UINT32 rs) { + rs &= 0xfff; + const UINT32 shift_and_idx = (iw >> 11) & 0x3; rsp_vec_t dqm = _mm_loadl_epi64((rsp_vec_t *) (m_vec_helpers.bdls_lut[shift_and_idx])); @@ -31,6 +33,8 @@ inline void vec_lfhpuv_sfhpuv(UINT32 iw, UINT32 rs) RSP_MEM_REQUEST_FOURTH }; + rs &= 0xfff; + const UINT32 addr = rs + (sign_extend_6(iw) << 3); const UINT32 element = (iw >> 21) & 0xf; UINT16* regp = m_v[(iw >> 16) & 0x1f].s; @@ -49,6 +53,8 @@ inline void vec_lfhpuv_sfhpuv(UINT32 iw, UINT32 rs) // LQV, LRV, SQV, SRV inline void vec_lqrv_sqrv(UINT32 iw, UINT32 rs) { + rs &= 0xfff; + const UINT32 addr = rs + (sign_extend_6(iw) << 4); const UINT32 element = (iw >> 21) & 0xf; UINT16* regp = m_v[(iw >> 16) & 0x1f].s;