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Fix for mid tx reset of scc channel

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This commit is contained in:
Joakim Larsson Edstrom 2016-07-05 15:14:26 +02:00
parent b3adfa8b35
commit a1177eef82
1 changed files with 1 additions and 0 deletions
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src/devices/machine/z80scc.cpp
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@ -1948,6 +1948,7 @@ void z80scc_channel::control_write(UINT8 data)
update_serial();
transmit_register_reset();
update_rts();
m_rr0 |= RR0_TX_BUFFER_EMPTY;
break;
case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break;
case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break;