diff --git a/hash/casio_rompack.xml b/hash/casio_rompack.xml index cd40772b03a..1a778743f5e 100644 --- a/hash/casio_rompack.xml +++ b/hash/casio_rompack.xml @@ -420,7 +420,7 @@ license:CC0-1.0 3 I Left My Heart In San Francisco 4 Memories Of You The earlier (1984) edition of this pack is labelled "Jazz Standards" while the later (1986) edition is "Great Standards." - There are apparently no other differences between the editions. + There are apparently no other differences between the editions. --> Great Standards (RO-355) diff --git a/hash/ibm5170_cdrom.xml b/hash/ibm5170_cdrom.xml index 3ddefe96168..17a8761de1e 100644 --- a/hash/ibm5170_cdrom.xml +++ b/hash/ibm5170_cdrom.xml @@ -3021,7 +3021,7 @@ Terminal Velocity: incompatible with Windows 95 (verify), has unsupported option Dune II - Battle for Arrakis (Netherlands) 1995 Hit Squad - + @@ -3041,7 +3041,7 @@ Terminal Velocity: incompatible with Windows 95 (verify), has unsupported option Dune II - Battle for Arrakis (Germany, PC Games Collection 2 release) 2001 Electronic Arts / Infogrames - + @@ -3060,7 +3060,7 @@ Terminal Velocity: incompatible with Windows 95 (verify), has unsupported option Dune II - The Building of a Dynasty (USA, Gold Medal 12 CD Pack) 1995 Virgin Games - + diff --git a/hash/spectrum_cass.xml b/hash/spectrum_cass.xml index 574c1781706..3317068ff04 100644 --- a/hash/spectrum_cass.xml +++ b/hash/spectrum_cass.xml @@ -23910,7 +23910,7 @@ Side B: Laser Shoot (original release) - + @@ -139449,7 +139449,7 @@ Nothing happens after loading the cassette Teodoro no Sabe Volar (Russian, TAP tape image) 2010 - Retroworks + Retroworks diff --git a/hash/zx81_cass.xml b/hash/zx81_cass.xml index 3dbae8af2fe..21f71e6c2be 100644 --- a/hash/zx81_cass.xml +++ b/hash/zx81_cass.xml @@ -245,15 +245,15 @@ Known dumps not yet added (as of 2023-06-14): 8 Programmes by GM4IHJ 198? diff --git a/src/devices/cpu/avr8/avr8.cpp b/src/devices/cpu/avr8/avr8.cpp index 4745e63c95a..f949ed0ef03 100644 --- a/src/devices/cpu/avr8/avr8.cpp +++ b/src/devices/cpu/avr8/avr8.cpp @@ -201,328 +201,328 @@ enum #define SPREG ((m_r[SPH] << 8) | m_r[SPL]) // I/O Defines -#define TCCR0B_CS_SHIFT 0 -#define TCCR0B_CS_MASK 0x07 -#define TCCR0B_WGM0_2_SHIFT 3 -#define TCCR0B_WGM0_2_MASK 0x08 -#define TCCR0B_FOC0B_SHIFT 6 -#define TCCR0B_FOC0B_MASK 0x40 -#define TCCR0B_FOC0A_SHIFT 7 -#define TCCR0B_FOC0A_MASK 0x80 -#define TIMER0_CLOCK_SELECT (m_r[TCCR0B] & TCCR0B_CS_MASK) +#define TCCR0B_CS_SHIFT 0 +#define TCCR0B_CS_MASK 0x07 +#define TCCR0B_WGM0_2_SHIFT 3 +#define TCCR0B_WGM0_2_MASK 0x08 +#define TCCR0B_FOC0B_SHIFT 6 +#define TCCR0B_FOC0B_MASK 0x40 +#define TCCR0B_FOC0A_SHIFT 7 +#define TCCR0B_FOC0A_MASK 0x80 +#define TIMER0_CLOCK_SELECT (m_r[TCCR0B] & TCCR0B_CS_MASK) -#define TCCR0A_WGM0_10_SHIFT 0 -#define TCCR0A_WGM0_10_MASK 0x03 -#define TCCR0A_COM0B_SHIFT 4 -#define TCCR0A_COM0B_MASK 0x30 -#define TCCR0A_COM0A_SHIFT 6 -#define TCCR0A_COM0A_MASK 0xc0 -#define TCCR0A_COM0A ((m_r[TCCR0A] & TCCR0A_COM0A_MASK) >> TCCR0A_COM0A_SHIFT) -#define TCCR0A_COM0B ((m_r[TCCR0A] & TCCR0A_COM0B_MASK) >> TCCR0A_COM0B_SHIFT) -#define TCCR0A_WGM0_10 (m_r[TCCR0A] & TCCR0A_WGM0_10_MASK) +#define TCCR0A_WGM0_10_SHIFT 0 +#define TCCR0A_WGM0_10_MASK 0x03 +#define TCCR0A_COM0B_SHIFT 4 +#define TCCR0A_COM0B_MASK 0x30 +#define TCCR0A_COM0A_SHIFT 6 +#define TCCR0A_COM0A_MASK 0xc0 +#define TCCR0A_COM0A ((m_r[TCCR0A] & TCCR0A_COM0A_MASK) >> TCCR0A_COM0A_SHIFT) +#define TCCR0A_COM0B ((m_r[TCCR0A] & TCCR0A_COM0B_MASK) >> TCCR0A_COM0B_SHIFT) +#define TCCR0A_WGM0_10 (m_r[TCCR0A] & TCCR0A_WGM0_10_MASK) -#define TIMSK0_TOIE0_BIT 0 -#define TIMSK0_OCIE0A_BIT 1 -#define TIMSK0_OCIE0B_BIT 2 -#define TIMSK0_TOIE0_MASK (1 << TIMSK0_TOIE0_BIT) -#define TIMSK0_OCIE0A_MASK (1 << TIMSK0_OCIE0A_BIT) -#define TIMSK0_OCIE0B_MASK (1 << TIMSK0_OCIE0B_BIT) -#define TIMSK0_TOIE0 (BIT(m_r[TIMSK0], TIMSK0_TOIE0_BIT)) -#define TIMSK0_OCIE0A (BIT(m_r[TIMSK0], TIMSK0_OCIE0A_BIT)) -#define TIMSK0_OCIE0B (BIT(m_r[TIMSK0], TIMSK0_OCIE0B_BIT)) +#define TIMSK0_TOIE0_BIT 0 +#define TIMSK0_OCIE0A_BIT 1 +#define TIMSK0_OCIE0B_BIT 2 +#define TIMSK0_TOIE0_MASK (1 << TIMSK0_TOIE0_BIT) +#define TIMSK0_OCIE0A_MASK (1 << TIMSK0_OCIE0A_BIT) +#define TIMSK0_OCIE0B_MASK (1 << TIMSK0_OCIE0B_BIT) +#define TIMSK0_TOIE0 (BIT(m_r[TIMSK0], TIMSK0_TOIE0_BIT)) +#define TIMSK0_OCIE0A (BIT(m_r[TIMSK0], TIMSK0_OCIE0A_BIT)) +#define TIMSK0_OCIE0B (BIT(m_r[TIMSK0], TIMSK0_OCIE0B_BIT)) -#define TIFR0_TOV0_SHIFT 0 -#define TIFR0_TOV0_MASK 0x01 -#define TIFR0_OCF0A_SHIFT 1 -#define TIFR0_OCF0A_MASK 0x02 -#define TIFR0_OCF0B_SHIFT 2 -#define TIFR0_OCF0B_MASK 0x04 -#define TIFR0_MASK (TIFR0_TOV0_MASK | TIFR0_OCF0B_MASK | TIFR0_OCF0A_MASK) +#define TIFR0_TOV0_SHIFT 0 +#define TIFR0_TOV0_MASK 0x01 +#define TIFR0_OCF0A_SHIFT 1 +#define TIFR0_OCF0A_MASK 0x02 +#define TIFR0_OCF0B_SHIFT 2 +#define TIFR0_OCF0B_MASK 0x04 +#define TIFR0_MASK (TIFR0_TOV0_MASK | TIFR0_OCF0B_MASK | TIFR0_OCF0A_MASK) -#define TCCR1B_CS_SHIFT 0 -#define TCCR1B_CS_MASK 0x07 -#define TCCR1B_WGM1_32_SHIFT 3 -#define TCCR1B_WGM1_32_MASK 0x18 -#define TCCR1B_ICES1_SHIFT 6 -#define TCCR1B_ICES1_MASK 0x40 -#define TCCR1B_ICNC1_SHIFT 7 -#define TCCR1B_ICNC1_MASK 0x80 -#define TIMER1_CLOCK_SELECT (m_r[TCCR1B] & TCCR1B_CS_MASK) +#define TCCR1B_CS_SHIFT 0 +#define TCCR1B_CS_MASK 0x07 +#define TCCR1B_WGM1_32_SHIFT 3 +#define TCCR1B_WGM1_32_MASK 0x18 +#define TCCR1B_ICES1_SHIFT 6 +#define TCCR1B_ICES1_MASK 0x40 +#define TCCR1B_ICNC1_SHIFT 7 +#define TCCR1B_ICNC1_MASK 0x80 +#define TIMER1_CLOCK_SELECT (m_r[TCCR1B] & TCCR1B_CS_MASK) -#define TCCR1A_WGM1_10_SHIFT 0 -#define TCCR1A_WGM1_10_MASK 0x03 -#define TCCR1A_COM1AB_SHIFT 4 -#define TCCR1A_COM1AB_MASK 0xf0 -#define TCCR1A_COM1B_SHIFT 4 -#define TCCR1A_COM1B_MASK 0x30 -#define TCCR1A_COM1A_SHIFT 6 -#define TCCR1A_COM1A_MASK 0xc0 -#define TCCR1A_COM1A ((m_r[TCCR1A] & TCCR1A_COM1A_MASK) >> TCCR1A_COM1A_SHIFT) -#define TCCR1A_COM1B ((m_r[TCCR1A] & TCCR1A_COM1B_MASK) >> TCCR1A_COM1B_SHIFT) -#define TCCR1A_WGM1_10 (m_r[TCCR1A] & TCCR1A_WGM1_10_MASK) +#define TCCR1A_WGM1_10_SHIFT 0 +#define TCCR1A_WGM1_10_MASK 0x03 +#define TCCR1A_COM1AB_SHIFT 4 +#define TCCR1A_COM1AB_MASK 0xf0 +#define TCCR1A_COM1B_SHIFT 4 +#define TCCR1A_COM1B_MASK 0x30 +#define TCCR1A_COM1A_SHIFT 6 +#define TCCR1A_COM1A_MASK 0xc0 +#define TCCR1A_COM1A ((m_r[TCCR1A] & TCCR1A_COM1A_MASK) >> TCCR1A_COM1A_SHIFT) +#define TCCR1A_COM1B ((m_r[TCCR1A] & TCCR1A_COM1B_MASK) >> TCCR1A_COM1B_SHIFT) +#define TCCR1A_WGM1_10 (m_r[TCCR1A] & TCCR1A_WGM1_10_MASK) -#define TIMSK1_TOIE1_BIT 0 -#define TIMSK1_OCIE1A_BIT 1 -#define TIMSK1_OCIE1B_BIT 2 -#define TIMSK1_ICIE1_BIT 5 -#define TIMSK1_TOIE1_MASK (1 << TIMSK1_TOIE1_BIT) -#define TIMSK1_OCIE1A_MASK (1 << TIMSK1_OCIE1A_BIT) -#define TIMSK1_OCIE1B_MASK (1 << TIMSK1_OCIE1B_BIT) -#define TIMSK1_ICIE1_MASK (1 << TIMSK1_ICIE1_BIT) -#define TIMSK1_TOIE1 (BIT(m_r[TIMSK1], TIMSK1_TOIE1_BIT)) -#define TIMSK1_OCIE1A (BIT(m_r[TIMSK1], TIMSK1_OCIE1A_BIT)) -#define TIMSK1_OCIE1B (BIT(m_r[TIMSK1], TIMSK1_OCIE1B_BIT)) -#define TIMSK1_ICIE1 (BIT(m_r[TIMSK1], TIMSK1_ICIE1_BIT)) +#define TIMSK1_TOIE1_BIT 0 +#define TIMSK1_OCIE1A_BIT 1 +#define TIMSK1_OCIE1B_BIT 2 +#define TIMSK1_ICIE1_BIT 5 +#define TIMSK1_TOIE1_MASK (1 << TIMSK1_TOIE1_BIT) +#define TIMSK1_OCIE1A_MASK (1 << TIMSK1_OCIE1A_BIT) +#define TIMSK1_OCIE1B_MASK (1 << TIMSK1_OCIE1B_BIT) +#define TIMSK1_ICIE1_MASK (1 << TIMSK1_ICIE1_BIT) +#define TIMSK1_TOIE1 (BIT(m_r[TIMSK1], TIMSK1_TOIE1_BIT)) +#define TIMSK1_OCIE1A (BIT(m_r[TIMSK1], TIMSK1_OCIE1A_BIT)) +#define TIMSK1_OCIE1B (BIT(m_r[TIMSK1], TIMSK1_OCIE1B_BIT)) +#define TIMSK1_ICIE1 (BIT(m_r[TIMSK1], TIMSK1_ICIE1_BIT)) -#define TIFR1_TOV1_SHIFT 0 -#define TIFR1_TOV1_MASK 0x01 -#define TIFR1_OCF1A_SHIFT 1 -#define TIFR1_OCF1A_MASK 0x02 -#define TIFR1_OCF1B_SHIFT 2 -#define TIFR1_OCF1B_MASK 0x04 -#define TIFR1_ICF1_SHIFT 5 -#define TIFR1_ICF1_MASK 0x20 -#define TIFR1_MASK (TIFR1_ICF1_MASK | TIFR1_TOV1_MASK | TIFR1_OCF1B_MASK | TIFR1_OCF1A_MASK) +#define TIFR1_TOV1_SHIFT 0 +#define TIFR1_TOV1_MASK 0x01 +#define TIFR1_OCF1A_SHIFT 1 +#define TIFR1_OCF1A_MASK 0x02 +#define TIFR1_OCF1B_SHIFT 2 +#define TIFR1_OCF1B_MASK 0x04 +#define TIFR1_ICF1_SHIFT 5 +#define TIFR1_ICF1_MASK 0x20 +#define TIFR1_MASK (TIFR1_ICF1_MASK | TIFR1_TOV1_MASK | TIFR1_OCF1B_MASK | TIFR1_OCF1A_MASK) -#define TCCR2B_CS_SHIFT 0 -#define TCCR2B_CS_MASK 0x07 -#define TCCR2B_WGM2_2_SHIFT 3 -#define TCCR2B_WGM2_2_MASK 0x08 -#define TCCR2B_FOC2B_SHIFT 6 -#define TCCR2B_FOC2B_MASK 0x40 -#define TCCR2B_FOC2A_SHIFT 7 -#define TCCR2B_FOC2A_MASK 0x80 -#define TIMER2_CLOCK_SELECT (m_r[TCCR2B] & TCCR2B_CS_MASK) +#define TCCR2B_CS_SHIFT 0 +#define TCCR2B_CS_MASK 0x07 +#define TCCR2B_WGM2_2_SHIFT 3 +#define TCCR2B_WGM2_2_MASK 0x08 +#define TCCR2B_FOC2B_SHIFT 6 +#define TCCR2B_FOC2B_MASK 0x40 +#define TCCR2B_FOC2A_SHIFT 7 +#define TCCR2B_FOC2A_MASK 0x80 +#define TIMER2_CLOCK_SELECT (m_r[TCCR2B] & TCCR2B_CS_MASK) -#define TCCR2A_WGM2_10_SHIFT 0 -#define TCCR2A_WGM2_10_MASK 0x03 -#define TCCR2A_COM2B_SHIFT 4 -#define TCCR2A_COM2B_MASK 0x30 -#define TCCR2A_COM2A_SHIFT 6 -#define TCCR2A_COM2A_MASK 0xc0 -#define TCCR2A_COM2A ((m_r[TCCR2A] & TCCR2A_COM2A_MASK) >> TCCR2A_COM2A_SHIFT) -#define TCCR2A_COM2B ((m_r[TCCR2A] & TCCR2A_COM2B_MASK) >> TCCR2A_COM2B_SHIFT) -#define TCCR2A_WGM2_10 (m_r[TCCR2A] & TCCR2A_WGM2_10_MASK) +#define TCCR2A_WGM2_10_SHIFT 0 +#define TCCR2A_WGM2_10_MASK 0x03 +#define TCCR2A_COM2B_SHIFT 4 +#define TCCR2A_COM2B_MASK 0x30 +#define TCCR2A_COM2A_SHIFT 6 +#define TCCR2A_COM2A_MASK 0xc0 +#define TCCR2A_COM2A ((m_r[TCCR2A] & TCCR2A_COM2A_MASK) >> TCCR2A_COM2A_SHIFT) +#define TCCR2A_COM2B ((m_r[TCCR2A] & TCCR2A_COM2B_MASK) >> TCCR2A_COM2B_SHIFT) +#define TCCR2A_WGM2_10 (m_r[TCCR2A] & TCCR2A_WGM2_10_MASK) -#define TIMSK2_TOIE2_BIT 0 -#define TIMSK2_OCIE2A_BIT 1 -#define TIMSK2_OCIE2B_BIT 2 -#define TIMSK2_TOIE2_MASK (1 << TIMSK2_TOIE2_BIT) -#define TIMSK2_OCIE2A_MASK (1 << TIMSK2_OCIE2A_BIT) -#define TIMSK2_OCIE2B_MASK (1 << TIMSK2_OCIE2B_BIT) -#define TIMSK2_TOIE2 (BIT(m_r[TIMSK2], TIMSK2_TOIE2_BIT)) -#define TIMSK2_OCIE2A (BIT(m_r[TIMSK2], TIMSK2_OCIE2A_BIT)) -#define TIMSK2_OCIE2B (BIT(m_r[TIMSK2], TIMSK2_OCIE2B_BIT)) +#define TIMSK2_TOIE2_BIT 0 +#define TIMSK2_OCIE2A_BIT 1 +#define TIMSK2_OCIE2B_BIT 2 +#define TIMSK2_TOIE2_MASK (1 << TIMSK2_TOIE2_BIT) +#define TIMSK2_OCIE2A_MASK (1 << TIMSK2_OCIE2A_BIT) +#define TIMSK2_OCIE2B_MASK (1 << TIMSK2_OCIE2B_BIT) +#define TIMSK2_TOIE2 (BIT(m_r[TIMSK2], TIMSK2_TOIE2_BIT)) +#define TIMSK2_OCIE2A (BIT(m_r[TIMSK2], TIMSK2_OCIE2A_BIT)) +#define TIMSK2_OCIE2B (BIT(m_r[TIMSK2], TIMSK2_OCIE2B_BIT)) -#define TIFR2_TOV2_SHIFT 0 -#define TIFR2_TOV2_MASK 0x01 -#define TIFR2_OCF2A_SHIFT 1 -#define TIFR2_OCF2A_MASK 0x02 -#define TIFR2_OCF2B_SHIFT 2 -#define TIFR2_OCF2B_MASK 0x04 -#define TIFR2_MASK (TIFR2_TOV2_MASK | TIFR2_OCF2B_MASK | TIFR2_OCF2A_MASK) +#define TIFR2_TOV2_SHIFT 0 +#define TIFR2_TOV2_MASK 0x01 +#define TIFR2_OCF2A_SHIFT 1 +#define TIFR2_OCF2A_MASK 0x02 +#define TIFR2_OCF2B_SHIFT 2 +#define TIFR2_OCF2B_MASK 0x04 +#define TIFR2_MASK (TIFR2_TOV2_MASK | TIFR2_OCF2B_MASK | TIFR2_OCF2A_MASK) -#define TIMSK3_TOIE3_BIT 0 -#define TIMSK3_OCIE3A_BIT 1 -#define TIMSK3_OCIE3B_BIT 2 -#define TIMSK3_OCIE3C_BIT 3 -#define TIMSK3_TOIE3 (BIT(m_r[TIMSK3], TIMSK3_TOIE3_BIT)) -#define TIMSK3_OCIE3A (BIT(m_r[TIMSK3], TIMSK3_OCIE3A_BIT)) -#define TIMSK3_OCIE3B (BIT(m_r[TIMSK3], TIMSK3_OCIE3B_BIT)) -#define TIMSK3_OCIE3C (BIT(m_r[TIMSK3], TIMSK3_OCIE3C_BIT)) +#define TIMSK3_TOIE3_BIT 0 +#define TIMSK3_OCIE3A_BIT 1 +#define TIMSK3_OCIE3B_BIT 2 +#define TIMSK3_OCIE3C_BIT 3 +#define TIMSK3_TOIE3 (BIT(m_r[TIMSK3], TIMSK3_TOIE3_BIT)) +#define TIMSK3_OCIE3A (BIT(m_r[TIMSK3], TIMSK3_OCIE3A_BIT)) +#define TIMSK3_OCIE3B (BIT(m_r[TIMSK3], TIMSK3_OCIE3B_BIT)) +#define TIMSK3_OCIE3C (BIT(m_r[TIMSK3], TIMSK3_OCIE3C_BIT)) -#define TCCR4B_CS_SHIFT 0 -#define TCCR4B_CS_MASK 0x07 -#define TCCR4B_WGM4_32_SHIFT 3 -#define TCCR4B_WGM4_32_MASK 0x18 -#define TCCR4B_FOC4C_SHIFT 5 -#define TCCR4B_FOC4C_MASK 0x20 -#define TCCR4B_FOC4B_SHIFT 6 -#define TCCR4B_FOC4B_MASK 0x40 -#define TCCR4B_FOC4A_SHIFT 7 -#define TCCR4B_FOC4A_MASK 0x80 -#define TIMER4_CLOCK_SELECT ((m_r[TCCR4B] & TCCR4B_CS_MASK) >> TCCR4B_CS_SHIFT) +#define TCCR4B_CS_SHIFT 0 +#define TCCR4B_CS_MASK 0x07 +#define TCCR4B_WGM4_32_SHIFT 3 +#define TCCR4B_WGM4_32_MASK 0x18 +#define TCCR4B_FOC4C_SHIFT 5 +#define TCCR4B_FOC4C_MASK 0x20 +#define TCCR4B_FOC4B_SHIFT 6 +#define TCCR4B_FOC4B_MASK 0x40 +#define TCCR4B_FOC4A_SHIFT 7 +#define TCCR4B_FOC4A_MASK 0x80 +#define TIMER4_CLOCK_SELECT ((m_r[TCCR4B] & TCCR4B_CS_MASK) >> TCCR4B_CS_SHIFT) -#define TCCR4A_WGM4_10_SHIFT 0 -#define TCCR4A_WGM4_10_MASK 0x03 -#define TCCR4A_COM4C_SHIFT 2 -#define TCCR4A_COM4C_MASK 0x0c -#define TCCR4A_COM4B_SHIFT 4 -#define TCCR4A_COM4B_MASK 0x30 -#define TCCR4A_COM4A_SHIFT 6 -#define TCCR4A_COM4A_MASK 0xc0 -#define TCCR4A_COM4A ((m_r[TCCR4A] & TCCR4A_COM4A_MASK) >> TCCR4A_COM4A_SHIFT) -#define TCCR4A_COM4B ((m_r[TCCR4A] & TCCR4A_COM4B_MASK) >> TCCR4A_COM4B_SHIFT) -#define TCCR4A_COM4C ((m_r[TCCR4A] & TCCR4A_COM4C_MASK) >> TCCR4A_COM4C_SHIFT) -#define TCCR4A_WGM2_10 (m_r[TCCR4A] & TCCR4A_WGM2_10_MASK) +#define TCCR4A_WGM4_10_SHIFT 0 +#define TCCR4A_WGM4_10_MASK 0x03 +#define TCCR4A_COM4C_SHIFT 2 +#define TCCR4A_COM4C_MASK 0x0c +#define TCCR4A_COM4B_SHIFT 4 +#define TCCR4A_COM4B_MASK 0x30 +#define TCCR4A_COM4A_SHIFT 6 +#define TCCR4A_COM4A_MASK 0xc0 +#define TCCR4A_COM4A ((m_r[TCCR4A] & TCCR4A_COM4A_MASK) >> TCCR4A_COM4A_SHIFT) +#define TCCR4A_COM4B ((m_r[TCCR4A] & TCCR4A_COM4B_MASK) >> TCCR4A_COM4B_SHIFT) +#define TCCR4A_COM4C ((m_r[TCCR4A] & TCCR4A_COM4C_MASK) >> TCCR4A_COM4C_SHIFT) +#define TCCR4A_WGM2_10 (m_r[TCCR4A] & TCCR4A_WGM2_10_MASK) -#define WGM4_32 ((m_r[TCCR4B] & TCCR4B_WGM4_32_MASK) >> TCCR4B_WGM4_32_SHIFT) -#define WGM4_10 ((m_r[TCCR4A] & TCCR4A_WGM4_10_MASK) >> TCCR4A_WGM4_10_SHIFT) -#define WGM4 ((WGM4_32 << 2) | WGM4_10) +#define WGM4_32 ((m_r[TCCR4B] & TCCR4B_WGM4_32_MASK) >> TCCR4B_WGM4_32_SHIFT) +#define WGM4_10 ((m_r[TCCR4A] & TCCR4A_WGM4_10_MASK) >> TCCR4A_WGM4_10_SHIFT) +#define WGM4 ((WGM4_32 << 2) | WGM4_10) -#define TIMSK4_TOIE4_BIT 0 -#define TIMSK4_OCIE4A_BIT 1 -#define TIMSK4_OCIE4B_BIT 2 -#define TIMSK4_TOIE4 (BIT(m_r[TIMSK4], TIMSK4_TOIE4_BIT)) -#define TIMSK4_OCIE4A (BIT(m_r[TIMSK4], TIMSK4_OCIE4A_BIT)) -#define TIMSK4_OCIE4B (BIT(m_r[TIMSK4], TIMSK4_OCIE4B_BIT)) +#define TIMSK4_TOIE4_BIT 0 +#define TIMSK4_OCIE4A_BIT 1 +#define TIMSK4_OCIE4B_BIT 2 +#define TIMSK4_TOIE4 (BIT(m_r[TIMSK4], TIMSK4_TOIE4_BIT)) +#define TIMSK4_OCIE4A (BIT(m_r[TIMSK4], TIMSK4_OCIE4A_BIT)) +#define TIMSK4_OCIE4B (BIT(m_r[TIMSK4], TIMSK4_OCIE4B_BIT)) -#define TIFR4_TOV4_SHIFT 0 -#define TIFR4_TOV4_MASK 0x01 -#define TIFR4_OCF4A_SHIFT 1 -#define TIFR4_OCF4A_MASK 0x02 -#define TIFR4_OCF4B_SHIFT 2 -#define TIFR4_OCF4B_MASK 0x04 -#define TIFR4_MASK (TIFR4_TOV4_MASK | TIFR4_OCF4B_MASK | TIFR4_OCF4A_MASK) +#define TIFR4_TOV4_SHIFT 0 +#define TIFR4_TOV4_MASK 0x01 +#define TIFR4_OCF4A_SHIFT 1 +#define TIFR4_OCF4A_MASK 0x02 +#define TIFR4_OCF4B_SHIFT 2 +#define TIFR4_OCF4B_MASK 0x04 +#define TIFR4_MASK (TIFR4_TOV4_MASK | TIFR4_OCF4B_MASK | TIFR4_OCF4A_MASK) -#define TCCR5C_FOC5C_SHIFT 5 -#define TCCR5C_FOC5C_MASK 0x20 -#define TCCR5C_FOC5B_SHIFT 6 -#define TCCR5C_FOC5B_MASK 0x40 -#define TCCR5C_FOC5A_SHIFT 7 -#define TCCR5C_FOC5A_MASK 0x80 +#define TCCR5C_FOC5C_SHIFT 5 +#define TCCR5C_FOC5C_MASK 0x20 +#define TCCR5C_FOC5B_SHIFT 6 +#define TCCR5C_FOC5B_MASK 0x40 +#define TCCR5C_FOC5A_SHIFT 7 +#define TCCR5C_FOC5A_MASK 0x80 -#define TCCR5B_CS_SHIFT 0 -#define TCCR5B_CS_MASK 0x07 -#define TCCR5B_WGM5_32_SHIFT 3 -#define TCCR5B_WGM5_32_MASK 0x18 -#define TCCR5B_ICES5_SHIFT 6 -#define TCCR5B_ICES5_MASK 0x40 -#define TCCR5B_ICNC5_SHIFT 7 -#define TCCR5B_ICNC5_MASK 0x80 -#define TIMER5_CLOCK_SELECT ((m_r[TCCR5B] & TCCR5B_CS_MASK) >> TCCR5B_CS_SHIFT) +#define TCCR5B_CS_SHIFT 0 +#define TCCR5B_CS_MASK 0x07 +#define TCCR5B_WGM5_32_SHIFT 3 +#define TCCR5B_WGM5_32_MASK 0x18 +#define TCCR5B_ICES5_SHIFT 6 +#define TCCR5B_ICES5_MASK 0x40 +#define TCCR5B_ICNC5_SHIFT 7 +#define TCCR5B_ICNC5_MASK 0x80 +#define TIMER5_CLOCK_SELECT ((m_r[TCCR5B] & TCCR5B_CS_MASK) >> TCCR5B_CS_SHIFT) -#define TCCR5A_WGM5_10_SHIFT 0 -#define TCCR5A_WGM5_10_MASK 0x03 -#define TCCR5A_COM5C_SHIFT 2 -#define TCCR5A_COM5C_MASK 0x0c -#define TCCR5A_COM5B_SHIFT 4 -#define TCCR5A_COM5B_MASK 0x30 -#define TCCR5A_COM5A_SHIFT 6 -#define TCCR5A_COM5A_MASK 0xc0 -#define TCCR5A_COM5A ((m_r[TCCR5A] & TCCR5A_COM5A_MASK) >> TCCR5A_COM5A_SHIFT) -#define TCCR5A_COM5B ((m_r[TCCR5A] & TCCR5A_COM5B_MASK) >> TCCR5A_COM5B_SHIFT) -#define TCCR5A_COM5C ((m_r[TCCR5A] & TCCR5A_COM5C_MASK) >> TCCR5A_COM5C_SHIFT) -#define TCCR5A_WGM5_10 (m_r[TCCR5A] & TCCR5A_WGM5_10_MASK) +#define TCCR5A_WGM5_10_SHIFT 0 +#define TCCR5A_WGM5_10_MASK 0x03 +#define TCCR5A_COM5C_SHIFT 2 +#define TCCR5A_COM5C_MASK 0x0c +#define TCCR5A_COM5B_SHIFT 4 +#define TCCR5A_COM5B_MASK 0x30 +#define TCCR5A_COM5A_SHIFT 6 +#define TCCR5A_COM5A_MASK 0xc0 +#define TCCR5A_COM5A ((m_r[TCCR5A] & TCCR5A_COM5A_MASK) >> TCCR5A_COM5A_SHIFT) +#define TCCR5A_COM5B ((m_r[TCCR5A] & TCCR5A_COM5B_MASK) >> TCCR5A_COM5B_SHIFT) +#define TCCR5A_COM5C ((m_r[TCCR5A] & TCCR5A_COM5C_MASK) >> TCCR5A_COM5C_SHIFT) +#define TCCR5A_WGM5_10 (m_r[TCCR5A] & TCCR5A_WGM5_10_MASK) -#define WGM5_32 ((m_r[TCCR5B] & TCCR5B_WGM5_32_MASK) >> TCCR5B_WGM5_32_SHIFT) -#define WGM5_10 ((m_r[TCCR5A] & TCCR5A_WGM5_10_MASK) >> TCCR5A_WGM5_10_SHIFT) -#define WGM5 ((WGM5_32 << 2) | WGM5_10) +#define WGM5_32 ((m_r[TCCR5B] & TCCR5B_WGM5_32_MASK) >> TCCR5B_WGM5_32_SHIFT) +#define WGM5_10 ((m_r[TCCR5A] & TCCR5A_WGM5_10_MASK) >> TCCR5A_WGM5_10_SHIFT) +#define WGM5 ((WGM5_32 << 2) | WGM5_10) -#define TIMSK5_TOIE5_BIT 0 -#define TIMSK5_OCIE5A_BIT 1 -#define TIMSK5_OCIE5B_BIT 2 -#define TIMSK5_OCIE5C_BIT 3 -#define TIMSK5_ICIE5_BIT 5 -#define TIMSK5_TOIE5_MASK (1 << TIMSK5_TOIE5_BIT) -#define TIMSK5_OCIE5A_MASK (1 << TIMSK5_OCIE5A_BIT) -#define TIMSK5_OCIE5B_MASK (1 << TIMSK5_OCIE5B_BIT) -#define TIMSK5_OCIE5C_MASK (1 << TIMSK5_OCIE5C_BIT) -#define TIMSK5_ICIE5_MASK (1 << TIMSK5_ICIE5_BIT) -#define TIMSK5_TOIE5 (BIT(m_r[TIMSK5], TIMSK5_TOIE5_BIT)) -#define TIMSK5_OCIE5A (BIT(m_r[TIMSK5], TIMSK5_OCIE5A_BIT)) -#define TIMSK5_OCIE5B (BIT(m_r[TIMSK5], TIMSK5_OCIE5B_BIT)) -#define TIMSK5_OCIE5C (BIT(m_r[TIMSK5], TIMSK5_OCIE5C_BIT)) -#define TIMSK5_ICIE5C (BIT(m_r[TIMSK5], TIMSK5_ICIE5C_BIT)) +#define TIMSK5_TOIE5_BIT 0 +#define TIMSK5_OCIE5A_BIT 1 +#define TIMSK5_OCIE5B_BIT 2 +#define TIMSK5_OCIE5C_BIT 3 +#define TIMSK5_ICIE5_BIT 5 +#define TIMSK5_TOIE5_MASK (1 << TIMSK5_TOIE5_BIT) +#define TIMSK5_OCIE5A_MASK (1 << TIMSK5_OCIE5A_BIT) +#define TIMSK5_OCIE5B_MASK (1 << TIMSK5_OCIE5B_BIT) +#define TIMSK5_OCIE5C_MASK (1 << TIMSK5_OCIE5C_BIT) +#define TIMSK5_ICIE5_MASK (1 << TIMSK5_ICIE5_BIT) +#define TIMSK5_TOIE5 (BIT(m_r[TIMSK5], TIMSK5_TOIE5_BIT)) +#define TIMSK5_OCIE5A (BIT(m_r[TIMSK5], TIMSK5_OCIE5A_BIT)) +#define TIMSK5_OCIE5B (BIT(m_r[TIMSK5], TIMSK5_OCIE5B_BIT)) +#define TIMSK5_OCIE5C (BIT(m_r[TIMSK5], TIMSK5_OCIE5C_BIT)) +#define TIMSK5_ICIE5C (BIT(m_r[TIMSK5], TIMSK5_ICIE5C_BIT)) -#define TIFR5_ICF5_MASK 0x20 -#define TIFR5_ICF5_SHIFT 5 -#define TIFR5_OCF5C_MASK 0x08 -#define TIFR5_OCF5C_SHIFT 3 -#define TIFR5_OCF5B_MASK 0x04 -#define TIFR5_OCF5B_SHIFT 2 -#define TIFR5_OCF5A_MASK 0x02 -#define TIFR5_OCF5A_SHIFT 1 -#define TIFR5_TOV5_MASK 0x01 -#define TIFR5_TOV5_SHIFT 0 -#define TIFR5_MASK (TIFR5_ICF5_MASK | TIFR5_OCF5C_MASK | TIFR5_OCF5B_MASK | TIFR5_OCF5A_MASK | TIFR5_TOV5_MASK) -#define TIFR5_ICF5 ((m_r[TIFR5] & TIFR5_ICF5_MASK) >> TIFR5_ICF5_SHIFT) -#define TIFR5_OCF5C ((m_r[TIFR5] & TIFR5_OCF5C_MASK) >> TIFR5_OCF5C_SHIFT) -#define TIFR5_OCF5B ((m_r[TIFR5] & TIFR5_OCF5B_MASK) >> TIFR5_OCF5B_SHIFT) -#define TIFR5_OCF5A ((m_r[TIFR5] & TIFR5_OCF5A_MASK) >> TIFR5_OCF5A_SHIFT) -#define TIFR5_TOV5 ((m_r[TIFR5] & TIFR5_TOV5_MASK) >> TIFR5_TOV5_SHIFT) +#define TIFR5_ICF5_MASK 0x20 +#define TIFR5_ICF5_SHIFT 5 +#define TIFR5_OCF5C_MASK 0x08 +#define TIFR5_OCF5C_SHIFT 3 +#define TIFR5_OCF5B_MASK 0x04 +#define TIFR5_OCF5B_SHIFT 2 +#define TIFR5_OCF5A_MASK 0x02 +#define TIFR5_OCF5A_SHIFT 1 +#define TIFR5_TOV5_MASK 0x01 +#define TIFR5_TOV5_SHIFT 0 +#define TIFR5_MASK (TIFR5_ICF5_MASK | TIFR5_OCF5C_MASK | TIFR5_OCF5B_MASK | TIFR5_OCF5A_MASK | TIFR5_TOV5_MASK) +#define TIFR5_ICF5 ((m_r[TIFR5] & TIFR5_ICF5_MASK) >> TIFR5_ICF5_SHIFT) +#define TIFR5_OCF5C ((m_r[TIFR5] & TIFR5_OCF5C_MASK) >> TIFR5_OCF5C_SHIFT) +#define TIFR5_OCF5B ((m_r[TIFR5] & TIFR5_OCF5B_MASK) >> TIFR5_OCF5B_SHIFT) +#define TIFR5_OCF5A ((m_r[TIFR5] & TIFR5_OCF5A_MASK) >> TIFR5_OCF5A_SHIFT) +#define TIFR5_TOV5 ((m_r[TIFR5] & TIFR5_TOV5_MASK) >> TIFR5_TOV5_SHIFT) //--------------------------------------------------------------- -#define WGM0 (((m_r[TCCR0B] & 0x08) >> 1) | (m_r[TCCR0A] & 0x03)) +#define WGM0 (((m_r[TCCR0B] & 0x08) >> 1) | (m_r[TCCR0A] & 0x03)) -#define OCR1A ((m_r[OCR1AH] << 8) | m_r[OCR1AL]) -#define OCR1B ((m_r[OCR1BH] << 8) | m_r[OCR1BL]) -#define OCR1C ((m_r[OCR1CH] << 8) | m_r[OCR1CL]) -#define ICR1 ((m_r[ICR1H] << 8) | m_r[ICR1L]) -#define WGM1 (((m_r[TCCR1B] & 0x18) >> 1) | (m_r[TCCR1A] & 0x03)) +#define OCR1A ((m_r[OCR1AH] << 8) | m_r[OCR1AL]) +#define OCR1B ((m_r[OCR1BH] << 8) | m_r[OCR1BL]) +#define OCR1C ((m_r[OCR1CH] << 8) | m_r[OCR1CL]) +#define ICR1 ((m_r[ICR1H] << 8) | m_r[ICR1L]) +#define WGM1 (((m_r[TCCR1B] & 0x18) >> 1) | (m_r[TCCR1A] & 0x03)) -#define WGM2 (((m_r[TCCR2B] & 0x08) >> 1) | (m_r[TCCR2A] & 0x03)) +#define WGM2 (((m_r[TCCR2B] & 0x08) >> 1) | (m_r[TCCR2A] & 0x03)) -#define ICR3 ((m_r[ICR3H] << 8) | m_r[ICR3L]) -#define OCR3A ((m_r[OCR3AH] << 8) | m_r[OCR3AL]) +#define ICR3 ((m_r[ICR3H] << 8) | m_r[ICR3L]) +#define OCR3A ((m_r[OCR3AH] << 8) | m_r[OCR3AL]) -#define ICR4 ((m_r[ICR4H] << 8) | m_r[ICR4L]) -#define OCR4A ((m_r[OCR4AH] << 8) | m_r[OCR4AL]) +#define ICR4 ((m_r[ICR4H] << 8) | m_r[ICR4L]) +#define OCR4A ((m_r[OCR4AH] << 8) | m_r[OCR4AL]) -#define ICR5 ((m_r[ICR5H] << 8) | m_r[ICR5L]) -#define OCR5A ((m_r[OCR5AH] << 8) | m_r[OCR5AL]) +#define ICR5 ((m_r[ICR5H] << 8) | m_r[ICR5L]) +#define OCR5A ((m_r[OCR5AH] << 8) | m_r[OCR5AL]) -#define GTCCR_PSRASY_MASK 0x02 -#define GTCCR_PSRASY_SHIFT 1 +#define GTCCR_PSRASY_MASK 0x02 +#define GTCCR_PSRASY_SHIFT 1 -#define SPSR_SPR2X (m_r[SPSR] & SPSR_SPR2X_MASK) +#define SPSR_SPR2X (m_r[SPSR] & SPSR_SPR2X_MASK) -#define SPCR_SPIE ((m_r[SPCR] & SPCR_SPIE_MASK) >> 7) -#define SPCR_SPE ((m_r[SPCR] & SPCR_SPE_MASK) >> 6) -#define SPCR_DORD ((m_r[SPCR] & SPCR_DORD_MASK) >> 5) -#define SPCR_MSTR ((m_r[SPCR] & SPCR_MSTR_MASK) >> 4) -#define SPCR_CPOL ((m_r[SPCR] & SPCR_CPOL_MASK) >> 3) -#define SPCR_CPHA ((m_r[SPCR] & SPCR_CPHA_MASK) >> 2) -#define SPCR_SPR (m_r[SPCR] & SPCR_SPR_MASK) +#define SPCR_SPIE ((m_r[SPCR] & SPCR_SPIE_MASK) >> 7) +#define SPCR_SPE ((m_r[SPCR] & SPCR_SPE_MASK) >> 6) +#define SPCR_DORD ((m_r[SPCR] & SPCR_DORD_MASK) >> 5) +#define SPCR_MSTR ((m_r[SPCR] & SPCR_MSTR_MASK) >> 4) +#define SPCR_CPOL ((m_r[SPCR] & SPCR_CPOL_MASK) >> 3) +#define SPCR_CPHA ((m_r[SPCR] & SPCR_CPHA_MASK) >> 2) +#define SPCR_SPR (m_r[SPCR] & SPCR_SPR_MASK) -#define SPI_RATE ((SPSR_SPR2X << 2) | SPCR_SPR) +#define SPI_RATE ((SPSR_SPR2X << 2) | SPCR_SPR) -#define PORTB_MOSI 0x08 +#define PORTB_MOSI 0x08 -#define EECR_MASK 0x3f -#define EECR_EERE_BIT 0 -#define EECR_EEPE_BIT 1 -#define EECR_EEMPE_BIT 2 -#define EECR_EERIE_BIT 3 -#define EECR_EEPM_BIT 4 -#define EECR_EERE_MASK (1 << EECR_EERE_BIT) -#define EECR_EEPE_MASK (1 << EECR_EEPE_BIT) -#define EECR_EEMPE_MASK (1 << EECR_EEMPE_BIT) -#define EECR_EERIE_MASK (1 << EECR_EERIE_BIT) -#define EECR_EEPM_MASK (3 << EECR_EEPM_BIT) -#define EECR_EERE (BIT(m_r[EECR], EECR_EERE_BIT)) -#define EECR_EEPE (BIT(m_r[EECR], EECR_EEPE_BIT)) -#define EECR_EEMPE (BIT(m_r[EECR], EECR_EEMPE_BIT)) -#define EECR_EERIE (BIT(m_r[EECR], EECR_EERIE_BIT)) -#define EECR_EEPM ((m_r[EECR] & EECR_EEPM_MASK) >> EECR_EEPM_BIT) +#define EECR_MASK 0x3f +#define EECR_EERE_BIT 0 +#define EECR_EEPE_BIT 1 +#define EECR_EEMPE_BIT 2 +#define EECR_EERIE_BIT 3 +#define EECR_EEPM_BIT 4 +#define EECR_EERE_MASK (1 << EECR_EERE_BIT) +#define EECR_EEPE_MASK (1 << EECR_EEPE_BIT) +#define EECR_EEMPE_MASK (1 << EECR_EEMPE_BIT) +#define EECR_EERIE_MASK (1 << EECR_EERIE_BIT) +#define EECR_EEPM_MASK (3 << EECR_EEPM_BIT) +#define EECR_EERE (BIT(m_r[EECR], EECR_EERE_BIT)) +#define EECR_EEPE (BIT(m_r[EECR], EECR_EEPE_BIT)) +#define EECR_EEMPE (BIT(m_r[EECR], EECR_EEMPE_BIT)) +#define EECR_EERIE (BIT(m_r[EECR], EECR_EERIE_BIT)) +#define EECR_EEPM ((m_r[EECR] & EECR_EEPM_MASK) >> EECR_EEPM_BIT) //--------------------------------------------------------------- -#define ADMUX_MUX_MASK 0x0f -#define ADMUX_ADLAR_MASK 0x20 -#define ADMUX_REFS_MASK 0xc0 -#define ADMUX_MUX ((m_r[ADMUX] & ADMUX_MUX_MASK) >> 0) -#define ADMUX_ADLAR ((m_r[ADMUX] & ADMUX_ADLAR_MASK) >> 5) -#define ADMUX_REFS ((m_r[ADMUX] & ADMUX_REFS_MASK) >> 6) +#define ADMUX_MUX_MASK 0x0f +#define ADMUX_ADLAR_MASK 0x20 +#define ADMUX_REFS_MASK 0xc0 +#define ADMUX_MUX ((m_r[ADMUX] & ADMUX_MUX_MASK) >> 0) +#define ADMUX_ADLAR ((m_r[ADMUX] & ADMUX_ADLAR_MASK) >> 5) +#define ADMUX_REFS ((m_r[ADMUX] & ADMUX_REFS_MASK) >> 6) -#define ADCSRB_ACME_MASK 0x40 -#define ADCSRB_ADTS_MASK 0x07 -#define ADCSRB_ACME ((m_r[ADCSRB] & ADCSRB_ACME_MASK) >> 6) -#define ADCSRB_ADTS ((m_r[ADCSRB] & ADCSRB_ADTS_MASK) >> 0) +#define ADCSRB_ACME_MASK 0x40 +#define ADCSRB_ADTS_MASK 0x07 +#define ADCSRB_ACME ((m_r[ADCSRB] & ADCSRB_ACME_MASK) >> 6) +#define ADCSRB_ADTS ((m_r[ADCSRB] & ADCSRB_ADTS_MASK) >> 0) -#define ADCSRA_ADPS_MASK 0x07 -#define ADCSRA_ADIE_MASK 0x08 -#define ADCSRA_ADIF_MASK 0x10 -#define ADCSRA_ADATE_MASK 0x20 -#define ADCSRA_ADSC_MASK 0x40 -#define ADCSRA_ADEN_MASK 0x80 -#define ADCSRA_ADPS (m_r[ADCSRA] & ADCSRA_ADPS_MASK) -#define ADCSRA_ADIE ((m_r[ADCSRA] & ADCSRA_ADIE_MASK) >> 3) -#define ADCSRA_ADIF ((m_r[ADCSRA] & ADCSRA_ADIF_MASK) >> 4) -#define ADCSRA_ADATE ((m_r[ADCSRA] & ADCSRA_ADATE_MASK) >> 5) -#define ADCSRA_ADSC ((m_r[ADCSRA] & ADCSRA_ADSC_MASK) >> 6) -#define ADCSRA_ADEN ((m_r[ADCSRA] & ADCSRA_ADEN_MASK) >> 7) +#define ADCSRA_ADPS_MASK 0x07 +#define ADCSRA_ADIE_MASK 0x08 +#define ADCSRA_ADIF_MASK 0x10 +#define ADCSRA_ADATE_MASK 0x20 +#define ADCSRA_ADSC_MASK 0x40 +#define ADCSRA_ADEN_MASK 0x80 +#define ADCSRA_ADPS (m_r[ADCSRA] & ADCSRA_ADPS_MASK) +#define ADCSRA_ADIE ((m_r[ADCSRA] & ADCSRA_ADIE_MASK) >> 3) +#define ADCSRA_ADIF ((m_r[ADCSRA] & ADCSRA_ADIF_MASK) >> 4) +#define ADCSRA_ADATE ((m_r[ADCSRA] & ADCSRA_ADATE_MASK) >> 5) +#define ADCSRA_ADSC ((m_r[ADCSRA] & ADCSRA_ADSC_MASK) >> 6) +#define ADCSRA_ADEN ((m_r[ADCSRA] & ADCSRA_ADEN_MASK) >> 7) //************************************************************************** diff --git a/src/devices/cpu/avr8/avr8.h b/src/devices/cpu/avr8/avr8.h index f6306b4838d..0254775273d 100644 --- a/src/devices/cpu/avr8/avr8.h +++ b/src/devices/cpu/avr8/avr8.h @@ -520,12 +520,12 @@ protected: // lock bit masks enum : uint8_t { - LB1 = (1 << 0), - LB2 = (1 << 1), - BLB01 = (1 << 2), - BLB02 = (1 << 3), - BLB11 = (1 << 4), - BLB12 = (1 << 5) + LB1 = (1 << 0), + LB2 = (1 << 1), + BLB01 = (1 << 2), + BLB02 = (1 << 3), + BLB11 = (1 << 4), + BLB12 = (1 << 5) }; // extended fuses bit masks @@ -539,27 +539,27 @@ protected: // high fuses bit masks enum : uint8_t { - BOOTRST = (1 << 0), + BOOTRST = (1 << 0), BOOTSZ0 = (1 << 1), BOOTSZ1 = (1 << 2), - EESAVE = (1 << 3), - WDTON = (1 << 4), - SPIEN = (1 << 5), - JTAGEN = (1 << 6), - OCDEN = (1 << 7) + EESAVE = (1 << 3), + WDTON = (1 << 4), + SPIEN = (1 << 5), + JTAGEN = (1 << 6), + OCDEN = (1 << 7) }; // low fuses bit masks enum : uint8_t { - CKSEL0 = (1 << 0), - CKSEL1 = (1 << 1), - CKSEL2 = (1 << 2), - CKSEL3 = (1 << 3), - SUT0 = (1 << 4), - SUT1 = (1 << 5), - CKOUT = (1 << 6), - CKDIV8 = (1 << 7) + CKSEL0 = (1 << 0), + CKSEL1 = (1 << 1), + CKSEL2 = (1 << 2), + CKSEL3 = (1 << 3), + SUT0 = (1 << 4), + SUT1 = (1 << 5), + CKOUT = (1 << 6), + CKDIV8 = (1 << 7) }; enum : uint8_t diff --git a/src/devices/machine/nandflash.h b/src/devices/machine/nandflash.h index 0c5a9be8277..dc1b3f0d134 100644 --- a/src/devices/machine/nandflash.h +++ b/src/devices/machine/nandflash.h @@ -157,6 +157,6 @@ DECLARE_DEVICE_TYPE(SAMSUNG_K9F2808U0B, samsung_k9f2808u0b_device) DECLARE_DEVICE_TYPE(SAMSUNG_K9F1G08U0B, samsung_k9f1g08u0b_device) DECLARE_DEVICE_TYPE(SAMSUNG_K9F1G08U0M, samsung_k9f1g08u0m_device) DECLARE_DEVICE_TYPE(SAMSUNG_K9LAG08U0M, samsung_k9lag08u0m_device) -DECLARE_DEVICE_TYPE(SAMSUNG_K9F2G08U0M, samsung_k9f2g08u0m_device) +DECLARE_DEVICE_TYPE(SAMSUNG_K9F2G08U0M, samsung_k9f2g08u0m_device) #endif // MAME_MACHINE_NANDFLASH_H diff --git a/src/devices/sound/swp00.cpp b/src/devices/sound/swp00.cpp index 830baba8e0a..d1936fd9c6f 100644 --- a/src/devices/sound/swp00.cpp +++ b/src/devices/sound/swp00.cpp @@ -567,8 +567,8 @@ template void swp00_device::lpf_info_w(offs_t offset, u8 data) if(m_lpf_info[chan] == old) return; - // if(!sel) - // logerror("lpf_info[%02x] = %04x\n", chan, m_lpf_info[chan]); + // if(!sel) + // logerror("lpf_info[%02x] = %04x\n", chan, m_lpf_info[chan]); u32 fb = m_lpf_info[chan] >> 11; u32 level = m_lpf_info[chan] & 0x7ff; @@ -593,7 +593,7 @@ void swp00_device::lpf_speed_w(offs_t offset, u8 data) return; m_stream->update(); m_lpf_speed[chan] = data; - // logerror("lpf_speed[%02x] = %02x\n", chan, m_lpf_speed[chan]); + // logerror("lpf_speed[%02x] = %02x\n", chan, m_lpf_speed[chan]); } u8 swp00_device::lpf_speed_r(offs_t offset) @@ -609,7 +609,7 @@ void swp00_device::lfo_famod_depth_w(offs_t offset, u8 data) return; m_stream->update(); m_lfo_famod_depth[chan] = data; - // logerror("lfo_famod_depth[%02x] = %02x\n", chan, m_lfo_famod_depth[chan]); + // logerror("lfo_famod_depth[%02x] = %02x\n", chan, m_lfo_famod_depth[chan]); } u8 swp00_device::lfo_famod_depth_r(offs_t offset) @@ -625,7 +625,7 @@ void swp00_device::rev_level_w(offs_t offset, u8 data) return; m_stream->update(); m_rev_level[chan] = data; - // logerror("rev_level[%02x] = %02x\n", chan, m_rev_level[chan]); + // logerror("rev_level[%02x] = %02x\n", chan, m_rev_level[chan]); } u8 swp00_device::rev_level_r(offs_t offset) @@ -641,7 +641,7 @@ void swp00_device::dry_level_w(offs_t offset, u8 data) return; m_stream->update(); m_dry_level[chan] = data; - // logerror("dry_level[%02x] = %02x\n", chan, m_dry_level[chan]); + // logerror("dry_level[%02x] = %02x\n", chan, m_dry_level[chan]); } u8 swp00_device::dry_level_r(offs_t offset) @@ -657,7 +657,7 @@ void swp00_device::cho_level_w(offs_t offset, u8 data) return; m_stream->update(); m_cho_level[chan] = data; - // logerror("cho_level[%02x] = %02x\n", chan, m_cho_level[chan]); + // logerror("cho_level[%02x] = %02x\n", chan, m_cho_level[chan]); } u8 swp00_device::cho_level_r(offs_t offset) @@ -673,7 +673,7 @@ void swp00_device::var_level_w(offs_t offset, u8 data) return; m_stream->update(); m_var_level[chan] = data; - // logerror("var_level[%02x] = %02x\n", chan, m_var_level[chan]); + // logerror("var_level[%02x] = %02x\n", chan, m_var_level[chan]); } u8 swp00_device::var_level_r(offs_t offset) @@ -688,7 +688,7 @@ void swp00_device::glo_level_w(offs_t offset, u8 data) if(m_glo_level[chan] == data) return; m_glo_level[chan] = data; - // logerror("glo_level[%02x] = %02x\n", chan, m_glo_level[chan]); + // logerror("glo_level[%02x] = %02x\n", chan, m_glo_level[chan]); } u8 swp00_device::glo_level_r(offs_t offset) @@ -704,7 +704,7 @@ void swp00_device::panning_w(offs_t offset, u8 data) return; m_stream->update(); m_panning[chan] = data; - // logerror("panning[%02x] = %02x\n", chan, m_panning[chan]); + // logerror("panning[%02x] = %02x\n", chan, m_panning[chan]); } u8 swp00_device::panning_r(offs_t offset) @@ -790,8 +790,8 @@ template void swp00_device::pitch_w(offs_t offset, u8 data) m_pitch[chan] = (m_pitch[chan] & ~(0xff << (8*sel))) | (data << (8*sel)); if(m_pitch[chan] == old) return; - // if(!sel) - // logerror("pitch[%02x] = %04x\n", chan, m_pitch[chan]); + // if(!sel) + // logerror("pitch[%02x] = %04x\n", chan, m_pitch[chan]); } template u8 swp00_device::pitch_r(offs_t offset) @@ -806,8 +806,8 @@ template void swp00_device::sample_start_w(offs_t offset, u8 data) m_stream->update(); m_sample_start[chan] = (m_sample_start[chan] & ~(0xff << (8*sel))) | (data << (8*sel)); - // if(!sel) - // logerror("sample_start[%02x] = %04x\n", chan, m_sample_start[chan]); + // if(!sel) + // logerror("sample_start[%02x] = %04x\n", chan, m_sample_start[chan]); } template u8 swp00_device::sample_start_r(offs_t offset) @@ -822,8 +822,8 @@ template void swp00_device::sample_end_w(offs_t offset, u8 data) m_stream->update(); m_sample_end[chan] = (m_sample_end[chan] & ~(0xff << (8*sel))) | (data << (8*sel)); - // if(!sel) - // logerror("sample_end[%02x] = %04x\n", chan, m_sample_end[chan]); + // if(!sel) + // logerror("sample_end[%02x] = %04x\n", chan, m_sample_end[chan]); } template u8 swp00_device::sample_end_r(offs_t offset) @@ -838,7 +838,7 @@ void swp00_device::sample_dec_and_format_w(offs_t offset, u8 data) m_stream->update(); m_sample_dec_and_format[chan] = data; - // logerror("sample_dec_and_format[%02x] = %02x\n", chan, m_sample_dec_and_format[chan]); + // logerror("sample_dec_and_format[%02x] = %02x\n", chan, m_sample_dec_and_format[chan]); } u8 swp00_device::sample_dec_and_format_r(offs_t offset) @@ -853,8 +853,8 @@ template void swp00_device::sample_address_w(offs_t offset, u8 data) m_stream->update(); m_sample_address[chan] = (m_sample_address[chan] & ~(0xff << (8*sel))) | (data << (8*sel)); - // if(!sel) - // logerror("sample_address[%02x] = %04x\n", chan, m_sample_address[chan]); + // if(!sel) + // logerror("sample_address[%02x] = %04x\n", chan, m_sample_address[chan]); } template u8 swp00_device::sample_address_r(offs_t offset) @@ -871,7 +871,7 @@ void swp00_device::lfo_step_w(offs_t offset, u8 data) m_stream->update(); m_lfo_step[chan] = data; - // logerror("lfo_step[%02x] = %02x\n", chan, m_lfo_step[chan]); + // logerror("lfo_step[%02x] = %02x\n", chan, m_lfo_step[chan]); } u8 swp00_device::lfo_step_r(offs_t offset) @@ -888,7 +888,7 @@ void swp00_device::lfo_pmod_depth_w(offs_t offset, u8 data) m_stream->update(); m_lfo_pmod_depth[chan] = data; - // logerror("lfo_pmod_depth[%02x] = %02x\n", chan, m_lfo_pmod_depth[chan]); + // logerror("lfo_pmod_depth[%02x] = %02x\n", chan, m_lfo_pmod_depth[chan]); } u8 swp00_device::lfo_pmod_depth_r(offs_t offset) @@ -1136,7 +1136,7 @@ template s32 swp00_device::delay_block::rlfo(int offreg, u32 s32 val0 = m_buffer[pos & (size - 1)]; s32 val1 = m_buffer[(pos + 1) & (size - 1)]; - // fprintf(stderr, "lfo %02x %x %x\n", offreg, val0, val1); + // fprintf(stderr, "lfo %02x %x %x\n", offreg, val0, val1); return s32((val1 * s64(lfo_i_frac) + val0 * s64(0x400000 - lfo_i_frac)) >> 22); } @@ -1151,7 +1151,7 @@ template s32 swp00_device::delay_block::rlfo2(int offreg, s32 s32 val0 = m_buffer[pos & (size - 1)]; s32 val1 = m_buffer[(pos + 1) & (size - 1)]; - // fprintf(stderr, "lfo %02x %x %x\n", offreg, val0, val1); + // fprintf(stderr, "lfo %02x %x %x\n", offreg, val0, val1); return s32((val1 * s64(lfo_i_frac) + val0 * s64(0x800 - lfo_i_frac)) >> 11); } diff --git a/src/devices/sound/swp20.cpp b/src/devices/sound/swp20.cpp index 3767f3af11e..947d2bb8b0a 100644 --- a/src/devices/sound/swp20.cpp +++ b/src/devices/sound/swp20.cpp @@ -122,8 +122,8 @@ template void swp20_device::sample_start_w(u8 data) m_stream->update(); m_sample_start[m_voice] = (m_sample_start[m_voice] & ~(0xff << (8*sel))) | (data << (8*sel)); - // if(!sel) - // logerror("sample_start[%02x] = %04x\n", m_voice, m_sample_start[m_voice]); + // if(!sel) + // logerror("sample_start[%02x] = %04x\n", m_voice, m_sample_start[m_voice]); } template u8 swp20_device::sample_start_r() @@ -136,8 +136,8 @@ template void swp20_device::sample_end_w(u8 data) m_stream->update(); m_sample_end[m_voice] = (m_sample_end[m_voice] & ~(0xff << (8*sel))) | (data << (8*sel)); - // if(!sel) - // logerror("sample_end[%02x] = %04x\n", m_voice, m_sample_end[m_voice]); + // if(!sel) + // logerror("sample_end[%02x] = %04x\n", m_voice, m_sample_end[m_voice]); } template u8 swp20_device::sample_end_r() @@ -185,7 +185,7 @@ void swp20_device::eq_w(u8 data) u8 swp20_device::snd_r(offs_t offset) { - // logerror("r %02x %s\n", offset, machine().describe_context()); + // logerror("r %02x %s\n", offset, machine().describe_context()); return 0; } diff --git a/src/devices/sound/swp30.cpp b/src/devices/sound/swp30.cpp index d7b8308288c..265f1fc3ce9 100644 --- a/src/devices/sound/swp30.cpp +++ b/src/devices/sound/swp30.cpp @@ -862,7 +862,7 @@ u16 swp30_device::lfo_step_pmod_r(offs_t offset) void swp30_device::lfo_step_pmod_w(offs_t offset, u16 data) { - // logerror("lfo_step_pmod[%02x] = %04x\n", offset >> 6, data); + // logerror("lfo_step_pmod[%02x] = %04x\n", offset >> 6, data); m_lfo_step_pmod[offset >> 6] = data; } @@ -873,7 +873,7 @@ u16 swp30_device::lfo_amod_r(offs_t offset) void swp30_device::lfo_amod_w(offs_t offset, u16 data) { - // logerror("lfo_amod[%02x] = %04x\n", offset >> 6, data); + // logerror("lfo_amod[%02x] = %04x\n", offset >> 6, data); m_lfo_amod[offset >> 6] = data; } @@ -1012,7 +1012,7 @@ template u16 swp30_device::meg_lfo_r(offs_t offset) template void swp30_device::meg_lfo_w(offs_t offset, u16 data) { - int slot = (offset >> 6)*2 + sel; + int slot = (offset >> 6)*2 + sel; m_meg_lfo[slot] = data; static const int dt[8] = { 0, 32, 64, 128, 256, 512, 1024, 2048 }; @@ -1218,7 +1218,7 @@ void swp30_device::execute_run() lfo_p_phase = lfo_a_phase = 0; // First, read the sample - + // - Find the base sample index and base address s32 sample_pos = m_sample_pos[chan]; if(m_sample_end[chan] & 0x80000000) @@ -1226,7 +1226,7 @@ void swp30_device::execute_run() s32 spos = sample_pos >> 8; offs_t base_address = m_sample_address[chan] & 0x1ffffff; - + // - Read/decompress the sample s16 val0, val1; switch(m_sample_address[chan] >> 30) { @@ -1452,7 +1452,7 @@ void swp30_device::execute_run() else m_decay2_done[chan] = fpstep(m_envelope_level[chan], (m_decay2[chan] & 0xff) << 20, m_global_step[(m_decay2[chan] >> 8) & 0x7f]); break; - + case RELEASE: if((m_release_glo[chan] & 0x6000) == 0x6000) { if(fpstep(m_envelope_level[chan], 0x8000000, decay_linear_step[(m_release_glo[chan] >> 8) & 0x1f])) @@ -1551,7 +1551,7 @@ void swp30_device::execute_run() } } } - + debugger_instruction_hook(m_meg_pc); m_icount --; m_meg_pc ++; diff --git a/src/devices/sound/upd933.cpp b/src/devices/sound/upd933.cpp index 38c352ce78c..6167ec2a3c1 100644 --- a/src/devices/sound/upd933.cpp +++ b/src/devices/sound/upd933.cpp @@ -199,8 +199,8 @@ void upd933_device::update_pending_irq() for (int i = 0; i < 8; i++) { env_active |= (m_dca[i].calc_timeout(new_time) - | m_dco[i].calc_timeout(new_time) - | m_dcw[i].calc_timeout(new_time)); + | m_dco[i].calc_timeout(new_time) + | m_dcw[i].calc_timeout(new_time)); } if (env_active) diff --git a/src/lib/netlist/tools/nl_convert.cpp b/src/lib/netlist/tools/nl_convert.cpp index acffed63a46..8fe3b19eca8 100644 --- a/src/lib/netlist/tools/nl_convert.cpp +++ b/src/lib/netlist/tools/nl_convert.cpp @@ -336,7 +336,7 @@ void nl_convert_spice_t::convert_block(const str_list &contents) int linenumber = 1; for (const auto &line : contents) { - try + try { process_line(line); } diff --git a/src/mame/atari/mediagx.cpp b/src/mame/atari/mediagx.cpp index 667b7eda035..9d5eb6ffb68 100644 --- a/src/mame/atari/mediagx.cpp +++ b/src/mame/atari/mediagx.cpp @@ -885,7 +885,7 @@ void mediagx_state::mediagx(machine_config &config) // TODO: checked at POST, wants a debug device? PC_LPT(config, m_lpt0); -// m_lpt0->irq_handler().set("mb:pic8259", FUNC(pic8259_device::ir7_w)); +// m_lpt0->irq_handler().set("mb:pic8259", FUNC(pic8259_device::ir7_w)); pcat_common(config); diff --git a/src/mame/dataeast/astrof.cpp b/src/mame/dataeast/astrof.cpp index 2928919d954..26332acdffd 100644 --- a/src/mame/dataeast/astrof.cpp +++ b/src/mame/dataeast/astrof.cpp @@ -1052,7 +1052,7 @@ ROM_START( astrof3 ) ROM_END // from an original Taito PCB with silkscreen -ROM_START( astroft ) +ROM_START( astroft ) ROM_REGION( 0x10000, "maincpu", 0 ) ROM_LOAD( "as_19.bin", 0xd000, 0x0800, CRC(fa9e5607) SHA1(246a3591196939ecca9088f44035cceb4ee3531e) ) ROM_LOAD( "as_18.bin", 0xd800, 0x0800, CRC(1c104d3d) SHA1(20015808ad87421e90c0eac806bb39dee5226b51) ) diff --git a/src/mame/itech/itech8.h b/src/mame/itech/itech8.h index d8aa1a9fa42..d8ebdffa458 100644 --- a/src/mame/itech/itech8.h +++ b/src/mame/itech/itech8.h @@ -219,7 +219,7 @@ private: TIMER_CALLBACK_MEMBER(delayed_z80_control_w); u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); - + void mem_hi_map(address_map &map); void mem_lo_map(address_map &map); void z80_io_map(address_map &map); diff --git a/src/mame/layout/bbombo.lay b/src/mame/layout/bbombo.lay index ee17195bcd9..717bb76ec90 100644 --- a/src/mame/layout/bbombo.lay +++ b/src/mame/layout/bbombo.lay @@ -792,7 +792,7 @@ copyright-holders: Roberto Fresca, Grull Osgo - + diff --git a/src/mame/misc/changyu.cpp b/src/mame/misc/changyu.cpp index bf3c140f7f2..3a8117fda94 100644 --- a/src/mame/misc/changyu.cpp +++ b/src/mame/misc/changyu.cpp @@ -132,7 +132,7 @@ void changyu_state::video_start() { m_bg_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(changyu_state::get_bg_tile_info)), TILEMAP_SCAN_ROWS, 8, 8, 64, 32); -// m_bg_tilemap->set_transparent_pen(0); +// m_bg_tilemap->set_transparent_pen(0); } uint32_t changyu_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) @@ -229,7 +229,7 @@ void changyu_state::changyu(machine_config &config) m_maincpu->set_addrmap(AS_PROGRAM, &changyu_state::main_map); I8751(config, m_mcu, XTAL(8'000'000)); -// m_mcu->set_disable(); +// m_mcu->set_disable(); screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); screen.set_refresh_hz(60); @@ -261,7 +261,7 @@ void changyu_state::changyu2(machine_config &config) m_maincpu->set_addrmap(AS_PROGRAM, &changyu_state::main2_map); I87C51(config.replace(), m_mcu, XTAL(8'000'000)); -// m_mcu->set_disable(); +// m_mcu->set_disable(); YM2413(config, "ymsnd", 3.579545_MHz_XTAL).add_route(ALL_OUTPUTS, "mono", 1.0); } diff --git a/src/mame/misc/cowtipping.cpp b/src/mame/misc/cowtipping.cpp index a9f42873bdb..fab09811389 100644 --- a/src/mame/misc/cowtipping.cpp +++ b/src/mame/misc/cowtipping.cpp @@ -89,7 +89,7 @@ void cowtipping_state::cowtipping(machine_config &config) PIC16C56(config, "pic", 4000000); // Actually PIC12C508/P, clock not verified -// TODO: AMD_29LV640MB (64 MBit with Boot Sector) +// TODO: AMD_29LV640MB (64 MBit with Boot Sector) screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); // wrong screen.set_refresh_hz(60); diff --git a/src/mame/misc/mirderby.cpp b/src/mame/misc/mirderby.cpp index a9ca9d312a5..ea77e56c62f 100644 --- a/src/mame/misc/mirderby.cpp +++ b/src/mame/misc/mirderby.cpp @@ -27,7 +27,7 @@ actually a CPU. Is this a bootleg of an Home Data original? Notes from Stefan Lindberg: -Eprom "x70_a04.5g" had wires attached to it, pin 2 and 16 was joined and pin 1,32,31,30 was joined, +Eprom "x70_a04.5g" had wires attached to it, pin 2 and 16 was joined and pin 1,32,31,30 was joined, i removed them and read the eprom as the type it was (D27c1000D). Measured frequencies: @@ -89,7 +89,7 @@ public: , m_subcpu(*this, "subcpu") , m_x70coincpu(*this, "audiocpu") , m_ymsnd(*this, "ymsnd") -// , m_vreg(*this, "vreg") +// , m_vreg(*this, "vreg") , m_screen(*this, "screen") , m_videoram(*this, "videoram") , m_spriteram(*this, "spriteram") @@ -107,13 +107,13 @@ public: void mirderby(machine_config &config); private: -// optional_region_ptr m_blit_rom; +// optional_region_ptr m_blit_rom; required_device m_maincpu; required_device m_subcpu; required_device m_x70coincpu; optional_device m_ymsnd; -// optional_shared_ptr m_vreg; +// optional_shared_ptr m_vreg; required_device m_screen; required_shared_ptr m_videoram; required_shared_ptr m_spriteram; @@ -150,9 +150,9 @@ private: void x70coin_io(address_map &map); tilemap_t *m_bg_tilemap{}; -// int m_visible_page = 0; -// int m_priority = 0; -// [[maybe_unused]] int m_flipscreen = 0; +// int m_visible_page = 0; +// int m_priority = 0; +// [[maybe_unused]] int m_flipscreen = 0; u8 m_prot_data = 0; u8 m_latch = 0; u16 m_gfx_flip = 0; @@ -191,7 +191,7 @@ void mirderby_state::video_start() { m_bg_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(mirderby_state::get_bg_tile_info)), TILEMAP_SCAN_ROWS, 8, 8, 64, 32); -// m_bg_tilemap->set_transparent_pen(0); +// m_bg_tilemap->set_transparent_pen(0); } TILE_GET_INFO_MEMBER(mirderby_state::get_bg_tile_info) @@ -233,7 +233,7 @@ void mirderby_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprec // TODO: missing sprites (signed wraparound?) //if (attr == 0) - // continue; + // continue; // draws in block strips of 16x16 const u8 tile_offs[4] = { 0, 1, 0x10, 0x11 }; @@ -319,7 +319,7 @@ void mirderby_state::shared_map(address_map &map) map(0x7000, 0x77ff).ram().share("nvram"); map(0x7800, 0x7800).rw(FUNC(mirderby_state::prot_r), FUNC(mirderby_state::prot_w)); //0x7ff0 onward seems CRTC -// map(0x7ff0, 0x7ff?).writeonly().share("vreg"); +// map(0x7ff0, 0x7ff?).writeonly().share("vreg"); map(0x7ff2, 0x7ff2).portr("SYSTEM"); map(0x7ff9, 0x7ffa).lr8( NAME([this] (offs_t offset) { @@ -372,7 +372,7 @@ void mirderby_state::shared_map(address_map &map) ); map(0x7fff, 0x7fff).lrw8( NAME([this] () { - // 0x7fff $e / $f writes -> DSW reads + // 0x7fff $e / $f writes -> DSW reads return m_ymsnd->read(1); }), NAME([this] (u8 data) { @@ -635,11 +635,11 @@ void mirderby_state::mirderby(machine_config &config) /* basic machine hardware */ MC6809E(config, m_maincpu, 16000000/8); /* MBL68B09E 2 Mhz */ m_maincpu->set_addrmap(AS_PROGRAM, &mirderby_state::main_map); -// m_maincpu->set_vblank_int("screen", FUNC(mirderby_state::homedata_irq)); +// m_maincpu->set_vblank_int("screen", FUNC(mirderby_state::homedata_irq)); MC6809E(config, m_subcpu, 16000000/8); /* MBL68B09E 2 Mhz */ m_subcpu->set_addrmap(AS_PROGRAM, &mirderby_state::sub_map); -// m_subcpu->set_vblank_int("screen", FUNC(mirderby_state::homedata_irq)); +// m_subcpu->set_vblank_int("screen", FUNC(mirderby_state::homedata_irq)); // im 0, doesn't bother in setting a vector table, // should just require a NMI from somewhere ... @@ -657,11 +657,11 @@ void mirderby_state::mirderby(machine_config &config) PIT8253(config, m_coin_pit, 0); m_coin_pit->set_clk<0>(XTAL(16'000'000) / 8); m_coin_pit->out_handler<0>().set_inputline(m_x70coincpu, INPUT_LINE_NMI); -// m_coin_pit->set_clk<1>(XTAL(16'000'000) / 8); -// m_coin_pit->set_clk<2>(XTAL(16'000'000) / 8); +// m_coin_pit->set_clk<1>(XTAL(16'000'000) / 8); +// m_coin_pit->set_clk<2>(XTAL(16'000'000) / 8); NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_1); -// config.set_maximum_quantum(attotime::from_hz(6000)); +// config.set_maximum_quantum(attotime::from_hz(6000)); config.set_perfect_quantum("maincpu"); SCREEN(config, m_screen, SCREEN_TYPE_RASTER); diff --git a/src/mame/misc/rfslots8085.cpp b/src/mame/misc/rfslots8085.cpp index 9163c7e75f6..75b3cafb1d3 100644 --- a/src/mame/misc/rfslots8085.cpp +++ b/src/mame/misc/rfslots8085.cpp @@ -671,7 +671,7 @@ u8 rfslots8085_state::kbd_rl_r() { m_lamps[18] = 109 * (1 + ( sin( (m_reel->get_pos() * 0.0628) - 1.57079))); // layout scale m_lamps[19] = m_reel->get_pos() % 3; -// logerror("%s: Anim. Bingo Roller: L18:%d - L19:%02x - pos:%d\n", machine().time().as_string(), m_lamps[18], m_lamps[19], m_reel->get_pos()); +// logerror("%s: Anim. Bingo Roller: L18:%d - L19:%02x - pos:%d\n", machine().time().as_string(), m_lamps[18], m_lamps[19], m_reel->get_pos()); } // Keyboard read (only scan line 0 is used) diff --git a/src/mame/misc/rfslotsmcs48.cpp b/src/mame/misc/rfslotsmcs48.cpp index 46abf9ca4fa..2795c757745 100644 --- a/src/mame/misc/rfslotsmcs48.cpp +++ b/src/mame/misc/rfslotsmcs48.cpp @@ -41,7 +41,7 @@ - Discover and emulate 100 Pts. coin in action, done by an owner hack in mainboard with a 74ls164. This 100 Pts. hack accepts this coin and gives back three 25 Pts. - coins as change, then only plays 25 Pts. as bet. + coins as change, then only plays 25 Pts. as bet. - Complete Baby Fruits 25 pts. emulation, partially emulated due to a bad dump of the main CPU ROM. @@ -745,26 +745,26 @@ void rfslotsmcs48_state::babyfrts(machine_config &config) m_sndbfcpu->p1_out_cb().set(FUNC(rfslotsmcs48_state::sound_p1_w)); m_sndbfcpu->p2_in_cb().set(FUNC(rfslotsmcs48_state::sound_p2_r)); -// I8243, m_ioexp[0]; PIA 1: fruits projectors +// I8243, m_ioexp[0]; PIA 1: fruits projectors m_ioexp[0]->p4_out_cb().set(FUNC(rfslotsmcs48_state::proy_1_w)); // left m_ioexp[0]->p5_out_cb().set(FUNC(rfslotsmcs48_state::proy_2_w)); // center m_ioexp[0]->p6_out_cb().set(FUNC(rfslotsmcs48_state::proy_3_w)); // right m_ioexp[0]->p7_out_cb().set(FUNC(rfslotsmcs48_state::exp1_p7_w)); // sound Reset + Int -// I8243, m_ioexp[1]; PIA 2 +// I8243, m_ioexp[1]; PIA 2 m_ioexp[1]->p4_out_cb().set(FUNC(rfslotsmcs48_state::exp2_p4_w)); // coils and EM counters m_ioexp[1]->p5_out_cb().set(FUNC(rfslotsmcs48_state::exp2_p5_w)); // game lights m_ioexp[1]->p6_out_cb().set(FUNC(rfslotsmcs48_state::exp2_p6_w)); // push buttons lights m_ioexp[1]->p7_out_cb().set(FUNC(rfslotsmcs48_state::exp2_p7_w)); // sound codes m_ioexp[1]->p7_in_cb().set(FUNC(rfslotsmcs48_state::exp2_p7_r)); // sound handshake -// I8243, m_ioexp[3]; PIA 4 +// I8243, m_ioexp[3]; PIA 4 m_ioexp[3]->p4_in_cb().set_ioport("IN0"); m_ioexp[3]->p5_in_cb().set_ioport("IN1"); m_ioexp[3]->p6_in_cb().set_ioport("IN4"); // SWA m_ioexp[3]->p7_in_cb().set_ioport("IN2"); -// I8243, m_ioexp[4]; PIA 5 +// I8243, m_ioexp[4]; PIA 5 m_ioexp[4]->p4_out_cb().set(FUNC(rfslotsmcs48_state::exp5_p4_w)); // Selector 1-16 m_ioexp[4]->p5_in_cb().set_ioport("IN5"); // SWB m_ioexp[4]->p7_in_cb().set_ioport("IN3"); @@ -787,26 +787,26 @@ void rfslotsmcs48_state::ajofrin(machine_config &config) m_sndajcpu->p1_out_cb().set("dac", FUNC(dac_byte_interface::data_w)); m_sndajcpu->p2_in_cb().set(FUNC(rfslotsmcs48_state::sound_p2_r)); -// I8243, m_ioexp[0]; PIA 1 +// I8243, m_ioexp[0]; PIA 1 m_ioexp[0]->p4_out_cb().set(FUNC(rfslotsmcs48_state::proy_1_w)); // to verify left projector m_ioexp[0]->p5_out_cb().set(FUNC(rfslotsmcs48_state::proy_2_w)); // to verify center projector m_ioexp[0]->p6_out_cb().set(FUNC(rfslotsmcs48_state::proy_3_w)); // to verify right projector - There is an extra projector. To be found. m_ioexp[0]->p7_out_cb().set(FUNC(rfslotsmcs48_state::aj_exp1_p7_w)); // sound + int to verify -// I8243, m_ioexp[1]; PIA 2 +// I8243, m_ioexp[1]; PIA 2 m_ioexp[1]->p4_out_cb().set(FUNC(rfslotsmcs48_state::exp2_p4_w)); // coils and EM counters - idem bfr m_ioexp[1]->p5_out_cb().set(FUNC(rfslotsmcs48_state::exp2_p5_w)); // game lights - idem bfr -// I8243, m_ioexp[2]; PIA 3 +// I8243, m_ioexp[2]; PIA 3 m_ioexp[2]->p7_in_cb().set_ioport("IN0"); -// I8243, m_ioexp[3]; PIA 4 +// I8243, m_ioexp[3]; PIA 4 m_ioexp[3]->p4_in_cb().set_ioport("IN1"); m_ioexp[3]->p5_in_cb().set_ioport("IN2"); m_ioexp[3]->p6_in_cb().set_ioport("IN3"); m_ioexp[3]->p7_in_cb().set_ioport("IN4"); -// I8243, m_ioexp[4]; PIA 5 +// I8243, m_ioexp[4]; PIA 5 m_ioexp[4]->p5_in_cb().set_ioport("IN5"); m_ioexp[4]->p6_out_cb().set(FUNC(rfslotsmcs48_state::aj_exp5_p6_w)); diff --git a/src/mame/nec/pc9801.cpp b/src/mame/nec/pc9801.cpp index ad0bd6d4709..675bd1f8785 100644 --- a/src/mame/nec/pc9801.cpp +++ b/src/mame/nec/pc9801.cpp @@ -648,7 +648,7 @@ void pc9801_state::pc9801_common_io(address_map &map) // (can be accessed only thru the $3fdb alias) map(0x0070, 0x0077).rw(m_pit, FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0xff00); map(0x0070, 0x007f).rw(FUNC(pc9801_state::txt_scrl_r), FUNC(pc9801_state::txt_scrl_w)).umask16(0x00ff); //display registers / i8253 pit -// map(0x0090, 0x0093).rw(m_sio, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0xff00); // CMT SIO (optional, C-Bus) +// map(0x0090, 0x0093).rw(m_sio, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0xff00); // CMT SIO (optional, C-Bus) map(0x7fd8, 0x7fdf).rw(m_ppi_mouse, FUNC(i8255_device::read), FUNC(i8255_device::write)).umask16(0xff00); } diff --git a/src/mame/nec/pc_h98.cpp b/src/mame/nec/pc_h98.cpp index 11be65ef5f1..aa4539da71e 100644 --- a/src/mame/nec/pc_h98.cpp +++ b/src/mame/nec/pc_h98.cpp @@ -33,7 +33,7 @@ protected: void pc_hyper98_state::pc_h98_map(address_map &map) { pc_hyper98_state::pc9801bx2_map(map); -// map(0x080000, 0x0bffff).unmaprw(); // RAM window +// map(0x080000, 0x0bffff).unmaprw(); // RAM window // TODO: bigger, needs fn mods map(0x0c0000, 0x0dffff).rw(FUNC(pc_hyper98_state::grcg_gvram0_r), FUNC(pc_hyper98_state::grcg_gvram0_w)); map(0x0e0000, 0x0e3fff).rw(FUNC(pc_hyper98_state::tvram_r), FUNC(pc_hyper98_state::tvram_w)); @@ -204,7 +204,7 @@ ROM_START( pc_h98s ) ROM_LOAD( "font.rom", 0x00000, 0x46800, BAD_DUMP CRC(a61c0649) SHA1(554b87377d176830d21bd03964dc71f8e98676b1) ) LOAD_KANJI_ROMS -// LOAD_IDE_ROM +// LOAD_IDE_ROM ROM_END COMP( 1991, pc_h98s, 0, 0, pc_h98s, pc_h98, pc_hyper98_state, init_pc9801_kanji, "NEC", "PC-H98S model 8/U8", MACHINE_IS_SKELETON ) diff --git a/src/mame/nintendo/nes_clone.cpp b/src/mame/nintendo/nes_clone.cpp index ce5ff86718e..4b3a7364f32 100644 --- a/src/mame/nintendo/nes_clone.cpp +++ b/src/mame/nintendo/nes_clone.cpp @@ -741,8 +741,8 @@ void nes_clone_afbm7800_state::handle_mmc3chr_banks(uint16_t* selected_chrbanks) /* not correct? desert falcon if (m_extraregs[0] & 0x80) { - bankmask = 0x0f; - outerchrbank = (m_extraregs[0] & 0x38) << 1; + bankmask = 0x0f; + outerchrbank = (m_extraregs[0] & 0x38) << 1; } else */ @@ -809,7 +809,7 @@ void nes_clone_taikee_new_state::handle_mmc3chr_banks(uint16_t* selected_chrbank else if (m_extraregs[0] == 0xe8) outerchrbank = 0x80; // 1f mask, but no sprites?? (hot racing) // 1111 0010 - else if (m_extraregs[0] == 0xf2) + else if (m_extraregs[0] == 0xf2) outerchrbank = 0x100; // (winter race) // 1111 1011 else if (m_extraregs[0] == 0xfb) diff --git a/src/mame/nintendo/nes_vt02_vt03.cpp b/src/mame/nintendo/nes_vt02_vt03.cpp index 9e7785a864d..bc6604f7dc6 100644 --- a/src/mame/nintendo/nes_vt02_vt03.cpp +++ b/src/mame/nintendo/nes_vt02_vt03.cpp @@ -1498,7 +1498,7 @@ CONS( 2004, vsmaxxvd, 0, 0, nes_vt_vh2009_8mb, nes_vt, nes_vt_swap_op_ CONS( 200?, vsmaxx77, 0, 0, nes_vt_vh2009_8mb, nes_vt, nes_vt_swap_op_d5_d6_state, empty_init, "Senario / JungleTac", "Vs Maxx Wireless 77-in-1", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) CONS( 200?, joysti30, 0, 0, nes_vt_vh2009_4mb, nes_vt, nes_vt_swap_op_d5_d6_state, empty_init, "WinFun / JungleTac", "Joystick 30", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // doesn't show WinFun onscreen, but packaging does -// has no audio, is there extra hardware, or is it just using unemulated VT features? +// has no audio, is there extra hardware, or is it just using unemulated VT features? CONS( 2005, lxnoddy, 0, 0, nes_vt_vh2009_pal_2mb, lxnoddy, nes_vt_swap_op_d5_d6_state, empty_init, "Lexibook", "Noddy's TV Console", MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND ) diff --git a/src/mame/pc/teradrive.cpp b/src/mame/pc/teradrive.cpp index 56809da637e..adbade52c99 100644 --- a/src/mame/pc/teradrive.cpp +++ b/src/mame/pc/teradrive.cpp @@ -54,12 +54,12 @@ void teradrive_state::at_softlists(machine_config &config) { SOFTWARE_LIST(config, "pc_disk_list").set_original("ibm5150"); SOFTWARE_LIST(config, "at_disk_list").set_original("ibm5170"); -// SOFTWARE_LIST(config, "at_cdrom_list").set_original("ibm5170_cdrom"); +// SOFTWARE_LIST(config, "at_cdrom_list").set_original("ibm5170_cdrom"); SOFTWARE_LIST(config, "at_hdd_list").set_original("ibm5170_hdd"); SOFTWARE_LIST(config, "midi_disk_list").set_compatible("midi_flop"); -// TODO: MD portion -// TODO: Teradrive SW list +// TODO: MD portion +// TODO: Teradrive SW list } void teradrive_state::teradrive_map(address_map &map) diff --git a/src/mame/seibu/goodejan.cpp b/src/mame/seibu/goodejan.cpp index df600b03edd..39ffa347253 100644 --- a/src/mame/seibu/goodejan.cpp +++ b/src/mame/seibu/goodejan.cpp @@ -324,7 +324,7 @@ void goodejan_state::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, c m_gfxdecode->gfx(0)->prio_transpen(bitmap, cliprect, sprite++, color, - fx, fy, + fx, fy, x + (dx - 1 - ax) * 16, y + ay * 16, screen.priority(), pri, 15); diff --git a/src/mame/skeleton/alphasma3k.cpp b/src/mame/skeleton/alphasma3k.cpp index 9c26782f25e..7457cf56044 100644 --- a/src/mame/skeleton/alphasma3k.cpp +++ b/src/mame/skeleton/alphasma3k.cpp @@ -59,7 +59,7 @@ public: , m_lcdc0(*this, "ks0066_0") , m_lcdc1(*this, "ks0066_1") , m_ram(*this, RAM_TAG) - , m_ipl(*this, "ipl") + , m_ipl(*this, "ipl") { } @@ -78,7 +78,7 @@ protected: virtual void machine_reset() override; private: - void main_map(address_map &map); + void main_map(address_map &map); }; void alphasmart3k_state::machine_start() @@ -97,7 +97,7 @@ void alphasmart3k_state::machine_reset() void alphasmart3k_state::main_map(address_map &map) { // map(0x0000'0000, 0x0003'ffff).ram().share("ram"); - map(0x0040'0000, 0x004f'ffff).rom().region("ipl", 0); + map(0x0040'0000, 0x004f'ffff).rom().region("ipl", 0); } static INPUT_PORTS_START( alphasmart3k ) @@ -109,7 +109,7 @@ void alphasmart3k_state::alphasmart3k(machine_config &config) { // Basic machine hardware MC68EZ328(config, m_maincpu, 16'000'000); // MC68EZ328PU16V, clock unverified - m_maincpu->set_addrmap(AS_PROGRAM, &alphasmart3k_state::main_map); + m_maincpu->set_addrmap(AS_PROGRAM, &alphasmart3k_state::main_map); // Values from AlphaSmart 2000, not confirmed for AlphaSmart 3000 // AlphaSmart 3000 uses a Data Image CM4040 LCD display, LCD is 40x4 according to ref diff --git a/src/mame/skeleton/evolution_handheld.cpp b/src/mame/skeleton/evolution_handheld.cpp index ef3691d2e1b..32adb8ef4d3 100644 --- a/src/mame/skeleton/evolution_handheld.cpp +++ b/src/mame/skeleton/evolution_handheld.cpp @@ -53,13 +53,13 @@ uint32_t evolution_handheldgame_state::screen_update(screen_device &screen, bitm void evolution_handheldgame_state::evolution_map(address_map &map) { - map(0x400000, 0x41ffff).rom().region("maincpu", 0x00000); + map(0x400000, 0x41ffff).rom().region("maincpu", 0x00000); } void evolution_handheldgame_state::evolhh(machine_config &config) { - EVOLUTION_CPU(config, m_maincpu, XTAL(16'000'000)); + EVOLUTION_CPU(config, m_maincpu, XTAL(16'000'000)); m_maincpu->set_addrmap(AS_PROGRAM, &evolution_handheldgame_state::evolution_map); screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); diff --git a/src/mame/subsino/subsino.cpp b/src/mame/subsino/subsino.cpp index acb704b3b1b..32be2cfd700 100644 --- a/src/mame/subsino/subsino.cpp +++ b/src/mame/subsino/subsino.cpp @@ -3287,7 +3287,7 @@ ROM_END - TI TPC1020AFN-084C. - Unpopulated locations on the PCB for a battery and a reset switch. */ ROM_START( newhunter ) - ROM_REGION( 0x4000, "maincpu", 0 ) // The MCU had its surface scratched out, but almost sure it's an HD647180X0CP8L + ROM_REGION( 0x4000, "maincpu", 0 ) // The MCU had its surface scratched out, but almost sure it's an HD647180X0CP8L ROM_LOAD( "hd647180.bin", 0x00000, 0x04000, NO_DUMP ) HD647180X_FAKE_INTERNAL_ROM diff --git a/src/mame/taito/taito_o.cpp b/src/mame/taito/taito_o.cpp index 33eeff0262f..e0e7f699950 100644 --- a/src/mame/taito/taito_o.cpp +++ b/src/mame/taito/taito_o.cpp @@ -183,7 +183,7 @@ Bit 15 : ? machine().bookkeeping().coin_counter_w(2, BIT(data, 2)); // machine().bookkeeping().coin_counter_w(3, BIT(data, 3)); // Games m_hopper->motor_w(BIT(data, 9)); - //logerror("Port a:lines: data:%04x\n", data); + //logerror("Port a:lines: data:%04x\n", data); } } @@ -221,7 +221,7 @@ Bit 14 : paid lamp? (one short pulse after all is paid) */ for (u8 i = 0; i < 16; i++) m_lamps[i] = BIT(data, i); -// logerror("Port b:lamps: data:%04x\n", data); +// logerror("Port b:lamps: data:%04x\n", data); } diff --git a/src/mame/yamaha/ympsr540.cpp b/src/mame/yamaha/ympsr540.cpp index 34831baadfc..7722baab179 100644 --- a/src/mame/yamaha/ympsr540.cpp +++ b/src/mame/yamaha/ympsr540.cpp @@ -53,7 +53,7 @@ void psr540_state::map(address_map &map) { map(0x0000000, 0x003ffff).ram().share(m_boot).unmapw(); map(0x0400000, 0x07fffff).rom().region("program_rom", 0); - map(0x1000000, 0x13fffff).ram(); // dram + map(0x1000000, 0x13fffff).ram(); // dram } static INPUT_PORTS_START( psr540 ) @@ -67,5 +67,5 @@ ROM_START( psr540 ) ROM_LOAD16_WORD_SWAP( "xw25320.ic310", 0, 0x400000, CRC(c7c4736d) SHA1(ff1052eb076557071ed8652e6c2fc0925144fbd5)) ROM_LOAD16_WORD_SWAP( "xw25320.ic310", 0, 0x200000, CRC(9ef56c4e) SHA1(f26b588f9bcfd7bdbf1c0b38e4a1ea57e2f29f10)) ROM_END - + SYST( 1999, psr540, 0, 0, psr540, psr540, psr540_state, empty_init, "Yamaha", "PSR540", MACHINE_IS_SKELETON )