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https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
improve SPARC disassembler: [Vas Crabb]
* Support SPARCv9 * Allow plug-in ASI comments * Fix format of some opcodes * Produce clr synthetic * Allow running in v7, v8 and v9 modes
This commit is contained in:
Vas Crabb
parent
cde8e14fb6
commit
a1625d2220
@ -2378,6 +2378,7 @@ end
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if (CPUS["MB86901"]~=null) then
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files {
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MAME_DIR .. "src/devices/cpu/sparc/mb86901.cpp",
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MAME_DIR .. "src/devices/cpu/sparc/sparcdasm.h",
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MAME_DIR .. "src/devices/cpu/sparc/sparcdefs.h",
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MAME_DIR .. "src/devices/cpu/sparc/sparc.h",
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}
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@ -37,6 +37,7 @@ const int mb86901_device::WINDOW_COUNT = 7;
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mb86901_device::mb86901_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: cpu_device(mconfig, MB86901, "Fujitsu MB86901", tag, owner, clock, "mb86901", __FILE__)
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, m_program_config("program", ENDIANNESS_BIG, 32, 32)
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, m_dasm(7)
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{
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}
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@ -351,8 +352,8 @@ UINT32 mb86901_device::disasm_max_opcode_bytes() const
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offs_t mb86901_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
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{
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extern CPU_DISASSEMBLE( sparc );
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return CPU_DISASSEMBLE_NAME(sparc)(this, buffer, pc, oprom, opram, options);
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UINT32 op = *reinterpret_cast<const UINT32 *>(oprom);
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return m_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(op));
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}
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@ -4,11 +4,13 @@
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SPARC v7 emulator
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*/
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#pragma once
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#ifndef __SPARC_H__
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#define __SPARC_H__
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#pragma once
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#include "sparcdasm.h"
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#define SPARC_NO_TRAP 256
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#define SPARC_RESET 0
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#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1
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@ -142,6 +144,7 @@ protected:
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// debugger helpers
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UINT32 m_dbgregs[24];
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sparc_disassembler m_dasm;
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// address spaces
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address_space *m_program;
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@ -190,6 +193,4 @@ enum
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SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111
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};
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CPU_DISASSEMBLE( sparc );
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#endif /* __SPARC_H__ */
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File diff suppressed because it is too large
Load Diff
201
src/devices/cpu/sparc/sparcdasm.h
Normal file
201
src/devices/cpu/sparc/sparcdasm.h
Normal file
@ -0,0 +1,201 @@
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// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz, Vas Crabb
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/*
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SPARC disassembler
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*/
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#ifndef MAME_DEVICES_CPU_SPARC_SPARC_DASM_H
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#define MAME_DEVICES_CPU_SPARC_SPARC_DASM_H
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#pragma once
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#include <map>
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class sparc_disassembler
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{
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public:
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struct asi_desc
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{
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const char *name = nullptr;
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const char *desc = nullptr;
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};
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typedef std::map<UINT8, asi_desc> asi_desc_map;
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struct state_reg_desc
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{
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bool reserved = false;
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const char *read_name = nullptr;
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const char *write_name = nullptr;
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};
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typedef std::map<UINT8, state_reg_desc> state_reg_desc_map;
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struct prftch_desc
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{
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const char *name = nullptr;
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};
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typedef std::map<UINT8, prftch_desc> prftch_desc_map;
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sparc_disassembler(unsigned version);
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template <typename T> void add_state_reg_desc(const T &desc)
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{
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for (const auto &it : desc)
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{
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auto ins = m_state_reg_desc.insert(it);
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if (!ins.second)
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{
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ins.first->second.reserved = it.second.reserved;
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if (it.second.read_name)
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ins.first->second.read_name = it.second.read_name;
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if (it.second.write_name)
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ins.first->second.write_name = it.second.write_name;
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}
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}
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}
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template <typename T> void add_asi_desc(const T &desc)
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{
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// TODO: support ranges
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for (const auto &it : desc)
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{
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auto ins = m_asi_desc.insert(it);
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if (!ins.second)
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{
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if (it.second.name)
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ins.first->second.name = it.second.name;
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if (it.second.desc)
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ins.first->second.desc = it.second.desc;
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}
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}
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}
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template <typename T> void add_prftch_desc(const T &desc)
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{
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for (const auto &it : desc)
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{
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auto ins = m_prftch_desc.insert(it);
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if (!ins.second)
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{
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if (it.second.name)
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ins.first->second.name = it.second.name;
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}
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}
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}
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offs_t dasm(char *buf, offs_t pc, UINT32 op) const;
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private:
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struct branch_desc
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{
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INT32 (*get_disp)(UINT32 op);
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int disp_width;
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bool use_pred, use_cc;
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const char *reg_cc[4];
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const char *mnemonic[16];
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};
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struct int_op_desc
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{
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unsigned min_version;
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bool hex_imm;
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const char *mnemonic;
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};
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typedef std::map<UINT8, int_op_desc> int_op_desc_map;
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struct fpop1_desc
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{
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bool three_op = true;
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bool rs1_shift = false;
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bool rs2_shift = false;
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bool rd_shift = false;
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const char *mnemonic = nullptr;
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};
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typedef std::map<UINT16, fpop1_desc> fpop1_desc_map;
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struct fpop2_desc
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{
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bool int_rs1 = false;
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bool shift = false;
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const char *mnemonic = nullptr;
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};
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typedef std::map<UINT16, fpop2_desc> fpop2_desc_map;
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struct ldst_desc
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{
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bool rd_first = false;
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bool alternate = false;
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char rd_alt_reg = '\0';
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bool rd_shift = false;
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const char *mnemonic = nullptr;
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const char *g0_synth = nullptr;
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};
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typedef std::map<UINT8, ldst_desc> ldst_desc_map;
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offs_t dasm_invalid(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_branch(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_shift(char *buf, offs_t pc, UINT32 op, const char *mnemonic, const char *mnemonicx, const char *mnemonicx0) const;
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offs_t dasm_read_state_reg(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_write_state_reg(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_move_cond(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_move_reg_cond(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_fpop1(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_fpop2(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_jmpl(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_return(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_tcc(char *buf, offs_t pc, UINT32 op) const;
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offs_t dasm_ldst(char *buf, offs_t pc, UINT32 op) const;
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void dasm_address(char *&output, UINT32 op) const;
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void dasm_asi(char *&output, UINT32 op) const;
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void dasm_asi_comment(char *&output, UINT32 op) const;
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UINT32 freg(UINT32 val, bool shift) const;
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template <typename T> void add_fpop1_desc(const T &desc);
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template <typename T> void add_fpop2_desc(const T &desc);
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template <typename T> void add_ldst_desc(const T &desc);
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void pad_op_field(char *buf, char *&output) const;
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ATTR_PRINTF(2, 3) static void print(char *&output, const char *fmt, ...);
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static const char * const REG_NAMES[32];
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static const branch_desc EMPTY_BRANCH_DESC;
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static const branch_desc BPCC_DESC;
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static const branch_desc BICC_DESC;
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static const branch_desc BPR_DESC;
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static const branch_desc FBPFCC_DESC;
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static const branch_desc FBFCC_DESC;
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static const branch_desc CBCCC_DESC;
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static const int_op_desc_map::value_type SIMPLE_INT_OP_DESC[];
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static const state_reg_desc_map::value_type V9_STATE_REG_DESC[];
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static const char * const MOVCC_CC_NAMES[8];
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static const char * const MOVCC_COND_NAMES[32];
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static const char * const MOVE_INT_COND_MNEMONICS[8];
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static const char * const V9_PRIV_REG_NAMES[32];
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static const fpop1_desc_map::value_type V7_FPOP1_DESC[];
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static const fpop1_desc_map::value_type V9_FPOP1_DESC[];
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static const fpop2_desc_map::value_type V7_FPOP2_DESC[];
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static const fpop2_desc_map::value_type V9_FPOP2_DESC[];
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static const ldst_desc_map::value_type V7_LDST_DESC[];
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static const ldst_desc_map::value_type V9_LDST_DESC[];
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static const asi_desc_map::value_type V9_ASI_DESC[];
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static const prftch_desc_map::value_type V9_PRFTCH_DESC[];
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unsigned m_version;
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int m_op_field_width;
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branch_desc m_branch_desc[8];
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int_op_desc_map m_simple_int_op_desc;
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state_reg_desc_map m_state_reg_desc;
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fpop1_desc_map m_fpop1_desc;
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fpop2_desc_map m_fpop2_desc;
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ldst_desc_map m_ldst_desc;
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asi_desc_map m_asi_desc;
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prftch_desc_map m_prftch_desc;
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};
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CPU_DISASSEMBLE( sparcv7 );
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CPU_DISASSEMBLE( sparcv8 );
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CPU_DISASSEMBLE( sparcv9 );
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#endif // MAME_DEVICES_CPU_SPARC_SPARC_DASM_H
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@ -83,20 +83,39 @@
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#define OP2 ((op >> 22) & 7)
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#define OP3 ((op >> 19) & 63)
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#define OPF ((op >> 5) & 0x1ff)
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#define OPC ((op >> 5) & 0x1ff)
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#define OPFLOW ((op >> 5) & 0x3f)
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#define DISP30 (op << 2)
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#define DISP22 (((INT32)(op << 10)) >> 8)
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#define DISP30 (INT32(op << 2))
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#define DISP22 (INT32(op << 10) >> 8)
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#define DISP19 (INT32(op << 13) >> 11)
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#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14)
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#define IMM22 (op << 10)
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#define CONST22 (op & 0x3fffff)
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#define SIMM13 (((INT32)(op << 19)) >> 19)
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#define SIMM13 (INT32(op << 19) >> 19)
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#define SIMM11 (INT32(op << 21) >> 21)
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#define SIMM10 (INT32(op << 22) >> 22)
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#define IMM7 (op & 0x7f)
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#define SIMM7 (((INT32)(op << 25)) >> 25)
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#define OPIMM (op & 0x00002000)
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#define SIMM7 (INT32(op << 25) >> 25)
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#define SIMM8 (INT32(op << 24) >> 24)
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#define SHCNT32 (op & 31)
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#define SHCNT64 (op & 63)
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#define USEIMM ((op >> 13) & 1)
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#define USEEXT ((op >> 12) & 1)
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#define COND ((op >> 25) & 15)
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#define RCOND ((op >> 10) & 7)
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#define MOVCOND ((op >> 14) & 15)
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#define PRED ((op >> 19) & 1)
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#define ANNUL ((op >> 29) & 1)
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#define ASI ((op >> 5) & 0xff)
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#define BRCC ((op >> 20) & 3)
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#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4))
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#define OPFCC ((op >> 11) & 7)
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#define TCCCC ((op >> 11) & 3)
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#define ASI ((op >> 5) & 255)
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#define MMASK (op & 15)
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#define CMASK ((op >> 4) & 7)
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#define RD ((op >> 25) & 31)
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#define RS1 ((op >> 14) & 31)
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@ -107,7 +126,7 @@
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#define RS1REG *m_regs[RS1]
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#define RS2REG *m_regs[RS2]
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#define SET_RDREG(x) if(RD) { RDREG = x; }
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#define ADDRESS (OPIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
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#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
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#define PC m_pc
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#define nPC m_npc
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