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Small mods for am_mg3 and mg24, they won't boot tho

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This commit is contained in:
Angelo Salese 2012-04-22 21:58:42 +00:00
parent 0ffbc7ee48
commit a19003ca09
1 changed files with 138 additions and 27 deletions
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165
src/mame/drivers/amaticmg.c
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@ -404,6 +404,9 @@ public:
required_shared_ptr<UINT8> m_vram; required_shared_ptr<UINT8> m_vram;
DECLARE_WRITE8_MEMBER(rombank_w); DECLARE_WRITE8_MEMBER(rombank_w);
DECLARE_WRITE8_MEMBER(nmi_mask_w);
UINT8 m_nmi_mask;
}; };
@ -441,6 +444,31 @@ static SCREEN_UPDATE_IND16( amaticmg )
return 0; return 0;
} }
static SCREEN_UPDATE_IND16( amaticmg3 )
{
amaticmg_state *state = screen.machine().driver_data<amaticmg_state>();
const gfx_element *gfx = screen.machine().gfx[0];
int y,x;
int count = 0;
for (y=0;y<32;y++)
{
for (x=0;x<96;x++)
{
UINT16 tile = state->m_vram[count];
UINT8 color;
tile += ((state->m_attr[count]&0xff)<<8);
color = 0;
drawgfx_opaque(bitmap,cliprect,gfx,tile,color,0,0,x*4,y*8);
count++;
}
}
return 0;
}
static PALETTE_INIT( amaticmg ) static PALETTE_INIT( amaticmg )
{ {
const UINT8 *color_prom = machine.root_device().memregion("proms")->base(); const UINT8 *color_prom = machine.root_device().memregion("proms")->base();
@ -494,6 +522,12 @@ WRITE8_MEMBER( amaticmg_state::rombank_w )
membank("bank1")->set_entry(data & 0xf); membank("bank1")->set_entry(data & 0xf);
} }
WRITE8_MEMBER( amaticmg_state::nmi_mask_w )
{
m_nmi_mask = (data & 1) ^ 1;
}
/************************************ /************************************
* Memory Map Information * * Memory Map Information *
************************************/ ************************************/
@ -512,7 +546,7 @@ static ADDRESS_MAP_START( amaticmg_portmap, AS_IO, 8, amaticmg_state )
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write) AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
AM_RANGE(0x40, 0x41) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w) AM_RANGE(0x40, 0x41) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w)
AM_RANGE(0x60, 0x60) AM_DEVWRITE("crtc", mc6845_device, address_w) AM_RANGE(0x60, 0x60) AM_DEVWRITE("crtc", mc6845_device, address_w)
AM_RANGE(0x61, 0x61) AM_DEVWRITE("crtc", mc6845_device, register_w) AM_RANGE(0x61, 0x61) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
AM_RANGE(0xc0, 0xc0) AM_WRITE(rombank_w) AM_RANGE(0xc0, 0xc0) AM_WRITE(rombank_w)
// AM_RANGE(0x00, 0x00) AM_DEVREADWRITE_LEGACY("ppi8255_2", ppi8255_r, ppi8255_w) // AM_RANGE(0x00, 0x00) AM_DEVREADWRITE_LEGACY("ppi8255_2", ppi8255_r, ppi8255_w)
// AM_RANGE(0x00, 0x00) AM_DEVWRITE_LEGACY("dac1", dac_signed_w) // AM_RANGE(0x00, 0x00) AM_DEVWRITE_LEGACY("dac1", dac_signed_w)
@ -520,6 +554,19 @@ static ADDRESS_MAP_START( amaticmg_portmap, AS_IO, 8, amaticmg_state )
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( amaticmg3_portmap, AS_IO, 8, amaticmg_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
// ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write)
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
AM_RANGE(0x40, 0x41) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w)
AM_RANGE(0x60, 0x60) AM_DEVWRITE("crtc", mc6845_device, address_w)
AM_RANGE(0x61, 0x61) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
AM_RANGE(0xc0, 0xc0) AM_WRITE(rombank_w)
AM_RANGE(0xe6, 0xe6) AM_WRITE(nmi_mask_w)
ADDRESS_MAP_END
/* /*
Unknown R/W Unknown R/W
----------- -----------
@ -534,34 +581,82 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( amaticmg ) static INPUT_PORTS_START( amaticmg )
PORT_START("IN0") PORT_START("IN0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-1") PORT_CODE(KEYCODE_1) PORT_DIPNAME( 0x01, 0x01, "IN0")
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-2") PORT_CODE(KEYCODE_2) PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-3") PORT_CODE(KEYCODE_3) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-4") PORT_CODE(KEYCODE_4) PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-5") PORT_CODE(KEYCODE_5) PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-6") PORT_CODE(KEYCODE_6) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-7") PORT_CODE(KEYCODE_7) PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0-8") PORT_CODE(KEYCODE_8) PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("IN1") PORT_START("IN1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-1") PORT_CODE(KEYCODE_Q) PORT_DIPNAME( 0x01, 0x01, "IN1")
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-2") PORT_CODE(KEYCODE_W) PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-3") PORT_CODE(KEYCODE_E) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-4") PORT_CODE(KEYCODE_R) PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-5") PORT_CODE(KEYCODE_T) PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-6") PORT_CODE(KEYCODE_Y) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-7") PORT_CODE(KEYCODE_U) PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1-8") PORT_CODE(KEYCODE_I) PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("IN2") PORT_START("IN2")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-1") PORT_CODE(KEYCODE_A) PORT_DIPNAME( 0x01, 0x01, "IN2")
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-2") PORT_CODE(KEYCODE_S) PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-3") PORT_CODE(KEYCODE_D) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-4") PORT_CODE(KEYCODE_F) PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-5") PORT_CODE(KEYCODE_G) PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-6") PORT_CODE(KEYCODE_H) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-7") PORT_CODE(KEYCODE_J) PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2-8") PORT_CODE(KEYCODE_K) PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("IN3") PORT_START("IN3")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3-1") PORT_CODE(KEYCODE_Z) PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3-1") PORT_CODE(KEYCODE_Z)
@ -574,7 +669,7 @@ static INPUT_PORTS_START( amaticmg )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3-8") PORT_CODE(KEYCODE_L) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3-8") PORT_CODE(KEYCODE_L)
PORT_START("SW1") PORT_START("SW1")
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPNAME( 0x01, 0x01, "SW1")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
@ -697,7 +792,7 @@ static MACHINE_START( amaticmg )
{ {
UINT8 *rombank = machine.root_device().memregion("maincpu")->base(); UINT8 *rombank = machine.root_device().memregion("maincpu")->base();
machine.root_device().membank("bank1")->configure_entries(0, 7, &rombank[0x8000], 0x4000); machine.root_device().membank("bank1")->configure_entries(0, 0x10, &rombank[0x8000], 0x4000);
} }
static MACHINE_RESET( amaticmg ) static MACHINE_RESET( amaticmg )
@ -705,6 +800,7 @@ static MACHINE_RESET( amaticmg )
amaticmg_state *state = machine.driver_data<amaticmg_state>(); amaticmg_state *state = machine.driver_data<amaticmg_state>();
state->membank("bank1")->set_entry(0); state->membank("bank1")->set_entry(0);
state->m_nmi_mask = 0;
} }
/************************************ /************************************
@ -756,8 +852,23 @@ static MACHINE_CONFIG_START( amaticmg, amaticmg_state )
MACHINE_CONFIG_END MACHINE_CONFIG_END
static INTERRUPT_GEN( amaticmg3_irq )
{
amaticmg_state *state = device->machine().driver_data<amaticmg_state>();
if(state->m_nmi_mask)
device_set_input_line(device, INPUT_LINE_NMI, PULSE_LINE);
}
static MACHINE_CONFIG_DERIVED( amaticmg3, amaticmg ) static MACHINE_CONFIG_DERIVED( amaticmg3, amaticmg )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_IO_MAP(amaticmg3_portmap)
MCFG_CPU_VBLANK_INT("screen", amaticmg3_irq)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_STATIC(amaticmg3)
MCFG_GFXDECODE(amaticmg3) MCFG_GFXDECODE(amaticmg3)
MCFG_PALETTE_INIT(amaticmg3) MCFG_PALETTE_INIT(amaticmg3)
MCFG_PALETTE_LENGTH(0x10000) MCFG_PALETTE_LENGTH(0x10000)