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SCC: Improved LOG printouts for synchrounous features of WR4 and WR10

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This commit is contained in:
Joakim Larsson Edstrom 2016-11-04 12:00:21 +01:00
parent 96802e527f
commit a23be114ea
2 changed files with 62 additions and 31 deletions
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28
src/devices/machine/z80scc.cpp
View File

@ -78,7 +78,7 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
/* Useful temporary debug printout format */
// printf("TAG %lld %s%s Data:%d\n", machine().firstcpu->total_cycles(), __PRETTY_FUNCTION__, m_owner->tag(), data);
#define VERBOSE 0
#define VERBOSE 2
#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
#define LOG(x) {} LOGPRINT(x)
#define LOGR(x) {} LOGPRINT(x)
@ -1827,10 +1827,14 @@ void z80scc_channel::do_sccreg_wr4(uint8_t data)
else
{
m_wr4 = data;
LOG(("- Parity Enable %u\n", (data & WR4_PARITY_ENABLE) ? 1 : 0));
LOG(("- Parity %s\n", (data & WR4_PARITY_EVEN) ? "Even" : "Odd"));
LOG(("- Stop Bits %s\n", stop_bits_tostring(get_stop_bits())));
LOG(("- Clock Mode %uX\n", get_clock_mode()));
LOG(("- Parity : %s\n", (data & WR4_PARITY_ENABLE) ? ((data & WR4_PARITY_EVEN) ? "Even" : "Odd") : "None"));
LOG(("- Stop Bits : %s\n", data & WR4_STOP_BITS_MASK ? stop_bits_tostring(get_stop_bits()) : "not used, sync modes enabled" ));
LOG(("- Sync Mode : %s\n", !(data & WR4_STOP_BITS_MASK) ?
(data & WR4_BIT5 ?
(data & WR4_BIT4 ? "External - not implemented" : "SDLC - not implemented")
: (data & WR4_BIT4 ? "16 bit" : "8 bit"))
: "Disabled"));
LOG(("- Clock Mode: %uX\n", get_clock_mode()));
update_serial();
safe_transmit_register_reset();
receive_register_reset();
@ -1924,13 +1928,21 @@ void z80scc_channel::do_sccreg_wr9(uint8_t data)
}
}
/* WR10 contains miscellaneous control bits for both the receiver and the transmitter. Bit positions
for WR10 are displayed in Figure . On the ESCC and 85C30 with the Extended Read option
enabled, this register may be read as RR11.*/
/* WR10 contains miscellaneous control bits for both the receiver and the transmitter.
On the ESCC and 85C30 with the Extended Read option enabled, this register may be read as RR11.*/
void z80scc_channel::do_sccreg_wr10(uint8_t data)
{
m_wr10 = data;
LOG(("\"%s\": %c : %s Misc Tx/Rx Control %02x - not implemented \n", m_owner->tag(), 'A' + m_index, FUNCNAME, data));
LOG(("- 6/8 bit sync %d\n", data & WR10_8_6_BIT_SYNC ? 1 : 0));
LOG(("- Loop Mode %d\n", data & WR10_LOOP_MODE ? 1 : 0));
LOG(("- Abort/Flag on underrun %d\n", data & WR10_ABORT_FLAG_UNDERRUN ? 1 : 0));
LOG(("- Mark/Flag Idle line %d\n", data & WR10_MARK_FLAG_IDLE ? 1 : 0));
LOG(("- Go active on poll %d\n", data & WR10_GO_ACTIVE_ON_POLL ? 1 : 0));
LOG(("- Encoding %s\n", data & WR10_BIT6 ?
(data & WR10_BIT5 ? "FM0" : "FM1") :
(data & WR10_BIT5 ? "NRZI" : "NRZ") ));
LOG(("- CRC Preset %d\n", data & WR10_CRC_PRESET ? 1 : 0));
}
/* WR11 is the Clock Mode Control register. The bits in this register control the sources of both the

65
src/devices/machine/z80scc.h
View File

@ -409,20 +409,20 @@ protected:
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL_PARITY = 0x10,
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
WR1_WRDY_ON_RX_TX = 0x20,
WR1_WRDY_FUNCTION = 0x40,
WR1_WRDY_ENABLE = 0x80
};
enum
{
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02, // not supported
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02,
WR3_ADDRESS_SEARCH_MODE = 0x04,
WR3_RX_CRC_ENABLE = 0x08,
WR3_ENTER_HUNT_PHASE = 0x10,
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
@ -437,13 +437,15 @@ protected:
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_1_5 = 0x08,
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_SYNC_MODE_MASK = 0x30,
WR4_SYNC_MODE_8_BIT = 0x00,
WR4_SYNC_MODE_16_BIT = 0x10,
WR4_BIT4 = 0x10,
WR4_SYNC_MODE_SDLC = 0x20,
WR4_BIT5 = 0x20,
WR4_SYNC_MODE_EXT = 0x30,
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
@ -453,11 +455,11 @@ protected:
enum
{
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_CRC_ENABLE = 0x01,
WR5_RTS = 0x02,
WR5_CRC16 = 0x04,
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
@ -479,14 +481,31 @@ protected:
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
};
enum
{
WR10_8_6_BIT_SYNC = 0x01,
WR10_LOOP_MODE = 0x02,
WR10_ABORT_FLAG_UNDERRUN = 0x04,
WR10_MARK_FLAG_IDLE = 0x08,
WR10_GO_ACTIVE_ON_POLL = 0x10,
WR10_ENCODING_MASK = 0x60,
WR10_NRZ_ENCODING = 0x00,
WR10_NRZI_ENCODING = 0x20,
WR10_BIT5 = 0x20,
WR10_FM1_ENCODING = 0x40,
WR10_BIT6 = 0x40,
WR10_FM0_ENCODING = 0x60,
WR10_CRC_PRESET = 0x80
};
enum
{
WR11_RCVCLK_TYPE = 0x80,