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https://github.com/holub/mame
synced 2025-04-26 18:23:08 +03:00
apple2: simplify LC handling even further (nw)
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7e9e3f5b4d
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a23d008d86
@ -31,13 +31,13 @@ const device_type A2BUS_RAMCARD16K = device_creator<a2bus_ramcard_device>;
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a2bus_ramcard_device::a2bus_ramcard_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
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device_t(mconfig, type, name, tag, owner, clock, shortname, source),
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device_a2bus_card_interface(mconfig, *this), m_inh_state(0), m_last_offset(0), m_last_access(0), m_dxxx_bank(0)
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device_a2bus_card_interface(mconfig, *this), m_inh_state(0), m_prewrite(false), m_dxxx_bank(0)
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{
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}
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a2bus_ramcard_device::a2bus_ramcard_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, A2BUS_RAMCARD16K, "Apple II 16K Language Card", tag, owner, clock, "a2ram16k", __FILE__),
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device_a2bus_card_interface(mconfig, *this), m_inh_state(0), m_last_offset(0), m_last_access(0), m_dxxx_bank(0)
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device_a2bus_card_interface(mconfig, *this), m_inh_state(0), m_prewrite(false), m_dxxx_bank(0)
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{
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}
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@ -55,51 +55,63 @@ void a2bus_ramcard_device::device_start()
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save_item(NAME(m_inh_state));
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save_item(NAME(m_ram));
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save_item(NAME(m_dxxx_bank));
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save_item(NAME(m_last_offset));
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save_item(NAME(m_last_access));
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save_item(NAME(m_prewrite));
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}
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void a2bus_ramcard_device::device_reset()
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{
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m_inh_state = INH_WRITE;
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m_dxxx_bank = 0;
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m_last_offset = -1;
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m_last_access = 0;
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m_prewrite = false;
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}
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void a2bus_ramcard_device::do_io(int offset, int access)
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void a2bus_ramcard_device::do_io(int offset, bool writing)
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{
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int old_inh_state = m_inh_state;
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m_inh_state = INH_NONE;
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//any even access disables pre-write and writing
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if ((offset & 1) == 0)
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{
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m_prewrite = false;
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m_inh_state &= ~INH_WRITE;
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}
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//any write disables pre-write
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//has no effect on write-enable if writing was enabled already
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if (writing == true)
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{
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m_prewrite = false;
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}
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//first odd read enables pre-write, second one enables writing
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else if ((offset & 1) == 1)
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{
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if (m_prewrite == false)
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{
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m_prewrite = true;
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}
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else
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{
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m_inh_state |= INH_WRITE;
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}
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}
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switch (offset & 3)
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{
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case 0:
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case 3:
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{
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m_inh_state = INH_READ;
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m_inh_state |= INH_READ;
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break;
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}
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case 3:
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{
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m_inh_state = INH_READ;
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} //fall through
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case 1:
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case 2:
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{
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//if accessed twice, then write-enable
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if (((m_last_offset & 1) == 1) && (access == m_last_access))
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{
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m_inh_state |= INH_WRITE;
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}
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m_inh_state &= ~INH_READ;
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break;
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}
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}
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m_last_offset = offset;
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m_last_access = access;
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m_dxxx_bank = 0;
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if (!(offset & 8))
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@ -127,7 +139,7 @@ void a2bus_ramcard_device::do_io(int offset, int access)
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uint8_t a2bus_ramcard_device::read_c0nx(address_space &space, uint8_t offset)
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{
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do_io(offset & 0xf, 0);
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do_io(offset & 0xf, false);
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return 0xff;
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}
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@ -138,7 +150,7 @@ uint8_t a2bus_ramcard_device::read_c0nx(address_space &space, uint8_t offset)
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void a2bus_ramcard_device::write_c0nx(address_space &space, uint8_t offset, uint8_t data)
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{
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do_io(offset & 0xf, 1);
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do_io(offset & 0xf, true);
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}
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uint8_t a2bus_ramcard_device::read_inh_rom(address_space &space, uint16_t offset)
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@ -40,11 +40,10 @@ protected:
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virtual int inh_type() override;
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private:
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void do_io(int offset, int access);
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void do_io(int offset, bool writing);
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int m_inh_state;
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int m_last_offset;
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int m_last_access;
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bool m_prewrite;
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int m_dxxx_bank;
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uint8_t m_ram[16*1024];
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};
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@ -369,8 +369,7 @@ private:
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bool m_slotc3rom;
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bool m_altzp;
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bool m_ramrd, m_ramwrt;
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bool m_lcram, m_lcram2, m_lcwriteenable;
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int m_last_offset, m_last_access;
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bool m_lcram, m_lcram2, m_lcprewrite, m_lcwriteenable;
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bool m_ioudis;
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bool m_romswitch;
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bool m_mockingboard4c;
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@ -402,7 +401,7 @@ private:
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void do_io(address_space &space, int offset, bool is_iic);
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uint8_t read_floatingbus();
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void update_slotrom_banks();
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void lc_update(int offset, int access);
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void lc_update(int offset, bool writing);
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uint8_t read_slot_rom(address_space &space, int slotbias, int offset);
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void write_slot_rom(address_space &space, int slotbias, int offset, uint8_t data);
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uint8_t read_int_rom(address_space &space, int slotbias, int offset);
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@ -702,9 +701,8 @@ void apple2e_state::machine_start()
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save_item(NAME(m_exp_addrmask));
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save_item(NAME(m_lcram));
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save_item(NAME(m_lcram2));
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save_item(NAME(m_lcprewrite));
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save_item(NAME(m_lcwriteenable));
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save_item(NAME(m_last_offset));
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save_item(NAME(m_last_access));
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save_item(NAME(m_mockingboard4c));
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save_item(NAME(m_intc8rom));
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}
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@ -760,9 +758,8 @@ void apple2e_state::machine_reset()
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// LC default state: read ROM, write enabled, Dxxx bank 2
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m_lcram = false;
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m_lcram2 = true;
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m_lcprewrite = false;
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m_lcwriteenable = true;
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m_last_offset = -1;
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m_last_access = 0;
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m_exp_bankhior = 0xf0;
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@ -1012,40 +1009,53 @@ void apple2e_state::update_slotrom_banks()
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}
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}
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void apple2e_state::lc_update(int offset, int access)
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void apple2e_state::lc_update(int offset, bool writing)
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{
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bool old_lcram = m_lcram;
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m_lcram = false;
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m_lcwriteenable = false;
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//any even access disables pre-write and writing
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if ((offset & 1) == 0)
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{
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m_lcprewrite = false;
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m_lcwriteenable = false;
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}
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//any write disables pre-write
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//has no effect on write-enable if writing was enabled already
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if (writing == true)
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{
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m_lcprewrite = false;
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}
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//first odd read enables pre-write, second one enables writing
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else if ((offset & 1) == 1)
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{
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if (m_lcprewrite == false)
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{
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m_lcprewrite = true;
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}
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else
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{
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m_lcwriteenable = true;
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}
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}
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switch (offset & 3)
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{
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case 0:
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case 3:
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{
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m_lcram = true;
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break;
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}
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case 3:
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{
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m_lcram = true;
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} //fall through
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case 1:
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case 2:
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{
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//if accessed twice, then write-enable
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if (((m_last_offset & 1) == 1) && (access == m_last_access))
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{
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m_lcwriteenable = true;
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}
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m_lcram = false;
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break;
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}
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}
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m_last_offset = offset;
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m_last_access = access;
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m_lcram2 = false;
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if (!(offset & 8))
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@ -1865,7 +1875,7 @@ READ8_MEMBER(apple2e_state::c080_r)
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if (slot == 0)
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{
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lc_update(offset & 0xf, 0);
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lc_update(offset & 0xf, false);
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}
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else
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{
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@ -1888,7 +1898,7 @@ WRITE8_MEMBER(apple2e_state::c080_w)
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if (slot == 0)
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{
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lc_update(offset & 0xf, 1);
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lc_update(offset & 0xf, true);
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}
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else
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{
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