mirror of
https://github.com/holub/mame
synced 2025-07-01 08:18:59 +03:00
rii: Many updates
- Identify CPU type used by vreadere as ePG3231 - Add preliminary port I/O handlers and callbacks - Add stub handlers and state variables for interrupt controller, timers, synthesizer, UART and SPI - Fix TBRD addressing of external data memory - Fix calculation of carry flag for normal additive operations - Implement multi-byte carry/borrow for applicable registers - Implement signed multiplication option - Add internal stack buffer for saving PCH during calls/interrupts
This commit is contained in:
parent
a73d55f52e
commit
a24caaede8
@ -16,8 +16,8 @@ using osd::u32;
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using util::BIT;
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using offs_t = u32;
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// FIXME: this set is an amalgam of ePG3231-EM202, EPD3332 and EPD3338
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const char *const riscii_disassembler::s_regs[0x60] =
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// TODO: add register sets for other models
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const char *const epg3231_disassembler::s_regs[0x60] =
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{
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"INDF0", "FSR0", "PCL", "PCM", "PCH", "BSR", "STKPTR", "BSR1",
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"INDF1", "FSR1", "ACC", "TABPTRL", "TABPTRM", "TABPTRH", "CPUCON", "STATUS",
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@ -27,8 +27,8 @@ const char *const riscii_disassembler::s_regs[0x60] =
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"TR2CON", "TRLIR", nullptr, "POST_ID", "ADCON", "PAINTEN", "PAINTSTA", "PAWAKE",
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"UARTCON", "UARTSTA", "PORTJ", "PORTK", "DCRB", "DCRC", "DCRDE", "DCRFG",
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"DCRHI", "DCRJK", "PBCON", "PCCON", "PLLF", "T0CL", "T0CH", "SPICON",
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"SPISTA", "SPRL", "SPRM", "SPRH", "SFCR", "ADDL1~ADDL4", "ADDM1~ADDM4", "ADDH1~ADDH4",
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"ENV1~4/SPHDR", "MTCON1~4/SPHTCON", "MTRL1~4/SPHTRL", "VOCON", "TR1C", "TR2C", "ADCF", nullptr,
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"SPISTA", "SPRL", "SPRM", "SPRH", "SFCR", "ADDL", "ADDM", "ADDH",
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"ENV/SPHDR", "MTCON/SPHTCON", "MTRL/SPHTRL", "VOCON", "TR1C", "TR2C", "ADCF", nullptr,
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr,
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr
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};
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@ -8,9 +8,6 @@
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class riscii_disassembler : public util::disasm_interface
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{
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public:
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riscii_disassembler() : riscii_disassembler(s_regs) { }
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protected:
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// construction/destruction
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riscii_disassembler(const char *const regs[]);
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@ -31,4 +28,13 @@ private:
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const char *const *m_regs;
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};
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class epg3231_disassembler : public riscii_disassembler
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{
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public:
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epg3231_disassembler() : riscii_disassembler(s_regs) { }
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private:
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static const char *const s_regs[0x60];
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};
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#endif // MAME_CPU_RII_RIIDASM_H
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File diff suppressed because it is too large
Load Diff
@ -30,16 +30,60 @@ public:
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RII_CPUCON,
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RII_STATUS,
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RII_PROD,
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RII_POST_ID
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RII_PFS,
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RII_INTCON,
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RII_INTSTA,
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RII_POST_ID,
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RII_PORTB, RII_PORTC, RII_PORTD, RII_PORTE, RII_PORTF, RII_PORTG, RII_PORTH, RII_PORTI, RII_PORTJ, RII_PORTK,
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RII_STBCON,
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RII_PAINTEN, RII_PAINTSTA, RII_PAWAKE,
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RII_DCRB, RII_DCRC, RII_DCRDE, RII_DCRFG, RII_DCRHI, RII_DCRJK,
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RII_PBCON, RII_PCCON,
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RII_UARTCON, RII_UARTSTA,
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RII_SPICON, RII_SPISTA,
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RII_TRL0, RII_TRL1, RII_TRL2,
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RII_TR01CON,
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RII_TR2CON,
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RII_TRLIR,
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RII_SFCR,
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RII_ADD1, RII_ADD2, RII_ADD3, RII_ADD4,
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RII_ENV1, RII_ENV2, RII_ENV3, RII_ENV4,
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RII_MTCON1, RII_MTCON2, RII_MTCON3, RII_MTCON4,
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RII_MTRL1, RII_MTRL2, RII_MTRL3, RII_MTRL4,
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RII_SPHDR,
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RII_SPHTCON,
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RII_SPHTRL,
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RII_VOCON
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};
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// construction/destruction
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riscii_series_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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// callback configuration
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auto in_porta_cb() { return m_porta_in_cb.bind(); }
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auto in_portb_cb() { return m_port_in_cb[0].bind(); }
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auto out_portb_cb() { return m_port_out_cb[0].bind(); }
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auto in_portc_cb() { return m_port_in_cb[1].bind(); }
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auto out_portc_cb() { return m_port_out_cb[1].bind(); }
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auto in_portd_cb() { return m_port_in_cb[2].bind(); }
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auto out_portd_cb() { return m_port_out_cb[2].bind(); }
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auto in_porte_cb() { return m_port_in_cb[3].bind(); }
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auto out_porte_cb() { return m_port_out_cb[3].bind(); }
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auto in_portf_cb() { return m_port_in_cb[4].bind(); }
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auto out_portf_cb() { return m_port_out_cb[4].bind(); }
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auto in_portg_cb() { return m_port_in_cb[5].bind(); }
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auto out_portg_cb() { return m_port_out_cb[5].bind(); }
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auto in_porth_cb() { return m_port_in_cb[6].bind(); }
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auto out_porth_cb() { return m_port_out_cb[6].bind(); }
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auto in_porti_cb() { return m_port_in_cb[7].bind(); }
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auto out_porti_cb() { return m_port_out_cb[7].bind(); }
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auto in_portj_cb() { return m_port_in_cb[8].bind(); }
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auto out_portj_cb() { return m_port_out_cb[8].bind(); }
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auto in_portk_cb() { return m_port_in_cb[9].bind(); }
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auto out_portk_cb() { return m_port_out_cb[9].bind(); }
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protected:
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riscii_series_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, unsigned prgbits, unsigned bankbits, uint8_t maxbank);
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riscii_series_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, unsigned addrbits, unsigned pcbits, u32 datastart, unsigned bankbits, u8 maxbank, u8 post_id_mask, address_map_constructor regs);
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// device-level overrides
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virtual void device_resolve_objects() override;
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virtual void device_start() override;
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virtual void device_reset() override;
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@ -47,16 +91,14 @@ protected:
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virtual void execute_run() override;
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virtual void execute_set_input(int inputnum, int state) override;
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// device_disasm_interface overrides
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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// device_state_interface overrides
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virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
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private:
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void core_regs_map(address_map &map);
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// register handlers
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u8 fsr0_r();
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void fsr0_w(u8 data);
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@ -90,12 +132,92 @@ private:
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void prodl_w(u8 data);
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u8 prodh_r();
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void prodh_w(u8 data);
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u8 pfs_r();
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void pfs_w(u8 data);
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u8 intcon_r();
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void intcon_w(u8 data);
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u8 intsta_r();
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void intsta_w(u8 data);
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u8 post_id_r();
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void post_id_w(u8 data);
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u8 porta_r();
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u8 port_r(offs_t offset);
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void port_w(offs_t offset, u8 data);
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u8 stbcon_r();
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void stbcon_w(u8 data);
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u8 painten_r();
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void painten_w(u8 data);
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u8 paintsta_r();
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void paintsta_w(u8 data);
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u8 pawake_r();
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void pawake_w(u8 data);
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u8 portjk_r(offs_t offset);
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void portjk_w(offs_t offset, u8 data);
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u8 dcr_r(offs_t offset);
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void dcr_w(offs_t offset, u8 data);
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u8 pcon_r(offs_t offset);
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void pcon_w(offs_t offset, u8 data);
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void uarttx_w(u8 data);
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u8 uartrx_r();
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u8 uartcon_r();
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void uartcon_w(u8 data);
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u8 uartsta_r();
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void uartsta_w(u8 data);
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u8 spicon_r();
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void spicon_w(u8 data);
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u8 spista_r();
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void spista_w(u8 data);
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u8 sprl_r();
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void sprl_w(u8 data);
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u8 sprm_r();
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void sprm_w(u8 data);
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u8 sprh_r();
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void sprh_w(u8 data);
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u8 trl0l_r();
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void trl0l_w(u8 data);
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u8 trl0h_r();
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void trl0h_w(u8 data);
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u8 trl1_r();
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void trl1_w(u8 data);
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u8 trl2_r();
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void trl2_w(u8 data);
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u8 tr01con_r();
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void tr01con_w(u8 data);
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u8 tr2con_r();
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void tr2con_w(u8 data);
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u8 trlir_r();
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void trlir_w(u8 data);
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u8 t0cl_r();
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u8 t0ch_r();
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u8 tr1c_r();
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u8 tr2c_r();
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u8 sfcr_r();
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void sfcr_w(u8 data);
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u8 addl_r();
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void addl_w(u8 data);
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u8 addm_r();
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void addm_w(u8 data);
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u8 addh_r();
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void addh_w(u8 data);
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u8 env_sphdr_r();
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void env_sphdr_w(u8 data);
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u8 mtcon_sphtcon_r();
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void mtcon_sphtcon_w(u8 data);
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u8 mtrl_sphtrl_r();
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void mtrl_sphtrl_w(u8 data);
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u8 vocon_r();
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void vocon_w(u8 data);
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private:
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// debugging helpers
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void debug_set_pc(u32 pc);
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// memory helpers
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u16 fetch_program_word();
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u16 get_banked_address(u8 reg);
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u32 tabptr_offset(int offset) const;
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void multi_byte_carry(u16 addr, bool cy);
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void multi_byte_borrow(u16 addr, bool cy);
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// execution
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void execute_move(u8 dstreg, u8 srcreg);
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@ -143,6 +265,7 @@ private:
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enum exec_state : u8 {
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EXEC_CYCLE1,
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EXEC_ADCPCM, EXEC_SBCPCM,
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EXEC_TBRD0, EXEC_TBRD1, EXEC_TBRD2, EXEC_TBRDA,
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EXEC_NOJMP,
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EXEC_L0JMP, EXEC_L1JMP, EXEC_L2JMP, EXEC_L3JMP,
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@ -155,8 +278,6 @@ private:
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EXEC_LCCALL, EXEC_LDCALL, EXEC_LECALL, EXEC_LFCALL
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};
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void regs_map(address_map &map);
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// address spaces
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address_space_config m_program_config;
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address_space_config m_regs_config;
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@ -164,10 +285,18 @@ private:
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address_space *m_regs;
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memory_access_cache<1, -1, ENDIANNESS_LITTLE> *m_cache;
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// device callbacks
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devcb_read8 m_porta_in_cb;
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devcb_read8 m_port_in_cb[10];
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devcb_write8 m_port_out_cb[10];
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// model-specific parameters
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const unsigned m_prgbits;
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const uint8_t m_bankmask;
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const uint8_t m_maxbank;
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const u32 m_pcmask;
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const u32 m_datastart;
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const u32 m_tbptmask;
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const u8 m_bankmask;
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const u8 m_maxbank;
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const u8 m_post_id_mask;
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// internal state
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u32 m_pc;
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@ -177,11 +306,51 @@ private:
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u8 m_bsr[2];
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u32 m_tabptr;
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u8 m_stkptr;
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std::unique_ptr<u8[]> m_pchstack;
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u8 m_cpucon;
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u8 m_status;
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u16 m_prod;
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u8 m_pfs;
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u8 m_intcon;
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u8 m_intsta;
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u8 m_post_id;
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// port state
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u8 m_port_data[10];
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u8 m_port_dcr[6];
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u8 m_port_control[2];
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u8 m_stbcon;
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u8 m_painten;
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u8 m_paintsta;
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u8 m_pawake;
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// UART state
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u8 m_uartcon;
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u8 m_uartsta;
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// SPI state
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u8 m_spicon;
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u8 m_spista;
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// timer state
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u16 m_trl0;
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u8 m_trl1;
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u8 m_trl2;
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u8 m_tr01con;
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u8 m_tr2con;
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u8 m_trlir;
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u8 m_sfcr;
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// synthesizer state
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u32 m_add[4];
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u8 m_env[4];
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u8 m_mtcon[4];
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u8 m_mtrl[4];
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u8 m_sphdr;
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u8 m_sphtcon;
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u8 m_sphtrl;
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u8 m_vocon;
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// execution sequencing
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s32 m_icount;
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exec_state m_exec_state;
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@ -189,6 +358,20 @@ private:
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u8 m_curreg;
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};
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DECLARE_DEVICE_TYPE(RISCII, riscii_series_device)
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class epg3231_device : public riscii_series_device
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{
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public:
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// construction/destruction
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epg3231_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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protected:
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// device_disasm_interface overrides
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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private:
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void regs_map(address_map &map);
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};
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DECLARE_DEVICE_TYPE(EPG3231, epg3231_device)
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#endif // MAME_CPU_RII_RISCII_H
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@ -1,7 +1,7 @@
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// license:BSD-3-Clause
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// copyright-holders:Sandro Ronco
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// CPU die is an Elan EU3A12 (Elan "RISC II Series" quasi-PIC with 16-bit opcodes)
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// CPU die (epoxy blob) is an Elan EU3A12 (Elan "RISC II Series" quasi-PIC with 16-bit opcodes)
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#include "emu.h"
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#include "cpu/rii/riscii.h"
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@ -22,7 +22,7 @@ private:
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void prog_map(address_map &map);
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required_device<cpu_device> m_maincpu;
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required_device<riscii_series_device> m_maincpu;
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};
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uint32_t vreadere_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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@ -32,7 +32,7 @@ uint32_t vreadere_state::screen_update(screen_device &screen, bitmap_rgb32 &bitm
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void vreadere_state::prog_map(address_map &map)
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{
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map(0x00000, 0x3ffff).rom().region("maincpu", 0);
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map(0x000000, 0x1fffff).rom().region("maincpu", 0);
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}
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static INPUT_PORTS_START( vreadere )
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@ -40,7 +40,7 @@ INPUT_PORTS_END
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void vreadere_state::vreadere(machine_config &config)
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{
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RISCII(config, m_maincpu, 10'000'000); // CPU type is unknown, epoxy blob
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EPG3231(config, m_maincpu, 10'000'000);
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m_maincpu->set_addrmap(AS_PROGRAM, &vreadere_state::prog_map);
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/* video hardware */
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@ -354,6 +354,7 @@ static const dasm_table_entry dasm_table[] =
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{ "dsp32c", le, 0, []() -> util::disasm_interface * { return new dsp32c_disassembler; } },
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{ "dsp56156", le, -1, []() -> util::disasm_interface * { return new dsp56156_disassembler; } },
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{ "e0c6200", be, -1, []() -> util::disasm_interface * { return new e0c6200_disassembler; } },
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{ "epg3231", le, -1, []() -> util::disasm_interface * { return new epg3231_disassembler; } },
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// { "es5510", be, 0, []() -> util::disasm_interface * { return new es5510_disassembler; } }, // Currently does nothing
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{ "esrip", be, 0, []() -> util::disasm_interface * { return new esrip_disassembler; } },
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{ "f2mc16", le, 0, []() -> util::disasm_interface * { return new f2mc16_disassembler; } },
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@ -448,7 +449,6 @@ static const dasm_table_entry dasm_table[] =
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{ "pps4", le, 0, []() -> util::disasm_interface * { return new pps4_disassembler; } },
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{ "psxcpu", le, 0, []() -> util::disasm_interface * { return new psxcpu_disassembler; } },
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{ "r65c02", le, 0, []() -> util::disasm_interface * { return new r65c02_disassembler; } },
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{ "rii", le, -1, []() -> util::disasm_interface * { return new riscii_disassembler; } },
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||||
{ "rsp", le, 0, []() -> util::disasm_interface * { return new rsp_disassembler; } },
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{ "s2650", le, 0, []() -> util::disasm_interface * { return new s2650_disassembler(&s2650_unidasm); } },
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{ "saturn", le, 0, []() -> util::disasm_interface * { return new saturn_disassembler(&saturn_unidasm); } },
|
||||
|
Loading…
Reference in New Issue
Block a user