mirror of
https://github.com/holub/mame
synced 2025-04-22 08:22:15 +03:00
Merge pull request #1659 from npwoods/dasmstream_arm
Changed the ARM disassembler to use 'std::ostream &' internally
This commit is contained in:
Vas Crabb
GitHub
commit
a261e9f4f2
@ -9,7 +9,7 @@
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#include "emu.h"
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#include "arm.h"
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static char *WriteImmediateOperand( char *pBuf, uint32_t opcode )
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static void WriteImmediateOperand( std::ostream &stream, uint32_t opcode )
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{
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/* rrrrbbbbbbbb */
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uint32_t imm;
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@ -18,69 +18,70 @@ static char *WriteImmediateOperand( char *pBuf, uint32_t opcode )
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imm = opcode&0xff;
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r = ((opcode>>8)&0xf)*2;
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imm = (imm>>r)|(r?(imm<<(32-r)):0);
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pBuf += sprintf( pBuf, ", #$%x", imm );
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return pBuf;
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util::stream_format( stream, ", #$%x", imm );
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}
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static char *WriteDataProcessingOperand( char *pBuf, uint32_t opcode, int printOp0, int printOp1, int printOp2 )
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static void WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, int printOp0, int printOp1, int printOp2 )
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{
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/* ccccctttmmmm */
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static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" };
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if (printOp0)
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pBuf += sprintf(pBuf,"R%d, ", (opcode>>12)&0xf);
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util::stream_format(stream, "R%d, ", (opcode>>12)&0xf);
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if (printOp1)
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pBuf += sprintf(pBuf,"R%d, ", (opcode>>16)&0xf);
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util::stream_format(stream, "R%d, ", (opcode>>16)&0xf);
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/* Immediate Op2 */
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if( opcode&0x02000000 )
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return WriteImmediateOperand(pBuf-2,opcode);
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if (opcode & 0x02000000)
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{
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stream.seekp(-2, std::ios_base::cur);
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WriteImmediateOperand(stream, opcode);
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return;
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}
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/* Register Op2 */
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if (printOp2)
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pBuf += sprintf(pBuf,"R%d, ", (opcode>>0)&0xf);
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util::stream_format(stream, "R%d, ", (opcode>>0)&0xf);
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pBuf += sprintf(pBuf, "%s ", pRegOp[(opcode>>5)&3] );
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util::stream_format(stream, "%s ", pRegOp[(opcode>>5)&3]);
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if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */
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{
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pBuf += sprintf( pBuf, "R%d", (opcode>>8)&0xf );
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util::stream_format( stream, "R%d", (opcode>>8)&0xf );
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}
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else /* Shift amount immediate 5 bit unsigned integer */
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{
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int c=(opcode>>7)&0x1f;
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if( c==0 ) c = 32;
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pBuf += sprintf( pBuf, "#%d", c );
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util::stream_format( stream, "#%d", c );
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}
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return pBuf;
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}
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static char *WriteRegisterOperand1( char *pBuf, uint32_t opcode )
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static void WriteRegisterOperand1( std::ostream &stream, uint32_t opcode )
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{
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/* ccccctttmmmm */
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static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" };
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pBuf += sprintf(
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pBuf,
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util::stream_format(
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stream,
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", R%d %s ", /* Operand 1 register, Operand 2 register, shift type */
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(opcode>> 0)&0xf,
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pRegOp[(opcode>>5)&3] );
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pRegOp[(opcode>>5)&3]);
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if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */
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{
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pBuf += sprintf( pBuf, "R%d", (opcode>>7)&0xf );
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util::stream_format( stream, "R%d", (opcode>>7)&0xf );
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}
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else /* Shift amount immediate 5 bit unsigned integer */
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{
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int c=(opcode>>7)&0x1f;
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if( c==0 ) c = 32;
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pBuf += sprintf( pBuf, "#%d", c );
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util::stream_format( stream, "#%d", c );
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}
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return pBuf;
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} /* WriteRegisterOperand */
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static char *WriteBranchAddress( char *pBuf, uint32_t pc, uint32_t opcode )
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static void WriteBranchAddress( std::ostream &stream, uint32_t pc, uint32_t opcode )
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{
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opcode &= 0x00ffffff;
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if( opcode&0x00800000 )
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@ -88,24 +89,18 @@ static char *WriteBranchAddress( char *pBuf, uint32_t pc, uint32_t opcode )
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opcode |= 0xff000000; /* sign-extend */
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}
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pc += 8+4*opcode;
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sprintf( pBuf, "$%x", pc );
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return pBuf;
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util::stream_format( stream, "$%x", pc );
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} /* WriteBranchAddress */
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static char *WritePadding( char *pBuf, const char *pBuf0 )
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static void WritePadding(std::ostream &stream, std::streampos start_position)
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{
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pBuf0 += 8;
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while( pBuf<pBuf0 )
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{
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*pBuf++ = ' ';
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}
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return pBuf;
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std::streamoff difference = stream.tellp() - start_position;
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for (std::streamoff i = difference; i < 8; i++)
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stream << ' ';
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}
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static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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static uint32_t arm_disasm( std::ostream &stream, uint32_t pc, uint32_t opcode )
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{
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const char *pBuf0;
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static const char *const pConditionCodeTable[16] =
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{
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"EQ","NE","CS","CC",
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@ -122,9 +117,9 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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};
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const char *pConditionCode;
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uint32_t dasmflags = 0;
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std::streampos start_position = stream.tellp();
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pConditionCode= pConditionCodeTable[opcode>>28];
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pBuf0 = pBuf;
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if( (opcode&0x0fc000f0)==0x00000090u )
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{
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@ -132,28 +127,28 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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/* xxxx0000 00ASdddd nnnnssss 1001mmmm */
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if( opcode&0x00200000 )
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{
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pBuf += sprintf( pBuf, "MLA" );
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util::stream_format( stream, "MLA" );
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}
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else
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{
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pBuf += sprintf( pBuf, "MUL" );
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util::stream_format( stream, "MUL" );
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}
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pBuf += sprintf( pBuf, "%s", pConditionCode );
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util::stream_format( stream, "%s", pConditionCode );
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if( opcode&0x00100000 )
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{
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*pBuf++ = 'S';
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stream << 'S';
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}
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pBuf = WritePadding( pBuf, pBuf0 );
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WritePadding(stream, start_position);
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pBuf += sprintf( pBuf,
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util::stream_format(stream,
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"R%d, R%d, R%d",
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(opcode>>16)&0xf,
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(opcode&0xf),
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(opcode>>8)&0xf );
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(opcode>>8)&0xf);
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if( opcode&0x00200000 )
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{
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pBuf += sprintf( pBuf, ", R%d", (opcode>>12)&0xf );
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util::stream_format( stream, ", R%d", (opcode>>12)&0xf );
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}
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}
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else if( (opcode&0x0c000000)==0 )
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@ -164,17 +159,17 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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/* xxxx001a aaaSnnnn ddddrrrr bbbbbbbb */
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/* xxxx000a aaaSnnnn ddddcccc ctttmmmm */
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pBuf += sprintf(
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pBuf, "%s%s",
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util::stream_format(stream,
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"%s%s",
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pOperation[op],
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pConditionCode );
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pConditionCode);
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if( (opcode&0x01000000) )
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{
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*pBuf++ = 'S';
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stream << 'S';
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}
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pBuf = WritePadding( pBuf, pBuf0 );
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WritePadding(stream, start_position);
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switch (op) {
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case 0x00:
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@ -187,20 +182,20 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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case 0x07:
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case 0x0c:
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case 0x0e:
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WriteDataProcessingOperand(pBuf, opcode, 1, 1, 1);
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WriteDataProcessingOperand(stream, opcode, 1, 1, 1);
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break;
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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WriteDataProcessingOperand(pBuf, opcode, 0, 1, 1);
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WriteDataProcessingOperand(stream, opcode, 0, 1, 1);
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break;
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case 0x0d:
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/* look for mov pc,lr */
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if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0)
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dasmflags = DASMFLAG_STEP_OUT;
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case 0x0f:
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WriteDataProcessingOperand(pBuf, opcode, 1, 0, 1);
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WriteDataProcessingOperand(stream, opcode, 1, 0, 1);
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break;
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}
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}
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@ -212,17 +207,17 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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/* xxxx011P UBWLnnnn ddddcccc ctt0mmmm Register form */
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if( opcode&0x00100000 )
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{
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pBuf += sprintf( pBuf, "LDR" );
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util::stream_format( stream, "LDR" );
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}
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else
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{
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pBuf += sprintf( pBuf, "STR" );
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util::stream_format( stream, "STR" );
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}
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pBuf += sprintf( pBuf, "%s", pConditionCode );
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util::stream_format( stream, "%s", pConditionCode );
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if( opcode&0x00400000 )
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{
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pBuf += sprintf( pBuf, "B" );
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util::stream_format( stream, "B" );
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}
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if( opcode&0x00200000 )
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@ -231,36 +226,36 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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if( opcode&0x01000000 )
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{
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/* pre-indexed addressing */
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pBuf += sprintf( pBuf, "!" );
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util::stream_format( stream, "!" );
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}
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else
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{
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/* post-indexed addressing */
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pBuf += sprintf( pBuf, "T" );
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util::stream_format( stream, "T" );
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}
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}
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pBuf = WritePadding( pBuf, pBuf0 );
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pBuf += sprintf( pBuf, "R%d, [R%d",
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WritePadding(stream, start_position);
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util::stream_format( stream, "R%d, [R%d",
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(opcode>>12)&0xf, (opcode>>16)&0xf );
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if( opcode&0x02000000 )
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{
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/* register form */
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pBuf = WriteRegisterOperand1( pBuf, opcode );
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pBuf += sprintf( pBuf, "]" );
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WriteRegisterOperand1( stream, opcode );
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util::stream_format( stream, "]" );
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}
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else
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{
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/* immediate form */
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pBuf += sprintf( pBuf, "]" );
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util::stream_format( stream, "]" );
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if( opcode&0x00800000 )
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{
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pBuf += sprintf( pBuf, ", #$%x", opcode&0xfff );
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util::stream_format( stream, ", #$%x", opcode&0xfff );
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}
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else
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{
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pBuf += sprintf( pBuf, ", -#$%x", opcode&0xfff );
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util::stream_format( stream, ", -#$%x", opcode&0xfff );
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}
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}
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}
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@ -271,33 +266,33 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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if( opcode&0x00100000 )
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{
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pBuf += sprintf( pBuf, "LDM" );
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util::stream_format( stream, "LDM" );
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}
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else
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{
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pBuf += sprintf( pBuf, "STM" );
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util::stream_format( stream, "STM" );
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}
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pBuf += sprintf( pBuf, "%s", pConditionCode );
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util::stream_format( stream, "%s", pConditionCode );
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if( opcode&0x01000000 )
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{
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pBuf += sprintf( pBuf, "P" );
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util::stream_format( stream, "P" );
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}
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if( opcode&0x00800000 )
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{
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pBuf += sprintf( pBuf, "U" );
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util::stream_format( stream, "U" );
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}
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if( opcode&0x00400000 )
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{
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pBuf += sprintf( pBuf, "^" );
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util::stream_format( stream, "^" );
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}
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if( opcode&0x00200000 )
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{
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pBuf += sprintf( pBuf, "W" );
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util::stream_format( stream, "W" );
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}
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pBuf = WritePadding( pBuf, pBuf0 );
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pBuf += sprintf( pBuf, "[R%d], {",(opcode>>16)&0xf);
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WritePadding(stream, start_position);
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util::stream_format( stream, "[R%d], {",(opcode>>16)&0xf);
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{
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int j=0,last=0,found=0;
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@ -308,20 +303,20 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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}
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else if ((opcode&(1<<j))==0 && found) {
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if (last==j-1)
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pBuf += sprintf( pBuf, " R%d,",last);
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util::stream_format( stream, " R%d,",last);
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else
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pBuf += sprintf( pBuf, " R%d-R%d,",last,j-1);
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util::stream_format( stream, " R%d-R%d,",last,j-1);
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found=0;
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}
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}
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if (found && last==15)
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pBuf += sprintf( pBuf, " R15,");
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util::stream_format( stream, " R15,");
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else if (found)
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pBuf += sprintf( pBuf, " R%d-R%d,",last,15);
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util::stream_format( stream, " R%d-R%d,",last,15);
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}
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pBuf--;
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pBuf += sprintf( pBuf, " }");
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stream.seekp(-1, std::ios_base::cur);
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util::stream_format( stream, " }");
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}
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else if( (opcode&0x0e000000)==0x0a000000 )
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{
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@ -329,19 +324,19 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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/* xxxx101L oooooooo oooooooo oooooooo */
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if( opcode&0x01000000 )
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{
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pBuf += sprintf( pBuf, "BL" );
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util::stream_format( stream, "BL" );
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dasmflags = DASMFLAG_STEP_OVER;
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}
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else
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{
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pBuf += sprintf( pBuf, "B" );
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util::stream_format( stream, "B" );
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}
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pBuf += sprintf( pBuf, "%s", pConditionCode );
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util::stream_format( stream, "%s", pConditionCode );
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pBuf = WritePadding( pBuf, pBuf0 );
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WritePadding(stream, start_position);
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pBuf = WriteBranchAddress( pBuf, pc, opcode );
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WriteBranchAddress( stream, pc, opcode );
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}
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else if( (opcode&0x0f000000) == 0x0e000000 )
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{
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@ -351,50 +346,59 @@ static uint32_t arm_disasm( char *pBuf, uint32_t pc, uint32_t opcode )
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{
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if( (opcode&0x0f100010)==0x0e100010 )
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{
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pBuf += sprintf( pBuf, "MRC" );
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util::stream_format( stream, "MRC" );
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}
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else if( (opcode&0x0f100010)==0x0e000010 )
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{
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pBuf += sprintf( pBuf, "MCR" );
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util::stream_format( stream, "MCR" );
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}
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else
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{
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pBuf += sprintf( pBuf, "???" );
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util::stream_format( stream, "???" );
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}
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pBuf += sprintf( pBuf, "%s", pConditionCode );
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pBuf = WritePadding( pBuf, pBuf0 );
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pBuf += sprintf( pBuf, "R%d, CR%d {CRM%d, q%d}",(opcode>>12)&0xf, (opcode>>16)&0xf, (opcode>>0)&0xf, (opcode>>5)&0x7);
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util::stream_format( stream, "%s", pConditionCode );
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WritePadding(stream, start_position);
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util::stream_format( stream, "R%d, CR%d {CRM%d, q%d}",(opcode>>12)&0xf, (opcode>>16)&0xf, (opcode>>0)&0xf, (opcode>>5)&0x7);
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/* Nb: full form should be o, p, R, CR, CRM, q */
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}
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else if( (opcode&0x0f000010)==0x0e000000 )
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{
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pBuf += sprintf( pBuf, "CDP" );
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pBuf += sprintf( pBuf, "%s", pConditionCode );
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pBuf = WritePadding( pBuf, pBuf0 );
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pBuf += sprintf( pBuf, "%08x", opcode );
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util::stream_format( stream, "CDP" );
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util::stream_format( stream, "%s", pConditionCode );
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WritePadding(stream, start_position);
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util::stream_format( stream, "%08x", opcode );
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}
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else
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{
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pBuf += sprintf( pBuf, "???" );
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util::stream_format( stream, "???" );
|
||||
}
|
||||
}
|
||||
else if( (opcode&0x0f000000) == 0x0f000000 )
|
||||
{
|
||||
/* Software Interrupt */
|
||||
pBuf += sprintf( pBuf, "SWI%s $%x",
|
||||
util::stream_format( stream, "SWI%s $%x",
|
||||
pConditionCode,
|
||||
opcode&0x00ffffff );
|
||||
dasmflags = DASMFLAG_STEP_OVER;
|
||||
}
|
||||
else
|
||||
{
|
||||
pBuf += sprintf( pBuf, "Undefined" );
|
||||
util::stream_format( stream, "Undefined" );
|
||||
}
|
||||
|
||||
return dasmflags | DASMFLAG_SUPPORTED;
|
||||
}
|
||||
|
||||
static uint32_t arm_disasm(char *buffer, uint32_t pc, uint32_t opcode)
|
||||
{
|
||||
std::ostringstream stream;
|
||||
uint32_t result = arm_disasm(stream, pc, opcode);
|
||||
std::string stream_str = stream.str();
|
||||
strcpy(buffer, stream_str.c_str());
|
||||
return result;
|
||||
}
|
||||
|
||||
CPU_DISASSEMBLE( arm )
|
||||
{
|
||||
uint32_t opcode = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user