start to make the z84 a proper cpu type, migrate code from niyanpai to the cpu.
spent most of the day (many hours) trying to work out why this was hanging with my changes only to find out the 68k change broke the driver (it's still broken, i don't have time to fix it) :/
This commit is contained in:
David Haywood
parent
f6005251d8
commit
a2cb0b3d7e
@ -3737,16 +3737,238 @@ nsc800_device::nsc800_device(const machine_config &mconfig, const char *tag, dev
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const device_type NSC800 = &device_creator<nsc800_device>;
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// todo, move per-driver implementations (eg. nbmj9195.c) to here with callbacks for the ports
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READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
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WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
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{
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int portdata = 0xff;
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switch (offset)
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{
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case 0: /* PA_0 */
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portdata = m_inports0();
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break;
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case 1: /* PB_0 */
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portdata = m_inports1();
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break;
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case 2: /* PC_0 */
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portdata = m_inports2();
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break;
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case 3: /* PD_0 */
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portdata = m_inports3();
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break;
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case 4: /* PE_0 */
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portdata = m_inports4();
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break;
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}
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return portdata;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
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{
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switch (offset)
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{
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case 0: /* PA_0 */
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m_outports0(data);
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break;
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case 1: /* PB_0 */
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m_outports1(data);
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break;
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case 2: /* PC_0 */
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m_outports2(data);
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break;
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case 3: /* PD_0 */
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m_outports3(data);
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break;
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case 4: /* PE_0 */
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m_outports4(data);
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break;
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}
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}
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/* CPU interface */
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
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{
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return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
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{
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return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
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{
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return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
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{
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return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
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{
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return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
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{
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m_pio_latch[0] = data;
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tmpz84c011_pio_w(space, 0, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
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{
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m_pio_latch[1] = data;
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tmpz84c011_pio_w(space, 1, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
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{
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m_pio_latch[2] = data;
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tmpz84c011_pio_w(space, 2, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
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{
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m_pio_latch[3] = data;
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tmpz84c011_pio_w(space, 3, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
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{
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m_pio_latch[4] = data;
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tmpz84c011_pio_w(space, 4, data);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
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{
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return m_pio_dir[0];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
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{
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return m_pio_dir[1];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
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{
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return m_pio_dir[2];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
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{
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return m_pio_dir[3];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
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{
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return m_pio_dir[4];
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
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{
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m_pio_dir[0] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
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{
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m_pio_dir[1] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
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{
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m_pio_dir[2] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
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{
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m_pio_dir[3] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
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{
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m_pio_dir[4] = data;
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}
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static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
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AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
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AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
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AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
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AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
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AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
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AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
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AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
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AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
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AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
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AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
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ADDRESS_MAP_END
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tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__)
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: z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
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m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
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m_outports0(*this),
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m_outports1(*this),
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m_outports2(*this),
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m_outports3(*this),
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m_outports4(*this),
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m_inports0(*this),
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m_inports1(*this),
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m_inports2(*this),
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m_inports3(*this),
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m_inports4(*this)
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{
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}
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const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
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void tmpz84c011_device::device_start()
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{
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z80_device::device_start();
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m_outports0.resolve_safe();
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m_outports1.resolve_safe();
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m_outports2.resolve_safe();
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m_outports3.resolve_safe();
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m_outports4.resolve_safe();
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m_inports0.resolve_safe(0);
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m_inports1.resolve_safe(0);
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m_inports2.resolve_safe(0);
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m_inports3.resolve_safe(0);
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m_inports4.resolve_safe(0);
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}
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void tmpz84c011_device::device_reset()
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{
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z80_device::device_reset();
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// initialize TMPZ84C011 PIO
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for (int i = 0; i < 5; i++)
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{
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m_pio_dir[i] = m_pio_latch[i] = 0;
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tmpz84c011_pio_w(*m_io, i, 0);
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}
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}
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WRITE_LINE_MEMBER( z80_device::irq_line )
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{
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set_input_line( INPUT_LINE_IRQ0, state );
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@ -334,15 +334,135 @@ protected:
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}
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};
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extern const device_type TLCS_Z80;
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#define MCFG_TMPZ84C011_PORTA_READ_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTB_READ_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTC_READ_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTD_READ_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTE_READ_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTA_WRITE_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTB_WRITE_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTC_WRITE_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTD_WRITE_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
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#define MCFG_TMPZ84C011_PORTE_WRITE_CALLBACK(_devcb) \
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devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
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class tmpz84c011_device : public z80_device
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{
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public:
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tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
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template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
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template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
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template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
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template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
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template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
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template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
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template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
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template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
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template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
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template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
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DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
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DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
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DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
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DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
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DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
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DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
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DECLARE_READ8_MEMBER(porta_default_r);
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DECLARE_READ8_MEMBER(portb_default_r);
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DECLARE_READ8_MEMBER(portc_default_r);
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DECLARE_READ8_MEMBER(portd_default_r);
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DECLARE_READ8_MEMBER(porte_default_r);
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DECLARE_WRITE8_MEMBER(porta_default_w);
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DECLARE_WRITE8_MEMBER(portb_default_w);
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DECLARE_WRITE8_MEMBER(portc_default_w);
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DECLARE_WRITE8_MEMBER(portd_default_w);
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DECLARE_WRITE8_MEMBER(porte_default_w);
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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const address_space_config m_io_space_config;
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const address_space_config *memory_space_config(address_spacenum spacenum) const
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{
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switch (spacenum)
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{
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case AS_IO: return &m_io_space_config;
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default: return z80_device::memory_space_config(spacenum);
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}
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}
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UINT8 m_pio_dir[5];
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UINT8 m_pio_latch[5];
|
||||
|
||||
private:
|
||||
devcb_write8 m_outports0;
|
||||
devcb_write8 m_outports1;
|
||||
devcb_write8 m_outports2;
|
||||
devcb_write8 m_outports3;
|
||||
devcb_write8 m_outports4;
|
||||
|
||||
devcb_read8 m_inports0;
|
||||
devcb_read8 m_inports1;
|
||||
devcb_read8 m_inports2;
|
||||
devcb_read8 m_inports3;
|
||||
devcb_read8 m_inports4;
|
||||
|
||||
};
|
||||
|
||||
extern const device_type TMPZ84C011;
|
||||
|
||||
@ -69,181 +69,34 @@ WRITE8_MEMBER(niyanpai_state::niyanpai_soundclr_w)
|
||||
}
|
||||
|
||||
|
||||
/* TMPZ84C011 PIO emulation */
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_pio_r)
|
||||
READ8_MEMBER(niyanpai_state::cpu_portd_r)
|
||||
{
|
||||
int portdata;
|
||||
|
||||
switch (offset)
|
||||
{
|
||||
case 0: /* PA_0 */
|
||||
portdata = 0xff;
|
||||
break;
|
||||
case 1: /* PB_0 */
|
||||
portdata = 0xff;
|
||||
break;
|
||||
case 2: /* PC_0 */
|
||||
portdata = 0xff;
|
||||
break;
|
||||
case 3: /* PD_0 */
|
||||
portdata = niyanpai_sound_r(space, 0);
|
||||
break;
|
||||
case 4: /* PE_0 */
|
||||
portdata = 0xff;
|
||||
break;
|
||||
|
||||
default:
|
||||
logerror("%s: TMPZ84C011_PIO Unknown Port Read %02X\n", machine().describe_context(), offset);
|
||||
portdata = 0xff;
|
||||
break;
|
||||
}
|
||||
|
||||
return portdata;
|
||||
return niyanpai_sound_r(space, 0);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_pio_w)
|
||||
WRITE8_MEMBER(niyanpai_state::cpu_porta_w)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
case 0: /* PA_0 */
|
||||
niyanpai_soundbank_w(data & 0x03);
|
||||
break;
|
||||
case 1: /* PB_0 */
|
||||
m_dac1->write_unsigned8(data);
|
||||
break;
|
||||
case 2: /* PC_0 */
|
||||
m_dac2->write_unsigned8(data);
|
||||
break;
|
||||
case 3: /* PD_0 */
|
||||
break;
|
||||
case 4: /* PE_0 */
|
||||
if (!(data & 0x01)) niyanpai_soundclr_w(space, 0, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
logerror("%s: TMPZ84C011_PIO Unknown Port Write %02X, %02X\n", machine().describe_context(), offset, data);
|
||||
break;
|
||||
}
|
||||
niyanpai_soundbank_w(data & 0x03);
|
||||
}
|
||||
|
||||
/* CPU interface */
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_pa_r)
|
||||
WRITE8_MEMBER(niyanpai_state::cpu_portb_w)
|
||||
{
|
||||
return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
|
||||
m_dac1->write_unsigned8(data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_pb_r)
|
||||
WRITE8_MEMBER(niyanpai_state::cpu_portc_w)
|
||||
{
|
||||
return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
|
||||
m_dac2->write_unsigned8(data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_pc_r)
|
||||
WRITE8_MEMBER(niyanpai_state::cpu_porte_w)
|
||||
{
|
||||
return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_pd_r)
|
||||
{
|
||||
return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_pe_r)
|
||||
{
|
||||
return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pa_w)
|
||||
{
|
||||
m_pio_latch[0] = data;
|
||||
tmpz84c011_pio_w(space, 0, data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pb_w)
|
||||
{
|
||||
m_pio_latch[1] = data;
|
||||
tmpz84c011_pio_w(space, 1, data);
|
||||
}
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pc_w)
|
||||
{
|
||||
m_pio_latch[2] = data;
|
||||
tmpz84c011_pio_w(space, 2, data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pd_w)
|
||||
{
|
||||
m_pio_latch[3] = data;
|
||||
tmpz84c011_pio_w(space, 3, data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pe_w)
|
||||
{
|
||||
m_pio_latch[4] = data;
|
||||
tmpz84c011_pio_w(space, 4, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pa_r)
|
||||
{
|
||||
return m_pio_dir[0];
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pb_r)
|
||||
{
|
||||
return m_pio_dir[1];
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pc_r)
|
||||
{
|
||||
return m_pio_dir[2];
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pd_r)
|
||||
{
|
||||
return m_pio_dir[3];
|
||||
}
|
||||
|
||||
READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pe_r)
|
||||
{
|
||||
return m_pio_dir[4];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pa_w)
|
||||
{
|
||||
m_pio_dir[0] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pb_w)
|
||||
{
|
||||
m_pio_dir[1] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pc_w)
|
||||
{
|
||||
m_pio_dir[2] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pd_w)
|
||||
{
|
||||
m_pio_dir[3] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pe_w)
|
||||
{
|
||||
m_pio_dir[4] = data;
|
||||
if (!(data & 0x01)) niyanpai_soundclr_w(space, 0, 0);
|
||||
}
|
||||
|
||||
|
||||
void niyanpai_state::machine_reset()
|
||||
{
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
int i;
|
||||
|
||||
// initialize TMPZ84C011 PIO
|
||||
for (i = 0; i < 5; i++)
|
||||
{
|
||||
m_pio_dir[i] = m_pio_latch[i] = 0;
|
||||
tmpz84c011_pio_w(space, i, 0);
|
||||
}
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(niyanpai_state,niyanpai)
|
||||
@ -484,16 +337,6 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( niyanpai_sound_io_map, AS_IO, 8, niyanpai_state )
|
||||
ADDRESS_MAP_GLOBAL_MASK(0xff)
|
||||
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
|
||||
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w)
|
||||
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w)
|
||||
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w)
|
||||
AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w)
|
||||
AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w)
|
||||
AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w)
|
||||
AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w)
|
||||
AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w)
|
||||
AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w)
|
||||
AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w)
|
||||
AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -926,6 +769,8 @@ static const z80_daisy_config daisy_chain_sound[] =
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
||||
|
||||
static MACHINE_CONFIG_START( niyanpai, niyanpai_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -937,17 +782,22 @@ static MACHINE_CONFIG_START( niyanpai, niyanpai_state )
|
||||
MCFG_DEVICE_ADD("tmp68301", TMP68301, 0)
|
||||
MCFG_TMP68301_OUT_PARALLEL_CB(WRITE16(niyanpai_state, tmp68301_parallel_port_w))
|
||||
|
||||
MCFG_CPU_ADD("audiocpu", Z80, 8000000) /* TMPZ84C011, 8.00 MHz */
|
||||
MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000) /* TMPZ84C011, 8.00 MHz */
|
||||
MCFG_CPU_CONFIG(daisy_chain_sound)
|
||||
MCFG_CPU_PROGRAM_MAP(niyanpai_sound_map)
|
||||
MCFG_CPU_IO_MAP(niyanpai_sound_io_map)
|
||||
MCFG_TMPZ84C011_PORTD_READ_CALLBACK(READ8(niyanpai_state, cpu_portd_r))
|
||||
MCFG_TMPZ84C011_PORTA_WRITE_CALLBACK(WRITE8(niyanpai_state, cpu_porta_w))
|
||||
MCFG_TMPZ84C011_PORTB_WRITE_CALLBACK(WRITE8(niyanpai_state,cpu_portb_w))
|
||||
MCFG_TMPZ84C011_PORTC_WRITE_CALLBACK(WRITE8(niyanpai_state,cpu_portc_w))
|
||||
MCFG_TMPZ84C011_PORTE_WRITE_CALLBACK(WRITE8(niyanpai_state,cpu_porte_w))
|
||||
|
||||
MCFG_DEVICE_ADD("ctc", Z80CTC, 8000000 /* same as "audiocpu" */)
|
||||
MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
|
||||
MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("ctc", z80ctc_device, trg3))
|
||||
|
||||
MCFG_NVRAM_ADD_0FILL("nvram")
|
||||
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_REFRESH_RATE(60)
|
||||
|
||||
@ -21,8 +21,7 @@ public:
|
||||
|
||||
int m_musobana_inputport;
|
||||
int m_musobana_outcoin_flag;
|
||||
UINT8 m_pio_dir[5];
|
||||
UINT8 m_pio_latch[5];
|
||||
|
||||
int m_scrollx[VRAM_MAX];
|
||||
int m_scrolly[VRAM_MAX];
|
||||
int m_blitter_destx[VRAM_MAX];
|
||||
@ -49,28 +48,13 @@ public:
|
||||
DECLARE_READ8_MEMBER(niyanpai_sound_r);
|
||||
DECLARE_WRITE16_MEMBER(niyanpai_sound_w);
|
||||
DECLARE_WRITE8_MEMBER(niyanpai_soundclr_w);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(cpu_portd_r);
|
||||
DECLARE_WRITE8_MEMBER(cpu_porta_w);
|
||||
DECLARE_WRITE8_MEMBER(cpu_portb_w);
|
||||
DECLARE_WRITE8_MEMBER(cpu_portc_w);
|
||||
DECLARE_WRITE8_MEMBER(cpu_porte_w);
|
||||
|
||||
DECLARE_READ16_MEMBER(niyanpai_dipsw_r);
|
||||
DECLARE_READ16_MEMBER(musobana_inputport_0_r);
|
||||
DECLARE_WRITE16_MEMBER(musobana_inputport_w);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user