mirror of
https://github.com/holub/mame
synced 2025-05-24 23:05:32 +03:00
harddriv updates: [Phil Bennett]
* Implemented diagnostic jumper and DIP switches for all games * Added a workaround to prevent racedrivb1 and racedrivg1 from crashing on boot * Use the common 68681 DUART implementation * Use XTAL values for CPU clocks New games added or promoted from NOT_WORKING status --------------------------------------------------- Hard Drivin' (cockpit, rev 1) Race Drivin' (cockpit, rev 1) Race Drivin' (cockpit, rev 2) Race Drivin' (cockpit, rev 3) Race Drivin' (cockpit, British, rev 1) Race Drivin' (cockpit, German, rev 2)
This commit is contained in:
Phil Bennett
parent
fdcf7d65a7
commit
a2e1e2a833
@ -316,30 +316,13 @@ Notes:
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68010 clock input - 8.000MHz [32/4]
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34010 clock input - 48.000MHz
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****************************************************************************
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Emulation notes
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---------------
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harddriv1:
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In the debugger, right after the game is loaded, type the following :
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maincpu.mb@2c99e=1
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The game boots and seems playable.
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Put a bp at 0x0164f8 and compare execution with 'harddriv2' (bp at same address) which skips some parts of the code.
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1st problem at 0x0164fc : jumps to 0x016526 instead of 0x016508.
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2nd problem at 0x016542 : jumps to 0x01654c instead of 0x016552. Game resets if you attemp to step over code at 0x01654c.
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****************************************************************************/
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#include "emu.h"
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#include "machine/atarigen.h"
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#include "machine/asic65.h"
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#include "machine/68681.h"
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#include "audio/atarijsa.h"
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#include "sound/dac.h"
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#include "includes/slapstic.h"
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@ -415,6 +398,21 @@ static const dsp32_config dsp32c_config =
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};
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/*************************************
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*
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* 68681 DUART config
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*
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*************************************/
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static const duart68681_config duart_config =
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{
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harddriv_duart_irq_handler, /* irq callback */
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NULL, /* serial transmit */
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NULL, /* output port */
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NULL /* input port */
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};
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/*************************************
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*
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@ -435,7 +433,7 @@ static ADDRESS_MAP_START( driver_68k_map, AS_PROGRAM, 16, harddriv_state )
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AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE_LEGACY(hd68k_adc12_r, hd68k_adc_control_w)
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AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE_LEGACY(hd68k_gsp_io_r, hd68k_gsp_io_w)
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AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE_LEGACY(hd68k_msp_io_r, hd68k_msp_io_w)
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AM_RANGE(0xff0000, 0xff001f) AM_READWRITE_LEGACY(hd68k_duart_r, hd68k_duart_w)
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AM_RANGE(0xff0000, 0xff001f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff00)
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AM_RANGE(0xff4000, 0xff4fff) AM_READWRITE_LEGACY(hd68k_zram_r, hd68k_zram_w) AM_SHARE("eeprom")
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AM_RANGE(0xff8000, 0xffffff) AM_RAM
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ADDRESS_MAP_END
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@ -483,7 +481,7 @@ static ADDRESS_MAP_START( multisync_68k_map, AS_PROGRAM, 16, harddriv_state )
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AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE_LEGACY(hd68k_adc12_r, hd68k_adc_control_w)
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AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE_LEGACY(hd68k_gsp_io_r, hd68k_gsp_io_w)
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AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE_LEGACY(hd68k_msp_io_r, hd68k_msp_io_w)
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AM_RANGE(0xff0000, 0xff001f) AM_READWRITE_LEGACY(hd68k_duart_r, hd68k_duart_w)
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AM_RANGE(0xff0000, 0xff001f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff00)
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AM_RANGE(0xff4000, 0xff4fff) AM_READWRITE_LEGACY(hd68k_zram_r, hd68k_zram_w) AM_SHARE("eeprom")
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AM_RANGE(0xff8000, 0xffffff) AM_RAM
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ADDRESS_MAP_END
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@ -521,7 +519,7 @@ static ADDRESS_MAP_START( multisync2_68k_map, AS_PROGRAM, 16, harddriv_state )
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AM_RANGE(0xb80000, 0xbfffff) AM_READWRITE_LEGACY(hd68k_adc12_r, hd68k_adc_control_w)
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AM_RANGE(0xc00000, 0xc03fff) AM_READWRITE_LEGACY(hd68k_gsp_io_r, hd68k_gsp_io_w)
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AM_RANGE(0xc04000, 0xc07fff) AM_READWRITE_LEGACY(hd68k_msp_io_r, hd68k_msp_io_w)
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AM_RANGE(0xfc0000, 0xfc001f) AM_READWRITE_LEGACY(hd68k_duart_r, hd68k_duart_w)
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AM_RANGE(0xfc0000, 0xfc001f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff00)
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AM_RANGE(0xfd0000, 0xfd0fff) AM_MIRROR(0x004000) AM_READWRITE_LEGACY(hd68k_zram_r, hd68k_zram_w) AM_SHARE("eeprom")
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AM_RANGE(0xff0000, 0xffffff) AM_RAM
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ADDRESS_MAP_END
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@ -702,15 +700,42 @@ ADDRESS_MAP_END
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static INPUT_PORTS_START( harddriv )
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PORT_START("IN0") /* 600000 */
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) /* diagnostic switch */
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x0020, IP_ACTIVE_LOW )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0xff00, IP_ACTIVE_HIGH, IPT_UNUSED ) /* option switches */
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PORT_DIPNAME( 0x01, 0x01, "Diagnostic jumper" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_START("SW1") /* 600002 */
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PORT_DIPNAME( 0x01, 0x01, "SW1:8" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, "SW1:7" )
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, "SW1:6" )
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, "SW1:5" )
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, "SW1:4" )
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, "SW1:3" )
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, "SW1:2" )
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x80, "SW1:1" )
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_START("a80000")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("Abort") /* abort */
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@ -758,15 +783,42 @@ INPUT_PORTS_END
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static INPUT_PORTS_START( racedriv )
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PORT_START("IN0") /* 600000 */
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) /* diagnostic switch */
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x0020, IP_ACTIVE_LOW )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0xff00, IP_ACTIVE_HIGH, IPT_UNUSED ) /* option switches */
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PORT_DIPNAME( 0x01, 0x01, "Diagnostic jumper" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_START("SW1") /* 600002 */
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PORT_DIPNAME( 0x01, 0x01, "SW1:8" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, "SW1:7" )
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, "SW1:6" )
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, "SW1:5" )
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, "SW1:4" )
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, "SW1:3" )
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, "SW1:2" )
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x80, "SW1:1" )
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_START("a80000")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("Abort") /* abort */
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@ -814,15 +866,42 @@ INPUT_PORTS_END
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static INPUT_PORTS_START( racedrivc )
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PORT_START("IN0") /* 60c000 */
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) /* diagnostic switch */
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x0020, IP_ACTIVE_LOW )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0xff00, IP_ACTIVE_HIGH, IPT_UNUSED ) /* option switches */
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PORT_DIPNAME( 0x01, 0x01, "Diagnostic jumper" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_START("SW1") /* 60c002 */
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PORT_DIPNAME( 0x01, 0x01, "SW1:8" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, "SW1:7" )
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, "SW1:6" )
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, "SW1:5" )
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, "SW1:4" )
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, "SW1:3" )
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, "SW1:2" )
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x80, "SW1:1" )
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_START("a80000")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("Abort")
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@ -876,15 +955,42 @@ INPUT_PORTS_END
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static INPUT_PORTS_START( stunrun )
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PORT_START("IN0") /* 60c000 */
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x0020, IP_ACTIVE_LOW )
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PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0xff00, IP_ACTIVE_HIGH, IPT_UNUSED ) /* Option switches */
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PORT_DIPNAME( 0x01, 0x01, "Diagnostic jumper" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
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PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_START("SW1") /* 60c002 */
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PORT_DIPNAME( 0x01, 0x00, "SW1:8" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x00, "SW1:7" )
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x00, "SW1:6" )
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x00, "SW1:5" )
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x00, "SW1:4" )
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x00, "SW1:3" )
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x00, "SW1:2" )
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x00, "SW1:1" )
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_START("a80000")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 )
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@ -938,15 +1044,42 @@ INPUT_PORTS_END
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|
||||
static INPUT_PORTS_START( steeltal )
|
||||
PORT_START("IN0") /* 60c000 */
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
|
||||
PORT_SERVICE( 0x0020, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x01, 0x01, "Diagnostic jumper" )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
|
||||
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
|
||||
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
|
||||
PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
|
||||
PORT_START("SW1") /* 60c002 */
|
||||
PORT_DIPNAME( 0x01, 0x00, "SW1:8" )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x02, 0x00, "SW1:7" )
|
||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x04, 0x00, "SW1:6" )
|
||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x08, 0x00, "SW1:5" )
|
||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x10, 0x00, "SW1:4" )
|
||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x20, 0x00, "SW1:3" )
|
||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x40, 0x00, "SW1:2" )
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x00, "SW1:1" )
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
|
||||
PORT_START("a80000")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Trigger")
|
||||
@ -1001,15 +1134,42 @@ INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( strtdriv )
|
||||
PORT_START("IN0") /* 60c000 */
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
|
||||
PORT_SERVICE( 0x0020, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x01, 0x01, "Diagnostic jumper" )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
|
||||
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
|
||||
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
|
||||
PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
|
||||
PORT_START("SW1") /* 60c002 */
|
||||
PORT_DIPNAME( 0x01, 0x01, "SW1:8" )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x02, 0x02, "SW1:7" )
|
||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x04, 0x04, "SW1:6" )
|
||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x08, 0x08, "SW1:5" )
|
||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x10, 0x10, "SW1:4" )
|
||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x20, 0x20, "SW1:3" )
|
||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x40, 0x40, "SW1:2" )
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x80, "SW1:1" )
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
|
||||
PORT_START("a80000")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START2 ) /* abort */
|
||||
@ -1064,15 +1224,42 @@ INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( hdrivair )
|
||||
PORT_START("IN0") /* 60c000 */
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
|
||||
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
|
||||
PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
|
||||
PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
|
||||
PORT_SERVICE( 0x0020, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x01, 0x01, "Diagnostic jumper" )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
|
||||
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 12-bit EOC */
|
||||
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 8-bit EOC */
|
||||
PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
|
||||
|
||||
PORT_START("SW1") /* 60c002 */
|
||||
PORT_DIPNAME( 0x01, 0x01, "SW1:8" )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x02, 0x02, "SW1:7" )
|
||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x04, 0x04, "SW1:6" )
|
||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x08, 0x08, "SW1:5" )
|
||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x10, 0x10, "SW1:4" )
|
||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x20, 0x20, "SW1:3" )
|
||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x40, 0x40, "SW1:2" )
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x80, "SW1:1" )
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
|
||||
PORT_START("a80000")
|
||||
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START2 ) /* abort */
|
||||
@ -1136,12 +1323,12 @@ INPUT_PORTS_END
|
||||
static MACHINE_CONFIG_START( driver_nomsp, harddriv_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M68010, 32000000/4)
|
||||
MCFG_CPU_ADD("maincpu", M68010, HARDDRIV_MASTER_CLOCK/4)
|
||||
MCFG_CPU_PROGRAM_MAP(driver_68k_map)
|
||||
MCFG_CPU_VBLANK_INT("screen", atarigen_video_int_gen)
|
||||
MCFG_CPU_PERIODIC_INT(hd68k_irq_gen, (double)32000000/16/16/16/16/2)
|
||||
MCFG_CPU_PERIODIC_INT(hd68k_irq_gen, (double)HARDDRIV_MASTER_CLOCK/16/16/16/16/2)
|
||||
|
||||
MCFG_CPU_ADD("gsp", TMS34010, 48000000)
|
||||
MCFG_CPU_ADD("gsp", TMS34010, HARDDRIV_GSP_CLOCK)
|
||||
MCFG_CPU_PROGRAM_MAP(driver_gsp_map)
|
||||
MCFG_CPU_CONFIG(gsp_config_driver)
|
||||
|
||||
@ -1151,14 +1338,14 @@ static MACHINE_CONFIG_START( driver_nomsp, harddriv_state )
|
||||
MCFG_MACHINE_RESET(harddriv)
|
||||
MCFG_NVRAM_ADD_1FILL("eeprom")
|
||||
|
||||
MCFG_TIMER_ADD("duart_timer", hd68k_duart_callback)
|
||||
MCFG_DUART68681_ADD("duart68681", XTAL_3_6864MHz, duart_config)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
|
||||
MCFG_PALETTE_LENGTH(1024)
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_RAW_PARAMS(4000000*4, 160*4, 0, 127*4, 417, 0, 384)
|
||||
MCFG_SCREEN_RAW_PARAMS(HARDDRIV_GSP_CLOCK/12*4, 160*4, 0, 127*4, 417, 0, 384)
|
||||
MCFG_SCREEN_UPDATE_STATIC(tms340x0_ind16)
|
||||
|
||||
MCFG_VIDEO_START(harddriv)
|
||||
@ -1169,7 +1356,7 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_DERIVED( driver_msp, driver_nomsp )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("msp", TMS34010, 50000000)
|
||||
MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(driver_msp_map)
|
||||
MCFG_CPU_CONFIG(msp_config)
|
||||
MACHINE_CONFIG_END
|
||||
@ -1188,7 +1375,7 @@ static MACHINE_CONFIG_DERIVED( multisync_nomsp, driver_nomsp )
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_MODIFY("screen")
|
||||
MCFG_SCREEN_RAW_PARAMS(6000000*2, 323*2, 0, 256*2, 308, 0, 288)
|
||||
MCFG_SCREEN_RAW_PARAMS(HARDDRIV_GSP_CLOCK/8*2, 323*2, 0, 256*2, 308, 0, 288)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
@ -1196,7 +1383,7 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_DERIVED( multisync_msp, multisync_nomsp )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("msp", TMS34010, 50000000)
|
||||
MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(driver_msp_map)
|
||||
MCFG_CPU_CONFIG(msp_config)
|
||||
MACHINE_CONFIG_END
|
||||
@ -1225,7 +1412,7 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_FRAGMENT( adsp )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("adsp", ADSP2100, 8000000)
|
||||
MCFG_CPU_ADD("adsp", ADSP2100, XTAL_32MHz/4)
|
||||
MCFG_CPU_PROGRAM_MAP(adsp_program_map)
|
||||
MCFG_CPU_DATA_MAP(adsp_data_map)
|
||||
MACHINE_CONFIG_END
|
||||
@ -1235,7 +1422,7 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_FRAGMENT( ds3 )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("adsp", ADSP2101, 12000000)
|
||||
MCFG_CPU_ADD("adsp", ADSP2101, XTAL_12MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(ds3_program_map)
|
||||
MCFG_CPU_DATA_MAP(ds3_data_map)
|
||||
|
||||
@ -1247,7 +1434,7 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_FRAGMENT( ds4 )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("adsp", ADSP2101, 12000000)
|
||||
MCFG_CPU_ADD("adsp", ADSP2101, XTAL_12MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(ds3_program_map)
|
||||
MCFG_CPU_DATA_MAP(ds3_data_map)
|
||||
|
||||
@ -1278,7 +1465,7 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_FRAGMENT( dsk )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("dsp32", DSP32C, 40000000)
|
||||
MCFG_CPU_ADD("dsp32", DSP32C, XTAL_40MHz)
|
||||
MCFG_DSP32C_CONFIG(dsp32c_config)
|
||||
MCFG_CPU_PROGRAM_MAP(dsk_dsp32_map)
|
||||
|
||||
@ -1291,7 +1478,7 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_FRAGMENT( dsk2 )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("dsp32", DSP32C, 40000000)
|
||||
MCFG_CPU_ADD("dsp32", DSP32C, XTAL_40MHz)
|
||||
MCFG_DSP32C_CONFIG(dsp32c_config)
|
||||
MCFG_CPU_PROGRAM_MAP(dsk2_dsp32_map)
|
||||
|
||||
@ -1310,10 +1497,10 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_FRAGMENT( driversnd )
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("soundcpu", M68000, 16000000/2)
|
||||
MCFG_CPU_ADD("soundcpu", M68000, XTAL_16MHz/2)
|
||||
MCFG_CPU_PROGRAM_MAP(driversnd_68k_map)
|
||||
|
||||
MCFG_CPU_ADD("sounddsp", TMS32010, 20000000)
|
||||
MCFG_CPU_ADD("sounddsp", TMS32010, XTAL_20MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(driversnd_dsp_program_map)
|
||||
/* Data Map is internal to the CPU */
|
||||
MCFG_CPU_IO_MAP(driversnd_dsp_io_map)
|
||||
@ -4168,7 +4355,23 @@ static void racedrivc_init_common(running_machine &machine, offs_t gsp_protectio
|
||||
static DRIVER_INIT( racedrivc ) { racedrivc_init_common(machine, 0xfff95cd0); }
|
||||
static DRIVER_INIT( racedrivc1 ) { racedrivc_init_common(machine, 0xfff7ecd0); }
|
||||
|
||||
static DRIVER_INIT( racedrivb1 )
|
||||
{
|
||||
harddriv_state *state = machine.driver_data<harddriv_state>();
|
||||
|
||||
/* this unpleasantness prevents racedrivb1 and racedrivg1 from crashing MAME during boot */
|
||||
/* both clear the DSP32C's RAM and then release it from reset, causing it to run through */
|
||||
/* its address space recursively executing instructions */
|
||||
state->m_dsp32->memory().space(AS_PROGRAM)->install_read_handler(0x002000, 0x5fffff, read32_delegate(FUNC(harddriv_state::rddsp_unmap_r),state));
|
||||
state->m_dsp32->memory().space(AS_PROGRAM)->install_read_handler(0x640000, 0xfff7ff, read32_delegate(FUNC(harddriv_state::rddsp_unmap_r),state));
|
||||
|
||||
DRIVER_INIT_CALL( racedriv );
|
||||
}
|
||||
|
||||
READ32_MEMBER(harddriv_state::rddsp_unmap_r)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ16_MEMBER(harddriv_state::steeltal_dummy_r)
|
||||
{
|
||||
@ -4317,7 +4520,7 @@ GAME( 1988, harddrivb5, harddriv, harddriv, harddriv, harddriv, ROT0, "Atari Gam
|
||||
GAME( 1988, harddrivg4, harddriv, harddriv, harddriv, harddriv, ROT0, "Atari Games", "Hard Drivin' (cockpit, German, rev 4)", 0 )
|
||||
GAME( 1988, harddriv3, harddriv, harddriv, harddriv, harddriv, ROT0, "Atari Games", "Hard Drivin' (cockpit, rev 3)", 0 )
|
||||
GAME( 1988, harddriv2, harddriv, harddriv, harddriv, harddriv, ROT0, "Atari Games", "Hard Drivin' (cockpit, rev 2)", 0 )
|
||||
GAME( 1988, harddriv1, harddriv, harddriv, harddriv, harddriv, ROT0, "Atari Games", "Hard Drivin' (cockpit, rev 1)", GAME_NOT_WORKING )
|
||||
GAME( 1988, harddriv1, harddriv, harddriv, harddriv, harddriv, ROT0, "Atari Games", "Hard Drivin' (cockpit, rev 1)", 0 )
|
||||
|
||||
GAME( 1990, harddrivc, harddriv, harddrivc, racedrivc, harddrivc, ROT0, "Atari Games", "Hard Drivin' (compact, rev 2)", 0 )
|
||||
GAME( 1990, harddrivcg, harddriv, harddrivc, racedrivc, harddrivc, ROT0, "Atari Games", "Hard Drivin' (compact, German, rev 2)", 0 )
|
||||
@ -4336,17 +4539,17 @@ GAME( 1989, stunrun2e, stunrun, stunrun, stunrun, stunrun, ROT0, "Atari Game
|
||||
GAME( 1989, stunrun0, stunrun, stunrun, stunrun, stunrun, ROT0, "Atari Games", "S.T.U.N. Runner (rev 0)", 0 )
|
||||
GAME( 1989, stunrunp, stunrun, stunrun, stunrun, stunrun, ROT0, "Atari Games", "S.T.U.N. Runner (upright prototype)", 0 )
|
||||
|
||||
GAME( 1990, racedriv, 0, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 5)", 0 )
|
||||
GAME( 1990, racedrivb, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, British, rev 5)", 0 )
|
||||
GAME( 1990, racedrivg, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, German, rev 5)", 0 )
|
||||
GAME( 1990, racedriv4, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 4)", 0 )
|
||||
GAME( 1990, racedrivb4, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, British, rev 4)", 0 )
|
||||
GAME( 1990, racedrivg4, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, German, rev 4)", 0 )
|
||||
GAME( 1990, racedriv3, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 3)", GAME_NOT_WORKING )
|
||||
GAME( 1990, racedriv2, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 2)", GAME_NOT_WORKING )
|
||||
GAME( 1990, racedriv1, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 1)", GAME_NOT_WORKING )
|
||||
GAME( 1990, racedrivb1, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, British, rev 1)", GAME_NOT_WORKING )
|
||||
GAME( 1990, racedrivg1, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, German, rev 2)", GAME_NOT_WORKING )
|
||||
GAME( 1990, racedriv, 0, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 5)", 0 )
|
||||
GAME( 1990, racedrivb, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, British, rev 5)", 0 )
|
||||
GAME( 1990, racedrivg, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, German, rev 5)", 0 )
|
||||
GAME( 1990, racedriv4, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 4)", 0 )
|
||||
GAME( 1990, racedrivb4, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, British, rev 4)", 0 )
|
||||
GAME( 1990, racedrivg4, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, German, rev 4)", 0 )
|
||||
GAME( 1990, racedriv3, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 3)", 0 )
|
||||
GAME( 1990, racedriv2, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 2)", 0 )
|
||||
GAME( 1990, racedriv1, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' (cockpit, rev 1)", 0 )
|
||||
GAME( 1990, racedrivb1, racedriv, racedriv, racedriv, racedrivb1, ROT0, "Atari Games", "Race Drivin' (cockpit, British, rev 1)", 0 )
|
||||
GAME( 1990, racedrivg1, racedriv, racedriv, racedriv, racedrivb1, ROT0, "Atari Games", "Race Drivin' (cockpit, German, rev 2)", 0 )
|
||||
|
||||
GAME( 1990, racedrivc, racedriv, racedrivc, racedrivc, racedrivc, ROT0, "Atari Games", "Race Drivin' (compact, rev 5)", 0 )
|
||||
GAME( 1990, racedrivcb, racedriv, racedrivc, racedrivc, racedrivc, ROT0, "Atari Games", "Race Drivin' (compact, British, rev 5)", 0 )
|
||||
@ -4354,8 +4557,8 @@ GAME( 1990, racedrivcg, racedriv, racedrivc, racedrivc, racedrivc, ROT0, "Atari
|
||||
GAME( 1990, racedrivc4, racedriv, racedrivc, racedrivc, racedrivc, ROT0, "Atari Games", "Race Drivin' (compact, rev 4)", 0 )
|
||||
GAME( 1990, racedrivcb4, racedriv, racedrivc, racedrivc, racedrivc, ROT0, "Atari Games", "Race Drivin' (compact, British, rev 4)", 0 )
|
||||
GAME( 1990, racedrivcg4, racedriv, racedrivc, racedrivc, racedrivc, ROT0, "Atari Games", "Race Drivin' (compact, German, rev 4)", 0 )
|
||||
GAME( 1990, racedrivc2, racedriv, racedrivc, racedrivc, racedrivc1,ROT0, "Atari Games", "Race Drivin' (compact, rev 2)", GAME_NOT_WORKING )
|
||||
GAME( 1990, racedrivc1, racedriv, racedrivc, racedrivc, racedrivc1,ROT0, "Atari Games", "Race Drivin' (compact, rev 1)", GAME_NOT_WORKING )
|
||||
GAME( 1990, racedrivc2, racedriv, racedrivc, racedrivc, racedrivc1,ROT0, "Atari Games", "Race Drivin' (compact, rev 2)", 0 )
|
||||
GAME( 1990, racedrivc1, racedriv, racedrivc, racedrivc, racedrivc1,ROT0, "Atari Games", "Race Drivin' (compact, rev 1)", 0 )
|
||||
|
||||
GAME( 1990, racedrivpan, racedriv, racedriv, racedriv, racedriv, ROT0, "Atari Games", "Race Drivin' Panorama (prototype, rev 2.1)", GAME_NOT_WORKING )
|
||||
|
||||
|
||||
@ -11,6 +11,9 @@
|
||||
#include "cpu/dsp32/dsp32.h"
|
||||
#include "machine/atarigen.h"
|
||||
|
||||
#define HARDDRIV_MASTER_CLOCK XTAL_32MHz
|
||||
#define HARDDRIV_GSP_CLOCK XTAL_48MHz
|
||||
|
||||
class harddriv_state : public atarigen_state
|
||||
{
|
||||
public:
|
||||
@ -34,8 +37,7 @@ public:
|
||||
m_gsp_control_lo(*this, "gsp_control_lo"),
|
||||
m_gsp_control_hi(*this, "gsp_control_hi"),
|
||||
m_gsp_paletteram_lo(*this, "gsp_palram_lo"),
|
||||
m_gsp_paletteram_hi(*this, "gsp_palram_hi"),
|
||||
m_duart_timer(*this, "duart_timer") { }
|
||||
m_gsp_paletteram_hi(*this, "gsp_palram_hi") { }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<tms34010_device> m_gsp;
|
||||
@ -95,11 +97,6 @@ public:
|
||||
UINT8 m_adsp_irq_state;
|
||||
UINT8 m_duart_irq_state;
|
||||
|
||||
UINT8 m_duart_read_data[16];
|
||||
UINT8 m_duart_write_data[16];
|
||||
UINT8 m_duart_output_port;
|
||||
optional_device<timer_device> m_duart_timer;
|
||||
|
||||
UINT8 m_last_gsp_shiftreg;
|
||||
|
||||
UINT8 m_m68k_zp1;
|
||||
@ -177,6 +174,7 @@ public:
|
||||
INT8 m_gfx_finescroll;
|
||||
UINT8 m_gfx_palettebank;
|
||||
DECLARE_READ16_MEMBER(steeltal_dummy_r);
|
||||
DECLARE_READ32_MEMBER(rddsp_unmap_r);
|
||||
DECLARE_READ16_MEMBER(hd68k_snd_data_r);
|
||||
DECLARE_READ16_MEMBER(hd68k_snd_status_r);
|
||||
DECLARE_WRITE16_MEMBER(hd68k_snd_data_w);
|
||||
@ -241,9 +239,7 @@ WRITE16_HANDLER( hdc68k_wheel_edge_reset_w );
|
||||
READ16_HANDLER( hd68k_zram_r );
|
||||
WRITE16_HANDLER( hd68k_zram_w );
|
||||
|
||||
TIMER_DEVICE_CALLBACK( hd68k_duart_callback );
|
||||
READ16_HANDLER( hd68k_duart_r );
|
||||
WRITE16_HANDLER( hd68k_duart_w );
|
||||
void harddriv_duart_irq_handler(device_t *device, int state, UINT8 vector);
|
||||
|
||||
WRITE16_HANDLER( hdgsp_io_w );
|
||||
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
*
|
||||
*************************************/
|
||||
|
||||
#define DUART_CLOCK (36864000)
|
||||
#define DS3_TRIGGER 7777
|
||||
|
||||
/* debugging tools */
|
||||
@ -90,11 +89,6 @@ MACHINE_RESET( harddriv )
|
||||
/* reset IRQ states */
|
||||
state->m_irq_state = state->m_gsp_irq_state = state->m_msp_irq_state = state->m_adsp_irq_state = state->m_duart_irq_state = 0;
|
||||
|
||||
/* reset the DUART */
|
||||
memset(state->m_duart_read_data, 0, sizeof(state->m_duart_read_data));
|
||||
memset(state->m_duart_write_data, 0, sizeof(state->m_duart_write_data));
|
||||
state->m_duart_output_port = 0;
|
||||
|
||||
/* reset the ADSP/DSIII/DSIV boards */
|
||||
state->m_adsp_halt = 1;
|
||||
state->m_adsp_br = 0;
|
||||
@ -238,7 +232,7 @@ READ16_HANDLER( hd68k_port0_r )
|
||||
.....
|
||||
0x8000 = SW1 #1
|
||||
*/
|
||||
int temp = space->machine().root_device().ioport("IN0")->read();
|
||||
int temp = (space->machine().root_device().ioport("SW1")->read() << 8) | space->machine().root_device().ioport("IN0")->read();
|
||||
if (atarigen_get_hblank(*space->machine().primary_screen)) temp ^= 0x0002;
|
||||
temp ^= 0x0018; /* both EOCs always high for now */
|
||||
return temp;
|
||||
@ -478,151 +472,18 @@ WRITE16_HANDLER( hd68k_zram_w )
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* 68000 DUART interface
|
||||
* 68681 DUART
|
||||
*
|
||||
*************************************/
|
||||
|
||||
/*
|
||||
DUART registers
|
||||
|
||||
Read Write
|
||||
---------------------------------- -------------------------------------------
|
||||
0x00 = Mode Register A (MR1A, MR2A) Mode Register A (MR1A, MR2A)
|
||||
0x02 = Status Register A (SRA) Clock-Select Register A (CSRA)
|
||||
0x04 = Clock-Select Register A 1 (CSRA) Command Register A (CRA)
|
||||
0x06 = Receiver Buffer A (RBA) Transmitter Buffer A (TBA)
|
||||
0x08 = Input Port Change Register (IPCR) Auxiliary Control Register (ACR)
|
||||
0x0a = Interrupt Status Register (ISR) Interrupt Mask Register (IMR)
|
||||
0x0c = Counter Mode: Current MSB of Counter/Timer Upper Register (CTUR)
|
||||
Counter (CUR)
|
||||
0x0e = Counter Mode: Current LSB of Counter/Timer Lower Register (CTLR)
|
||||
Counter (CLR)
|
||||
0x10 = Mode Register B (MR1B, MR2B) Mode Register B (MR1B, MR2B)
|
||||
0x12 = Status Register B (SRB) Clock-Select Register B (CSRB)
|
||||
0x14 = Clock-Select Register B 2 (CSRB) Command Register B (CRB)
|
||||
0x16 = Receiver Buffer B (RBB) Transmitter Buffer B (TBB)
|
||||
0x18 = Interrupt-Vector Register (IVR) Interrupt-Vector Register (IVR)
|
||||
0x1a = Input Port (IP) Output Port Configuration Register (OPCR)
|
||||
0x1c = Start-Counter Command 3 Output Port Register (OPR): Bit Set Command 3
|
||||
0x1e = Stop-Counter Command 3 Output Port Register (OPR): Bit Reset Command 3
|
||||
*/
|
||||
|
||||
|
||||
INLINE int duart_clock(harddriv_state *state)
|
||||
void harddriv_duart_irq_handler(device_t *device, int state, UINT8 vector)
|
||||
{
|
||||
int mode = (state->m_duart_write_data[0x04] >> 4) & 7;
|
||||
if (mode != 3)
|
||||
logerror("DUART: unsupported clock mode %d\n", mode);
|
||||
return DUART_CLOCK / 16;
|
||||
harddriv_state *hd_state = device->machine().driver_data<harddriv_state>();
|
||||
hd_state->m_duart_irq_state = state;
|
||||
atarigen_update_interrupts(device->machine());
|
||||
}
|
||||
|
||||
|
||||
INLINE attotime duart_clock_period(harddriv_state *state)
|
||||
{
|
||||
return attotime::from_hz(duart_clock(state));
|
||||
}
|
||||
|
||||
|
||||
TIMER_DEVICE_CALLBACK( hd68k_duart_callback )
|
||||
{
|
||||
harddriv_state *state = timer.machine().driver_data<harddriv_state>();
|
||||
logerror("DUART timer fired\n");
|
||||
if (state->m_duart_write_data[0x05] & 0x08)
|
||||
{
|
||||
logerror("DUART interrupt generated\n");
|
||||
state->m_duart_read_data[0x05] |= 0x08;
|
||||
state->m_duart_irq_state = (state->m_duart_read_data[0x05] & state->m_duart_write_data[0x05]) != 0;
|
||||
atarigen_update_interrupts(timer.machine());
|
||||
}
|
||||
timer.adjust(duart_clock_period(state) * 65536);
|
||||
}
|
||||
|
||||
|
||||
READ16_HANDLER( hd68k_duart_r )
|
||||
{
|
||||
harddriv_state *state = space->machine().driver_data<harddriv_state>();
|
||||
switch (offset)
|
||||
{
|
||||
case 0x00: /* Mode Register A (MR1A, MR2A) */
|
||||
case 0x08: /* Mode Register B (MR1B, MR2B) */
|
||||
return (state->m_duart_write_data[0x00] << 8) | 0x00ff;
|
||||
case 0x01: /* Status Register A (SRA) */
|
||||
case 0x02: /* Clock-Select Register A 1 (CSRA) */
|
||||
case 0x03: /* Receiver Buffer A (RBA) */
|
||||
case 0x04: /* Input Port Change Register (IPCR) */
|
||||
case 0x05: /* Interrupt Status Register (ISR) */
|
||||
case 0x06: /* Counter Mode: Current MSB of Counter (CUR) */
|
||||
case 0x07: /* Counter Mode: Current LSB of Counter (CLR) */
|
||||
case 0x09: /* Status Register B (SRB) */
|
||||
case 0x0a: /* Clock-Select Register B 2 (CSRB) */
|
||||
case 0x0b: /* Receiver Buffer B (RBB) */
|
||||
case 0x0c: /* Interrupt-Vector Register (IVR) */
|
||||
case 0x0d: /* Input Port (IP) */
|
||||
return (state->m_duart_read_data[offset] << 8) | 0x00ff;
|
||||
case 0x0e: /* Start-Counter Command 3 */
|
||||
{
|
||||
int reps = (state->m_duart_write_data[0x06] << 8) | state->m_duart_write_data[0x07];
|
||||
state->m_duart_timer->adjust(duart_clock_period(state) * reps);
|
||||
logerror("DUART timer started (period=%f)\n", (duart_clock_period(state) * reps).as_double());
|
||||
return 0x00ff;
|
||||
}
|
||||
case 0x0f: /* Stop-Counter Command 3 */
|
||||
{
|
||||
int reps = (state->m_duart_timer->time_left() * duart_clock(state)).as_double();
|
||||
state->m_duart_timer->reset();
|
||||
state->m_duart_read_data[0x06] = reps >> 8;
|
||||
state->m_duart_read_data[0x07] = reps & 0xff;
|
||||
logerror("DUART timer stopped (final count=%04X)\n", reps);
|
||||
}
|
||||
state->m_duart_read_data[0x05] &= ~0x08;
|
||||
state->m_duart_irq_state = (state->m_duart_read_data[0x05] & state->m_duart_write_data[0x05]) != 0;
|
||||
atarigen_update_interrupts(space->machine());
|
||||
return 0x00ff;
|
||||
}
|
||||
return 0x00ff;
|
||||
}
|
||||
|
||||
|
||||
WRITE16_HANDLER( hd68k_duart_w )
|
||||
{
|
||||
harddriv_state *state = space->machine().driver_data<harddriv_state>();
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
int newdata = (data >> 8) & 0xff;
|
||||
state->m_duart_write_data[offset] = newdata;
|
||||
|
||||
switch (offset)
|
||||
{
|
||||
case 0x00: /* Mode Register A (MR1A, MR2A) */
|
||||
case 0x01: /* Clock-Select Register A (CSRA) */
|
||||
case 0x02: /* Command Register A (CRA) */
|
||||
case 0x03: /* Transmitter Buffer A (TBA) */
|
||||
case 0x04: /* Auxiliary Control Register (ACR) */
|
||||
case 0x05: /* Interrupt Mask Register (IMR) */
|
||||
case 0x06: /* Counter/Timer Upper Register (CTUR) */
|
||||
case 0x07: /* Counter/Timer Lower Register (CTLR) */
|
||||
case 0x08: /* Mode Register B (MR1B, MR2B) */
|
||||
case 0x09: /* Clock-Select Register B (CSRB) */
|
||||
case 0x0a: /* Command Register B (CRB) */
|
||||
case 0x0b: /* Transmitter Buffer B (TBB) */
|
||||
case 0x0c: /* Interrupt-Vector Register (IVR) */
|
||||
case 0x0d: /* Output Port Configuration Register (OPCR) */
|
||||
break;
|
||||
case 0x0e: /* Output Port Register (OPR): Bit Set Command 3 */
|
||||
state->m_duart_output_port |= newdata;
|
||||
break;
|
||||
case 0x0f: /* Output Port Register (OPR): Bit Reset Command 3 */
|
||||
state->m_duart_output_port &= ~newdata;
|
||||
break;
|
||||
}
|
||||
logerror("DUART write %02X @ %02X\n", (data >> 8) & 0xff, offset);
|
||||
}
|
||||
else
|
||||
logerror("Unexpected DUART write %02X @ %02X\n", data, offset);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* GSP I/O register writes
|
||||
|
||||
Loading…
Reference in New Issue
Block a user