mirror of
https://github.com/holub/mame
synced 2025-04-24 17:30:55 +03:00
netlist: Fix the 7448 mess.
Moved truth table implementation of 7448 in macro. At the same time added power terminals and update game netlists accordingly.
This commit is contained in:
couriersud
parent
e669c0c472
commit
a2f8153411
@ -67,8 +67,10 @@ namespace devices
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LIB_ENTRY(2102A_dip)
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LIB_ENTRY(2716)
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LIB_ENTRY(2716_dip)
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#if !(USE_TRUTHTABLE_7448)
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LIB_ENTRY(7448)
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LIB_ENTRY(7448_dip)
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#endif
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LIB_ENTRY(7450)
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LIB_ENTRY(7450_dip)
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LIB_ENTRY(7473)
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@ -7,6 +7,7 @@
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#include "nld_7448.h"
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#include "nlid_truthtable.h"
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#include "nlid_system.h"
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#include <array>
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@ -14,12 +15,7 @@ namespace netlist
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{
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namespace devices
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{
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#if (USE_TRUTHTABLE_7448)
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NETLIB_TRUTHTABLE(7448, 7, 7);
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#else
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#if !(USE_TRUTHTABLE_7448)
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NETLIB_OBJECT(7448)
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{
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NETLIB_CONSTRUCTOR(7448)
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@ -32,6 +28,7 @@ namespace netlist
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, m_RBIQ(*this, "RBIQ")
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, m_state(*this, "m_state", 0)
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, m_Q(*this, {{"a", "b", "c", "d", "e", "f", "g"}})
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, m_power_pins(*this)
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{
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}
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@ -52,6 +49,7 @@ namespace netlist
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state_var<unsigned> m_state;
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object_array_t<logic_output_t, 7> m_Q; /* a .. g */
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nld_power_pins m_power_pins;
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};
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@ -66,6 +64,7 @@ namespace netlist
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register_subalias("5", m_RBIQ);
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register_subalias("6", m_D);
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register_subalias("7", m_A);
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register_subalias("8", "GND");
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register_subalias("9", m_Q[4]); // e
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register_subalias("10", m_Q[3]); // d
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@ -74,66 +73,13 @@ namespace netlist
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register_subalias("13", m_Q[0]); // a
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register_subalias("14", m_Q[6]); // g
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register_subalias("15", m_Q[5]); // f
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register_subalias("16", "VCC");
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}
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};
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#endif
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#if (USE_TRUTHTABLE_7448)
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nld_7448::truthtable_t nld_7448::m_ttbl;
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std::vector<pstring> nld_7448::m_desc = {
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" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g",
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" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100",
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" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100",
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" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100",
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" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100",
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// BI/RBO is input output. In the next case it is used as an input will go low.
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" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100", // RBI
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" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100", // LT
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// This condition has precedence
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" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100", // BI
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""
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};
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NETLIB_OBJECT_DERIVED(7448_dip, 7448)
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{
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NETLIB_CONSTRUCTOR_DERIVED(7448_dip, 7448)
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{
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register_subalias("1", m_I[4]); // B
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register_subalias("2", m_I[5]); // C
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register_subalias("3", m_I[0]); // LTQ
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register_subalias("4", m_I[1]); // BIQ
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register_subalias("5", m_I[2]); // RBIQ
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register_subalias("6", m_I[6]); // D
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register_subalias("7", m_I[3]); // A
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register_subalias("9", m_Q[4]); // e
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register_subalias("10", m_Q[3]); // d
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register_subalias("11", m_Q[2]); // c
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register_subalias("12", m_Q[1]); // b
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register_subalias("13", m_Q[0]); // a
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register_subalias("14", m_Q[6]); // g
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register_subalias("15", m_Q[5]); // f
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}
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};
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#else
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#if !(USE_TRUTHTABLE_7448)
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#define BITS7(b6,b5,b4,b3,b2,b1,b0) ((b6)<<6) | ((b5)<<5) | ((b4)<<4) | ((b3)<<3) | ((b2)<<2) | ((b1)<<1) | ((b0)<<0)
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@ -213,11 +159,11 @@ namespace netlist
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}
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}
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#endif
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NETLIB_DEVICE_IMPL(7448, "TTL_7448", "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ")
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NETLIB_DEVICE_IMPL(7448, "TTL_7448", "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
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NETLIB_DEVICE_IMPL(7448_dip, "TTL_7448_DIP", "")
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#endif
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} //namespace devices
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} // namespace netlist
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@ -27,20 +27,23 @@
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#include "netlist/nl_setup.h"
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#ifndef NL_AUTO_DEVICES
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#define TTL_7448(name, cA0, cA1, cA2, cA3, cLTQ, cBIQ, cRBIQ) \
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NET_REGISTER_DEV(TTL_7448, name) \
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NET_CONNECT(name, A, cA0) \
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NET_CONNECT(name, B, cA1) \
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NET_CONNECT(name, C, cA2) \
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NET_CONNECT(name, D, cA3) \
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NET_CONNECT(name, LTQ, cLTQ) \
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NET_CONNECT(name, BIQ, cBIQ) \
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#if !(USE_TRUTHTABLE_7448)
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#define TTL_7448(name, cA0, cA1, cA2, cA3, cLTQ, cBIQ, cRBIQ) \
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NET_REGISTER_DEV(TTL_7448, name) \
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NET_CONNECT(name, VCC, VCC) \
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NET_CONNECT(name, GND, GND) \
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NET_CONNECT(name, A, cA0) \
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NET_CONNECT(name, B, cA1) \
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NET_CONNECT(name, C, cA2) \
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NET_CONNECT(name, D, cA3) \
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NET_CONNECT(name, LTQ, cLTQ) \
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NET_CONNECT(name, BIQ, cBIQ) \
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NET_CONNECT(name, RBIQ, cRBIQ)
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#define TTL_7448_DIP(name) \
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#define TTL_7448_DIP(name) \
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NET_REGISTER_DEV(TTL_7448_DIP, name)
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#endif
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#endif
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#endif /* NLD_7448_H_ */
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@ -15,19 +15,6 @@
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#include "netlist/nl_setup.h"
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#include "plib/putil.h"
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#define NETLIB_TRUTHTABLE(cname, nIN, nOUT) \
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class NETLIB_NAME(cname) : public nld_truthtable_t<nIN, nOUT> \
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{ \
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public: \
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template <class C> \
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NETLIB_NAME(cname)(C &owner, const pstring &name) \
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: nld_truthtable_t<nIN, nOUT>(owner, name, family_TTL(), &m_ttbl, m_desc) { } \
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private: \
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static truthtable_t m_ttbl; \
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static std::vector<pstring> m_desc; \
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}
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namespace netlist
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{
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namespace devices
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@ -818,6 +818,47 @@ static NETLIST_START(DM9312_DIP)
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)
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NETLIST_END()
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#if (USE_TRUTHTABLE_7448)
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/*
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* DM7448: BCD to 7-Segment decoders/drivers
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*
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* +--------------+
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* B |1 ++ 16| VCC
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* C |2 15| f
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* LAMP TEST |3 14| g
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* BI/RBQ |4 7448 13| a
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* RBI |5 12| b
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* D |6 11| c
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* A |7 10| d
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* GND |8 9| e
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* +--------------+
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*
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*
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* Naming conventions follow National Semiconductor datasheet
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*
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*/
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#ifndef __PLIB_PREPROCESSOR__
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#define TTL_7448_TT(name) \
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NET_REGISTER_DEV(TTL_7448_TT, name)
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#endif
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static NETLIST_START(TTL_7448_DIP)
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TTL_7448_TT(s)
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DIPPINS( /* +--------------+ */
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s.B, /* B |1 ++ 16| VCC */ s.VCC,
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s.C, /* C |2 15| f */ s.f,
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s.LTQ, /* LTQ |3 14| g */ s.g,
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s.BIQ, /* BIQ |4 7448 13| a */ s.a,
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s.RBIQ, /* RBIQ |5 12| b */ s.b,
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s.D, /* D |6 11| c */ s.c,
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s.A, /* A |7 10| d */ s.d,
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s.GND, /* GND |8 9| e */ s.e
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/* +--------------+ */
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)
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NETLIST_END()
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#endif
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NETLIST_START(TTL74XX_lib)
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NET_MODEL("DM7414 SCHMITT_TRIGGER(VTP=1.7 VTM=0.9 VI=4.35 RI=6.15k VOH=3.5 ROH=120 VOL=0.1 ROL=37.5 TPLH=15 TPHL=15)")
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@ -1046,6 +1087,72 @@ NETLIST_START(TTL74XX_lib)
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TT_FAMILY("74XX")
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TRUTHTABLE_END()
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#if (USE_TRUTHTABLE_7448)
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TRUTHTABLE_START(TTL_7448, 7, 7, "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
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TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
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TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
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// BI/RBO is input output. In the next case it is used as an input will go low.
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TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
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TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
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// This condition has precedence
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TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
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TT_FAMILY("74XX")
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TRUTHTABLE_END()
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// FIXME: We need a more elegant solution than defining twice
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TRUTHTABLE_START(TTL_7448_TT, 7, 7, "")
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TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
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TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
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TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
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// BI/RBO is input output. In the next case it is used as an input will go low.
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TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
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TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
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// This condition has precedence
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TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
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TT_FAMILY("74XX")
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TRUTHTABLE_END()
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#endif
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TRUTHTABLE_START(TTL_7437_NAND, 2, 1, "+A,+B")
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TT_HEAD("A,B|Q ")
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TT_LINE("0,X|1|22")
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@ -1197,6 +1304,9 @@ NETLIST_START(TTL74XX_lib)
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LOCAL_LIB_ENTRY(TTL_7430_DIP)
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LOCAL_LIB_ENTRY(TTL_7432_DIP)
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LOCAL_LIB_ENTRY(TTL_7437_DIP)
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#if (USE_TRUTHTABLE_7448)
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LOCAL_LIB_ENTRY(TTL_7448_DIP)
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#endif
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LOCAL_LIB_ENTRY(TTL_7486_DIP)
|
||||
LOCAL_LIB_ENTRY(TTL_74155_DIP)
|
||||
LOCAL_LIB_ENTRY(TTL_74156_DIP)
|
||||
|
||||
@ -209,6 +209,24 @@
|
||||
NET_REGISTER_DEV(TTL_7437_DIP, name)
|
||||
|
||||
|
||||
#if (USE_TRUTHTABLE_7448)
|
||||
#define TTL_7448(name, cA0, cA1, cA2, cA3, cLTQ, cBIQ, cRBIQ) \
|
||||
NET_REGISTER_DEV(TTL_7448, name) \
|
||||
NET_CONNECT(name, VCC, VCC) \
|
||||
NET_CONNECT(name, GND, GND) \
|
||||
NET_CONNECT(name, A, cA0) \
|
||||
NET_CONNECT(name, B, cA1) \
|
||||
NET_CONNECT(name, C, cA2) \
|
||||
NET_CONNECT(name, D, cA3) \
|
||||
NET_CONNECT(name, LTQ, cLTQ) \
|
||||
NET_CONNECT(name, BIQ, cBIQ) \
|
||||
NET_CONNECT(name, RBIQ, cRBIQ)
|
||||
|
||||
#define TTL_7448_DIP(name) \
|
||||
NET_REGISTER_DEV(TTL_7448_DIP, name)
|
||||
|
||||
#endif
|
||||
|
||||
#define TTL_7486_GATE(name) \
|
||||
NET_REGISTER_DEV(TTL_7486_GATE, name)
|
||||
|
||||
|
||||
@ -287,9 +287,6 @@ CIRCUIT_LAYOUT( breakout )
|
||||
CHIP("J3", 7402)
|
||||
DM9312_DIP(J4)
|
||||
CHIP("J5", 7448)
|
||||
#if USE_TRUTHTABLE_7448
|
||||
PARAM(J5.USE_DEACTIVATE, 0) // only use this if compiled with 7448 as a truthtable
|
||||
#endif
|
||||
CHIP("J6", 9310)
|
||||
CHIP("J7", 7420)
|
||||
CHIP("J8", 74279)
|
||||
@ -1715,7 +1712,7 @@ CIRCUIT_LAYOUT( breakout )
|
||||
E1.14, E2.14, E3.14, E4.14, E5.14, E6.14, E7.14, E8.14, E9.14,
|
||||
F2.14, F4.14, F5.14, F6.16, F7.16, F8.14, F9.14,
|
||||
H1.14, H2.14, H3.14, H4.14, H5.16, H6.16, H7.14, H8.14, H9.14,
|
||||
J1.16, J2.14, J3.14, J4.16, J6.16, J7.14, J8.16, J9.14,
|
||||
J1.16, J2.14, J3.14, J4.16, J5.16, J6.16, J7.14, J8.16, J9.14,
|
||||
K1.16, K2.14, K3.14, K4.14, K5.16, K6.16, K7.14, K8.14, K9.14,
|
||||
L1.16, L2.14, L3.16, L4.14, L5.16, L6.16, L7.14, L8.16, L9.14,
|
||||
M1.16, M2.5, M3.14, M4.14, M5.16, M6.16, M8.14, M9.14,
|
||||
@ -1727,7 +1724,7 @@ CIRCUIT_LAYOUT( breakout )
|
||||
E1.7, E2.7, E3.7, E4.7, E5.7, E6.7, E7.7, E8.7, E9.7,
|
||||
F2.7, F4.7, F5.7, F6.8, F7.8, F8.7, F9.7,
|
||||
H1.7, H2.7, H3.7, H4.7, H5.8, H6.8, H7.7, H8.7, H9.7,
|
||||
J1.8, J2.7, J3.7, J4.8, J6.8, J7.7, J8.8, J9.7,
|
||||
J1.8, J2.7, J3.7, J4.8, J5.8, J6.8, J7.7, J8.8, J9.7,
|
||||
K1.8, K2.7, K3.7, K4.7, K5.8, K6.8, K7.7, K8.7, K9.7,
|
||||
L1.8, L2.7, L3.8, L4.7, L5.8, L6.8, L7.7, L8.8, L9.7,
|
||||
M1.8, M2.12, M3.7, M4.7, M5.8, M6.8, M8.7, M9.7,
|
||||
@ -1747,7 +1744,11 @@ CIRCUIT_LAYOUT( breakout )
|
||||
HINT(H2.A, NO_DEACTIVATE)
|
||||
HINT(H3.A, NO_DEACTIVATE)
|
||||
HINT(J3.D, NO_DEACTIVATE)
|
||||
HINT(J5, NO_DEACTIVATE)
|
||||
#if (USE_TRUTHTABLE_7448)
|
||||
HINT(J5.s, NO_DEACTIVATE) // 7448 needs to be disabled in all cases
|
||||
#else
|
||||
HINT(J5, NO_DEACTIVATE) // 7448 needs to be disabled in all cases
|
||||
#endif
|
||||
HINT(J6, NO_DEACTIVATE)
|
||||
HINT(J8.A, NO_DEACTIVATE)
|
||||
HINT(J8.C, NO_DEACTIVATE)
|
||||
|
||||
@ -1207,7 +1207,7 @@ CIRCUIT_LAYOUT( pongdoubles )
|
||||
|
||||
NET_C(V5, A1.16, A2.14, A4.16, A5.14, A6.14, A7.5, A8.14, A9.5,
|
||||
B1.16, B2.14, B3.14, B4.16, B5.5, B6.14, B7.14, B8.14,
|
||||
C1.5, C2.14, C3.14, C4.14, C5.14, C7.16, C8.5, C9.14, C10.14,
|
||||
C1.5, C2.14, C3.14, C4.14, C5.14, C6.16, C7.16, C8.5, C9.14, C10.14,
|
||||
D1.5, D2.14, D3.14, D4.14, D5.14, D6.14, D7.16, D8.5, D9.14, D10.14,
|
||||
E1.14, E2.14, E3.14, E4.14, E5.14, E6.14, E7.14, E8.14, E9.5, E10.5,
|
||||
F1.14, F2.5, F3.14, F4.14, F6.14, F7.14, F8.14, F9.5, F10.5,
|
||||
@ -1216,7 +1216,7 @@ CIRCUIT_LAYOUT( pongdoubles )
|
||||
J1.14, J10.14)
|
||||
NET_C(GND, A1.8, A2.7, A4.8, A5.7, A6.7, A7.10, A8.7, A9.10,
|
||||
B1.8, B2.7, B3.7, B4.8, B5.12, B6.7, B7.7, B8.7,
|
||||
C1.10, C2.7, C3.7, C4.7, C5.7, C7.8, C8.10, C9.7, C10.7,
|
||||
C1.10, C2.7, C3.7, C4.7, C5.7, C6.8, C7.8, C8.10, C9.7, C10.7,
|
||||
D1.10, D2.7, D3.7, D4.7, D5.7, D6.7, D7.8, D8.10, D9.7, D10.7,
|
||||
E1.7, E2.7, E3.7, E4.7, E5.7, E6.7, E7.7, E8.7, E9.10, E10.10,
|
||||
F1.7, F2.10, F3.7, F4.7, F6.7, F7.7, F8.7, F9.10, F10.10,
|
||||
|
||||
@ -1282,7 +1282,7 @@ NETLIST_START(rebound_schematics)
|
||||
F1.14, F2.14, F3.14, F4.14, F5.5, F6.14, F7.14, F8.14, F9.14,
|
||||
H1.14, H2.14, H3.5, H4.14, H5.5, H6.14, H7.14, H8.14, H9.14,
|
||||
J1.14, J2.14, J3.5, J4.14, J5.14, J6.14, J7.14, J8.16, J9.5,
|
||||
K2.5, K3.16, K4.14, K5.14, K6.14, K8.16, K9.5)
|
||||
K2.5, K3.16, K4.14, K5.14, K6.14, K7.16, K8.16, K9.5)
|
||||
NET_C(GND, A1.7,
|
||||
B1.7, B2.7, B3.7, B4.8, B5.7, B6.8, B7.8, B8.7,
|
||||
C1.10, C2.7, C3.7, C4.8, C5.7, C6.7, C7.8, C8.7,
|
||||
@ -1291,5 +1291,5 @@ NETLIST_START(rebound_schematics)
|
||||
F1.7, F2.7, F3.7, F4.7, F5.10, F6.7, F7.7, F8.7, F9.7,
|
||||
H1.7, H2.7, H3.10, H4.7, H5.10, H6.7, H7.7, H8.7, H9.7,
|
||||
J1.7, J2.7, J3.10, J4.7, J5.7, J6.7, J7.7, J8.8, J9.10,
|
||||
K2.10, K3.8, K4.7, K5.7, K6.7, K8.8, K9.10)
|
||||
K2.10, K3.8, K4.7, K5.7, K6.7, K7.8, K8.8, K9.10)
|
||||
NETLIST_END()
|
||||
|
||||
Loading…
Reference in New Issue
Block a user