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Added explicit checks on functions making use of SH4 internal registers to ensure they don't accidentally get used on SH3 (some were) and split the code paths in various places so that areas where the sh3 differs can be implemented properly (interrupt controller especially) Also logging of some internal registers etc. accessed by some games, and rudimentary fixing of a few opcodes (like trap) which were also tied to internal stuff. From Haze (nw)

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This commit is contained in:
Scott Stone 2011-10-03 16:41:06 +00:00
parent ad39fb1a14
commit a2f9a37099
10 changed files with 672 additions and 102 deletions
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2
.gitattributes vendored
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@ -444,6 +444,8 @@ src/emu/cpu/sh2/sh2comn.h svneol=native#text/plain
src/emu/cpu/sh2/sh2dasm.c svneol=native#text/plain
src/emu/cpu/sh2/sh2drc.c svneol=native#text/plain
src/emu/cpu/sh2/sh2fe.c svneol=native#text/plain
src/emu/cpu/sh4/sh3comn.c svneol=native#text/plain
src/emu/cpu/sh4/sh3comn.h svneol=native#text/plain
src/emu/cpu/sh4/sh4.c svneol=native#text/plain
src/emu/cpu/sh4/sh4.h svneol=native#text/plain
src/emu/cpu/sh4/sh4comn.c svneol=native#text/plain

9
src/emu/cpu/cpu.mak
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@ -532,20 +532,25 @@ $(CPUOBJ)/sh2/sh2fe.o: $(CPUSRC)/sh2/sh2fe.c \
ifneq ($(filter SH4,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/sh4
CPUOBJS += $(CPUOBJ)/sh4/sh4.o $(CPUOBJ)/sh4/sh4comn.o
CPUOBJS += $(CPUOBJ)/sh4/sh4.o $(CPUOBJ)/sh4/sh4comn.o $(CPUOBJ)/sh4/sh3comn.o
DASMOBJS += $(CPUOBJ)/sh4/sh4dasm.o
endif
$(CPUOBJ)/sh4/sh4.o: $(CPUSRC)/sh4/sh4.c \
$(CPUSRC)/sh4/sh4.h \
$(CPUSRC)/sh4/sh4regs.h \
$(CPUSRC)/sh4/sh4comn.h
$(CPUSRC)/sh4/sh4comn.h \
$(CPUSRC)/sh4/sh3comn.h
$(CPUOBJ)/sh4/sh4comn.o: $(CPUSRC)/sh4/sh4comn.c \
$(CPUSRC)/sh4/sh4comn.h \
$(CPUSRC)/sh4/sh4regs.h \
$(CPUSRC)/sh4/sh4.h
$(CPUOBJ)/sh4/sh3comn.o: $(CPUSRC)/sh4/sh3comn.c \
$(CPUSRC)/sh4/sh3comn.h \
#-------------------------------------------------
# Hudsonsoft 6280
#-------------------------------------------------

269
src/emu/cpu/sh4/sh3comn.c Normal file
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@ -0,0 +1,269 @@
/* Handlers for SH3 internals */
#include "emu.h"
#include "debugger.h"
#include "sh4.h"
#include "sh4comn.h"
#include "sh3comn.h"
/* High internal area (ffffxxxx) */
WRITE32_HANDLER( sh3_internal_high_w )
{
sh4_state *sh4 = get_safe_token(&space->device());
COMBINE_DATA(&sh4->m_sh3internal_upper[offset]);
}
READ32_HANDLER( sh3_internal_high_r )
{
sh4_state *sh4 = get_safe_token(&space->device());
switch (offset)
{
case SH3_TRA:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
return sh4->m_sh3internal_upper[offset];
case SH3_EXPEVT:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
return sh4->m_sh3internal_upper[offset];
case SH3_INTEVT:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
return sh4->m_sh3internal_upper[offset];
default:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask);
return sh4->m_sh3internal_upper[offset];
}
}
READ32_HANDLER( sh3_internal_r )
{
sh4_state *sh4 = get_safe_token(&space->device());
if (offset<0x1000)
{
switch (offset)
{
case INTEVT2:
{
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset];
}
break;
case PEDR_PFDR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
return (0x20)<<24;
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
}
}
break;
case PJDR_PKDR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
return (0x40)<<24;
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
}
}
break;
default:
{
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
sh4->device->tag(), sh4->pc & AM,
(offset *4)+0x4000000,
mem_mask);
}
break;
}
}
else
{
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
sh4->device->tag(), sh4->pc & AM,
(offset *4)+0x4000000,
mem_mask);
}
return 0;
}
/* Lower internal area */
WRITE32_HANDLER( sh3_internal_w )
{
sh4_state *sh4 = get_safe_token(&space->device());
if (offset<0x1000)
{
//UINT32 old = sh4->m_sh3internal_lower[offset];
COMBINE_DATA(&sh4->m_sh3internal_lower[offset]);
switch (offset)
{
case PINTER_IPRC:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
case PCCR_PDCR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
case PECR_PFCR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
case PGCR_PHCR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
case PJCR_PKCR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
case PLCR_SCPCR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
case PEDR_PFDR:
{
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
case PJDR_PKDR:
{
if (mem_mask & 0xffff0000)
{
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
if (mem_mask & 0x0000ffff)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
}
}
break;
default:
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
sh4->device->tag(), sh4->pc & AM,
(offset *4)+0x4000000,
data,
mem_mask);
}
break;
}
}
else
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
sh4->device->tag(), sh4->pc & AM,
(offset *4)+0x4000000,
data,
mem_mask);
}
}

32
src/emu/cpu/sh4/sh3comn.h Normal file
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@ -0,0 +1,32 @@
#pragma once
#ifndef __SH3COMN_H__
#define __SH3COMN_H__
/* SH3 lower area regs */
#define SH3_LOWER_REGBASE (0x04000000)
#define SH3_LOWER_REGEND (0x07ffffff)
#define INTEVT2 ((0x4000000 - SH3_LOWER_REGBASE)/4)
#define PINTER_IPRC ((0x4000014 - SH3_LOWER_REGBASE)/4)
#define PCCR_PDCR ((0x4000104 - SH3_LOWER_REGBASE)/4)
#define PECR_PFCR ((0x4000108 - SH3_LOWER_REGBASE)/4)
#define PGCR_PHCR ((0x400010c - SH3_LOWER_REGBASE)/4)
#define PJCR_PKCR ((0x4000110 - SH3_LOWER_REGBASE)/4)
#define PLCR_SCPCR ((0x4000114 - SH3_LOWER_REGBASE)/4)
#define PEDR_PFDR ((0x4000128 - SH3_LOWER_REGBASE)/4)
#define PJDR_PKDR ((0x4000130 - SH3_LOWER_REGBASE)/4)
/* SH3 upper area */
#define SH3_UPPER_REGBASE (0xffffd000)
#define SH3_UPPER_REGEND (0xffffffff)
#define SH3_TRA ((0xffffffd0 - SH3_UPPER_REGBASE)/4)
#define SH3_EXPEVT ((0xffffffd4 - SH3_UPPER_REGBASE)/4)
#define SH3_INTEVT ((0xffffffd8 - SH3_UPPER_REGBASE)/4)
#endif /* __SH3COMN_H__ */

84
src/emu/cpu/sh4/sh4.c
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@ -27,6 +27,7 @@
#include "sh4.h"
#include "sh4regs.h"
#include "sh4comn.h"
#include "sh3comn.h"
#ifndef USE_SH4DRC
@ -1707,7 +1708,16 @@ INLINE void TRAPA(sh4_state *sh4, UINT32 i)
{
UINT32 imm = i & 0xff;
sh4->m[TRA] = imm;
if (sh4->cpu_type == CPU_TYPE_SH4)
{
sh4->m[SH3_TRA] = imm;
}
else /* SH3 */
{
sh4->m_sh3internal_upper[SH3_TRA] = imm;
}
sh4->ssr = sh4->sr;
sh4->spc = sh4->pc;
sh4->sgr = sh4->r[15];
@ -1721,7 +1731,15 @@ INLINE void TRAPA(sh4_state *sh4, UINT32 i)
sh4->sr |= BL;
sh4_exception_recompute(sh4);
sh4->m[EXPEVT] = 0x00000160;
if (sh4->cpu_type == CPU_TYPE_SH4)
{
sh4->m[SH3_EXPEVT] = 0x00000160;
}
else /* SH3 */
{
sh4->m_sh3internal_upper[SH3_EXPEVT] = 0x00000160;
}
sh4->pc = sh4->vbr + 0x00000100;
sh4->sh4_icount -= 7;
@ -2064,9 +2082,28 @@ INLINE void PREFM(sh4_state *sh4, UINT32 n)
sq = (addr & 0x20) >> 5;
dest = addr & 0x03FFFFE0;
if (sq == 0)
dest |= (sh4->m[QACR0] & 0x1C) << 24;
{
if (sh4->cpu_type == CPU_TYPE_SH4)
{
dest |= (sh4->m[QACR0] & 0x1C) << 24;
}
else
{
fatalerror("sh4->cpu_type != CPU_TYPE_SH4 but access internal regs\n");
}
}
else
dest |= (sh4->m[QACR1] & 0x1C) << 24;
{
if (sh4->cpu_type == CPU_TYPE_SH4)
{
dest |= (sh4->m[QACR1] & 0x1C) << 24;
}
else
{
fatalerror("sh4->cpu_type != CPU_TYPE_SH4 but access internal regs\n");
}
}
addr = addr & 0xFFFFFFE0;
}
@ -3187,7 +3224,7 @@ INLINE void op1111(sh4_state *sh4, UINT16 opcode)
* MAME CPU INTERFACE
*****************************************************************************/
static CPU_RESET( sh4 )
static CPU_RESET( common_sh4_reset )
{
sh4_state *sh4 = get_safe_token(device);
emu_timer *tsaved[4];
@ -3244,13 +3281,17 @@ static CPU_RESET( sh4 )
memset(sh4->exception_requesting, 0, sizeof(sh4->exception_requesting));
sh4->rtc_timer->adjust(attotime::from_hz(128));
sh4->m[RCR2] = 0x09;
sh4->m[TCOR0] = 0xffffffff;
sh4->m[TCNT0] = 0xffffffff;
sh4->m[TCOR1] = 0xffffffff;
sh4->m[TCNT1] = 0xffffffff;
sh4->m[TCOR2] = 0xffffffff;
sh4->m[TCNT2] = 0xffffffff;
if (sh4->cpu_type == CPU_TYPE_SH4)
{
sh4->m[RCR2] = 0x09;
sh4->m[TCOR0] = 0xffffffff;
sh4->m[TCNT0] = 0xffffffff;
sh4->m[TCOR1] = 0xffffffff;
sh4->m[TCNT1] = 0xffffffff;
sh4->m[TCOR2] = 0xffffffff;
sh4->m[TCNT2] = 0xffffffff;
}
sh4->pc = 0xa0000000;
sh4->r[15] = RL(sh4,4);
@ -3266,8 +3307,6 @@ static CPU_RESET( sh4 )
sh4->sleep_mode = 0;
sh4->sh4_mmu_enabled = 0;
sh4->cpu_type = CPU_TYPE_SH4;
}
/*-------------------------------------------------
@ -3277,8 +3316,21 @@ static CPU_RESET( sh4 )
static CPU_RESET( sh3 )
{
sh4_state *sh4 = get_safe_token(device);
CPU_RESET_CALL(sh4);
CPU_RESET_CALL(common_sh4_reset);
sh4->cpu_type = CPU_TYPE_SH3;
}
static CPU_RESET( sh4 )
{
sh4_state *sh4 = get_safe_token(device);
CPU_RESET_CALL(common_sh4_reset);
sh4->cpu_type = CPU_TYPE_SH4;
}
/* Execute cycles - returns number of cycles actually run */
@ -3649,6 +3701,8 @@ static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64 )
ADDRESS_MAP_END
static ADDRESS_MAP_START( sh3_internal_map, AS_PROGRAM, 64 )
AM_RANGE(SH3_LOWER_REGBASE, SH3_LOWER_REGEND) AM_READWRITE32(sh3_internal_r, sh3_internal_w, U64(0xffffffffffffffff))
AM_RANGE(SH3_UPPER_REGBASE, SH3_UPPER_REGEND) AM_READWRITE32(sh3_internal_high_r, sh3_internal_high_w, U64(0xffffffffffffffff))
ADDRESS_MAP_END

7
src/emu/cpu/sh4/sh4.h
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@ -107,6 +107,13 @@ DECLARE_LEGACY_CPU_DEVICE(SH4BE, sh4be);
WRITE32_HANDLER( sh4_internal_w );
READ32_HANDLER( sh4_internal_r );
WRITE32_HANDLER( sh3_internal_w );
READ32_HANDLER( sh3_internal_r );
WRITE32_HANDLER( sh3_internal_high_w );
READ32_HANDLER( sh3_internal_high_r );
void sh4_set_frt_input(device_t *device, int state);
void sh4_set_irln_input(device_t *device, int value);
void sh4_set_ftcsr_callback(device_t *device, sh4_ftcsr_callback callback);

289
src/emu/cpu/sh4/sh4comn.c
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@ -11,6 +11,7 @@
#include "sh4.h"
#include "sh4regs.h"
#include "sh4comn.h"
#include "sh3comn.h"
static const int tcnt_div[8] = { 4, 16, 64, 256, 1024, 1, 1, 1 };
static const int rtcnt_div[8] = { 0, 4, 16, 64, 256, 1024, 2048, 4096 };
@ -26,6 +27,8 @@ static const int exception_codes[] = { 0x000, 0x020, 0x000, 0x140, 0x140, 0x1E0,
0x7E0, 0x6C0, 0xB00, 0xB80, 0x400, 0x420, 0x440, 0x460, 0x480, 0x4A0, 0x4C0, 0x4E0, 0x500, 0x520, 0x540, 0x700, 0x720, 0x740, 0x760,
0x560, 0x580, 0x5A0 };
/* SH3 INTEVT2 uses a different table */
static const UINT16 tcnt[] = { TCNT0, TCNT1, TCNT2 };
static const UINT16 tcor[] = { TCOR0, TCOR1, TCOR2 };
static const UINT16 tcr[] = { TCR0, TCR1, TCR2 };
@ -161,30 +164,76 @@ void sh4_exception(sh4_state *sh4, const char *message, int exception) // handle
{
UINT32 vector;
if (exception < SH4_INTC_NMI)
return; // Not yet supported
if (exception == SH4_INTC_NMI) {
if ((sh4->sr & BL) && (!(sh4->m[ICR] & 0x200)))
if (sh4->cpu_type == CPU_TYPE_SH4)
{
if (exception < SH4_INTC_NMI)
return; // Not yet supported
if (exception == SH4_INTC_NMI) {
if ((sh4->sr & BL) && (!(sh4->m[ICR] & 0x200)))
return;
sh4->m[ICR] &= ~0x200;
sh4->m[INTEVT] = 0x1c0;
vector = 0x600;
sh4->irq_callback(sh4->device, INPUT_LINE_NMI);
LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4->device->tag(), message));
} else {
// if ((sh4->m[ICR] & 0x4000) && (sh4->nmi_line_state == ASSERT_LINE))
// return;
if (sh4->sr & BL)
return;
if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
return;
sh4->m[INTEVT] = exception_codes[exception];
vector = 0x600;
if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
sh4->irq_callback(sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
else
sh4->irq_callback(sh4->device, SH4_IRL3+1);
LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
}
}
else /* SH3 exceptions */
{
/***** ASSUME THIS TO BE WRONG FOR NOW *****/
if (exception < SH4_INTC_NMI)
return; // Not yet supported
if (exception == SH4_INTC_NMI)
{
return;
sh4->m[ICR] &= ~0x200;
sh4->m[INTEVT] = 0x1c0;
vector = 0x600;
sh4->irq_callback(sh4->device, INPUT_LINE_NMI);
LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4->device->tag(), message));
} else {
// if ((sh4->m[ICR] & 0x4000) && (sh4->nmi_line_state == ASSERT_LINE))
// return;
if (sh4->sr & BL)
return;
if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
return;
sh4->m[INTEVT] = exception_codes[exception];
vector = 0x600;
if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
sh4->irq_callback(sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
}
else
sh4->irq_callback(sh4->device, SH4_IRL3+1);
LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
{
if (sh4->sr & BL)
return;
if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
return;
vector = 0x600;
int callbackval = 0;
if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
callbackval = sh4->irq_callback(sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
else
callbackval = sh4->irq_callback(sh4->device, SH4_IRL3+1);
// we should put the value here based on a table, like the regular exception codes! (values are different tho)
//printf("exception %04x\n", exception);
//sh4->m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception];
sh4->m_sh3internal_lower[INTEVT2] = callbackval;
sh4->m_sh3internal_upper[SH3_EXPEVT] = exception_codes[exception];
LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
}
/***** END ASSUME THIS TO BE WRONG FOR NOW *****/
}
sh4_exception_checkunrequest(sh4, exception);
@ -219,6 +268,10 @@ static void sh4_refresh_timer_recompute(sh4_state *sh4)
{
UINT32 ticks;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_refresh_timer_recompute uses sh4->m[] with SH3\n");
//if rtcnt < rtcor then rtcor-rtcnt
//if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt
ticks = sh4->m[RTCOR]-sh4->m[RTCNT];
@ -250,6 +303,10 @@ static void sh4_timer_recompute(sh4_state *sh4, int which)
{
double ticks;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_timer_recompute uses sh4->m[] with SH3\n");
ticks = sh4->m[tcnt[which]];
sh4->timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(sh4->pm_clock) * tcnt_div[sh4->m[tcr[which]] & 7], ticks), which);
}
@ -258,6 +315,9 @@ static TIMER_CALLBACK( sh4_refresh_timer_callback )
{
sh4_state *sh4 = (sh4_state *)ptr;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_refresh_timer_callback uses sh4->m[] with SH3\n");
sh4->m[RTCNT] = 0;
sh4_refresh_timer_recompute(sh4);
sh4->m[RTCSR] |= 128;
@ -276,6 +336,9 @@ static void increment_rtc_time(sh4_state *sh4, int mode)
{
int carry, year, leap, days;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("increment_rtc_time uses sh4->m[] with SH3\n");
if (mode == 0)
{
carry = 0;
@ -369,6 +432,12 @@ static TIMER_CALLBACK( sh4_rtc_timer_callback )
{
sh4_state *sh4 = (sh4_state *)ptr;
if (sh4->cpu_type != CPU_TYPE_SH4)
{
logerror("sh4_rtc_timer_callback uses sh4->m[] with SH3\n");
return;
}
sh4->rtc_timer->adjust(attotime::from_hz(128));
sh4->m[R64CNT] = (sh4->m[R64CNT]+1) & 0x7f;
if (sh4->m[R64CNT] == 64)
@ -386,6 +455,9 @@ static TIMER_CALLBACK( sh4_timer_callback )
int which = param;
int idx = tcr[which];
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_timer_callback uses sh4->m[] with SH3\n");
sh4->m[tcnt[which]] = sh4->m[tcor[which]];
sh4_timer_recompute(sh4, which);
sh4->m[idx] = sh4->m[idx] | 0x100;
@ -398,6 +470,9 @@ static TIMER_CALLBACK( sh4_dmac_callback )
sh4_state *sh4 = (sh4_state *)ptr;
int channel = param;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_dmac_callback uses sh4->m[] with SH3\n");
LOG(("SH4 '%s': DMA %d complete\n", sh4->device->tag(), channel));
sh4->dma_timer_active[channel] = 0;
switch (channel)
@ -601,6 +676,9 @@ static void sh4_dmac_check(sh4_state *sh4, int channel)
{
UINT32 dmatcr, chcr, sar, dar;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_dmac_check uses sh4->m[] with SH3\n");
switch (channel)
{
case 0:
@ -657,6 +735,9 @@ static void sh4_dmac_nmi(sh4_state *sh4) // manage dma when nmi gets asserted
{
int s;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_dmac_nmi uses sh4->m[] with SH3\n");
sh4->m[DMAOR] |= DMAOR_NMIF;
for (s = 0;s < 4;s++)
{
@ -676,6 +757,9 @@ WRITE32_HANDLER( sh4_internal_w )
UINT32 addr = (offset << 2) + 0xfe000000;
offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_internal_w uses sh4->m[] with SH3\n");
UINT32 old = sh4->m[offset];
COMBINE_DATA(sh4->m+offset);
@ -991,6 +1075,9 @@ READ32_HANDLER( sh4_internal_r )
{
sh4_state *sh4 = get_safe_token(&space->device());
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_internal_r uses sh4->m[] with SH3\n");
UINT32 addr = (offset << 2) + 0xfe000000;
offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
@ -1058,6 +1145,9 @@ void sh4_set_frt_input(device_t *device, int state)
{
sh4_state *sh4 = get_safe_token(device);
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n");
if(state == PULSE_LINE)
{
sh4_set_frt_input(device, ASSERT_LINE);
@ -1071,15 +1161,23 @@ void sh4_set_frt_input(device_t *device, int state)
sh4->frt_input = state;
if(sh4->m[5] & 0x8000) {
if(state == CLEAR_LINE) {
return;
}
} else {
if(state == ASSERT_LINE) {
return;
if (sh4->cpu_type == CPU_TYPE_SH4)
{
if(sh4->m[5] & 0x8000) {
if(state == CLEAR_LINE) {
return;
}
} else {
if(state == ASSERT_LINE) {
return;
}
}
}
else
{
fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n");
}
#if 0
sh4_timer_resync();
@ -1103,42 +1201,18 @@ void sh4_set_irln_input(device_t *device, int value)
void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of external interrupt line
{
int s;
if (irqline == INPUT_LINE_NMI)
{
if (sh4->nmi_line_state == state)
return;
if (sh4->m[ICR] & 0x100)
{
if ((state == CLEAR_LINE) && (sh4->nmi_line_state == ASSERT_LINE)) // rising
{
LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
sh4_exception_request(sh4, SH4_INTC_NMI);
sh4_dmac_nmi(sh4);
}
}
else
{
if ((state == ASSERT_LINE) && (sh4->nmi_line_state == CLEAR_LINE)) // falling
{
LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
sh4_exception_request(sh4, SH4_INTC_NMI);
sh4_dmac_nmi(sh4);
}
}
if (state == CLEAR_LINE)
sh4->m[ICR] ^= 0x8000;
else
sh4->m[ICR] |= 0x8000;
sh4->nmi_line_state = state;
}
else
if (sh4->cpu_type == CPU_TYPE_SH3)
{
if (sh4->m[ICR] & 0x80) // four independent external interrupt sources
/***** ASSUME THIS TO BE WRONG FOR NOW *****/
if (irqline == INPUT_LINE_NMI)
{
if (irqline > SH4_IRL3)
return;
fatalerror("SH3 NMI Unimplemented\n");
}
else
{
//if (irqline > SH4_IRL3)
// return;
if (sh4->irq_line_state[irqline] == state)
return;
sh4->irq_line_state[irqline] = state;
@ -1153,22 +1227,80 @@ void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of ex
LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline));
sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
}
}
else // level-encoded interrupt
{
if (irqline != SH4_IRLn)
return;
if ((sh4->irln > 15) || (sh4->irln < 0))
return;
for (s = 0; s < 15; s++)
sh4_exception_unrequest(sh4, SH4_INTC_IRLn0+s);
if (sh4->irln < 15)
sh4_exception_request(sh4, SH4_INTC_IRLn0+sh4->irln);
LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4->device->tag(), sh4->irln));
}
/***** END ASSUME THIS TO BE WRONG FOR NOW *****/
}
else
{
int s;
if (irqline == INPUT_LINE_NMI)
{
if (sh4->nmi_line_state == state)
return;
if (sh4->m[ICR] & 0x100)
{
if ((state == CLEAR_LINE) && (sh4->nmi_line_state == ASSERT_LINE)) // rising
{
LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
sh4_exception_request(sh4, SH4_INTC_NMI);
sh4_dmac_nmi(sh4);
}
}
else
{
if ((state == ASSERT_LINE) && (sh4->nmi_line_state == CLEAR_LINE)) // falling
{
LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
sh4_exception_request(sh4, SH4_INTC_NMI);
sh4_dmac_nmi(sh4);
}
}
if (state == CLEAR_LINE)
sh4->m[ICR] ^= 0x8000;
else
sh4->m[ICR] |= 0x8000;
sh4->nmi_line_state = state;
}
else
{
if (sh4->m[ICR] & 0x80) // four independent external interrupt sources
{
if (irqline > SH4_IRL3)
return;
if (sh4->irq_line_state[irqline] == state)
return;
sh4->irq_line_state[irqline] = state;
if( state == CLEAR_LINE )
{
LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4->device->tag(), irqline));
sh4_exception_unrequest(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
}
else
{
LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline));
sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
}
}
else // level-encoded interrupt
{
if (irqline != SH4_IRLn)
return;
if ((sh4->irln > 15) || (sh4->irln < 0))
return;
for (s = 0; s < 15; s++)
sh4_exception_unrequest(sh4, SH4_INTC_IRLn0+s);
if (sh4->irln < 15)
sh4_exception_request(sh4, SH4_INTC_IRLn0+sh4->irln);
LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4->device->tag(), sh4->irln));
}
}
if (sh4->test_irq && (!sh4->delay))
sh4_check_pending_irq(sh4, "sh4_set_irq_line");
}
if (sh4->test_irq && (!sh4->delay))
sh4_check_pending_irq(sh4, "sh4_set_irq_line");
}
void sh4_parse_configuration(sh4_state *sh4, const struct sh4_config *conf)
@ -1388,6 +1520,9 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
UINT64 *p32bytes;
UINT32 pos,len,siz;
if (sh4->cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_dma_ddt uses sh4->m[] with SH3\n");
if (sh4->dma_timer_active[s->channel])
return;
if (s->mode >= 0) {

8
src/emu/cpu/sh4/sh4comn.h
View File

@ -78,7 +78,14 @@ typedef struct
address_space *program;
direct_read_data *direct;
address_space *io;
// sh4 internal
UINT32 *m;
// sh3 internal
UINT32 m_sh3internal_upper[0x3000/4];
UINT32 m_sh3internal_lower[0x1000];
INT8 nmi_line_state;
UINT8 sleep_mode;
@ -272,6 +279,7 @@ UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address);
READ64_HANDLER( sh4_tlb_r );
WRITE64_HANDLER( sh4_tlb_w );
INLINE void sh4_check_pending_irq(sh4_state *sh4, const char *message) // look for highest priority active exception and handle it
{
int a,irq,z;

73
src/mame/drivers/cavesh3.c
View File

@ -24,6 +24,19 @@ SCREEN_UPDATE(cavesh3)
return 0;
}
static READ64_HANDLER( cave_unk_status_r )
{
static int i = 0;
i^=1;
logerror("'maincpu' (%08x): unmapped cavesh3 read from %08x mask %08x%08x (unknown)\n",cpu_get_pc(&space->device()),(offset *8)+0x18000010,(UINT32)((mem_mask>>32)&0xffffffff),(UINT32)(mem_mask&0xffffffff));
if (i==0)
return U64(0xffffffffffffffff);
else
return U64(0x0000000000000000);
}
static ADDRESS_MAP_START( cavesh3_map, AS_PROGRAM, 64 )
AM_RANGE(0x00000000, 0x001fffff) AM_ROM AM_REGION("maincpu", 0)
@ -31,6 +44,8 @@ static ADDRESS_MAP_START( cavesh3_map, AS_PROGRAM, 64 )
// I/O at 040xxxxx - 04000130 appears to be the FPGA programming port
// NAND at 0b00xxxx (the "u2" ROM is read this way)
AM_RANGE(0x0c000000, 0x0c7fffff) AM_RAM // work RAM
AM_RANGE(0x18000010, 0x18000017) AM_READ(cave_unk_status_r)
AM_RANGE(0xF0000000, 0xF0003fff) AM_RAM // mem mapped cache (sh3 internal?)
ADDRESS_MAP_END
static ADDRESS_MAP_START( cavesh3_port, AS_IO, 64 )
@ -45,12 +60,39 @@ INPUT_PORTS_END
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CAVE_CPU_CLOCK };
/*static TIMER_CALLBACK( cavesh3_interrupt_off )
{
cputag_set_input_line(machine, "maincpu", 3, CLEAR_LINE);
}
*/
static IRQ_CALLBACK(cavesh3_int_callback)
{
printf("irqline %02x\n",irqline);
cputag_set_input_line(device->machine(), "maincpu", 2, CLEAR_LINE);
return 0x640; // hack vector until SH3 core works better
}
static INTERRUPT_GEN(cavesh3_interrupt)
{
device_set_input_line(device, 2, ASSERT_LINE);
// device->machine().scheduler().timer_set(downcast<cpu_device *>(device)->cycles_to_attotime(10000), FUNC(cavesh3_interrupt_off));
}
static MACHINE_RESET( cavesh3 )
{
device_set_irq_callback(machine.device("maincpu"), cavesh3_int_callback);
}
static MACHINE_CONFIG_START( cavesh3, cavesh3_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", SH3BE, CAVE_CPU_CLOCK)
MCFG_CPU_CONFIG(sh4cpu_config)
MCFG_CPU_PROGRAM_MAP(cavesh3_map)
MCFG_CPU_IO_MAP(cavesh3_port)
MCFG_CPU_VBLANK_INT("screen", cavesh3_interrupt)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -60,6 +102,7 @@ static MACHINE_CONFIG_START( cavesh3, cavesh3_state )
MCFG_SCREEN_SIZE(640, 480)
MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
MCFG_SCREEN_UPDATE(cavesh3)
MCFG_MACHINE_RESET(cavesh3)
MCFG_PALETTE_LENGTH(0x1000)
@ -102,7 +145,7 @@ ROM_START( espgal2 )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(09c908bb) SHA1(7d6031fd3542b3e1d296ff218feb40502fd78694) ) /* (2005/11/14 MASTER VER) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(222f58c7) SHA1(d47a5085a1debd9cb8c61d88cd39e4f5036d1797) ) /* (2005/11/14 MASTER VER) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(222f58c7) SHA1(d47a5085a1debd9cb8c61d88cd39e4f5036d1797) ) /* (2005/11/14 MASTER VER) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(b9a10c22) SHA1(4561f95c6018c9716077224bfe9660e61fb84681) )
@ -150,7 +193,7 @@ ROM_START( futari10 )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(b127dca7) SHA1(e1f518bc72fc1cdf69aefa89eafa4edaf4e84778) ) /* (2006/10/23 MASTER VER.) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(78ffcd0c) SHA1(0e2937edec15ce3f5741b72ebd3bbaaefffb556e) ) /* (2006/10/23 MASTER VER.) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(78ffcd0c) SHA1(0e2937edec15ce3f5741b72ebd3bbaaefffb556e) ) /* (2006/10/23 MASTER VER.) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(39f1e1f4) SHA1(53d12f59a56df35c705408c76e6e02118da656f1) )
@ -162,7 +205,7 @@ ROM_START( futariblk )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(6db13c62) SHA1(6a53ce7f70b754936ccbb3a4674d4b2f03979644) ) /* (2007/12/11 BLACK LABEL VER) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(08c6fd62) SHA1(e1fc386b2b0e41906c724287cbf82304297e0150) ) /* (2007/12/11 BLACK LABEL VER) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(08c6fd62) SHA1(e1fc386b2b0e41906c724287cbf82304297e0150) ) /* (2007/12/11 BLACK LABEL VER) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(39f1e1f4) SHA1(53d12f59a56df35c705408c76e6e02118da656f1) )
@ -174,7 +217,7 @@ ROM_START( ibara )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(8e6c155d) SHA1(38ac2107dc7824836e2b4e04c7180d5ae43c9b79) ) /* (2005/03/22 MASTER VER..) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(55840976) SHA1(4982bdce84f9603adfed7a618f18bc80359ab81e) ) /* (2005/03/22 MASTER VER..) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(55840976) SHA1(4982bdce84f9603adfed7a618f18bc80359ab81e) ) /* (2005/03/22 MASTER VER..) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(ee5e585d) SHA1(7eeba4ee693060e927f8c46b16e39227c6a62392) )
@ -186,7 +229,7 @@ ROM_START( ibarablk )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(ee1f1f77) SHA1(ac276f3955aa4dde2544af4912819a7ae6bcf8dd) ) /* (2006/02/06. MASTER VER.) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(5e46be44) SHA1(bed5f1bf452f2cac58747ecabec3c4392566a3a7) ) /* (2006/02/06. MASTER VER.) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(5e46be44) SHA1(bed5f1bf452f2cac58747ecabec3c4392566a3a7) ) /* (2006/02/06. MASTER VER.) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(a436bb22) SHA1(0556e771cc02638bf8814315ba671c2d442594f1) ) /* (2006/02/06 MASTER VER.) */
@ -198,7 +241,7 @@ ROM_START( ibarablka )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(a9d43839) SHA1(507696e616608c05893c7ac2814b3365e9cb0720) ) /* (2006/02/06 MASTER VER.) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(33400d96) SHA1(09c22b5431ac3726bf88c56efd970f56793f825a) ) /* (2006/02/06 MASTER VER.) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(33400d96) SHA1(09c22b5431ac3726bf88c56efd970f56793f825a) ) /* (2006/02/06 MASTER VER.) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(a436bb22) SHA1(0556e771cc02638bf8814315ba671c2d442594f1) ) /* (2006/02/06 MASTER VER.) */
@ -210,7 +253,7 @@ ROM_START( deathsml )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(1a7b98bf) SHA1(07798a4a846e5802756396b34df47d106895c1f1) ) /* (2007/10/09 MASTER VER) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(d45b0698) SHA1(7077b9445f5ed4749c7f683191ccd312180fac38) ) /* (2007/10/09 MASTER VER) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(d45b0698) SHA1(7077b9445f5ed4749c7f683191ccd312180fac38) ) /* (2007/10/09 MASTER VER) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(aab718c8) SHA1(0e636c46d06151abd6f73232bc479dafcafe5327) )
@ -222,13 +265,26 @@ ROM_START( mmpork )
ROM_LOAD16_WORD_SWAP( "u4", 0x000000, 0x200000, CRC(d06cfa42) SHA1(5707feb4b3e5265daf5926f38c38612b24106f1f) ) /* (2007/ 4/17 MASTER VER.) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u2", 0x000000, 0x8400000, CRC(1ee961b8) SHA1(81a2eba704ac1cf7fc44fa7c6a3f50e3570c104f) ) /* (2007/ 4/17 MASTER VER.) */
ROM_LOAD( "u2", 0x000000, 0x8400000, CRC(1ee961b8) SHA1(81a2eba704ac1cf7fc44fa7c6a3f50e3570c104f) ) /* (2007/ 4/17 MASTER VER.) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(4a4b36df) SHA1(5db5ce6fa47e5ca3263d4bd19315890c6d29df66) )
ROM_LOAD16_WORD_SWAP( "u24", 0x400000, 0x400000, CRC(ce83d07b) SHA1(a5947467c8f5b7c4b0ad8e32df2ee29b787e355f) )
ROM_END
ROM_START( mmmbnk )
ROM_REGION( 0x200000, "maincpu", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u4", 0x0000, 0x200000, CRC(5589d8c6) SHA1(43fbdb0effe2bc0e7135698757b6ee50200aecde) ) /* (2007/06/05 MASTER VER.) */
ROM_REGION64_BE( 0x8400000, "game", ROMREGION_ERASEFF)
ROM_LOAD( "u2", 0x0000, 0x8400000, CRC(f3b50c30) SHA1(962327798081b292b2d3fd3b7845c0197f9f2d8a) ) /* (2007/06/05 MASTER VER.) */
ROM_REGION( 0x800000, "samples", ROMREGION_ERASEFF)
ROM_LOAD16_WORD_SWAP( "u23", 0x000000, 0x400000, CRC(4caaa1bf) SHA1(9b92c13eac05601da4d9bb3eb727c156974e9f0c) )
ROM_LOAD16_WORD_SWAP( "u24", 0x400000, 0x400000, CRC(8e3a51ba) SHA1(e34cf9acb13c3d8ca6cd1306b060b1d429872abd) )
ROM_END
GAME( 2004, mushisam, 0, cavesh3, cavesh3, 0, ROT0, "Cave", "Mushihime Sama (2004/10/12 MASTER VER.)", GAME_NOT_WORKING | GAME_NO_SOUND )
GAME( 2004, mushisama, mushisam, cavesh3, cavesh3, 0, ROT0, "Cave", "Mushihime Sama (2004/10/12 MASTER VER)", GAME_NOT_WORKING | GAME_NO_SOUND )
@ -243,6 +299,7 @@ GAME( 2006, ibarablk, 0, cavesh3, cavesh3, 0, ROT0, "Cave", "Ibara
GAME( 2006, ibarablka, ibarablk, cavesh3, cavesh3, 0, ROT0, "Cave", "Ibara Kuro - Black Label (2006/02/06 MASTER VER.)", GAME_NOT_WORKING | GAME_NO_SOUND )
GAME( 2007, deathsml, 0, cavesh3, cavesh3, 0, ROT0, "Cave", "Death Smiles (2007/10/09 MASTER VER)", GAME_NOT_WORKING | GAME_NO_SOUND )
GAME( 2007, mmpork, 0, cavesh3, cavesh3, 0, ROT0, "Cave", "Muchi Muchi Pork (2007/ 4/17 MASTER VER.)", GAME_NOT_WORKING | GAME_NO_SOUND )
GAME( 2007, mmmbnk, 0, cavesh3, cavesh3, 0, ROT0, "Cave", "Medal Majhong moukari Banchou no Kiban (2007/06/05 MASTER VER.)", GAME_NOT_WORKING | GAME_NO_SOUND )
/*

1
src/mame/mame.lst
View File

@ -2576,6 +2576,7 @@ ibarablk // (c) 2006 Cave
ibarablka // (c) 2006 Cave
deathsml // (c) 2007 Cave
mmpork // (c) 2007 Cave
mmmbnk // (c) 2007 Cave
// Kyugo games
// Kyugo only made four games: Repulse, Flash Gal, SRD Mission and Air Wolf.